S3C: Allow to completly disable low-level messages
[kernel.git] / arch / arm / plat-samsung / include / plat / uncompress.h
1 /* arch/arm/plat-samsung/include/plat/uncompress.h
2  *
3  * Copyright 2003, 2007 Simtec Electronics
4  *      http://armlinux.simtec.co.uk/
5  *      Ben Dooks <ben@simtec.co.uk>
6  *
7  * S3C - uncompress code
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12 */
13
14 #ifndef __ASM_PLAT_UNCOMPRESS_H
15 #define __ASM_PLAT_UNCOMPRESS_H
16
17 typedef unsigned int upf_t;     /* cannot include linux/serial_core.h */
18
19 /* uart setup */
20
21 static unsigned int fifo_mask;
22 static unsigned int fifo_max;
23
24 /* forward declerations */
25
26 static void arch_detect_cpu(void);
27
28 /* defines for UART registers */
29
30 #include <plat/regs-serial.h>
31 #include <plat/regs-watchdog.h>
32
33 /* working in physical space... */
34 #undef S3C2410_WDOGREG
35 #define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
36
37 /* how many bytes we allow into the FIFO at a time in FIFO mode */
38 #define FIFO_MAX         (14)
39
40 #if  CONFIG_S3C_LOWLEVEL_UART_PORT >= 0
41
42 #define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
43
44 static __inline__ void
45 uart_wr(unsigned int reg, unsigned int val)
46 {
47         volatile unsigned int *ptr;
48
49         ptr = (volatile unsigned int *)(reg + uart_base);
50         *ptr = val;
51 }
52
53 static __inline__ unsigned int
54 uart_rd(unsigned int reg)
55 {
56         volatile unsigned int *ptr;
57
58         ptr = (volatile unsigned int *)(reg + uart_base);
59         return *ptr;
60 }
61
62 /* we can deal with the case the UARTs are being run
63  * in FIFO mode, so that we don't hold up our execution
64  * waiting for tx to happen...
65 */
66
67 static void putc(int ch)
68 {
69         if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
70                 int level;
71
72                 while (1) {
73                         level = uart_rd(S3C2410_UFSTAT);
74                         level &= fifo_mask;
75
76                         if (level < fifo_max)
77                                 break;
78                 }
79
80         } else {
81                 /* not using fifos */
82
83                 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
84                         barrier();
85         }
86
87         /* write byte to transmission register */
88         uart_wr(S3C2410_UTXH, ch);
89 }
90
91 #define __raw_writel(d, ad)                     \
92         do {                                                    \
93                 *((volatile unsigned int __force *)(ad)) = (d); \
94         } while (0)
95
96 /* CONFIG_S3C_BOOT_WATCHDOG
97  *
98  * Simple boot-time watchdog setup, to reboot the system if there is
99  * any problem with the boot process
100 */
101
102 #ifdef CONFIG_S3C_BOOT_WATCHDOG
103
104 #define WDOG_COUNT (0xff00)
105
106 static inline void arch_decomp_wdog(void)
107 {
108         __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
109 }
110
111 static void arch_decomp_wdog_start(void)
112 {
113         __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
114         __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
115         __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
116 }
117
118 #else
119 #define arch_decomp_wdog_start()
120 #define arch_decomp_wdog()
121 #endif
122
123 #ifdef CONFIG_S3C_BOOT_ERROR_RESET
124
125 static void arch_decomp_error(const char *x)
126 {
127         putstr("\n\n");
128         putstr(x);
129         putstr("\n\n -- System resetting\n");
130
131         __raw_writel(0x4000, S3C2410_WTDAT);
132         __raw_writel(0x4000, S3C2410_WTCNT);
133         __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
134
135         while(1);
136 }
137
138 #define arch_error arch_decomp_error
139 #endif
140
141 #ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
142 static inline void arch_enable_uart_fifo(void)
143 {
144         u32 fifocon = uart_rd(S3C2410_UFCON);
145
146         if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
147                 fifocon |= S3C2410_UFCON_RESETBOTH;
148                 uart_wr(S3C2410_UFCON, fifocon);
149
150                 /* wait for fifo reset to complete */
151                 while (1) {
152                         fifocon = uart_rd(S3C2410_UFCON);
153                         if (!(fifocon & S3C2410_UFCON_RESETBOTH))
154                                 break;
155                 }
156         }
157 }
158 #else
159 #define arch_enable_uart_fifo() do { } while(0)
160 #endif
161
162 #else
163 static inline void putc(int ch)
164 {
165 }
166
167 #define arch_enable_uart_fifo() do { } while(0)
168 #define arch_decomp_wdog_start()
169 #define arch_decomp_wdog()
170 #endif
171
172 static inline void flush(void)
173 {
174 }
175
176 static void
177 arch_decomp_setup(void)
178 {
179         /* we may need to setup the uart(s) here if we are not running
180          * on an BAST... the BAST will have left the uarts configured
181          * after calling linux.
182          */
183
184         arch_detect_cpu();
185         arch_decomp_wdog_start();
186
187         /* Enable the UART FIFOs if they where not enabled and our
188          * configuration says we should turn them on.
189          */
190
191         arch_enable_uart_fifo();
192 }
193
194
195 #endif /* __ASM_PLAT_UNCOMPRESS_H */