23073fedea27b8b0a1f9da0bfe024615d875d903
[kernel.git] / drivers / mfd / glamo / glamo-core.c
1 /* Smedia Glamo 3362 driver
2  *
3  * (C) 2007 by Openmoko, Inc.
4  * Author: Harald Welte <laforge@openmoko.org>
5  * (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
6  * All rights reserved.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/errno.h>
27 #include <linux/string.h>
28 #include <linux/mm.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/irq.h>
32 #include <linux/interrupt.h>
33 #include <linux/workqueue.h>
34 #include <linux/platform_device.h>
35 #include <linux/kernel_stat.h>
36 #include <linux/spinlock.h>
37 #include <linux/mfd/core.h>
38 #include <linux/mfd/glamo.h>
39 #include <linux/io.h>
40 #include <linux/slab.h>
41
42 #include <linux/pm.h>
43
44 #include "glamo-regs.h"
45 #include "glamo-core.h"
46
47 #define GLAMO_MEM_REFRESH_COUNT 0x100
48
49 #define GLAMO_NR_IRQS 9
50
51 #define GLAMO_IRQ_HOSTBUS       0
52 #define GLAMO_IRQ_JPEG          1
53 #define GLAMO_IRQ_MPEG          2
54 #define GLAMO_IRQ_MPROC1        3
55 #define GLAMO_IRQ_MPROC0        4
56 #define GLAMO_IRQ_CMDQUEUE      5
57 #define GLAMO_IRQ_2D            6
58 #define GLAMO_IRQ_MMC           7
59 #define GLAMO_IRQ_RISC          8
60
61 /*
62  * Glamo internal settings
63  *
64  * We run the memory interface from the faster PLLB on 2.6.28 kernels and
65  * above.  Couple of GTA02 users report trouble with memory bus when they
66  * upgraded from 2.6.24.  So this parameter allows reversion to 2.6.24
67  * scheme if their Glamo chip needs it.
68  *
69  * you can override the faster default on kernel commandline using
70  *
71  *   glamo3362.slow_memory=1
72  *
73  * for example
74  */
75
76 static int slow_memory;
77 module_param(slow_memory, int, 0644);
78
79 struct reg_range {
80         int start;
81         int count;
82         char *name;
83         unsigned dump:1;
84 };
85
86 static const struct reg_range reg_range[] = {
87         { 0x0000, 0x76,         "General",      1 },
88         { 0x0200, 0x18,         "Host Bus",     1 },
89         { 0x0300, 0x38,         "Memory",       1 },
90 /*      { 0x0400, 0x100,        "Sensor",       0 }, */
91 /*      { 0x0500, 0x300,        "ISP",          0 }, */
92 /*      { 0x0800, 0x400,        "JPEG",         0 }, */
93 /*      { 0x0c00, 0xcc,         "MPEG",         0 }, */
94         { 0x1100, 0xb2,         "LCD 1",        1 },
95         { 0x1200, 0x64,         "LCD 2",        1 },
96         { 0x1400, 0x42,         "MMC",          1 },
97 /*      { 0x1500, 0x080,        "MPU 0",        0 },
98         { 0x1580, 0x080,        "MPU 1",        0 },
99         { 0x1600, 0x080,        "Cmd Queue",    0 },
100         { 0x1680, 0x080,        "RISC CPU",     0 },*/
101         { 0x1700, 0x400,        "2D Unit",      1 },
102 /*      { 0x1b00, 0x900,        "3D Unit",      0 }, */
103 };
104
105 static inline void __reg_write(struct glamo_core *glamo,
106                                 uint16_t reg, uint16_t val)
107 {
108         writew(val, glamo->base + reg);
109 }
110
111 void glamo_reg_write(struct glamo_core *glamo,
112                                 uint16_t reg, uint16_t val)
113 {
114         spin_lock(&glamo->lock);
115         __reg_write(glamo, reg, val);
116         spin_unlock(&glamo->lock);
117 }
118 EXPORT_SYMBOL_GPL(glamo_reg_write);
119
120
121 static inline uint16_t __reg_read(struct glamo_core *glamo,
122                                         uint16_t reg)
123 {
124         return readw(glamo->base + reg);
125 }
126
127 uint16_t glamo_reg_read(struct glamo_core *glamo, uint16_t reg)
128 {
129         uint16_t val;
130         spin_lock(&glamo->lock);
131         val = __reg_read(glamo, reg);
132         spin_unlock(&glamo->lock);
133
134         return val;
135 }
136 EXPORT_SYMBOL_GPL(glamo_reg_read);
137
138 static void __reg_set_bit_mask(struct glamo_core *glamo,
139                                 uint16_t reg, uint16_t mask,
140                                 uint16_t val)
141 {
142         uint16_t tmp;
143
144         val &= mask;
145
146         tmp = __reg_read(glamo, reg);
147         tmp &= ~mask;
148         tmp |= val;
149         __reg_write(glamo, reg, tmp);
150 }
151
152 static void reg_set_bit_mask(struct glamo_core *glamo,
153                                 uint16_t reg, uint16_t mask,
154                                 uint16_t val)
155 {
156         spin_lock(&glamo->lock);
157         __reg_set_bit_mask(glamo, reg, mask, val);
158         spin_unlock(&glamo->lock);
159 }
160
161 static inline void __reg_set_bit(struct glamo_core *glamo,
162                                  uint16_t reg, uint16_t bit)
163 {
164         uint16_t tmp;
165         tmp = __reg_read(glamo, reg);
166         tmp |= bit;
167         __reg_write(glamo, reg, tmp);
168 }
169
170 static inline void __reg_clear_bit(struct glamo_core *glamo,
171                                         uint16_t reg, uint16_t bit)
172 {
173         uint16_t tmp;
174         tmp = __reg_read(glamo, reg);
175         tmp &= ~bit;
176         __reg_write(glamo, reg, tmp);
177 }
178
179 static void __reg_write_batch(struct glamo_core *glamo, uint16_t reg,
180                                 uint16_t count, uint16_t *values)
181 {
182         uint16_t end;
183         for (end = reg + count * 2; reg < end; reg += 2, ++values)
184                 __reg_write(glamo, reg, *values);
185 }
186
187 static void __reg_read_batch(struct glamo_core *glamo, uint16_t reg,
188                                 uint16_t count, uint16_t *values)
189 {
190         uint16_t end;
191         for (end = reg + count * 2; reg < end; reg += 2, ++values)
192                 *values = __reg_read(glamo, reg);
193 }
194
195 void glamo_reg_write_batch(struct glamo_core *glamo, uint16_t reg,
196                                 uint16_t count, uint16_t *values)
197 {
198         spin_lock(&glamo->lock);
199         __reg_write_batch(glamo, reg, count, values);
200         spin_unlock(&glamo->lock);
201 }
202 EXPORT_SYMBOL(glamo_reg_write_batch);
203
204 void glamo_reg_read_batch(struct glamo_core *glamo, uint16_t reg,
205                                 uint16_t count, uint16_t *values)
206 {
207         spin_lock(&glamo->lock);
208         __reg_read_batch(glamo, reg, count, values);
209         spin_unlock(&glamo->lock);
210 }
211 EXPORT_SYMBOL(glamo_reg_read_batch);
212
213 /***********************************************************************
214  * resources of sibling devices
215  ***********************************************************************/
216
217 static struct resource glamo_fb_resources[] = {
218         {
219                 .name   = "glamo-fb-regs",
220                 .start  = GLAMO_REGOFS_LCD,
221                 .end    = GLAMO_REGOFS_MMC - 1,
222                 .flags  = IORESOURCE_MEM,
223         }, {
224                 .name   = "glamo-fb-mem",
225                 .start  = GLAMO_OFFSET_FB,
226                 .end    = GLAMO_OFFSET_FB + GLAMO_FB_SIZE - 1,
227                 .flags  = IORESOURCE_MEM,
228         },
229 };
230
231 static struct resource glamo_mmc_resources[] = {
232         {
233                 .name   = "glamo-mmc-regs",
234                 .start  = GLAMO_REGOFS_MMC,
235                 .end    = GLAMO_REGOFS_MPROC0 - 1,
236                 .flags  = IORESOURCE_MEM
237         }, {
238                 .name   = "glamo-mmc-mem",
239                 .start  = GLAMO_OFFSET_FB + GLAMO_FB_SIZE,
240                 .end    = GLAMO_OFFSET_FB + GLAMO_FB_SIZE +
241                                   GLAMO_MMC_BUFFER_SIZE - 1,
242                 .flags  = IORESOURCE_MEM
243         }, {
244                 .start  = GLAMO_IRQ_MMC,
245                 .end    = GLAMO_IRQ_MMC,
246                 .flags  = IORESOURCE_IRQ,
247         },
248 };
249
250 enum glamo_cells {
251         GLAMO_CELL_FB,
252         GLAMO_CELL_MMC,
253         GLAMO_CELL_GPIO,
254 };
255
256 static const struct mfd_cell glamo_cells[] = {
257         [GLAMO_CELL_FB] = {
258                 .name = "glamo-fb",
259                 .num_resources = ARRAY_SIZE(glamo_fb_resources),
260                 .resources = glamo_fb_resources,
261         },
262         [GLAMO_CELL_MMC] = {
263                 .name = "glamo-mci",
264                 .num_resources = ARRAY_SIZE(glamo_mmc_resources),
265                 .resources = glamo_mmc_resources,
266         },
267         [GLAMO_CELL_GPIO] = {
268                 .name = "glamo-gpio",
269         },
270 };
271
272 /***********************************************************************
273  * IRQ demultiplexer
274  ***********************************************************************/
275 #define glamo_irq_bit(glamo, x) BIT(x - glamo->irq_base)
276
277 static inline struct glamo_core *irq_to_glamo(unsigned int irq)
278 {
279         return (struct glamo_core *)get_irq_chip_data(irq);
280 }
281
282 static void glamo_ack_irq(unsigned int irq)
283 {
284         struct glamo_core *glamo = irq_to_glamo(irq);
285         /* clear interrupt source */
286         __reg_write(glamo, GLAMO_REG_IRQ_CLEAR, glamo_irq_bit(glamo, irq));
287 }
288
289 static void glamo_mask_irq(unsigned int irq)
290 {
291         struct glamo_core *glamo = irq_to_glamo(irq);
292
293         /* clear bit in enable register */
294         __reg_clear_bit(glamo, GLAMO_REG_IRQ_ENABLE, glamo_irq_bit(glamo, irq));
295 }
296
297 static void glamo_unmask_irq(unsigned int irq)
298 {
299         struct glamo_core *glamo = irq_to_glamo(irq);
300
301         /* set bit in enable register */
302         __reg_set_bit(glamo, GLAMO_REG_IRQ_ENABLE, glamo_irq_bit(glamo, irq));
303 }
304
305 static struct irq_chip glamo_irq_chip = {
306         .name   = "glamo",
307         .ack    = glamo_ack_irq,
308         .mask   = glamo_mask_irq,
309         .unmask = glamo_unmask_irq,
310 };
311
312 static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
313 {
314         struct glamo_core *glamo = get_irq_desc_data(desc);
315         desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
316
317         if (unlikely(desc->status & IRQ_INPROGRESS)) {
318                 desc->status |= (IRQ_PENDING | IRQ_MASKED);
319                 desc->chip->mask(irq);
320                 desc->chip->ack(irq);
321                 return;
322         }
323         kstat_incr_irqs_this_cpu(irq, desc);
324
325         desc->chip->ack(irq);
326         desc->status |= IRQ_INPROGRESS;
327
328         do {
329                 uint16_t irqstatus;
330                 int i;
331
332                 if (unlikely((desc->status &
333                                 (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
334                                 (IRQ_PENDING | IRQ_MASKED))) {
335                         /* dealing with pending IRQ, unmasking */
336                         desc->chip->unmask(irq);
337                         desc->status &= ~IRQ_MASKED;
338                 }
339
340                 desc->status &= ~IRQ_PENDING;
341
342                 /* read IRQ status register */
343                 irqstatus = __reg_read(glamo, GLAMO_REG_IRQ_STATUS);
344                 for (i = 0; i < 9; ++i) {
345                         if (irqstatus & BIT(i))
346                                 generic_handle_irq(glamo->irq_base + i);
347                 }
348
349         } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
350
351         desc->status &= ~IRQ_INPROGRESS;
352 }
353
354 /*
355 sysfs
356 */
357
358 static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
359                                 const char *buf, size_t count)
360 {
361         struct glamo_core *glamo = dev_get_drvdata(dev);
362         unsigned int reg;
363         unsigned int val;
364
365         sscanf(buf, "%u %u", &reg, &val);
366         printk(KERN_INFO"reg 0x%02x <-- 0x%04x\n",
367                 reg, val);
368
369         glamo_reg_write(glamo, reg, val);
370
371         return count;
372 }
373
374 static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
375                         char *buf)
376 {
377         struct glamo_core *glamo = dev_get_drvdata(dev);
378         int i, n;
379         char *end = buf;
380         const struct reg_range *rr = reg_range;
381
382         spin_lock(&glamo->lock);
383
384         for (i = 0; i < ARRAY_SIZE(reg_range); ++i, ++rr) {
385                 if (!rr->dump)
386                         continue;
387                 end += sprintf(end, "\n%s\n", rr->name);
388                 for (n = rr->start; n < rr->start + rr->count; n += 2) {
389                         if ((n & 15) == 0)
390                                 end += sprintf(end, "\n%04X:  ", n);
391                         end += sprintf(end, "%04x ", __reg_read(glamo, n));
392                 }
393                 end += sprintf(end, "\n");
394         }
395         spin_unlock(&glamo->lock);
396
397         return end - buf;
398 }
399
400 static DEVICE_ATTR(regs, 0644, regs_read, regs_write);
401
402 struct glamo_engine_reg_set {
403         uint16_t reg;
404         uint16_t mask_suspended;
405         uint16_t mask_enabled;
406 };
407
408 struct glamo_engine_desc {
409         const char *name;
410         uint16_t hostbus;
411         const struct glamo_engine_reg_set *regs;
412         int num_regs;
413 };
414
415 static const struct glamo_engine_reg_set glamo_lcd_regs[] = {
416         { GLAMO_REG_CLOCK_LCD,
417         GLAMO_CLOCK_LCD_EN_M5CLK |
418         GLAMO_CLOCK_LCD_DG_M5CLK |
419         GLAMO_CLOCK_LCD_EN_DMCLK,
420
421         GLAMO_CLOCK_LCD_EN_DHCLK |
422         GLAMO_CLOCK_LCD_EN_DCLK
423         },
424         { GLAMO_REG_CLOCK_GEN5_1,
425         GLAMO_CLOCK_GEN51_EN_DIV_DMCLK,
426
427         GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
428         GLAMO_CLOCK_GEN51_EN_DIV_DCLK
429         }
430 };
431
432 static const struct glamo_engine_reg_set glamo_mmc_regs[] = {
433         { GLAMO_REG_CLOCK_MMC,
434         GLAMO_CLOCK_MMC_EN_M9CLK |
435         GLAMO_CLOCK_MMC_DG_M9CLK,
436
437         GLAMO_CLOCK_MMC_EN_TCLK |
438         GLAMO_CLOCK_MMC_DG_TCLK
439         },
440         { GLAMO_REG_CLOCK_GEN5_1,
441         0,
442         GLAMO_CLOCK_GEN51_EN_DIV_TCLK
443         }
444 };
445
446 static const struct glamo_engine_reg_set glamo_2d_regs[] = {
447         { GLAMO_REG_CLOCK_2D,
448         GLAMO_CLOCK_2D_EN_M7CLK |
449         GLAMO_CLOCK_2D_DG_M7CLK,
450
451         GLAMO_CLOCK_2D_EN_GCLK |
452         GLAMO_CLOCK_2D_DG_GCLK
453         },
454         { GLAMO_REG_CLOCK_GEN5_1,
455         0,
456         GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
457         }
458 };
459
460 static const struct glamo_engine_reg_set glamo_cmdq_regs[] = {
461         { GLAMO_REG_CLOCK_2D,
462         GLAMO_CLOCK_2D_EN_M6CLK,
463         0
464         },
465 };
466
467 #define GLAMO_ENGINE(xname, xhostbus, xregs) { \
468         .name = xname, \
469         .hostbus = xhostbus, \
470         .num_regs = ARRAY_SIZE(xregs), \
471         .regs = xregs, \
472 }
473
474 static const struct glamo_engine_desc glamo_engines[] = {
475         [GLAMO_ENGINE_LCD] = GLAMO_ENGINE("LCD", GLAMO_HOSTBUS2_MMIO_EN_LCD,
476                                         glamo_lcd_regs),
477         [GLAMO_ENGINE_MMC] = GLAMO_ENGINE("MMC", GLAMO_HOSTBUS2_MMIO_EN_MMC,
478                                         glamo_mmc_regs),
479         [GLAMO_ENGINE_2D] = GLAMO_ENGINE("2D", GLAMO_HOSTBUS2_MMIO_EN_2D,
480                                         glamo_2d_regs),
481         [GLAMO_ENGINE_CMDQ] = GLAMO_ENGINE("CMDQ", GLAMO_HOSTBUS2_MMIO_EN_CQ,
482                                         glamo_cmdq_regs),
483 };
484
485 static inline const char *glamo_engine_name(enum glamo_engine engine)
486 {
487         return glamo_engines[engine].name;
488 }
489
490 /***********************************************************************
491  * 'engine' support
492  ***********************************************************************/
493
494 int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
495 {
496         int i;
497         const struct glamo_engine_desc *engine_desc = &glamo_engines[engine];
498         const struct glamo_engine_reg_set *reg;
499
500         switch (engine) {
501         case GLAMO_ENGINE_LCD:
502         case GLAMO_ENGINE_MMC:
503         case GLAMO_ENGINE_2D:
504         case GLAMO_ENGINE_CMDQ:
505                 break;
506         default:
507                 return -EINVAL;
508         }
509
510         reg = engine_desc->regs;
511
512         __reg_set_bit(glamo, GLAMO_REG_HOSTBUS(2),
513                         engine_desc->hostbus);
514         for (i = engine_desc->num_regs; i; --i, ++reg)
515                 __reg_set_bit(glamo, reg->reg,
516                                 reg->mask_suspended | reg->mask_enabled);
517
518         return 0;
519 }
520
521 int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
522 {
523         int ret = 0;
524
525         spin_lock(&glamo->lock);
526
527         if (glamo->engine_state[engine] != GLAMO_ENGINE_ENABLED) {
528                 ret = __glamo_engine_enable(glamo, engine);
529                 if (!ret)
530                         glamo->engine_state[engine] = GLAMO_ENGINE_ENABLED;
531         }
532
533         spin_unlock(&glamo->lock);
534
535         return ret;
536 }
537 EXPORT_SYMBOL_GPL(glamo_engine_enable);
538
539 int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
540 {
541         int i;
542         const struct glamo_engine_desc *engine_desc = &glamo_engines[engine];
543         const struct glamo_engine_reg_set *reg;
544
545         switch (engine) {
546         case GLAMO_ENGINE_LCD:
547         case GLAMO_ENGINE_MMC:
548         case GLAMO_ENGINE_2D:
549         case GLAMO_ENGINE_CMDQ:
550                 break;
551         default:
552                 return -EINVAL;
553         }
554
555         reg = engine_desc->regs;
556
557         __reg_clear_bit(glamo, GLAMO_REG_HOSTBUS(2),
558                         engine_desc->hostbus);
559         for (i = engine_desc->num_regs; i; --i, ++reg)
560                 __reg_clear_bit(glamo, reg->reg,
561                                 reg->mask_suspended | reg->mask_enabled);
562
563         return 0;
564 }
565 int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
566 {
567         int ret = 0;
568
569         spin_lock(&glamo->lock);
570
571         if (glamo->engine_state[engine] != GLAMO_ENGINE_DISABLED) {
572                 ret = __glamo_engine_disable(glamo, engine);
573                 if (!ret)
574                         glamo->engine_state[engine] = GLAMO_ENGINE_DISABLED;
575         }
576
577         spin_unlock(&glamo->lock);
578
579         return ret;
580 }
581 EXPORT_SYMBOL_GPL(glamo_engine_disable);
582
583 int __glamo_engine_suspend(struct glamo_core *glamo, enum glamo_engine engine)
584 {
585         int i;
586         const struct glamo_engine_desc *engine_desc = &glamo_engines[engine];
587         const struct glamo_engine_reg_set *reg;
588
589         switch (engine) {
590         case GLAMO_ENGINE_LCD:
591         case GLAMO_ENGINE_MMC:
592         case GLAMO_ENGINE_2D:
593         case GLAMO_ENGINE_CMDQ:
594                 break;
595         default:
596                 return -EINVAL;
597         }
598
599         reg = engine_desc->regs;
600
601         __reg_set_bit(glamo, GLAMO_REG_HOSTBUS(2),
602                         engine_desc->hostbus);
603         for (i = engine_desc->num_regs; i; --i, ++reg) {
604                 __reg_set_bit(glamo, reg->reg, reg->mask_suspended);
605                 __reg_clear_bit(glamo, reg->reg, reg->mask_enabled);
606         }
607
608         return 0;
609 }
610
611 int glamo_engine_suspend(struct glamo_core *glamo, enum glamo_engine engine)
612 {
613         int ret = 0;
614
615         spin_lock(&glamo->lock);
616
617         if (glamo->engine_state[engine] != GLAMO_ENGINE_SUSPENDED) {
618                 ret = __glamo_engine_suspend(glamo, engine);
619                 if (!ret)
620                         glamo->engine_state[engine] = GLAMO_ENGINE_SUSPENDED;
621         }
622
623         spin_unlock(&glamo->lock);
624
625         return ret;
626 }
627 EXPORT_SYMBOL_GPL(glamo_engine_suspend);
628
629 static const struct glamo_script reset_regs[] = {
630         [GLAMO_ENGINE_LCD] = {
631                 GLAMO_REG_CLOCK_LCD, GLAMO_CLOCK_LCD_RESET
632         },
633         [GLAMO_ENGINE_MMC] = {
634                 GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
635         },
636         [GLAMO_ENGINE_CMDQ] = {
637                 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_CQ_RESET
638         },
639         [GLAMO_ENGINE_2D] = {
640                 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
641         },
642         [GLAMO_ENGINE_JPEG] = {
643                 GLAMO_REG_CLOCK_JPEG, GLAMO_CLOCK_JPEG_RESET
644         },
645 };
646
647 void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
648 {
649         uint16_t reg = reset_regs[engine].reg;
650         uint16_t val = reset_regs[engine].val;
651
652         if (engine >= ARRAY_SIZE(reset_regs)) {
653                 dev_warn(&glamo->pdev->dev, "unknown engine %u ", engine);
654                 return;
655         }
656
657         spin_lock(&glamo->lock);
658         __reg_set_bit(glamo, reg, val);
659         __reg_clear_bit(glamo, reg, val);
660         spin_unlock(&glamo->lock);
661 }
662 EXPORT_SYMBOL_GPL(glamo_engine_reset);
663
664 int glamo_pll_rate(struct glamo_core *glamo,
665                           enum glamo_pll pll)
666 {
667         uint16_t reg;
668         unsigned int osci = glamo->pdata->osci_clock_rate;
669
670         switch (pll) {
671         case GLAMO_PLL1:
672                 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
673                 break;
674         case GLAMO_PLL2:
675                 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
676                 break;
677         default:
678                 return -EINVAL;
679         }
680
681         return (int)osci * (int)reg;
682 }
683 EXPORT_SYMBOL_GPL(glamo_pll_rate);
684
685 int glamo_engine_reclock(struct glamo_core *glamo,
686                          enum glamo_engine engine,
687                          int hz)
688 {
689         int pll;
690         uint16_t reg, mask, div;
691
692         if (!hz)
693                 return -EINVAL;
694
695         switch (engine) {
696         case GLAMO_ENGINE_LCD:
697                 pll = GLAMO_PLL1;
698                 reg = GLAMO_REG_CLOCK_GEN7;
699                 mask = 0xff;
700                 break;
701         case GLAMO_ENGINE_MMC:
702                 pll = GLAMO_PLL1;
703                 reg = GLAMO_REG_CLOCK_GEN8;
704                 mask = 0xff;
705                 break;
706         default:
707                 dev_warn(&glamo->pdev->dev,
708                          "reclock of engine 0x%x not supported\n", engine);
709                 return -EINVAL;
710                 break;
711         }
712
713         pll = glamo_pll_rate(glamo, pll);
714
715         div = pll / hz;
716
717         if (div != 0 && pll / div <= hz)
718                 --div;
719
720         if (div > mask)
721                 div = mask;
722
723         dev_dbg(&glamo->pdev->dev,
724                         "PLL %d, kHZ %d, div %d\n", pll, hz / 1000, div);
725
726         reg_set_bit_mask(glamo, reg, mask, div);
727         mdelay(5); /* wait some time to stabilize */
728
729         return pll / (div + 1);
730 }
731 EXPORT_SYMBOL_GPL(glamo_engine_reclock);
732
733 /***********************************************************************
734  * script support
735  ***********************************************************************/
736
737 #define GLAMO_SCRIPT_END        0xffff
738 #define GLAMO_SCRIPT_WAIT       0xfffe
739 #define GLAMO_SCRIPT_LOCK_PLL   0xfffd
740
741 /*
742  * couple of people reported artefacts with 2.6.28 changes, this
743  * allows reversion to 2.6.24 settings
744 */
745 static const uint16_t reg_0x200[] = {
746 0xe03, /* 0 waits on Async BB R & W, Use PLL 2 for mem bus */
747 0xef0, /* 3 waits on Async BB R & W, Use PLL 1 for mem bus */
748 0xea0, /* 2 waits on Async BB R & W, Use PLL 1 for mem bus */
749 0xe50, /* 1 waits on Async BB R & W, Use PLL 1 for mem bus */
750 0xe00, /* 0 waits on Async BB R & W, Use PLL 1 for mem bus */
751 0xef3, /* 3 waits on Async BB R & W, Use PLL 2 for mem bus */
752 0xea3, /* 2 waits on Async BB R & W, Use PLL 2 for mem bus */
753 0xe53, /* 1 waits on Async BB R & W, Use PLL 2 for mem bus */
754 };
755
756 static int glamo_run_script(struct glamo_core *glamo,
757                                 const struct glamo_script *script, int len,
758                                 int may_sleep)
759 {
760         int i;
761         uint16_t status;
762         const struct glamo_script *line = script;
763
764         for (i = 0; i < len; ++i, ++line) {
765                 switch (line->reg) {
766                 case GLAMO_SCRIPT_END:
767                         return 0;
768                 case GLAMO_SCRIPT_WAIT:
769                         if (may_sleep)
770                                 msleep(line->val);
771                         else
772                                 mdelay(line->val * 4);
773                         break;
774                 case GLAMO_SCRIPT_LOCK_PLL:
775                         /* spin until PLLs lock */
776                         do {
777                                 status = __reg_read(glamo, GLAMO_REG_PLL_GEN5);
778                         } while ((status & 3) != 3);
779                         break;
780                 case 0x200:
781                         __reg_write(glamo, line->reg,
782                                         reg_0x200[slow_memory & 0x8]);
783                         break;
784                 default:
785                         __reg_write(glamo, line->reg, line->val);
786                         break;
787                 }
788         }
789
790         return 0;
791 }
792
793 static const struct glamo_script glamo_init_script[] = {
794         { GLAMO_REG_CLOCK_HOST,         0x1000 },
795         { GLAMO_SCRIPT_WAIT,                 2 },
796         { GLAMO_REG_CLOCK_MEMORY,       0x1000 },
797         { GLAMO_REG_CLOCK_MEMORY,       0x2000 },
798         { GLAMO_REG_CLOCK_LCD,          0x1000 },
799         { GLAMO_REG_CLOCK_MMC,          0x1000 },
800         { GLAMO_REG_CLOCK_ISP,          0x1000 },
801         { GLAMO_REG_CLOCK_ISP,          0x3000 },
802         { GLAMO_REG_CLOCK_JPEG,         0x1000 },
803         { GLAMO_REG_CLOCK_3D,           0x1000 },
804         { GLAMO_REG_CLOCK_3D,           0x3000 },
805         { GLAMO_REG_CLOCK_2D,           0x1000 },
806         { GLAMO_REG_CLOCK_2D,           0x3000 },
807         { GLAMO_REG_CLOCK_RISC1,        0x1000 },
808         { GLAMO_REG_CLOCK_MPEG,         0x1000 },
809         { GLAMO_REG_CLOCK_MPEG,         0x3000 },
810         { GLAMO_REG_CLOCK_MPROC,        0x1000 /*0x100f*/ },
811         { GLAMO_SCRIPT_WAIT,                 2 },
812         { GLAMO_REG_CLOCK_HOST,         0x0000 },
813         { GLAMO_REG_CLOCK_MEMORY,       0x0000 },
814         { GLAMO_REG_CLOCK_LCD,          0x0000 },
815         { GLAMO_REG_CLOCK_MMC,          0x0000 },
816         { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
817         { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
818         { GLAMO_SCRIPT_LOCK_PLL, 0 },
819         /*
820          * b9 of this register MUST be zero to get any interrupts on INT#
821          * the other set bits enable all the engine interrupt sources
822          */
823         { GLAMO_REG_IRQ_ENABLE,         0x0100 },
824         { GLAMO_REG_CLOCK_GEN6,         0x2000 },
825         { GLAMO_REG_CLOCK_GEN7,         0x0101 },
826         { GLAMO_REG_CLOCK_GEN8,         0x0100 },
827         { GLAMO_REG_CLOCK_HOST,         0x000d },
828         /*
829          * b7..b4 = 0 = no wait states on read or write
830          * b0 = 1 select PLL2 for Host interface, b1 = enable it
831          */
832         { GLAMO_REG_HOSTBUS(0),         0x0e03 /* this is replaced by script parser */ },
833         { GLAMO_REG_HOSTBUS(1),         0x07ff }, /* TODO: Disable all */
834         { GLAMO_REG_HOSTBUS(10),        0x0000 },
835         { GLAMO_REG_HOSTBUS(11),        0x4000 },
836         { GLAMO_REG_HOSTBUS(12),        0xf00e },
837
838         /* S-Media recommended "set tiling mode to 512 mode for memory access
839          * more efficiency when 640x480" */
840         { GLAMO_REG_MEM_TYPE,           0x0c74 }, /* 8MB, 16 word pg wr+rd */
841         { GLAMO_REG_MEM_GEN,            0xafaf }, /* 63 grants min + max */
842
843         { GLAMO_REG_MEM_TIMING1,        0x0108 },
844         { GLAMO_REG_MEM_TIMING2,        0x0010 }, /* Taa = 3 MCLK */
845         { GLAMO_REG_MEM_TIMING3,        0x0000 },
846         { GLAMO_REG_MEM_TIMING4,        0x0000 }, /* CE1# delay fall/rise */
847         { GLAMO_REG_MEM_TIMING5,        0x0000 }, /* UB# LB# */
848         { GLAMO_REG_MEM_TIMING6,        0x0000 }, /* OE# */
849         { GLAMO_REG_MEM_TIMING7,        0x0000 }, /* WE# */
850         { GLAMO_REG_MEM_TIMING8,        0x1002 }, /* MCLK delay, was 0x1000 */
851         { GLAMO_REG_MEM_TIMING9,        0x6006 },
852         { GLAMO_REG_MEM_TIMING10,       0x00ff },
853         { GLAMO_REG_MEM_TIMING11,       0x0001 },
854         { GLAMO_REG_MEM_POWER1,         0x0020 },
855         { GLAMO_REG_MEM_POWER2,         0x0000 },
856         { GLAMO_REG_MEM_DRAM1,          0x0000 },
857         { GLAMO_SCRIPT_WAIT,                 1 },
858         { GLAMO_REG_MEM_DRAM1,          0xc100 },
859         { GLAMO_SCRIPT_WAIT,                 1 },
860         { GLAMO_REG_MEM_DRAM1,          0xe100 },
861         { GLAMO_REG_MEM_DRAM2,          0x01d6 },
862         { GLAMO_REG_CLOCK_MEMORY,       0x000b },
863 };
864
865 /* Find out if we can support this version of the Glamo chip */
866 static int __devinit glamo_supported(struct glamo_core *glamo)
867 {
868         uint16_t dev_id, rev_id;
869
870         dev_id = __reg_read(glamo, GLAMO_REG_DEVICE_ID);
871         rev_id = __reg_read(glamo, GLAMO_REG_REVISION_ID);
872
873         switch (dev_id) {
874         case 0x3650:
875                 switch (rev_id) {
876                 case GLAMO_CORE_REV_A2:
877                         break;
878                 case GLAMO_CORE_REV_A0:
879                 case GLAMO_CORE_REV_A1:
880                 case GLAMO_CORE_REV_A3:
881                         dev_warn(&glamo->pdev->dev, "untested core revision "
882                                  "%04x, your mileage may vary\n", rev_id);
883                         break;
884                 default:
885                         dev_warn(&glamo->pdev->dev, "unknown glamo revision "
886                                  "%04x, your mileage may vary\n", rev_id);
887                 }
888                 break;
889         default:
890                 dev_err(&glamo->pdev->dev, "unsupported Glamo device %04x\n",
891                         dev_id);
892                 return 0;
893         }
894
895         dev_dbg(&glamo->pdev->dev, "Detected Glamo core %04x Revision %04x "
896                  "(%uHz CPU / %uHz Memory)\n", dev_id, rev_id,
897                  glamo_pll_rate(glamo, GLAMO_PLL1),
898                  glamo_pll_rate(glamo, GLAMO_PLL2));
899
900         return 1;
901 }
902
903 static int __devinit glamo_probe(struct platform_device *pdev)
904 {
905         int ret = 0, irq, irq_base;
906         struct glamo_core *glamo;
907         struct resource *mem;
908
909         glamo = kmalloc(GFP_KERNEL, sizeof(*glamo));
910         if (!glamo)
911                 return -ENOMEM;
912
913         spin_lock_init(&glamo->lock);
914
915         glamo->pdev = pdev;
916         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
917         glamo->irq = platform_get_irq(pdev, 0);
918         glamo->irq_base = irq_base = platform_get_irq(pdev, 1);
919         glamo->pdata = pdev->dev.platform_data;
920
921         if (glamo->irq < 0) {
922                 ret = glamo->irq;
923                 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
924                 goto err_free;
925         }
926
927         if (irq_base < 0) {
928                 ret = glamo->irq;
929                 dev_err(&pdev->dev, "Failed to get glamo irq base: %d\n", ret);
930                 goto err_free;
931         }
932
933         if (!mem) {
934                 dev_err(&pdev->dev, "Failed to get platform memory\n");
935                 ret = -ENOENT;
936                 goto err_free;
937         }
938
939         if (!glamo->pdata) {
940                 dev_err(&pdev->dev, "Missing platform data\n");
941                 ret = -ENOENT;
942                 goto err_free;
943         }
944
945         /* only request the generic, hostbus and memory controller registers */
946         glamo->mem = request_mem_region(mem->start, GLAMO_REGOFS_VIDCAP,
947                                         pdev->name);
948
949         if (!glamo->mem) {
950                 dev_err(&pdev->dev, "Failed to request io memory region\n");
951                 ret = -ENOENT;
952                 goto err_free;
953         }
954
955         glamo->base = ioremap(glamo->mem->start, resource_size(glamo->mem));
956         if (!glamo->base) {
957                 dev_err(&pdev->dev, "Failed to ioremap() memory region\n");
958                 goto err_release_mem_region;
959         }
960
961         /* confirm it isn't insane version */
962         if (!glamo_supported(glamo)) {
963                 dev_err(&pdev->dev,
964                         "This version of the Glamo is not supported\n");
965                 goto err_iounmap;
966         }
967
968         platform_set_drvdata(pdev, glamo);
969
970         /* sysfs */
971         ret = device_create_file(&pdev->dev, &dev_attr_regs);
972         if (ret < 0) {
973                 dev_err(&pdev->dev, "Failed to create sysfs file\n");
974                 goto err_iounmap;
975         }
976
977         /* init the chip with canned register set */
978         glamo_run_script(glamo, glamo_init_script,
979                          ARRAY_SIZE(glamo_init_script), 1);
980
981         /*
982          * finally set the mfd interrupts up
983          */
984         for (irq = irq_base; irq < irq_base + GLAMO_NR_IRQS; ++irq) {
985 #ifdef CONFIG_ARM
986                 set_irq_flags(irq, IRQF_VALID);
987 #else
988                 set_irq_noprobe(irq);
989 #endif
990                 set_irq_chip_data(irq, glamo);
991                 set_irq_chip_and_handler(irq, &glamo_irq_chip,
992                                         handle_level_irq);
993         }
994
995         set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING);
996         set_irq_data(glamo->irq, glamo);
997         set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
998         glamo->irq_works = 1;
999
1000         ret = mfd_add_devices(&pdev->dev, pdev->id, glamo_cells,
1001                                 ARRAY_SIZE(glamo_cells), mem, glamo->irq_base);
1002
1003         if (ret) {
1004                 dev_err(&pdev->dev, "Failed to add child devices: %d\n", ret);
1005                 goto err_free_irqs;
1006         }
1007
1008         dev_info(&glamo->pdev->dev, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
1009                  glamo_pll_rate(glamo, GLAMO_PLL1),
1010                  glamo_pll_rate(glamo, GLAMO_PLL2));
1011
1012         return 0;
1013
1014 err_free_irqs:
1015         disable_irq(glamo->irq);
1016         set_irq_chained_handler(glamo->irq, NULL);
1017         set_irq_chip_data(glamo->irq, NULL);
1018
1019         for (irq = irq_base; irq < irq_base + GLAMO_NR_IRQS; ++irq) {
1020                 set_irq_chip(irq, NULL);
1021 #ifdef CONFIG_ARM
1022                 set_irq_flags(irq, 0);
1023 #else
1024                 set_irq_probe(irq);
1025 #endif
1026                 set_irq_chip_data(irq, NULL);
1027         }
1028 err_iounmap:
1029         iounmap(glamo->base);
1030 err_release_mem_region:
1031         release_mem_region(glamo->mem->start, resource_size(glamo->mem));
1032 err_free:
1033         platform_set_drvdata(pdev, NULL);
1034         kfree(glamo);
1035
1036         return ret;
1037 }
1038
1039 static int __devexit glamo_remove(struct platform_device *pdev)
1040 {
1041         struct glamo_core *glamo = platform_get_drvdata(pdev);
1042         int irq;
1043         int irq_base = glamo->irq_base;
1044
1045         mfd_remove_devices(&pdev->dev);
1046
1047         disable_irq(glamo->irq);
1048         set_irq_chained_handler(glamo->irq, NULL);
1049         set_irq_chip_data(glamo->irq, NULL);
1050
1051         for (irq = irq_base; irq < irq_base + GLAMO_NR_IRQS; ++irq) {
1052 #ifdef CONFIG_ARM
1053                 set_irq_flags(irq, 0);
1054 #else
1055                 set_irq_noprobe();
1056 #endif
1057                 set_irq_chip(irq, NULL);
1058                 set_irq_chip_data(irq, NULL);
1059         }
1060
1061         platform_set_drvdata(pdev, NULL);
1062         iounmap(glamo->base);
1063         release_mem_region(glamo->mem->start, resource_size(glamo->mem));
1064         kfree(glamo);
1065
1066         return 0;
1067 }
1068
1069 #ifdef CONFIG_PM
1070 #if 0
1071 static struct glamo_script glamo_resume_script[] = {
1072
1073         { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
1074         { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
1075         { GLAMO_REG_DFT_GEN6, 1 },
1076                 { 0xfffe, 100 },
1077                 { 0xfffd, 0 },
1078         { 0x200,        0x0e03 },
1079
1080         /*
1081          * b9 of this register MUST be zero to get any interrupts on INT#
1082          * the other set bits enable all the engine interrupt sources
1083          */
1084         { GLAMO_REG_IRQ_ENABLE,         0x01ff },
1085         { GLAMO_REG_CLOCK_HOST,         0x0018 },
1086         { GLAMO_REG_CLOCK_GEN5_1, 0x18b1 },
1087
1088         { GLAMO_REG_MEM_DRAM1,          0x0000 },
1089                 { 0xfffe, 1 },
1090         { GLAMO_REG_MEM_DRAM1,          0xc100 },
1091                 { 0xfffe, 1 },
1092         { GLAMO_REG_MEM_DRAM1,          0xe100 },
1093         { GLAMO_REG_MEM_DRAM2,          0x01d6 },
1094         { GLAMO_REG_CLOCK_MEMORY,       0x000b },
1095 };
1096 #endif
1097
1098 #if 0
1099 static void glamo_power(struct glamo_core *glamo)
1100 {
1101         unsigned long flags;
1102
1103         spin_lock_irqsave(&glamo->lock, flags);
1104
1105         /*
1106 Power management
1107 static const REG_VALUE_MASK_TYPE reg_powerOn[] =
1108 {
1109         { REG_GEN_DFT6,     REG_BIT_ALL,    REG_DATA(1u << 0)           },
1110         { REG_GEN_PLL3,     0u,             REG_DATA(1u << 13)          },
1111         { REG_GEN_MEM_CLK,  REG_BIT_ALL,    REG_BIT_EN_MOCACLK          },
1112         { REG_MEM_DRAM2,    0u,             REG_BIT_EN_DEEP_POWER_DOWN  },
1113         { REG_MEM_DRAM1,    0u,             REG_BIT_SELF_REFRESH        }
1114 };
1115
1116 static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
1117 {
1118         { REG_MEM_DRAM1,    REG_BIT_ALL,    REG_BIT_SELF_REFRESH    },
1119         { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK      },
1120         { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)      },
1121         { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)       }
1122 };
1123
1124 static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
1125 {
1126         { REG_MEM_DRAM2,    REG_BIT_ALL,    REG_BIT_EN_DEEP_POWER_DOWN  },
1127         { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK          },
1128         { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)          },
1129         { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)           }
1130 };
1131 */
1132         switch (new_state) {
1133         case GLAMO_POWER_ON:
1134
1135                 /*
1136                  * glamo state on resume is nondeterministic in some
1137                  * fundamental way, it has also been observed that the
1138                  * Glamo reset pin can get asserted by, eg, touching it with
1139                  * a scope probe.  So the only answer is to roll with it and
1140                  * force an external reset on the Glamo during resume.
1141                  */
1142
1143
1144                 break;
1145
1146         case GLAMO_POWER_SUSPEND:
1147
1148                 break;
1149         }
1150         spin_unlock_irqrestore(&glamo->lock, flags);
1151 }
1152 #endif
1153
1154 static int glamo_suspend(struct device *dev)
1155 {
1156         struct glamo_core *glamo = dev_get_drvdata(dev);
1157         int n;
1158
1159         spin_lock(&glamo->lock);
1160
1161         glamo->saved_irq_mask = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE);
1162
1163         /* nuke interrupts */
1164         __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, 0x200);
1165
1166         /* take down each engine before we kill mem and pll */
1167         for (n = 0; n < __NUM_GLAMO_ENGINES; n++) {
1168                 if (glamo->engine_state != GLAMO_ENGINE_DISABLED)
1169                         __glamo_engine_disable(glamo, n);
1170         }
1171
1172         /* enable self-refresh */
1173
1174         __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
1175                                 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
1176                                 GLAMO_MEM_DRAM1_EN_GATE_CKE |
1177                                 GLAMO_MEM_DRAM1_SELF_REFRESH |
1178                                 GLAMO_MEM_REFRESH_COUNT);
1179         __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
1180                                 GLAMO_MEM_DRAM1_EN_MODEREG_SET |
1181                                 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
1182                                 GLAMO_MEM_DRAM1_EN_GATE_CKE |
1183                                 GLAMO_MEM_DRAM1_SELF_REFRESH |
1184                                 GLAMO_MEM_REFRESH_COUNT);
1185
1186         /* force RAM into deep powerdown */
1187         __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
1188                                 GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
1189                                 (7 << 6) | /* tRC */
1190                                 (1 << 4) | /* tRP */
1191                                 (1 << 2) | /* tRCD */
1192                                 2); /* CAS latency */
1193
1194         /* disable clocks to memory */
1195         __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
1196
1197         /* all dividers from OSCI */
1198         __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0x400, 0x400);
1199
1200         /* PLL2 into bypass */
1201         __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 12, 1 << 12);
1202
1203         __reg_write(glamo, GLAMO_BASIC_MMC_EN_TCLK_DLYA1, 0x0e00);
1204
1205         /* kill PLLS 1 then 2 */
1206         __reg_write(glamo, GLAMO_REG_DFT_GEN5, 0x0001);
1207         __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 13, 1 << 13);
1208
1209         spin_unlock(&glamo->lock);
1210
1211         return 0;
1212 }
1213
1214 static int glamo_resume(struct device *dev)
1215 {
1216         struct glamo_core *glamo = dev_get_drvdata(dev);
1217         int n;
1218
1219         (glamo->pdata->glamo_external_reset)(0);
1220         udelay(10);
1221         (glamo->pdata->glamo_external_reset)(1);
1222         mdelay(5);
1223
1224         spin_lock(&glamo->lock);
1225
1226         glamo_run_script(glamo, glamo_init_script,
1227                          ARRAY_SIZE(glamo_init_script), 0);
1228
1229
1230         for (n = 0; n < __NUM_GLAMO_ENGINES; n++) {
1231                 switch (glamo->engine_state[n]) {
1232                 case GLAMO_ENGINE_SUSPENDED:
1233                         __glamo_engine_suspend(glamo, n);
1234                         break;
1235                 case GLAMO_ENGINE_ENABLED:
1236                         __glamo_engine_enable(glamo, n);
1237                         break;
1238                 default:
1239                         break;
1240                 }
1241         }
1242
1243         __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, glamo->saved_irq_mask);
1244
1245         spin_unlock(&glamo->lock);
1246
1247         return 0;
1248 }
1249
1250 static struct dev_pm_ops glamo_pm_ops = {
1251         .suspend    = glamo_suspend,
1252         .resume     = glamo_resume,
1253         .poweroff   = glamo_suspend,
1254         .restore    = glamo_resume,
1255 };
1256
1257 #define GLAMO_PM_OPS (&glamo_pm_ops)
1258
1259 #else
1260 #define GLAMO_PM_OPS NULL
1261 #endif
1262
1263 static struct platform_driver glamo_driver = {
1264         .probe          = glamo_probe,
1265         .remove         = __devexit_p(glamo_remove),
1266         .driver         = {
1267                 .name   = "glamo3362",
1268                 .owner  = THIS_MODULE,
1269                 .pm     = GLAMO_PM_OPS,
1270         },
1271 };
1272
1273 static int __devinit glamo_init(void)
1274 {
1275         return platform_driver_register(&glamo_driver);
1276 }
1277 module_init(glamo_init);
1278
1279 static void __exit glamo_exit(void)
1280 {
1281         platform_driver_unregister(&glamo_driver);
1282 }
1283 module_exit(glamo_exit);
1284
1285 MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
1286 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1287 MODULE_DESCRIPTION("Smedia Glamo 3362 core/resource driver");
1288 MODULE_LICENSE("GPL");
1289 MODULE_ALIAS("platform:glamo3362");