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[kernel.git] / drivers / mfd / glamo / glamo-core.c
1 /* Smedia Glamo 3362 driver
2  *
3  * (C) 2007 by Openmoko, Inc.
4  * Author: Harald Welte <laforge@openmoko.org>
5  * (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
6  * All rights reserved.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/errno.h>
27 #include <linux/string.h>
28 #include <linux/mm.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/irq.h>
32 #include <linux/interrupt.h>
33 #include <linux/workqueue.h>
34 #include <linux/platform_device.h>
35 #include <linux/kernel_stat.h>
36 #include <linux/spinlock.h>
37 #include <linux/mfd/core.h>
38 #include <linux/mfd/glamo.h>
39 #include <linux/io.h>
40 #include <linux/slab.h>
41
42 #include <linux/pm.h>
43
44 #include "glamo-regs.h"
45 #include "glamo-core.h"
46
47 #define GLAMO_MEM_REFRESH_COUNT 0x100
48
49 #define GLAMO_NR_IRQS 9
50
51 #define GLAMO_IRQ_HOSTBUS       0
52 #define GLAMO_IRQ_JPEG          1
53 #define GLAMO_IRQ_MPEG          2
54 #define GLAMO_IRQ_MPROC1        3
55 #define GLAMO_IRQ_MPROC0        4
56 #define GLAMO_IRQ_CMDQUEUE      5
57 #define GLAMO_IRQ_2D            6
58 #define GLAMO_IRQ_MMC           7
59 #define GLAMO_IRQ_RISC          8
60
61 /*
62  * Glamo internal settings
63  *
64  * We run the memory interface from the faster PLLB on 2.6.28 kernels and
65  * above.  Couple of GTA02 users report trouble with memory bus when they
66  * upgraded from 2.6.24.  So this parameter allows reversion to 2.6.24
67  * scheme if their Glamo chip needs it.
68  *
69  * you can override the faster default on kernel commandline using
70  *
71  *   glamo3362.slow_memory=1
72  *
73  * for example
74  */
75
76 static int slow_memory;
77 module_param(slow_memory, int, 0644);
78
79 struct reg_range {
80         int start;
81         int count;
82         char *name;
83         unsigned dump:1;
84 };
85
86 static const struct reg_range reg_range[] = {
87         { 0x0000, 0x76,         "General",      1 },
88         { 0x0200, 0x18,         "Host Bus",     1 },
89         { 0x0300, 0x38,         "Memory",       1 },
90 /*      { 0x0400, 0x100,        "Sensor",       0 }, */
91 /*      { 0x0500, 0x300,        "ISP",          0 }, */
92 /*      { 0x0800, 0x400,        "JPEG",         0 }, */
93 /*      { 0x0c00, 0xcc,         "MPEG",         0 }, */
94         { 0x1100, 0xb2,         "LCD 1",        0 },
95         { 0x1200, 0x64,         "LCD 2",        0 },
96         { 0x1400, 0x42,         "MMC",          0 },
97 /*      { 0x1500, 0x080,        "MPU 0",        0 },
98         { 0x1580, 0x080,        "MPU 1",        0 },
99         { 0x1600, 0x080,        "Cmd Queue",    0 },
100         { 0x1680, 0x080,        "RISC CPU",     0 },*/
101         { 0x1700, 0x400,        "2D Unit",      0 },
102 /*      { 0x1b00, 0x900,        "3D Unit",      0 }, */
103 };
104
105 static inline void __reg_write(struct glamo_core *glamo,
106                                 uint16_t reg, uint16_t val)
107 {
108         writew(val, glamo->base + reg);
109 }
110
111 void glamo_reg_write(struct glamo_core *glamo,
112                                 uint16_t reg, uint16_t val)
113 {
114         spin_lock(&glamo->lock);
115         __reg_write(glamo, reg, val);
116         spin_unlock(&glamo->lock);
117 }
118 EXPORT_SYMBOL_GPL(glamo_reg_write);
119
120
121 static inline uint16_t __reg_read(struct glamo_core *glamo,
122                                         uint16_t reg)
123 {
124         return readw(glamo->base + reg);
125 }
126
127 uint16_t glamo_reg_read(struct glamo_core *glamo, uint16_t reg)
128 {
129         uint16_t val;
130         spin_lock(&glamo->lock);
131         val = __reg_read(glamo, reg);
132         spin_unlock(&glamo->lock);
133
134         return val;
135 }
136 EXPORT_SYMBOL_GPL(glamo_reg_read);
137
138 static void __reg_set_bit_mask(struct glamo_core *glamo,
139                                 uint16_t reg, uint16_t mask,
140                                 uint16_t val)
141 {
142         uint16_t tmp;
143
144         val &= mask;
145
146         tmp = __reg_read(glamo, reg);
147         tmp &= ~mask;
148         tmp |= val;
149         __reg_write(glamo, reg, tmp);
150 }
151
152 static void reg_set_bit_mask(struct glamo_core *glamo,
153                                 uint16_t reg, uint16_t mask,
154                                 uint16_t val)
155 {
156         spin_lock(&glamo->lock);
157         __reg_set_bit_mask(glamo, reg, mask, val);
158         spin_unlock(&glamo->lock);
159 }
160
161 static inline void __reg_set_bit(struct glamo_core *glamo,
162                                  uint16_t reg, uint16_t bit)
163 {
164         uint16_t tmp;
165         tmp = __reg_read(glamo, reg);
166         tmp |= bit;
167         __reg_write(glamo, reg, tmp);
168 }
169
170 static inline void __reg_clear_bit(struct glamo_core *glamo,
171                                         uint16_t reg, uint16_t bit)
172 {
173         uint16_t tmp;
174         tmp = __reg_read(glamo, reg);
175         tmp &= ~bit;
176         __reg_write(glamo, reg, tmp);
177 }
178
179 static void __reg_write_batch(struct glamo_core *glamo, uint16_t reg,
180                                 uint16_t count, uint16_t *values)
181 {
182         uint16_t end;
183         for (end = reg + count * 2; reg < end; reg += 2, ++values)
184                 __reg_write(glamo, reg, *values);
185 }
186
187 static void __reg_read_batch(struct glamo_core *glamo, uint16_t reg,
188                                 uint16_t count, uint16_t *values)
189 {
190         uint16_t end;
191         for (end = reg + count * 2; reg < end; reg += 2, ++values)
192                 *values = __reg_read(glamo, reg);
193 }
194
195 void glamo_reg_write_batch(struct glamo_core *glamo, uint16_t reg,
196                                 uint16_t count, uint16_t *values)
197 {
198         spin_lock(&glamo->lock);
199         __reg_write_batch(glamo, reg, count, values);
200         spin_unlock(&glamo->lock);
201 }
202 EXPORT_SYMBOL(glamo_reg_write_batch);
203
204 void glamo_reg_read_batch(struct glamo_core *glamo, uint16_t reg,
205                                 uint16_t count, uint16_t *values)
206 {
207         spin_lock(&glamo->lock);
208         __reg_read_batch(glamo, reg, count, values);
209         spin_unlock(&glamo->lock);
210 }
211 EXPORT_SYMBOL(glamo_reg_read_batch);
212
213 /***********************************************************************
214  * resources of sibling devices
215  ***********************************************************************/
216
217 static struct resource glamo_fb_resources[] = {
218         {
219                 .name   = "glamo-fb-regs",
220                 .start  = GLAMO_REGOFS_LCD,
221                 .end    = GLAMO_REGOFS_MMC - 1,
222                 .flags  = IORESOURCE_MEM,
223         }, {
224                 .name   = "glamo-fb-mem",
225                 .start  = GLAMO_MEM_BASE + GLAMO_OFFSET_FB,
226                 .end    = GLAMO_MEM_BASE + GLAMO_OFFSET_FB + GLAMO_FB_SIZE - 1,
227                 .flags  = IORESOURCE_MEM,
228         }, {
229                 .name   = "glamo-cmdq-regs",
230                 .start  = GLAMO_REGOFS_CMDQUEUE,
231                 .end    = GLAMO_REGOFS_RISC - 1,
232                 .flags  = IORESOURCE_MEM,
233         }, {
234                 .name   = "glamo-2d-regs",
235                 .start  = GLAMO_REGOFS_2D,
236                 .end    = GLAMO_REGOFS_3D- 1,
237                 .flags  = IORESOURCE_MEM,
238         }, {
239                 .name   = "glamo-2d-irq",
240                 .start  = GLAMO_IRQ_2D,
241                 .end    = GLAMO_IRQ_2D,
242                 .flags  = IORESOURCE_IRQ,
243         }
244 };
245
246 static struct resource glamo_mmc_resources[] = {
247         {
248                 .name   = "glamo-mmc-regs",
249                 .start  = GLAMO_REGOFS_MMC,
250                 .end    = GLAMO_REGOFS_MPROC0 - 1,
251                 .flags  = IORESOURCE_MEM
252         }, {
253                 .name   = "glamo-mmc-mem",
254                 .start  = GLAMO_MEM_BASE + GLAMO_OFFSET_MMC,
255                 .end    = GLAMO_MEM_BASE + GLAMO_OFFSET_MMC
256                                          + GLAMO_MMC_BUFFER_SIZE - 1,
257                 .flags  = IORESOURCE_MEM
258         }, {
259                 .start  = GLAMO_IRQ_MMC,
260                 .end    = GLAMO_IRQ_MMC,
261                 .flags  = IORESOURCE_IRQ,
262         },
263 };
264
265 enum glamo_cells {
266         GLAMO_CELL_FB,
267         GLAMO_CELL_MMC,
268         GLAMO_CELL_GPIO,
269 };
270
271 static const struct mfd_cell glamo_cells[] = {
272         [GLAMO_CELL_FB] = {
273                 .name = "glamo-fb",
274                 .num_resources = ARRAY_SIZE(glamo_fb_resources),
275                 .resources = glamo_fb_resources,
276         },
277         [GLAMO_CELL_MMC] = {
278                 .name = "glamo-mci",
279                 .num_resources = ARRAY_SIZE(glamo_mmc_resources),
280                 .resources = glamo_mmc_resources,
281         },
282         [GLAMO_CELL_GPIO] = {
283                 .name = "glamo-gpio",
284         },
285 };
286
287 /***********************************************************************
288  * IRQ demultiplexer
289  ***********************************************************************/
290 #define glamo_irq_bit(glamo, x) BIT(x - glamo->irq_base)
291
292 static inline struct glamo_core *irq_to_glamo(unsigned int irq)
293 {
294         return (struct glamo_core *)get_irq_chip_data(irq);
295 }
296
297 static void glamo_ack_irq(unsigned int irq)
298 {
299         struct glamo_core *glamo = irq_to_glamo(irq);
300         /* clear interrupt source */
301         __reg_write(glamo, GLAMO_REG_IRQ_CLEAR, glamo_irq_bit(glamo, irq));
302 }
303
304 static void glamo_mask_irq(unsigned int irq)
305 {
306         struct glamo_core *glamo = irq_to_glamo(irq);
307
308         /* clear bit in enable register */
309         __reg_clear_bit(glamo, GLAMO_REG_IRQ_ENABLE, glamo_irq_bit(glamo, irq));
310 }
311
312 static void glamo_unmask_irq(unsigned int irq)
313 {
314         struct glamo_core *glamo = irq_to_glamo(irq);
315
316         /* set bit in enable register */
317         __reg_set_bit(glamo, GLAMO_REG_IRQ_ENABLE, glamo_irq_bit(glamo, irq));
318 }
319
320 static struct irq_chip glamo_irq_chip = {
321         .name   = "glamo",
322         .ack    = glamo_ack_irq,
323         .mask   = glamo_mask_irq,
324         .unmask = glamo_unmask_irq,
325 };
326
327 static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
328 {
329         struct glamo_core *glamo = get_irq_desc_data(desc);
330         desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
331
332         if (unlikely(desc->status & IRQ_INPROGRESS)) {
333                 desc->status |= (IRQ_PENDING | IRQ_MASKED);
334                 desc->chip->mask(irq);
335                 desc->chip->ack(irq);
336                 return;
337         }
338         kstat_incr_irqs_this_cpu(irq, desc);
339
340         desc->chip->ack(irq);
341         desc->status |= IRQ_INPROGRESS;
342
343         do {
344                 uint16_t irqstatus;
345                 int i;
346
347                 if (unlikely((desc->status &
348                                 (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
349                                 (IRQ_PENDING | IRQ_MASKED))) {
350                         /* dealing with pending IRQ, unmasking */
351                         desc->chip->unmask(irq);
352                         desc->status &= ~IRQ_MASKED;
353                 }
354
355                 desc->status &= ~IRQ_PENDING;
356
357                 /* read IRQ status register */
358                 irqstatus = __reg_read(glamo, GLAMO_REG_IRQ_STATUS);
359                 for (i = 0; i < 9; ++i) {
360                         if (irqstatus & BIT(i))
361                                 generic_handle_irq(glamo->irq_base + i);
362                 }
363
364         } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
365
366         desc->status &= ~IRQ_INPROGRESS;
367 }
368
369 /*
370 sysfs
371 */
372
373 static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
374                                 const char *buf, size_t count)
375 {
376         struct glamo_core *glamo = dev_get_drvdata(dev);
377         unsigned int reg;
378         unsigned int val;
379
380         sscanf(buf, "%u %u", &reg, &val);
381         printk(KERN_INFO"reg 0x%02x <-- 0x%04x\n",
382                 reg, val);
383
384         glamo_reg_write(glamo, reg, val);
385
386         return count;
387 }
388
389 static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
390                         char *buf)
391 {
392         struct glamo_core *glamo = dev_get_drvdata(dev);
393         int i, n;
394         char *end = buf;
395         const struct reg_range *rr = reg_range;
396
397         spin_lock(&glamo->lock);
398
399         for (i = 0; i < ARRAY_SIZE(reg_range); ++i, ++rr) {
400                 if (!rr->dump)
401                         continue;
402                 end += sprintf(end, "\n%s\n", rr->name);
403                 for (n = rr->start; n < rr->start + rr->count; n += 2) {
404                         if ((n & 15) == 0)
405                                 end += sprintf(end, "\n%04X:  ", n);
406                         end += sprintf(end, "%04x ", __reg_read(glamo, n));
407                 }
408                 end += sprintf(end, "\n");
409         }
410         spin_unlock(&glamo->lock);
411
412         return end - buf;
413 }
414
415 static DEVICE_ATTR(regs, 0644, regs_read, regs_write);
416
417 struct glamo_engine_reg_set {
418         uint16_t reg;
419         uint16_t mask_suspended;
420         uint16_t mask_enabled;
421 };
422
423 struct glamo_engine_desc {
424         const char *name;
425         uint16_t hostbus;
426         const struct glamo_engine_reg_set *regs;
427         int num_regs;
428 };
429
430 static const struct glamo_engine_reg_set glamo_lcd_regs[] = {
431         { GLAMO_REG_CLOCK_LCD,
432         GLAMO_CLOCK_LCD_EN_M5CLK |
433         GLAMO_CLOCK_LCD_DG_M5CLK |
434         GLAMO_CLOCK_LCD_EN_DMCLK,
435
436         GLAMO_CLOCK_LCD_EN_DHCLK |
437         GLAMO_CLOCK_LCD_EN_DCLK
438         },
439         { GLAMO_REG_CLOCK_GEN5_1,
440         GLAMO_CLOCK_GEN51_EN_DIV_DMCLK,
441
442         GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
443         GLAMO_CLOCK_GEN51_EN_DIV_DCLK
444         }
445 };
446
447 static const struct glamo_engine_reg_set glamo_mmc_regs[] = {
448         { GLAMO_REG_CLOCK_MMC,
449         GLAMO_CLOCK_MMC_EN_M9CLK |
450         GLAMO_CLOCK_MMC_DG_M9CLK,
451
452         GLAMO_CLOCK_MMC_EN_TCLK |
453         GLAMO_CLOCK_MMC_DG_TCLK
454         },
455         { GLAMO_REG_CLOCK_GEN5_1,
456         0,
457         GLAMO_CLOCK_GEN51_EN_DIV_TCLK
458         }
459 };
460
461 static const struct glamo_engine_reg_set glamo_2d_regs[] = {
462         { GLAMO_REG_CLOCK_2D,
463         GLAMO_CLOCK_2D_EN_M7CLK |
464         GLAMO_CLOCK_2D_DG_M7CLK,
465
466         GLAMO_CLOCK_2D_EN_GCLK |
467         GLAMO_CLOCK_2D_DG_GCLK
468         },
469         { GLAMO_REG_CLOCK_GEN5_1,
470         0,
471         GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
472         }
473 };
474
475 static const struct glamo_engine_reg_set glamo_3d_regs[] = {
476         { GLAMO_REG_CLOCK_3D,
477         GLAMO_CLOCK_3D_EN_M8CLK |
478         GLAMO_CLOCK_3D_DG_M8CLK,
479
480         GLAMO_CLOCK_3D_EN_ECLK |
481         GLAMO_CLOCK_3D_DG_ECLK,
482
483         GLAMO_CLOCK_3D_EN_RCLK |
484         GLAMO_CLOCK_3D_DG_RCLK
485         },
486         { GLAMO_REG_CLOCK_GEN5_1,
487         0,
488         GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
489         }
490 };
491
492 static const struct glamo_engine_reg_set glamo_cmdq_regs[] = {
493         { GLAMO_REG_CLOCK_2D,
494         GLAMO_CLOCK_2D_EN_M6CLK,
495         0
496         },
497 };
498
499 #define GLAMO_ENGINE(xname, xhostbus, xregs) { \
500         .name = xname, \
501         .hostbus = xhostbus, \
502         .num_regs = ARRAY_SIZE(xregs), \
503         .regs = xregs, \
504 }
505
506 static const struct glamo_engine_desc glamo_engines[] = {
507         [GLAMO_ENGINE_LCD] = GLAMO_ENGINE("LCD", GLAMO_HOSTBUS2_MMIO_EN_LCD,
508                                         glamo_lcd_regs),
509         [GLAMO_ENGINE_MMC] = GLAMO_ENGINE("MMC", GLAMO_HOSTBUS2_MMIO_EN_MMC,
510                                         glamo_mmc_regs),
511         [GLAMO_ENGINE_2D] = GLAMO_ENGINE("2D", GLAMO_HOSTBUS2_MMIO_EN_2D,
512                                         glamo_2d_regs),
513         [GLAMO_ENGINE_3D] = GLAMO_ENGINE("3D", GLAMO_HOSTBUS2_MMIO_EN_3D,
514                                         glamo_3d_regs),
515         [GLAMO_ENGINE_CMDQ] = GLAMO_ENGINE("CMDQ", GLAMO_HOSTBUS2_MMIO_EN_CQ,
516                                         glamo_cmdq_regs),
517 };
518
519 static inline const char *glamo_engine_name(enum glamo_engine engine)
520 {
521         return glamo_engines[engine].name;
522 }
523
524 /***********************************************************************
525  * 'engine' support
526  ***********************************************************************/
527
528 int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
529 {
530         int i;
531         const struct glamo_engine_desc *engine_desc = &glamo_engines[engine];
532         const struct glamo_engine_reg_set *reg;
533
534         switch (engine) {
535         case GLAMO_ENGINE_LCD:
536         case GLAMO_ENGINE_MMC:
537         case GLAMO_ENGINE_2D:
538         case GLAMO_ENGINE_3D:
539         case GLAMO_ENGINE_CMDQ:
540                 break;
541         default:
542                 return -EINVAL;
543         }
544
545         reg = engine_desc->regs;
546
547         __reg_set_bit(glamo, GLAMO_REG_HOSTBUS(2),
548                         engine_desc->hostbus);
549         for (i = engine_desc->num_regs; i; --i, ++reg)
550                 __reg_set_bit(glamo, reg->reg,
551                                 reg->mask_suspended | reg->mask_enabled);
552
553         return 0;
554 }
555
556 int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
557 {
558         int ret = 0;
559
560         spin_lock(&glamo->lock);
561
562         if (glamo->engine_state[engine] != GLAMO_ENGINE_ENABLED) {
563                 ret = __glamo_engine_enable(glamo, engine);
564                 if (!ret)
565                         glamo->engine_state[engine] = GLAMO_ENGINE_ENABLED;
566         }
567
568         spin_unlock(&glamo->lock);
569
570         return ret;
571 }
572 EXPORT_SYMBOL_GPL(glamo_engine_enable);
573
574 int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
575 {
576         int i;
577         const struct glamo_engine_desc *engine_desc = &glamo_engines[engine];
578         const struct glamo_engine_reg_set *reg;
579
580         switch (engine) {
581         case GLAMO_ENGINE_LCD:
582         case GLAMO_ENGINE_MMC:
583         case GLAMO_ENGINE_2D:
584         case GLAMO_ENGINE_CMDQ:
585         case GLAMO_ENGINE_3D:
586                 break;
587         default:
588                 return -EINVAL;
589         }
590
591         reg = engine_desc->regs;
592
593         __reg_clear_bit(glamo, GLAMO_REG_HOSTBUS(2),
594                         engine_desc->hostbus);
595         for (i = engine_desc->num_regs; i; --i, ++reg)
596                 __reg_clear_bit(glamo, reg->reg,
597                                 reg->mask_suspended | reg->mask_enabled);
598
599         return 0;
600 }
601 int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
602 {
603         int ret = 0;
604
605         spin_lock(&glamo->lock);
606
607         if (glamo->engine_state[engine] != GLAMO_ENGINE_DISABLED) {
608                 ret = __glamo_engine_disable(glamo, engine);
609                 if (!ret)
610                         glamo->engine_state[engine] = GLAMO_ENGINE_DISABLED;
611         }
612
613         spin_unlock(&glamo->lock);
614
615         return ret;
616 }
617 EXPORT_SYMBOL_GPL(glamo_engine_disable);
618
619 int __glamo_engine_suspend(struct glamo_core *glamo, enum glamo_engine engine)
620 {
621         int i;
622         const struct glamo_engine_desc *engine_desc = &glamo_engines[engine];
623         const struct glamo_engine_reg_set *reg;
624
625         switch (engine) {
626         case GLAMO_ENGINE_LCD:
627         case GLAMO_ENGINE_MMC:
628         case GLAMO_ENGINE_2D:
629         case GLAMO_ENGINE_CMDQ:
630                 break;
631         default:
632                 return -EINVAL;
633         }
634
635         reg = engine_desc->regs;
636
637         __reg_set_bit(glamo, GLAMO_REG_HOSTBUS(2),
638                         engine_desc->hostbus);
639         for (i = engine_desc->num_regs; i; --i, ++reg) {
640                 __reg_set_bit(glamo, reg->reg, reg->mask_suspended);
641                 __reg_clear_bit(glamo, reg->reg, reg->mask_enabled);
642         }
643
644         return 0;
645 }
646
647 int glamo_engine_suspend(struct glamo_core *glamo, enum glamo_engine engine)
648 {
649         int ret = 0;
650
651         spin_lock(&glamo->lock);
652
653         if (glamo->engine_state[engine] != GLAMO_ENGINE_SUSPENDED) {
654                 ret = __glamo_engine_suspend(glamo, engine);
655                 if (!ret)
656                         glamo->engine_state[engine] = GLAMO_ENGINE_SUSPENDED;
657         }
658
659         spin_unlock(&glamo->lock);
660
661         return ret;
662 }
663 EXPORT_SYMBOL_GPL(glamo_engine_suspend);
664
665 static const struct glamo_script reset_regs[] = {
666         [GLAMO_ENGINE_LCD] = {
667                 GLAMO_REG_CLOCK_LCD, GLAMO_CLOCK_LCD_RESET
668         },
669         [GLAMO_ENGINE_MMC] = {
670                 GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
671         },
672         [GLAMO_ENGINE_CMDQ] = {
673                 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_CQ_RESET
674         },
675         [GLAMO_ENGINE_2D] = {
676                 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
677         },
678         [GLAMO_ENGINE_3D] = {
679                 GLAMO_REG_CLOCK_3D, GLAMO_CLOCK_3D_BACK_RESET |
680                                     GLAMO_CLOCK_3D_FRONT_RESET
681         },
682         [GLAMO_ENGINE_JPEG] = {
683                 GLAMO_REG_CLOCK_JPEG, GLAMO_CLOCK_JPEG_RESET
684         },
685 };
686
687 void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
688 {
689         uint16_t reg = reset_regs[engine].reg;
690         uint16_t val = reset_regs[engine].val;
691
692         if (engine >= ARRAY_SIZE(reset_regs)) {
693                 dev_warn(&glamo->pdev->dev, "unknown engine %u ", engine);
694                 return;
695         }
696
697         spin_lock(&glamo->lock);
698         __reg_set_bit(glamo, reg, val);
699         __reg_clear_bit(glamo, reg, val);
700         spin_unlock(&glamo->lock);
701 }
702 EXPORT_SYMBOL_GPL(glamo_engine_reset);
703
704 int glamo_pll_rate(struct glamo_core *glamo,
705                           enum glamo_pll pll)
706 {
707         uint16_t reg;
708         unsigned int osci = glamo->pdata->osci_clock_rate;
709
710         switch (pll) {
711         case GLAMO_PLL1:
712                 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
713                 break;
714         case GLAMO_PLL2:
715                 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
716                 break;
717         default:
718                 return -EINVAL;
719         }
720
721         return (int)osci * (int)reg;
722 }
723 EXPORT_SYMBOL_GPL(glamo_pll_rate);
724
725 int glamo_engine_reclock(struct glamo_core *glamo,
726                          enum glamo_engine engine,
727                          int hz)
728 {
729         int pll;
730         uint16_t reg, mask, div;
731
732         if (!hz)
733                 return -EINVAL;
734
735         switch (engine) {
736         case GLAMO_ENGINE_LCD:
737                 pll = GLAMO_PLL1;
738                 reg = GLAMO_REG_CLOCK_GEN7;
739                 mask = 0xff;
740                 break;
741         case GLAMO_ENGINE_MMC:
742                 pll = GLAMO_PLL1;
743                 reg = GLAMO_REG_CLOCK_GEN8;
744                 mask = 0xff;
745                 break;
746         default:
747                 dev_warn(&glamo->pdev->dev,
748                          "reclock of engine 0x%x not supported\n", engine);
749                 return -EINVAL;
750                 break;
751         }
752
753         pll = glamo_pll_rate(glamo, pll);
754
755         div = pll / hz;
756
757         if (div != 0 && pll / div <= hz)
758                 --div;
759
760         if (div > mask)
761                 div = mask;
762
763         dev_dbg(&glamo->pdev->dev,
764                         "PLL %d, kHZ %d, div %d\n", pll, hz / 1000, div);
765
766         reg_set_bit_mask(glamo, reg, mask, div);
767         mdelay(5); /* wait some time to stabilize */
768
769         return pll / (div + 1);
770 }
771 EXPORT_SYMBOL_GPL(glamo_engine_reclock);
772
773 /***********************************************************************
774  * script support
775  ***********************************************************************/
776
777 #define GLAMO_SCRIPT_END        0xffff
778 #define GLAMO_SCRIPT_WAIT       0xfffe
779 #define GLAMO_SCRIPT_LOCK_PLL   0xfffd
780
781 /*
782  * couple of people reported artefacts with 2.6.28 changes, this
783  * allows reversion to 2.6.24 settings
784 */
785 static const uint16_t reg_0x200[] = {
786 0xe03, /* 0 waits on Async BB R & W, Use PLL 2 for mem bus */
787 0xef0, /* 3 waits on Async BB R & W, Use PLL 1 for mem bus */
788 0xea0, /* 2 waits on Async BB R & W, Use PLL 1 for mem bus */
789 0xe50, /* 1 waits on Async BB R & W, Use PLL 1 for mem bus */
790 0xe00, /* 0 waits on Async BB R & W, Use PLL 1 for mem bus */
791 0xef3, /* 3 waits on Async BB R & W, Use PLL 2 for mem bus */
792 0xea3, /* 2 waits on Async BB R & W, Use PLL 2 for mem bus */
793 0xe53, /* 1 waits on Async BB R & W, Use PLL 2 for mem bus */
794 };
795
796 static int glamo_run_script(struct glamo_core *glamo,
797                                 const struct glamo_script *script, int len,
798                                 int may_sleep)
799 {
800         int i;
801         uint16_t status;
802         const struct glamo_script *line = script;
803
804         for (i = 0; i < len; ++i, ++line) {
805                 switch (line->reg) {
806                 case GLAMO_SCRIPT_END:
807                         return 0;
808                 case GLAMO_SCRIPT_WAIT:
809                         if (may_sleep)
810                                 msleep(line->val);
811                         else
812                                 mdelay(line->val * 4);
813                         break;
814                 case GLAMO_SCRIPT_LOCK_PLL:
815                         /* spin until PLLs lock */
816                         do {
817                                 status = __reg_read(glamo, GLAMO_REG_PLL_GEN5);
818                         } while ((status & 3) != 3);
819                         break;
820                 case 0x200:
821                         __reg_write(glamo, line->reg,
822                                         reg_0x200[slow_memory & 0x8]);
823                         break;
824                 default:
825                         __reg_write(glamo, line->reg, line->val);
826                         break;
827                 }
828         }
829
830         return 0;
831 }
832
833 static const struct glamo_script glamo_init_script[] = {
834         { GLAMO_REG_CLOCK_HOST,         0x1000 },
835         { GLAMO_SCRIPT_WAIT,                 2 },
836         { GLAMO_REG_CLOCK_MEMORY,       0x1000 },
837         { GLAMO_REG_CLOCK_MEMORY,       0x2000 },
838         { GLAMO_REG_CLOCK_LCD,          0x1000 },
839         { GLAMO_REG_CLOCK_MMC,          0x1000 },
840         { GLAMO_REG_CLOCK_ISP,          0x1000 },
841         { GLAMO_REG_CLOCK_ISP,          0x3000 },
842         { GLAMO_REG_CLOCK_JPEG,         0x1000 },
843         { GLAMO_REG_CLOCK_3D,           0x1000 },
844         { GLAMO_REG_CLOCK_3D,           0x3000 },
845         { GLAMO_REG_CLOCK_2D,           0x1000 },
846         { GLAMO_REG_CLOCK_2D,           0x3000 },
847         { GLAMO_REG_CLOCK_RISC1,        0x1000 },
848         { GLAMO_REG_CLOCK_MPEG,         0x1000 },
849         { GLAMO_REG_CLOCK_MPEG,         0x3000 },
850         { GLAMO_REG_CLOCK_MPROC,        0x1000 /*0x100f*/ },
851         { GLAMO_SCRIPT_WAIT,                 2 },
852         { GLAMO_REG_CLOCK_HOST,         0x0000 },
853         { GLAMO_REG_CLOCK_MEMORY,       0x0000 },
854         { GLAMO_REG_CLOCK_LCD,          0x0000 },
855         { GLAMO_REG_CLOCK_MMC,          0x0000 },
856         { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
857         { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
858         { GLAMO_SCRIPT_LOCK_PLL, 0 },
859         /*
860          * b9 of this register MUST be zero to get any interrupts on INT#
861          * the other set bits enable all the engine interrupt sources
862          */
863         { GLAMO_REG_IRQ_ENABLE,         0x0100 },
864         { GLAMO_REG_CLOCK_GEN6,         0x2000 },
865         { GLAMO_REG_CLOCK_GEN7,         0x0101 },
866         { GLAMO_REG_CLOCK_GEN8,         0x0100 },
867         { GLAMO_REG_CLOCK_HOST,         0x000d },
868         /*
869          * b7..b4 = 0 = no wait states on read or write
870          * b0 = 1 select PLL2 for Host interface, b1 = enable it
871          */
872         { GLAMO_REG_HOSTBUS(0),         0x0e03 /* this is replaced by script parser */ },
873         { GLAMO_REG_HOSTBUS(1),         0x07ff }, /* TODO: Disable all */
874         { GLAMO_REG_HOSTBUS(10),        0x0000 },
875         { GLAMO_REG_HOSTBUS(11),        0x4000 },
876         { GLAMO_REG_HOSTBUS(12),        0xf00e },
877
878         /* S-Media recommended "set tiling mode to 512 mode for memory access
879          * more efficiency when 640x480" */
880         { GLAMO_REG_MEM_TYPE,           0x0c74 }, /* 8MB, 16 word pg wr+rd */
881         { GLAMO_REG_MEM_GEN,            0xafaf }, /* 63 grants min + max */
882
883         { GLAMO_REG_MEM_TIMING1,        0x0108 },
884         { GLAMO_REG_MEM_TIMING2,        0x0010 }, /* Taa = 3 MCLK */
885         { GLAMO_REG_MEM_TIMING3,        0x0000 },
886         { GLAMO_REG_MEM_TIMING4,        0x0000 }, /* CE1# delay fall/rise */
887         { GLAMO_REG_MEM_TIMING5,        0x0000 }, /* UB# LB# */
888         { GLAMO_REG_MEM_TIMING6,        0x0000 }, /* OE# */
889         { GLAMO_REG_MEM_TIMING7,        0x0000 }, /* WE# */
890         { GLAMO_REG_MEM_TIMING8,        0x1002 }, /* MCLK delay, was 0x1000 */
891         { GLAMO_REG_MEM_TIMING9,        0x6006 },
892         { GLAMO_REG_MEM_TIMING10,       0x00ff },
893         { GLAMO_REG_MEM_TIMING11,       0x0001 },
894         { GLAMO_REG_MEM_POWER1,         0x0020 },
895         { GLAMO_REG_MEM_POWER2,         0x0000 },
896         { GLAMO_REG_MEM_DRAM1,          0x0000 },
897         { GLAMO_SCRIPT_WAIT,                 1 },
898         { GLAMO_REG_MEM_DRAM1,          0xc100 },
899         { GLAMO_SCRIPT_WAIT,                 1 },
900         { GLAMO_REG_MEM_DRAM1,          0xe100 },
901         { GLAMO_REG_MEM_DRAM2,          0x01d6 },
902         { GLAMO_REG_CLOCK_MEMORY,       0x000b },
903 };
904
905 /* Find out if we can support this version of the Glamo chip */
906 static int __devinit glamo_supported(struct glamo_core *glamo)
907 {
908         uint16_t dev_id, rev_id;
909
910         dev_id = __reg_read(glamo, GLAMO_REG_DEVICE_ID);
911         rev_id = __reg_read(glamo, GLAMO_REG_REVISION_ID);
912
913         switch (dev_id) {
914         case 0x3650:
915                 switch (rev_id) {
916                 case GLAMO_CORE_REV_A2:
917                         break;
918                 case GLAMO_CORE_REV_A0:
919                 case GLAMO_CORE_REV_A1:
920                 case GLAMO_CORE_REV_A3:
921                         dev_warn(&glamo->pdev->dev, "untested core revision "
922                                  "%04x, your mileage may vary\n", rev_id);
923                         break;
924                 default:
925                         dev_warn(&glamo->pdev->dev, "unknown glamo revision "
926                                  "%04x, your mileage may vary\n", rev_id);
927                 }
928                 break;
929         default:
930                 dev_err(&glamo->pdev->dev, "unsupported Glamo device %04x\n",
931                         dev_id);
932                 return 0;
933         }
934
935         dev_dbg(&glamo->pdev->dev, "Detected Glamo core %04x Revision %04x "
936                  "(%uHz CPU / %uHz Memory)\n", dev_id, rev_id,
937                  glamo_pll_rate(glamo, GLAMO_PLL1),
938                  glamo_pll_rate(glamo, GLAMO_PLL2));
939
940         return 1;
941 }
942
943 static int __devinit glamo_probe(struct platform_device *pdev)
944 {
945         int ret = 0, irq, irq_base;
946         struct glamo_core *glamo;
947         struct resource *mem;
948
949         glamo = kmalloc(GFP_KERNEL, sizeof(*glamo));
950         if (!glamo)
951                 return -ENOMEM;
952
953         spin_lock_init(&glamo->lock);
954
955         glamo->pdev = pdev;
956         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
957         glamo->irq = platform_get_irq(pdev, 0);
958         glamo->irq_base = irq_base = platform_get_irq(pdev, 1);
959         glamo->pdata = pdev->dev.platform_data;
960
961         if (glamo->irq < 0) {
962                 ret = glamo->irq;
963                 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
964                 goto err_free;
965         }
966
967         if (irq_base < 0) {
968                 ret = glamo->irq;
969                 dev_err(&pdev->dev, "Failed to get glamo irq base: %d\n", ret);
970                 goto err_free;
971         }
972
973         if (!mem) {
974                 dev_err(&pdev->dev, "Failed to get platform memory\n");
975                 ret = -ENOENT;
976                 goto err_free;
977         }
978
979         if (!glamo->pdata) {
980                 dev_err(&pdev->dev, "Missing platform data\n");
981                 ret = -ENOENT;
982                 goto err_free;
983         }
984
985         /* only request the generic, hostbus and memory controller registers */
986         glamo->mem = request_mem_region(mem->start, GLAMO_REGOFS_VIDCAP,
987                                         pdev->name);
988
989         if (!glamo->mem) {
990                 dev_err(&pdev->dev, "Failed to request io memory region\n");
991                 ret = -ENOENT;
992                 goto err_free;
993         }
994
995         glamo->base = ioremap(glamo->mem->start, resource_size(glamo->mem));
996         if (!glamo->base) {
997                 dev_err(&pdev->dev, "Failed to ioremap() memory region\n");
998                 goto err_release_mem_region;
999         }
1000
1001         /* confirm it isn't insane version */
1002         if (!glamo_supported(glamo)) {
1003                 dev_err(&pdev->dev,
1004                         "This version of the Glamo is not supported\n");
1005                 goto err_iounmap;
1006         }
1007
1008         platform_set_drvdata(pdev, glamo);
1009
1010         /* sysfs */
1011         ret = device_create_file(&pdev->dev, &dev_attr_regs);
1012         if (ret < 0) {
1013                 dev_err(&pdev->dev, "Failed to create sysfs file\n");
1014                 goto err_iounmap;
1015         }
1016
1017         /* init the chip with canned register set */
1018         glamo_run_script(glamo, glamo_init_script,
1019                          ARRAY_SIZE(glamo_init_script), 1);
1020
1021         /*
1022          * finally set the mfd interrupts up
1023          */
1024         for (irq = irq_base; irq < irq_base + GLAMO_NR_IRQS; ++irq) {
1025 #ifdef CONFIG_ARM
1026                 set_irq_flags(irq, IRQF_VALID);
1027 #else
1028                 set_irq_noprobe(irq);
1029 #endif
1030                 set_irq_chip_data(irq, glamo);
1031                 set_irq_chip_and_handler(irq, &glamo_irq_chip,
1032                                         handle_level_irq);
1033         }
1034
1035         set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING);
1036         set_irq_data(glamo->irq, glamo);
1037         set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
1038         glamo->irq_works = 1;
1039
1040         ret = mfd_add_devices(&pdev->dev, pdev->id, glamo_cells,
1041                                 ARRAY_SIZE(glamo_cells), mem, glamo->irq_base);
1042
1043         if (ret) {
1044                 dev_err(&pdev->dev, "Failed to add child devices: %d\n", ret);
1045                 goto err_free_irqs;
1046         }
1047
1048         dev_info(&glamo->pdev->dev, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
1049                  glamo_pll_rate(glamo, GLAMO_PLL1),
1050                  glamo_pll_rate(glamo, GLAMO_PLL2));
1051
1052         return 0;
1053
1054 err_free_irqs:
1055         disable_irq(glamo->irq);
1056         set_irq_chained_handler(glamo->irq, NULL);
1057         set_irq_chip_data(glamo->irq, NULL);
1058
1059         for (irq = irq_base; irq < irq_base + GLAMO_NR_IRQS; ++irq) {
1060                 set_irq_chip(irq, NULL);
1061 #ifdef CONFIG_ARM
1062                 set_irq_flags(irq, 0);
1063 #else
1064                 set_irq_probe(irq);
1065 #endif
1066                 set_irq_chip_data(irq, NULL);
1067         }
1068 err_iounmap:
1069         iounmap(glamo->base);
1070 err_release_mem_region:
1071         release_mem_region(glamo->mem->start, resource_size(glamo->mem));
1072 err_free:
1073         platform_set_drvdata(pdev, NULL);
1074         kfree(glamo);
1075
1076         return ret;
1077 }
1078
1079 static int __devexit glamo_remove(struct platform_device *pdev)
1080 {
1081         struct glamo_core *glamo = platform_get_drvdata(pdev);
1082         int irq;
1083         int irq_base = glamo->irq_base;
1084
1085         mfd_remove_devices(&pdev->dev);
1086
1087         disable_irq(glamo->irq);
1088         set_irq_chained_handler(glamo->irq, NULL);
1089         set_irq_chip_data(glamo->irq, NULL);
1090
1091         for (irq = irq_base; irq < irq_base + GLAMO_NR_IRQS; ++irq) {
1092 #ifdef CONFIG_ARM
1093                 set_irq_flags(irq, 0);
1094 #else
1095                 set_irq_noprobe();
1096 #endif
1097                 set_irq_chip(irq, NULL);
1098                 set_irq_chip_data(irq, NULL);
1099         }
1100
1101         platform_set_drvdata(pdev, NULL);
1102         iounmap(glamo->base);
1103         release_mem_region(glamo->mem->start, resource_size(glamo->mem));
1104         kfree(glamo);
1105
1106         return 0;
1107 }
1108
1109 #ifdef CONFIG_PM
1110 #if 0
1111 static struct glamo_script glamo_resume_script[] = {
1112
1113         { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
1114         { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
1115         { GLAMO_REG_DFT_GEN6, 1 },
1116                 { 0xfffe, 100 },
1117                 { 0xfffd, 0 },
1118         { 0x200,        0x0e03 },
1119
1120         /*
1121          * b9 of this register MUST be zero to get any interrupts on INT#
1122          * the other set bits enable all the engine interrupt sources
1123          */
1124         { GLAMO_REG_IRQ_ENABLE,         0x01ff },
1125         { GLAMO_REG_CLOCK_HOST,         0x0018 },
1126         { GLAMO_REG_CLOCK_GEN5_1, 0x18b1 },
1127
1128         { GLAMO_REG_MEM_DRAM1,          0x0000 },
1129                 { 0xfffe, 1 },
1130         { GLAMO_REG_MEM_DRAM1,          0xc100 },
1131                 { 0xfffe, 1 },
1132         { GLAMO_REG_MEM_DRAM1,          0xe100 },
1133         { GLAMO_REG_MEM_DRAM2,          0x01d6 },
1134         { GLAMO_REG_CLOCK_MEMORY,       0x000b },
1135 };
1136 #endif
1137
1138 #if 0
1139 static void glamo_power(struct glamo_core *glamo)
1140 {
1141         unsigned long flags;
1142
1143         spin_lock_irqsave(&glamo->lock, flags);
1144
1145         /*
1146 Power management
1147 static const REG_VALUE_MASK_TYPE reg_powerOn[] =
1148 {
1149         { REG_GEN_DFT6,     REG_BIT_ALL,    REG_DATA(1u << 0)           },
1150         { REG_GEN_PLL3,     0u,             REG_DATA(1u << 13)          },
1151         { REG_GEN_MEM_CLK,  REG_BIT_ALL,    REG_BIT_EN_MOCACLK          },
1152         { REG_MEM_DRAM2,    0u,             REG_BIT_EN_DEEP_POWER_DOWN  },
1153         { REG_MEM_DRAM1,    0u,             REG_BIT_SELF_REFRESH        }
1154 };
1155
1156 static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
1157 {
1158         { REG_MEM_DRAM1,    REG_BIT_ALL,    REG_BIT_SELF_REFRESH    },
1159         { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK      },
1160         { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)      },
1161         { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)       }
1162 };
1163
1164 static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
1165 {
1166         { REG_MEM_DRAM2,    REG_BIT_ALL,    REG_BIT_EN_DEEP_POWER_DOWN  },
1167         { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK          },
1168         { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)          },
1169         { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)           }
1170 };
1171 */
1172         switch (new_state) {
1173         case GLAMO_POWER_ON:
1174
1175                 /*
1176                  * glamo state on resume is nondeterministic in some
1177                  * fundamental way, it has also been observed that the
1178                  * Glamo reset pin can get asserted by, eg, touching it with
1179                  * a scope probe.  So the only answer is to roll with it and
1180                  * force an external reset on the Glamo during resume.
1181                  */
1182
1183
1184                 break;
1185
1186         case GLAMO_POWER_SUSPEND:
1187
1188                 break;
1189         }
1190         spin_unlock_irqrestore(&glamo->lock, flags);
1191 }
1192 #endif
1193
1194 static int glamo_suspend(struct device *dev)
1195 {
1196         struct glamo_core *glamo = dev_get_drvdata(dev);
1197         int n;
1198
1199         spin_lock(&glamo->lock);
1200
1201         glamo->saved_irq_mask = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE);
1202
1203         /* nuke interrupts */
1204         __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, 0x200);
1205
1206         /* take down each engine before we kill mem and pll */
1207         for (n = 0; n < __NUM_GLAMO_ENGINES; n++) {
1208                 if (glamo->engine_state != GLAMO_ENGINE_DISABLED)
1209                         __glamo_engine_disable(glamo, n);
1210         }
1211
1212         /* enable self-refresh */
1213
1214         __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
1215                                 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
1216                                 GLAMO_MEM_DRAM1_EN_GATE_CKE |
1217                                 GLAMO_MEM_DRAM1_SELF_REFRESH |
1218                                 GLAMO_MEM_REFRESH_COUNT);
1219         __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
1220                                 GLAMO_MEM_DRAM1_EN_MODEREG_SET |
1221                                 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
1222                                 GLAMO_MEM_DRAM1_EN_GATE_CKE |
1223                                 GLAMO_MEM_DRAM1_SELF_REFRESH |
1224                                 GLAMO_MEM_REFRESH_COUNT);
1225
1226         /* force RAM into deep powerdown */
1227         __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
1228                                 GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
1229                                 (7 << 6) | /* tRC */
1230                                 (1 << 4) | /* tRP */
1231                                 (1 << 2) | /* tRCD */
1232                                 2); /* CAS latency */
1233
1234         /* disable clocks to memory */
1235         __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
1236
1237         /* all dividers from OSCI */
1238         __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0x400, 0x400);
1239
1240         /* PLL2 into bypass */
1241         __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 12, 1 << 12);
1242
1243         __reg_write(glamo, GLAMO_BASIC_MMC_EN_TCLK_DLYA1, 0x0e00);
1244
1245         /* kill PLLS 1 then 2 */
1246         __reg_write(glamo, GLAMO_REG_DFT_GEN5, 0x0001);
1247         __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 13, 1 << 13);
1248
1249         spin_unlock(&glamo->lock);
1250
1251         return 0;
1252 }
1253
1254 static int glamo_resume(struct device *dev)
1255 {
1256         struct glamo_core *glamo = dev_get_drvdata(dev);
1257         int n;
1258
1259         (glamo->pdata->glamo_external_reset)(0);
1260         udelay(10);
1261         (glamo->pdata->glamo_external_reset)(1);
1262         mdelay(5);
1263
1264         spin_lock(&glamo->lock);
1265
1266         glamo_run_script(glamo, glamo_init_script,
1267                          ARRAY_SIZE(glamo_init_script), 0);
1268
1269
1270         for (n = 0; n < __NUM_GLAMO_ENGINES; n++) {
1271                 switch (glamo->engine_state[n]) {
1272                 case GLAMO_ENGINE_SUSPENDED:
1273                         __glamo_engine_suspend(glamo, n);
1274                         break;
1275                 case GLAMO_ENGINE_ENABLED:
1276                         __glamo_engine_enable(glamo, n);
1277                         break;
1278                 default:
1279                         break;
1280                 }
1281         }
1282
1283         __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, glamo->saved_irq_mask);
1284
1285         spin_unlock(&glamo->lock);
1286
1287         return 0;
1288 }
1289
1290 static struct dev_pm_ops glamo_pm_ops = {
1291         .suspend    = glamo_suspend,
1292         .resume     = glamo_resume,
1293         .poweroff   = glamo_suspend,
1294         .restore    = glamo_resume,
1295 };
1296
1297 #define GLAMO_PM_OPS (&glamo_pm_ops)
1298
1299 #else
1300 #define GLAMO_PM_OPS NULL
1301 #endif
1302
1303 static struct platform_driver glamo_driver = {
1304         .probe          = glamo_probe,
1305         .remove         = __devexit_p(glamo_remove),
1306         .driver         = {
1307                 .name   = "glamo3362",
1308                 .owner  = THIS_MODULE,
1309                 .pm     = GLAMO_PM_OPS,
1310         },
1311 };
1312
1313 static int __devinit glamo_init(void)
1314 {
1315         return platform_driver_register(&glamo_driver);
1316 }
1317 module_init(glamo_init);
1318
1319 static void __exit glamo_exit(void)
1320 {
1321         platform_driver_unregister(&glamo_driver);
1322 }
1323 module_exit(glamo_exit);
1324
1325 MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
1326 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1327 MODULE_DESCRIPTION("Smedia Glamo 3362 core/resource driver");
1328 MODULE_LICENSE("GPL");
1329 MODULE_ALIAS("platform:glamo3362");