Add hdq and bq27000 driver.
[kernel.git] / drivers / power / hdq.c
1 /*
2  * HDQ generic GPIO bitbang driver using FIQ
3  *
4  * (C) 2006-2007 by Openmoko, Inc.
5  * Author: Andy Green <andy@openmoko.com>
6  * All rights reserved.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  */
13
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/platform_device.h>
18 #include <linux/hdq.h>
19
20 #define HDQ_READ 0
21 #define HDQ_WRITE 0x80
22
23 enum hdq_bitbang_states {
24         HDQB_IDLE = 0,
25         HDQB_TX_BREAK,
26         HDQB_TX_BREAK_RECOVERY,
27         HDQB_ADS_CALC,
28         HDQB_ADS_LOW,
29         HDQB_ADS_HIGH,
30         HDQB_WAIT_RX,
31         HDQB_DATA_RX_LOW,
32         HDQB_DATA_RX_HIGH,
33         HDQB_WAIT_TX,
34 };
35
36 static struct hdq_priv {
37         u8 hdq_probed; /* nonzero after HDQ driver probed */
38         struct mutex hdq_lock; /* if you want to use hdq, you have to take lock */
39         u8 hdq_ads; /* b7..b6 = register address, b0 = r/w */
40         u8 hdq_tx_data; /* data to tx for write action */
41         u8 hdq_rx_data; /* data received in read action */
42         u8 hdq_request_ctr; /* incremented by "user" to request a transfer */
43         u8 hdq_transaction_ctr; /* incremented after each transfer */
44         u8 hdq_error; /* 0 = no error */
45         u8 hdq_ctr;
46         u8 hdq_ctr2;
47         u8 hdq_bit;
48         u8 hdq_shifter;
49         u8 hdq_tx_data_done;
50         enum hdq_bitbang_states hdq_state;
51         int reported_error;
52
53         struct hdq_platform_data *pdata;
54 } hdq_priv;
55
56
57 static void hdq_bad(void)
58 {
59         if (!hdq_priv.reported_error)
60                 printk(KERN_ERR "HDQ error: %d\n", hdq_priv.hdq_error);
61         hdq_priv.reported_error = 1;
62 }
63
64 static void hdq_good(void)
65 {
66         if (hdq_priv.reported_error)
67                 printk(KERN_INFO "HDQ responds again\n");
68         hdq_priv.reported_error = 0;
69 }
70
71 int hdq_fiq_handler(void)
72 {
73         if (!hdq_priv.hdq_probed)
74                 return 0;
75
76         switch (hdq_priv.hdq_state) {
77         case HDQB_IDLE:
78                 if (hdq_priv.hdq_request_ctr == hdq_priv.hdq_transaction_ctr)
79                         break;
80                 hdq_priv.hdq_ctr = 250 / HDQ_SAMPLE_PERIOD_US;
81                 hdq_priv.pdata->gpio_set(0);
82                 hdq_priv.pdata->gpio_dir_out();
83                 hdq_priv.hdq_tx_data_done = 0;
84                 hdq_priv.hdq_state = HDQB_TX_BREAK;
85                 break;
86
87         case HDQB_TX_BREAK: /* issue low for > 190us */
88                 if (--hdq_priv.hdq_ctr == 0) {
89                         hdq_priv.hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US;
90                         hdq_priv.hdq_state = HDQB_TX_BREAK_RECOVERY;
91                         hdq_priv.pdata->gpio_set(1);
92                 }
93                 break;
94
95         case HDQB_TX_BREAK_RECOVERY: /* issue low for > 40us */
96                 if (--hdq_priv.hdq_ctr)
97                         break;
98                 hdq_priv.hdq_shifter = hdq_priv.hdq_ads;
99                 hdq_priv.hdq_bit = 8; /* 8 bits of ads / rw */
100                 hdq_priv.hdq_tx_data_done = 0; /* doing ads */
101                 /* fallthru on last one */
102         case HDQB_ADS_CALC:
103                 if (hdq_priv.hdq_shifter & 1)
104                         hdq_priv.hdq_ctr = 50 / HDQ_SAMPLE_PERIOD_US;
105                 else
106                         hdq_priv.hdq_ctr = 120 / HDQ_SAMPLE_PERIOD_US;
107                 /* carefully precompute the other phase length */
108                 hdq_priv.hdq_ctr2 = (210 - (hdq_priv.hdq_ctr * HDQ_SAMPLE_PERIOD_US)) /
109                                 HDQ_SAMPLE_PERIOD_US;
110                 hdq_priv.hdq_state = HDQB_ADS_LOW;
111                 hdq_priv.hdq_shifter >>= 1;
112                 hdq_priv.hdq_bit--;
113                 hdq_priv.pdata->gpio_set(0);
114                 break;
115
116         case HDQB_ADS_LOW:
117                 if (--hdq_priv.hdq_ctr)
118                         break;
119                 hdq_priv.pdata->gpio_set(1);
120                 hdq_priv.hdq_state = HDQB_ADS_HIGH;
121                 break;
122
123         case HDQB_ADS_HIGH:
124                 if (--hdq_priv.hdq_ctr2 > 1) /* account for HDQB_ADS_CALC */
125                         break;
126                 if (hdq_priv.hdq_bit) { /* more bits to do */
127                         hdq_priv.hdq_state = HDQB_ADS_CALC;
128                         break;
129                 }
130                 /* no more bits, wait it out until hdq_priv.hdq_ctr2 exhausted */
131                 if (hdq_priv.hdq_ctr2)
132                         break;
133                 /* ok no more bits and very last state */
134                 hdq_priv.hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US;
135                 /* FIXME 0 = read */
136                 if (hdq_priv.hdq_ads & 0x80) { /* write the byte out */
137                          /* set delay before payload */
138                         hdq_priv.hdq_ctr = 300 / HDQ_SAMPLE_PERIOD_US;
139                         /* already high, no need to write */
140                         hdq_priv.hdq_state = HDQB_WAIT_TX;
141                         break;
142                 }
143                 /* read the next byte */
144                 hdq_priv.hdq_bit = 8; /* 8 bits of data */
145                 hdq_priv.hdq_ctr = 2500 / HDQ_SAMPLE_PERIOD_US;
146                 hdq_priv.hdq_state = HDQB_WAIT_RX;
147                 hdq_priv.pdata->gpio_dir_in();
148                 break;
149
150         case HDQB_WAIT_TX: /* issue low for > 40us */
151                 if (--hdq_priv.hdq_ctr)
152                         break;
153                 if (!hdq_priv.hdq_tx_data_done) { /* was that the data sent? */
154                         hdq_priv.hdq_tx_data_done++;
155                         hdq_priv.hdq_shifter = hdq_priv.hdq_tx_data;
156                         hdq_priv.hdq_bit = 8; /* 8 bits of data */
157                         hdq_priv.hdq_state = HDQB_ADS_CALC; /* start sending */
158                         break;
159                 }
160                 hdq_priv.hdq_error = 0;
161                 hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr;
162                 hdq_priv.hdq_state = HDQB_IDLE; /* all tx is done */
163                 /* idle in input mode, it's pulled up by 10K */
164                 hdq_priv.pdata->gpio_dir_in();
165                 break;
166
167         case HDQB_WAIT_RX: /* wait for battery to talk to us */
168                 if (hdq_priv.pdata->gpio_get() == 0) {
169                         /* it talks to us! */
170                         hdq_priv.hdq_ctr2 = 1;
171                         hdq_priv.hdq_bit = 8; /* 8 bits of data */
172                         /* timeout */
173                         hdq_priv.hdq_ctr = 500 / HDQ_SAMPLE_PERIOD_US;
174                         hdq_priv.hdq_state = HDQB_DATA_RX_LOW;
175                         break;
176                 }
177                 if (--hdq_priv.hdq_ctr == 0) { /* timed out, error */
178                         hdq_priv.hdq_error = 1;
179                         hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr;
180                         hdq_priv.hdq_state = HDQB_IDLE; /* abort */
181                 }
182                 break;
183
184         /*
185          * HDQ basically works by measuring the low time of the bit cell
186          * 32-50us --> '1', 80 - 145us --> '0'
187          */
188
189         case HDQB_DATA_RX_LOW:
190                 if (hdq_priv.pdata->gpio_get()) {
191                         hdq_priv.hdq_rx_data >>= 1;
192                         if (hdq_priv.hdq_ctr2 <= (65 / HDQ_SAMPLE_PERIOD_US))
193                                 hdq_priv.hdq_rx_data |= 0x80;
194
195                         if (--hdq_priv.hdq_bit == 0) {
196                                 hdq_priv.hdq_error = 0;
197                                 hdq_priv.hdq_transaction_ctr =
198                                                         hdq_priv.hdq_request_ctr;
199
200                                 hdq_priv.hdq_state = HDQB_IDLE;
201                         } else
202                                 hdq_priv.hdq_state = HDQB_DATA_RX_HIGH;
203                         /* timeout */
204                         hdq_priv.hdq_ctr = 1000 / HDQ_SAMPLE_PERIOD_US;
205                         hdq_priv.hdq_ctr2 = 1;
206                         break;
207                 }
208                 hdq_priv.hdq_ctr2++;
209                 if (--hdq_priv.hdq_ctr)
210                         break;
211                  /* timed out, error */
212                 hdq_priv.hdq_error = 2;
213                 hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr;
214                 hdq_priv.hdq_state = HDQB_IDLE; /* abort */
215                 break;
216
217         case HDQB_DATA_RX_HIGH:
218                 if (!hdq_priv.pdata->gpio_get()) {
219                         /* it talks to us! */
220                         hdq_priv.hdq_ctr2 = 1;
221                         /* timeout */
222                         hdq_priv.hdq_ctr = 400 / HDQ_SAMPLE_PERIOD_US;
223                         hdq_priv.hdq_state = HDQB_DATA_RX_LOW;
224                         break;
225                 }
226                 if (--hdq_priv.hdq_ctr)
227                         break;
228                 /* timed out, error */
229                 hdq_priv.hdq_error = 3;
230                 hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr;
231
232                 /* we're in input mode already */
233                 hdq_priv.hdq_state = HDQB_IDLE; /* abort */
234                 break;
235         }
236
237         /* Are we interested in keeping the FIQ source alive ? */
238         if (hdq_priv.hdq_state != HDQB_IDLE)
239                 return 1;
240         else
241                 return 0;
242 }
243 static int fiq_busy(void)
244 {
245         int request = (volatile u8)hdq_priv.hdq_request_ctr;
246         int transact = (volatile u8)hdq_priv.hdq_transaction_ctr;
247
248
249         return (request != transact);
250 }
251
252 int hdq_initialized(void)
253 {
254         return hdq_priv.hdq_probed;
255 }
256 EXPORT_SYMBOL_GPL(hdq_initialized);
257
258 int hdq_read(int address)
259 {
260         int count_sleeps = 5;
261         int ret = -ETIME;
262
263         if (!hdq_priv.hdq_probed)
264                 return -EINVAL;
265
266         mutex_lock(&hdq_priv.hdq_lock);
267
268         hdq_priv.hdq_error = 0;
269         hdq_priv.hdq_ads = address | HDQ_READ;
270         hdq_priv.hdq_request_ctr++;
271         hdq_priv.pdata->kick_fiq();
272         /*
273          * FIQ takes care of it while we block our calling process
274          * But we're not spinning -- other processes run normally while
275          * we wait for the result
276          */
277         while (count_sleeps--) {
278                 msleep(10); /* valid transaction always completes in < 10ms */
279
280                 if (fiq_busy())
281                         continue;
282
283                 if (hdq_priv.hdq_error) {
284                         hdq_bad();
285                         goto done; /* didn't see a response in good time */
286                 }
287                 hdq_good();
288
289                 ret = hdq_priv.hdq_rx_data;
290                 goto done;
291         }
292
293 done:
294         mutex_unlock(&hdq_priv.hdq_lock);
295         return ret;
296 }
297 EXPORT_SYMBOL_GPL(hdq_read);
298
299 int hdq_write(int address, u8 data)
300 {
301         int count_sleeps = 5;
302         int ret = -ETIME;
303
304         if (!hdq_priv.hdq_probed)
305                 return -EINVAL;
306
307         mutex_lock(&hdq_priv.hdq_lock);
308
309         hdq_priv.hdq_error = 0;
310         hdq_priv.hdq_ads = address | HDQ_WRITE;
311         hdq_priv.hdq_tx_data = data;
312         hdq_priv.hdq_request_ctr++;
313         hdq_priv.pdata->kick_fiq();
314         /*
315          * FIQ takes care of it while we block our calling process
316          * But we're not spinning -- other processes run normally while
317          * we wait for the result
318          */
319         while (count_sleeps--) {
320                 msleep(10); /* valid transaction always completes in < 10ms */
321
322                 if (fiq_busy())
323                         continue; /* something bad with FIQ */
324
325                 if (hdq_priv.hdq_error) {
326                         hdq_bad();
327                         goto done; /* didn't see a response in good time */
328                 }
329                 hdq_good();
330
331                 ret = 0;
332                 goto done;
333         }
334
335 done:
336         mutex_unlock(&hdq_priv.hdq_lock);
337         return ret;
338 }
339 EXPORT_SYMBOL_GPL(hdq_write);
340
341 /* sysfs */
342
343 static ssize_t hdq_sysfs_dump(struct device *dev, struct device_attribute *attr,
344                          char *buf)
345 {
346         int n;
347         int v;
348         u8 u8a[128]; /* whole address space for HDQ */
349         char *end = buf;
350
351         if (!hdq_priv.hdq_probed)
352                 return -EINVAL;
353
354         /* the dump does not take care about 16 bit regs, because at this
355          * bus level we don't know about the chip details
356          */
357         for (n = 0; n < sizeof(u8a); n++) {
358                 v = hdq_read(n);
359                 if (v < 0)
360                         goto bail;
361                 u8a[n] = v;
362         }
363
364         for (n = 0; n < sizeof(u8a); n += 16) {
365                 hex_dump_to_buffer(u8a + n, sizeof(u8a), 16, 1, end, 4096, 0);
366                 end += strlen(end);
367                 *end++ = '\n';
368                 *end = '\0';
369         }
370         return (end - buf);
371
372 bail:
373         return sprintf(buf, "ERROR %d\n", v);
374 }
375
376 /* you write by <address> <data>, eg, "34 128" */
377
378 #define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
379
380 static ssize_t hdq_sysfs_write(struct device *dev,
381                                struct device_attribute *attr,
382                                const char *buf, size_t count)
383 {
384         const char *end = buf + count;
385         int address = atoi(buf);
386
387         if (!hdq_priv.hdq_probed)
388                 return -EINVAL;
389
390         while ((buf != end) && (*buf != ' '))
391                 buf++;
392         if (buf >= end)
393                 return 0;
394         while ((buf < end) && (*buf == ' '))
395                 buf++;
396         if (buf >= end)
397                 return 0;
398
399         hdq_write(address, atoi(buf));
400
401         return count;
402 }
403
404 static DEVICE_ATTR(dump, 0400, hdq_sysfs_dump, NULL);
405 static DEVICE_ATTR(write, 0600, NULL, hdq_sysfs_write);
406
407 static struct attribute *hdq_sysfs_entries[] = {
408         &dev_attr_dump.attr,
409         &dev_attr_write.attr,
410         NULL
411 };
412
413 static struct attribute_group hdq_attr_group = {
414         .name   = "hdq",
415         .attrs  = hdq_sysfs_entries,
416 };
417
418
419 #ifdef CONFIG_PM
420 static int hdq_suspend(struct platform_device *pdev, pm_message_t state)
421 {
422         /* after 18s of this, the battery monitor will also go to sleep */
423         hdq_priv.pdata->gpio_dir_in();
424         hdq_priv.pdata->disable_fiq();
425         return 0;
426 }
427
428 static int hdq_resume(struct platform_device *pdev)
429 {
430         hdq_priv.pdata->gpio_set(1);
431         hdq_priv.pdata->gpio_dir_out();
432         hdq_priv.pdata->enable_fiq();
433         return 0;
434 }
435 #endif
436
437 static int __init hdq_probe(struct platform_device *pdev)
438 {
439         int ret;
440         struct hdq_platform_data *pdata = pdev->dev.platform_data;
441
442         if (!pdata)
443                 return -EINVAL;
444
445         platform_set_drvdata(pdev, NULL);
446
447         mutex_init(&hdq_priv.hdq_lock);
448
449         /* set our HDQ comms pin from the platform data */
450         hdq_priv.pdata = pdata;
451
452         hdq_priv.pdata->gpio_set(1);
453         hdq_priv.pdata->gpio_dir_out();
454
455         /* Initialize FIQ */
456         if (hdq_priv.pdata->enable_fiq() < 0) {
457                 dev_err(&pdev->dev, "Could not enable FIQ source\n");
458                 return -EINVAL;
459         }
460
461         ret = sysfs_create_group(&pdev->dev.kobj, &hdq_attr_group);
462         if (ret)
463                 return ret;
464
465         hdq_priv.hdq_probed = 1; /* we are ready to do stuff now */
466
467         /*
468          * if wanted, users can defer registration of devices
469          * that depend on HDQ until after we register, and can use our
470          * device as parent so suspend-resume ordering is correct
471          */
472         if (pdata->attach_child_devices)
473                 (pdata->attach_child_devices)(&pdev->dev);
474
475         hdq_priv.pdata = pdata;
476
477         return 0;
478 }
479
480 static int hdq_remove(struct platform_device *pdev)
481 {
482         sysfs_remove_group(&pdev->dev.kobj, &hdq_attr_group);
483         return 0;
484 }
485
486 static struct platform_driver hdq_driver = {
487         .probe          = hdq_probe,
488         .remove         = hdq_remove,
489 #ifdef CONFIG_PM
490         .suspend        = hdq_suspend,
491         .resume         = hdq_resume,
492 #endif
493         .driver         = {
494                 .name           = "hdq",
495         },
496 };
497
498 static int __init hdq_init(void)
499 {
500         return platform_driver_register(&hdq_driver);
501 }
502
503 static void __exit hdq_exit(void)
504 {
505         platform_driver_unregister(&hdq_driver);
506 }
507
508 module_init(hdq_init);
509 module_exit(hdq_exit);
510
511 MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
512 MODULE_DESCRIPTION("HDQ driver");