s3c24xx: Fix level irqs on external interrupts.
[kernel.git] / arch / arm / plat-s3c24xx / irq.c
1 /* linux/arch/arm/plat-s3c24xx/irq.c
2  *
3  * Copyright (c) 2003-2004 Simtec Electronics
4  *      Ben Dooks <ben@simtec.co.uk>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19 */
20
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/sysdev.h>
26
27 #include <asm/irq.h>
28 #include <asm/mach/irq.h>
29
30 #include <plat/regs-irqtype.h>
31 #include <mach/regs-irq.h>
32 #include <mach/regs-gpio.h>
33
34 #include <plat/cpu.h>
35 #include <plat/pm.h>
36 #include <plat/irq.h>
37
38 static void
39 s3c_irq_mask(unsigned int irqno)
40 {
41         unsigned long mask;
42 #ifdef CONFIG_S3C2440_C_FIQ
43         unsigned long flags;
44 #endif
45         irqno -= IRQ_EINT0;
46 #ifdef CONFIG_S3C2440_C_FIQ
47         local_save_flags(flags);
48         local_fiq_disable();
49 #endif
50         mask = __raw_readl(S3C2410_INTMSK);
51         mask |= 1UL << irqno;
52         __raw_writel(mask, S3C2410_INTMSK);
53 #ifdef CONFIG_S3C2440_C_FIQ
54         local_irq_restore(flags);
55 #endif
56 }
57
58 static inline void
59 s3c_irq_ack(unsigned int irqno)
60 {
61         unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
62
63         __raw_writel(bitval, S3C2410_SRCPND);
64         __raw_writel(bitval, S3C2410_INTPND);
65 }
66
67 static inline void
68 s3c_irq_maskack(unsigned int irqno)
69 {
70         unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
71         unsigned long mask;
72 #ifdef CONFIG_S3C2440_C_FIQ
73         unsigned long flags;
74 #endif
75
76 #ifdef CONFIG_S3C2440_C_FIQ
77         local_save_flags(flags);
78         local_fiq_disable();
79 #endif
80         mask = __raw_readl(S3C2410_INTMSK);
81         __raw_writel(mask|bitval, S3C2410_INTMSK);
82 #ifdef CONFIG_S3C2440_C_FIQ
83         local_irq_restore(flags);
84 #endif
85
86         __raw_writel(bitval, S3C2410_SRCPND);
87         __raw_writel(bitval, S3C2410_INTPND);
88 }
89
90
91 static void
92 s3c_irq_unmask(unsigned int irqno)
93 {
94         unsigned long mask;
95 #ifdef CONFIG_S3C2440_C_FIQ
96         unsigned long flags;
97 #endif
98
99         if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
100                 irqdbf2("s3c_irq_unmask %d\n", irqno);
101
102         irqno -= IRQ_EINT0;
103
104 #ifdef CONFIG_S3C2440_C_FIQ
105         local_save_flags(flags);
106         local_fiq_disable();
107 #endif
108         mask = __raw_readl(S3C2410_INTMSK);
109         mask &= ~(1UL << irqno);
110         __raw_writel(mask, S3C2410_INTMSK);
111 #ifdef CONFIG_S3C2440_C_FIQ
112         local_irq_restore(flags);
113 #endif
114 }
115
116 struct irq_chip s3c_irq_level_chip = {
117         .name           = "s3c-level",
118         .ack            = s3c_irq_maskack,
119         .mask           = s3c_irq_mask,
120         .unmask         = s3c_irq_unmask,
121         .set_wake       = s3c_irq_wake
122 };
123
124 struct irq_chip s3c_irq_chip = {
125         .name           = "s3c",
126         .ack            = s3c_irq_ack,
127         .mask           = s3c_irq_mask,
128         .unmask         = s3c_irq_unmask,
129         .set_wake       = s3c_irq_wake
130 };
131
132 static void
133 s3c_irqext_mask(unsigned int irqno)
134 {
135         unsigned long mask;
136
137         irqno -= EXTINT_OFF;
138
139         mask = __raw_readl(S3C24XX_EINTMASK);
140         mask |= ( 1UL << irqno);
141         __raw_writel(mask, S3C24XX_EINTMASK);
142 }
143
144 static void
145 s3c_irqext_ack(unsigned int irqno)
146 {
147         unsigned long req;
148         unsigned long bit;
149         unsigned long mask;
150
151         bit = 1UL << (irqno - EXTINT_OFF);
152
153         mask = __raw_readl(S3C24XX_EINTMASK);
154
155         __raw_writel(bit, S3C24XX_EINTPEND);
156
157         req = __raw_readl(S3C24XX_EINTPEND);
158         req &= ~mask;
159
160         /* not sure if we should be acking the parent irq... */
161
162         if (irqno <= IRQ_EINT7 ) {
163                 if ((req & 0xf0) == 0)
164                         s3c_irq_ack(IRQ_EINT4t7);
165         } else {
166                 if ((req >> 8) == 0)
167                         s3c_irq_ack(IRQ_EINT8t23);
168         }
169 }
170
171 static void
172 s3c_irqext_unmask(unsigned int irqno)
173 {
174         unsigned long mask;
175
176         irqno -= EXTINT_OFF;
177
178         mask = __raw_readl(S3C24XX_EINTMASK);
179         mask &= ~( 1UL << irqno);
180         __raw_writel(mask, S3C24XX_EINTMASK);
181 }
182
183 int
184 s3c_irqext_type(unsigned int irq, unsigned int type)
185 {
186         void __iomem *extint_reg;
187         void __iomem *gpcon_reg;
188         unsigned long gpcon_offset, extint_offset;
189         unsigned long newvalue = 0, value;
190
191         if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3))
192         {
193                 gpcon_reg = S3C2410_GPFCON;
194                 extint_reg = S3C24XX_EXTINT0;
195                 gpcon_offset = (irq - IRQ_EINT0) * 2;
196                 extint_offset = (irq - IRQ_EINT0) * 4;
197         }
198         else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))
199         {
200                 gpcon_reg = S3C2410_GPFCON;
201                 extint_reg = S3C24XX_EXTINT0;
202                 gpcon_offset = (irq - (EXTINT_OFF)) * 2;
203                 extint_offset = (irq - (EXTINT_OFF)) * 4;
204         }
205         else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))
206         {
207                 gpcon_reg = S3C2410_GPGCON;
208                 extint_reg = S3C24XX_EXTINT1;
209                 gpcon_offset = (irq - IRQ_EINT8) * 2;
210                 extint_offset = (irq - IRQ_EINT8) * 4;
211         }
212         else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))
213         {
214                 gpcon_reg = S3C2410_GPGCON;
215                 extint_reg = S3C24XX_EXTINT2;
216                 gpcon_offset = (irq - IRQ_EINT8) * 2;
217                 extint_offset = (irq - IRQ_EINT16) * 4;
218         } else
219                 return -1;
220
221         /* Set the GPIO to external interrupt mode */
222         value = __raw_readl(gpcon_reg);
223         value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
224         __raw_writel(value, gpcon_reg);
225
226         /* Set the external interrupt to pointed trigger type */
227         switch (type)
228         {
229                 case IRQ_TYPE_NONE:
230                         printk(KERN_WARNING "No edge setting!\n");
231                         break;
232
233                 case IRQ_TYPE_EDGE_RISING:
234                         newvalue = S3C2410_EXTINT_RISEEDGE;
235                         break;
236
237                 case IRQ_TYPE_EDGE_FALLING:
238                         newvalue = S3C2410_EXTINT_FALLEDGE;
239                         break;
240
241                 case IRQ_TYPE_EDGE_BOTH:
242                         newvalue = S3C2410_EXTINT_BOTHEDGE;
243                         break;
244
245                 case IRQ_TYPE_LEVEL_LOW:
246                         newvalue = S3C2410_EXTINT_LOWLEV;
247                         break;
248
249                 case IRQ_TYPE_LEVEL_HIGH:
250                         newvalue = S3C2410_EXTINT_HILEV;
251                         break;
252
253                 default:
254                         printk(KERN_ERR "No such irq type %d", type);
255                         return -1;
256         }
257
258         value = __raw_readl(extint_reg);
259         value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
260         __raw_writel(value, extint_reg);
261
262         return 0;
263 }
264
265 static struct irq_chip s3c_irqext_chip = {
266         .name           = "s3c-ext",
267         .mask           = s3c_irqext_mask,
268         .unmask         = s3c_irqext_unmask,
269         .ack            = s3c_irqext_ack,
270         .set_type       = s3c_irqext_type,
271         .set_wake       = s3c_irqext_wake
272 };
273
274 static struct irq_chip s3c_irq_eint0t4 = {
275         .name           = "s3c-ext0",
276         .ack            = s3c_irq_ack,
277         .mask           = s3c_irq_mask,
278         .unmask         = s3c_irq_unmask,
279         .set_wake       = s3c_irq_wake,
280         .set_type       = s3c_irqext_type,
281 };
282
283 /* mask values for the parent registers for each of the interrupt types */
284
285 #define INTMSK_UART0     (1UL << (IRQ_UART0 - IRQ_EINT0))
286 #define INTMSK_UART1     (1UL << (IRQ_UART1 - IRQ_EINT0))
287 #define INTMSK_UART2     (1UL << (IRQ_UART2 - IRQ_EINT0))
288 #define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
289
290
291 /* UART0 */
292
293 static void
294 s3c_irq_uart0_mask(unsigned int irqno)
295 {
296         s3c_irqsub_mask(irqno, INTMSK_UART0, 7);
297 }
298
299 static void
300 s3c_irq_uart0_unmask(unsigned int irqno)
301 {
302         s3c_irqsub_unmask(irqno, INTMSK_UART0);
303 }
304
305 static void
306 s3c_irq_uart0_ack(unsigned int irqno)
307 {
308         s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
309 }
310
311 static struct irq_chip s3c_irq_uart0 = {
312         .name           = "s3c-uart0",
313         .mask           = s3c_irq_uart0_mask,
314         .unmask         = s3c_irq_uart0_unmask,
315         .ack            = s3c_irq_uart0_ack,
316 };
317
318 /* UART1 */
319
320 static void
321 s3c_irq_uart1_mask(unsigned int irqno)
322 {
323         s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3);
324 }
325
326 static void
327 s3c_irq_uart1_unmask(unsigned int irqno)
328 {
329         s3c_irqsub_unmask(irqno, INTMSK_UART1);
330 }
331
332 static void
333 s3c_irq_uart1_ack(unsigned int irqno)
334 {
335         s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
336 }
337
338 static struct irq_chip s3c_irq_uart1 = {
339         .name           = "s3c-uart1",
340         .mask           = s3c_irq_uart1_mask,
341         .unmask         = s3c_irq_uart1_unmask,
342         .ack            = s3c_irq_uart1_ack,
343 };
344
345 /* UART2 */
346
347 static void
348 s3c_irq_uart2_mask(unsigned int irqno)
349 {
350         s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6);
351 }
352
353 static void
354 s3c_irq_uart2_unmask(unsigned int irqno)
355 {
356         s3c_irqsub_unmask(irqno, INTMSK_UART2);
357 }
358
359 static void
360 s3c_irq_uart2_ack(unsigned int irqno)
361 {
362         s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
363 }
364
365 static struct irq_chip s3c_irq_uart2 = {
366         .name           = "s3c-uart2",
367         .mask           = s3c_irq_uart2_mask,
368         .unmask         = s3c_irq_uart2_unmask,
369         .ack            = s3c_irq_uart2_ack,
370 };
371
372 /* ADC and Touchscreen */
373
374 static void
375 s3c_irq_adc_mask(unsigned int irqno)
376 {
377         s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9);
378 }
379
380 static void
381 s3c_irq_adc_unmask(unsigned int irqno)
382 {
383         s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT);
384 }
385
386 static void
387 s3c_irq_adc_ack(unsigned int irqno)
388 {
389         s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
390 }
391
392 static struct irq_chip s3c_irq_adc = {
393         .name           = "s3c-adc",
394         .mask           = s3c_irq_adc_mask,
395         .unmask         = s3c_irq_adc_unmask,
396         .ack            = s3c_irq_adc_ack,
397 };
398
399 /* irq demux for adc */
400 static void s3c_irq_demux_adc(unsigned int irq,
401                               struct irq_desc *desc)
402 {
403         unsigned int subsrc, submsk;
404         unsigned int offset = 9;
405
406         /* read the current pending interrupts, and the mask
407          * for what it is available */
408
409         subsrc = __raw_readl(S3C2410_SUBSRCPND);
410         submsk = __raw_readl(S3C2410_INTSUBMSK);
411
412         subsrc &= ~submsk;
413         subsrc >>= offset;
414         subsrc &= 3;
415
416         if (subsrc != 0) {
417                 if (subsrc & 1) {
418                         generic_handle_irq(IRQ_TC);
419                 }
420                 if (subsrc & 2) {
421                         generic_handle_irq(IRQ_ADC);
422                 }
423         }
424 }
425
426 static void s3c_irq_demux_uart(unsigned int start)
427 {
428         unsigned int subsrc, submsk;
429         unsigned int offset = start - IRQ_S3CUART_RX0;
430
431         /* read the current pending interrupts, and the mask
432          * for what it is available */
433
434         subsrc = __raw_readl(S3C2410_SUBSRCPND);
435         submsk = __raw_readl(S3C2410_INTSUBMSK);
436
437         irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
438                 start, offset, subsrc, submsk);
439
440         subsrc &= ~submsk;
441         subsrc >>= offset;
442         subsrc &= 7;
443
444         if (subsrc != 0) {
445                 if (subsrc & 1)
446                         generic_handle_irq(start);
447
448                 if (subsrc & 2)
449                         generic_handle_irq(start+1);
450
451                 if (subsrc & 4)
452                         generic_handle_irq(start+2);
453         }
454 }
455
456 /* uart demux entry points */
457
458 static void
459 s3c_irq_demux_uart0(unsigned int irq,
460                     struct irq_desc *desc)
461 {
462         irq = irq;
463         s3c_irq_demux_uart(IRQ_S3CUART_RX0);
464 }
465
466 static void
467 s3c_irq_demux_uart1(unsigned int irq,
468                     struct irq_desc *desc)
469 {
470         irq = irq;
471         s3c_irq_demux_uart(IRQ_S3CUART_RX1);
472 }
473
474 static void
475 s3c_irq_demux_uart2(unsigned int irq,
476                     struct irq_desc *desc)
477 {
478         irq = irq;
479         s3c_irq_demux_uart(IRQ_S3CUART_RX2);
480 }
481
482 static void
483 s3c_irq_demux_extint8(unsigned int irq,
484                       struct irq_desc *desc)
485 {
486         unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
487         unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
488
489         eintpnd &= ~eintmsk;
490         eintpnd &= ~0xff;       /* ignore lower irqs */
491
492         /* we may as well handle all the pending IRQs here */
493
494         while (eintpnd) {
495                 irq = __ffs(eintpnd);
496                 eintpnd &= ~(1<<irq);
497
498                 irq += (IRQ_EINT4 - 4);
499                 generic_handle_irq(irq);
500         }
501
502 }
503
504 static void
505 s3c_irq_demux_extint4t7(unsigned int irq,
506                         struct irq_desc *desc)
507 {
508         unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
509         unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
510
511         eintpnd &= ~eintmsk;
512         eintpnd &= 0xff;        /* only lower irqs */
513
514         /* we may as well handle all the pending IRQs here */
515
516         while (eintpnd) {
517                 irq = __ffs(eintpnd);
518                 eintpnd &= ~(1<<irq);
519
520                 irq += (IRQ_EINT4 - 4);
521
522                 generic_handle_irq(irq);
523         }
524 }
525
526 #ifdef CONFIG_FIQ
527 /**
528  * s3c24xx_set_fiq - set the FIQ routing
529  * @irq: IRQ number to route to FIQ on processor.
530  * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
531  *
532  * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
533  * @on is true, the @irq is checked to see if it can be routed and the
534  * interrupt controller updated to route the IRQ. If @on is false, the FIQ
535  * routing is cleared, regardless of which @irq is specified.
536  */
537 int s3c24xx_set_fiq(unsigned int irq, bool on)
538 {
539         u32 intmod;
540         unsigned offs;
541
542         if (on) {
543                 offs = irq - FIQ_START;
544                 if (offs > 31)
545                         return -EINVAL;
546
547                 intmod = 1 << offs;
548         } else {
549                 intmod = 0;
550         }
551
552         __raw_writel(intmod, S3C2410_INTMOD);
553         return 0;
554 }
555
556 EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
557 #endif
558
559
560 /* s3c24xx_init_irq
561  *
562  * Initialise S3C2410 IRQ system
563 */
564
565 void __init s3c24xx_init_irq(void)
566 {
567         unsigned long pend;
568         unsigned long last;
569         int irqno;
570         int i;
571
572 #ifdef CONFIG_FIQ
573         init_FIQ();
574 #endif
575
576         irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
577
578         /* first, clear all interrupts pending... */
579
580         last = 0;
581         for (i = 0; i < 4; i++) {
582                 pend = __raw_readl(S3C24XX_EINTPEND);
583
584                 if (pend == 0 || pend == last)
585                         break;
586
587                 __raw_writel(pend, S3C24XX_EINTPEND);
588                 printk("irq: clearing pending ext status %08x\n", (int)pend);
589                 last = pend;
590         }
591
592         last = 0;
593         for (i = 0; i < 4; i++) {
594                 pend = __raw_readl(S3C2410_SUBSRCPND);
595
596                 if (pend == 0 || pend == last)
597                         break;
598
599                 printk("irq: clearing subpending status %08x\n", (int)pend);
600                 __raw_writel(pend, S3C2410_SUBSRCPND);
601                 last = pend;
602         }
603
604         last = 0;
605         for (i = 0; i < 4; i++) {
606                 pend = __raw_readl(S3C2410_INTPND);
607
608                 if (pend == 0 || pend == last)
609                         break;
610
611                 __raw_writel(pend, S3C2410_SRCPND);
612                 __raw_writel(pend, S3C2410_INTPND);
613                 printk("irq: clearing pending status %08x\n", (int)pend);
614                 last = pend;
615         }
616
617         /* register the main interrupts */
618
619         irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
620
621         for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
622                 /* set all the s3c2410 internal irqs */
623
624                 switch (irqno) {
625                         /* deal with the special IRQs (cascaded) */
626
627                 case IRQ_EINT4t7:
628                 case IRQ_EINT8t23:
629                 case IRQ_UART0:
630                 case IRQ_UART1:
631                 case IRQ_UART2:
632                 case IRQ_ADCPARENT:
633                         set_irq_chip(irqno, &s3c_irq_level_chip);
634                         set_irq_handler(irqno, handle_level_irq);
635                         break;
636
637                 case IRQ_RESERVED6:
638                 case IRQ_RESERVED24:
639                         /* no IRQ here */
640                         break;
641
642                 default:
643                         //irqdbf("registering irq %d (s3c irq)\n", irqno);
644                         set_irq_chip(irqno, &s3c_irq_chip);
645                         set_irq_handler(irqno, handle_edge_irq);
646                         set_irq_flags(irqno, IRQF_VALID);
647                 }
648         }
649
650         /* setup the cascade irq handlers */
651
652         set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
653         set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
654
655         set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
656         set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
657         set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
658         set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
659
660         /* external interrupts */
661
662         for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
663                 irqdbf("registering irq %d (ext int)\n", irqno);
664                 set_irq_chip_and_handler(irqno, &s3c_irq_eint0t4, handle_level_irq);
665                 set_irq_flags(irqno, IRQF_VALID);
666         }
667
668         for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
669                 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
670                 set_irq_chip_and_handler(irqno, &s3c_irqext_chip, handle_level_irq);
671                 set_irq_flags(irqno, IRQF_VALID);
672         }
673
674         /* register the uart interrupts */
675
676         irqdbf("s3c2410: registering external interrupts\n");
677
678         for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
679                 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
680                 set_irq_chip(irqno, &s3c_irq_uart0);
681                 set_irq_handler(irqno, handle_level_irq);
682                 set_irq_flags(irqno, IRQF_VALID);
683         }
684
685         for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
686                 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
687                 set_irq_chip(irqno, &s3c_irq_uart1);
688                 set_irq_handler(irqno, handle_level_irq);
689                 set_irq_flags(irqno, IRQF_VALID);
690         }
691
692         for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
693                 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
694                 set_irq_chip(irqno, &s3c_irq_uart2);
695                 set_irq_handler(irqno, handle_level_irq);
696                 set_irq_flags(irqno, IRQF_VALID);
697         }
698
699         for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
700                 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
701                 set_irq_chip(irqno, &s3c_irq_adc);
702                 set_irq_handler(irqno, handle_edge_irq);
703                 set_irq_flags(irqno, IRQF_VALID);
704         }
705
706         irqdbf("s3c2410: registered interrupt handlers\n");
707 }