MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1
[kernel.git] / arch / mips / include / asm / mipsregs.h
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7  * Copyright (C) 2000 Silicon Graphics, Inc.
8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
12  */
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
15
16 #include <linux/linkage.h>
17 #include <asm/hazards.h>
18 #include <asm/war.h>
19
20 /*
21  * The following macros are especially useful for __asm__
22  * inline assembler.
23  */
24 #ifndef __STR
25 #define __STR(x) #x
26 #endif
27 #ifndef STR
28 #define STR(x) __STR(x)
29 #endif
30
31 /*
32  *  Configure language
33  */
34 #ifdef __ASSEMBLY__
35 #define _ULCAST_
36 #else
37 #define _ULCAST_ (unsigned long)
38 #endif
39
40 /*
41  * Coprocessor 0 register names
42  */
43 #define CP0_INDEX $0
44 #define CP0_RANDOM $1
45 #define CP0_ENTRYLO0 $2
46 #define CP0_ENTRYLO1 $3
47 #define CP0_CONF $3
48 #define CP0_CONTEXT $4
49 #define CP0_PAGEMASK $5
50 #define CP0_WIRED $6
51 #define CP0_INFO $7
52 #define CP0_BADVADDR $8
53 #define CP0_COUNT $9
54 #define CP0_ENTRYHI $10
55 #define CP0_COMPARE $11
56 #define CP0_STATUS $12
57 #define CP0_CAUSE $13
58 #define CP0_EPC $14
59 #define CP0_PRID $15
60 #define CP0_CONFIG $16
61 #define CP0_LLADDR $17
62 #define CP0_WATCHLO $18
63 #define CP0_WATCHHI $19
64 #define CP0_XCONTEXT $20
65 #define CP0_FRAMEMASK $21
66 #define CP0_DIAGNOSTIC $22
67 #define CP0_DEBUG $23
68 #define CP0_DEPC $24
69 #define CP0_PERFORMANCE $25
70 #define CP0_ECC $26
71 #define CP0_CACHEERR $27
72 #define CP0_TAGLO $28
73 #define CP0_TAGHI $29
74 #define CP0_ERROREPC $30
75 #define CP0_DESAVE $31
76
77 /*
78  * R4640/R4650 cp0 register names.  These registers are listed
79  * here only for completeness; without MMU these CPUs are not useable
80  * by Linux.  A future ELKS port might take make Linux run on them
81  * though ...
82  */
83 #define CP0_IBASE $0
84 #define CP0_IBOUND $1
85 #define CP0_DBASE $2
86 #define CP0_DBOUND $3
87 #define CP0_CALG $17
88 #define CP0_IWATCH $18
89 #define CP0_DWATCH $19
90
91 /*
92  * Coprocessor 0 Set 1 register names
93  */
94 #define CP0_S1_DERRADDR0  $26
95 #define CP0_S1_DERRADDR1  $27
96 #define CP0_S1_INTCONTROL $20
97
98 /*
99  * Coprocessor 0 Set 2 register names
100  */
101 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
102
103 /*
104  * Coprocessor 0 Set 3 register names
105  */
106 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
107
108 /*
109  *  TX39 Series
110  */
111 #define CP0_TX39_CACHE  $7
112
113 /*
114  * Coprocessor 1 (FPU) register names
115  */
116 #define CP1_REVISION   $0
117 #define CP1_STATUS     $31
118
119 /*
120  * FPU Status Register Values
121  */
122 /*
123  * Status Register Values
124  */
125
126 #define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
127 #define FPU_CSR_COND    0x00800000      /* $fcc0 */
128 #define FPU_CSR_COND0   0x00800000      /* $fcc0 */
129 #define FPU_CSR_COND1   0x02000000      /* $fcc1 */
130 #define FPU_CSR_COND2   0x04000000      /* $fcc2 */
131 #define FPU_CSR_COND3   0x08000000      /* $fcc3 */
132 #define FPU_CSR_COND4   0x10000000      /* $fcc4 */
133 #define FPU_CSR_COND5   0x20000000      /* $fcc5 */
134 #define FPU_CSR_COND6   0x40000000      /* $fcc6 */
135 #define FPU_CSR_COND7   0x80000000      /* $fcc7 */
136
137 /*
138  * Bits 18 - 20 of the FPU Status Register will be read as 0,
139  * and should be written as zero.
140  */
141 #define FPU_CSR_RSVD    0x001c0000
142
143 /*
144  * X the exception cause indicator
145  * E the exception enable
146  * S the sticky/flag bit
147 */
148 #define FPU_CSR_ALL_X   0x0003f000
149 #define FPU_CSR_UNI_X   0x00020000
150 #define FPU_CSR_INV_X   0x00010000
151 #define FPU_CSR_DIV_X   0x00008000
152 #define FPU_CSR_OVF_X   0x00004000
153 #define FPU_CSR_UDF_X   0x00002000
154 #define FPU_CSR_INE_X   0x00001000
155
156 #define FPU_CSR_ALL_E   0x00000f80
157 #define FPU_CSR_INV_E   0x00000800
158 #define FPU_CSR_DIV_E   0x00000400
159 #define FPU_CSR_OVF_E   0x00000200
160 #define FPU_CSR_UDF_E   0x00000100
161 #define FPU_CSR_INE_E   0x00000080
162
163 #define FPU_CSR_ALL_S   0x0000007c
164 #define FPU_CSR_INV_S   0x00000040
165 #define FPU_CSR_DIV_S   0x00000020
166 #define FPU_CSR_OVF_S   0x00000010
167 #define FPU_CSR_UDF_S   0x00000008
168 #define FPU_CSR_INE_S   0x00000004
169
170 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
171 #define FPU_CSR_RM      0x00000003
172 #define FPU_CSR_RN      0x0     /* nearest */
173 #define FPU_CSR_RZ      0x1     /* towards zero */
174 #define FPU_CSR_RU      0x2     /* towards +Infinity */
175 #define FPU_CSR_RD      0x3     /* towards -Infinity */
176
177
178 /*
179  * Values for PageMask register
180  */
181 #ifdef CONFIG_CPU_VR41XX
182
183 /* Why doesn't stupidity hurt ... */
184
185 #define PM_1K           0x00000000
186 #define PM_4K           0x00001800
187 #define PM_16K          0x00007800
188 #define PM_64K          0x0001f800
189 #define PM_256K         0x0007f800
190
191 #else
192
193 #define PM_4K           0x00000000
194 #define PM_8K           0x00002000
195 #define PM_16K          0x00006000
196 #define PM_32K          0x0000e000
197 #define PM_64K          0x0001e000
198 #define PM_128K         0x0003e000
199 #define PM_256K         0x0007e000
200 #define PM_512K         0x000fe000
201 #define PM_1M           0x001fe000
202 #define PM_2M           0x003fe000
203 #define PM_4M           0x007fe000
204 #define PM_8M           0x00ffe000
205 #define PM_16M          0x01ffe000
206 #define PM_32M          0x03ffe000
207 #define PM_64M          0x07ffe000
208 #define PM_256M         0x1fffe000
209 #define PM_1G           0x7fffe000
210
211 #endif
212
213 /*
214  * Default page size for a given kernel configuration
215  */
216 #ifdef CONFIG_PAGE_SIZE_4KB
217 #define PM_DEFAULT_MASK PM_4K
218 #elif defined(CONFIG_PAGE_SIZE_8KB)
219 #define PM_DEFAULT_MASK PM_8K
220 #elif defined(CONFIG_PAGE_SIZE_16KB)
221 #define PM_DEFAULT_MASK PM_16K
222 #elif defined(CONFIG_PAGE_SIZE_32KB)
223 #define PM_DEFAULT_MASK PM_32K
224 #elif defined(CONFIG_PAGE_SIZE_64KB)
225 #define PM_DEFAULT_MASK PM_64K
226 #else
227 #error Bad page size configuration!
228 #endif
229
230 /*
231  * Default huge tlb size for a given kernel configuration
232  */
233 #ifdef CONFIG_PAGE_SIZE_4KB
234 #define PM_HUGE_MASK    PM_1M
235 #elif defined(CONFIG_PAGE_SIZE_8KB)
236 #define PM_HUGE_MASK    PM_4M
237 #elif defined(CONFIG_PAGE_SIZE_16KB)
238 #define PM_HUGE_MASK    PM_16M
239 #elif defined(CONFIG_PAGE_SIZE_32KB)
240 #define PM_HUGE_MASK    PM_64M
241 #elif defined(CONFIG_PAGE_SIZE_64KB)
242 #define PM_HUGE_MASK    PM_256M
243 #elif defined(CONFIG_HUGETLB_PAGE)
244 #error Bad page size configuration for hugetlbfs!
245 #endif
246
247 /*
248  * Values used for computation of new tlb entries
249  */
250 #define PL_4K           12
251 #define PL_16K          14
252 #define PL_64K          16
253 #define PL_256K         18
254 #define PL_1M           20
255 #define PL_4M           22
256 #define PL_16M          24
257 #define PL_64M          26
258 #define PL_256M         28
259
260 /*
261  * PageGrain bits
262  */
263 #define PG_RIE          (_ULCAST_(1) <<  31)
264 #define PG_XIE          (_ULCAST_(1) <<  30)
265 #define PG_ELPA         (_ULCAST_(1) <<  29)
266 #define PG_ESP          (_ULCAST_(1) <<  28)
267
268 /*
269  * R4x00 interrupt enable / cause bits
270  */
271 #define IE_SW0          (_ULCAST_(1) <<  8)
272 #define IE_SW1          (_ULCAST_(1) <<  9)
273 #define IE_IRQ0         (_ULCAST_(1) << 10)
274 #define IE_IRQ1         (_ULCAST_(1) << 11)
275 #define IE_IRQ2         (_ULCAST_(1) << 12)
276 #define IE_IRQ3         (_ULCAST_(1) << 13)
277 #define IE_IRQ4         (_ULCAST_(1) << 14)
278 #define IE_IRQ5         (_ULCAST_(1) << 15)
279
280 /*
281  * R4x00 interrupt cause bits
282  */
283 #define C_SW0           (_ULCAST_(1) <<  8)
284 #define C_SW1           (_ULCAST_(1) <<  9)
285 #define C_IRQ0          (_ULCAST_(1) << 10)
286 #define C_IRQ1          (_ULCAST_(1) << 11)
287 #define C_IRQ2          (_ULCAST_(1) << 12)
288 #define C_IRQ3          (_ULCAST_(1) << 13)
289 #define C_IRQ4          (_ULCAST_(1) << 14)
290 #define C_IRQ5          (_ULCAST_(1) << 15)
291
292 /*
293  * Bitfields in the R4xx0 cp0 status register
294  */
295 #define ST0_IE                  0x00000001
296 #define ST0_EXL                 0x00000002
297 #define ST0_ERL                 0x00000004
298 #define ST0_KSU                 0x00000018
299 #  define KSU_USER              0x00000010
300 #  define KSU_SUPERVISOR        0x00000008
301 #  define KSU_KERNEL            0x00000000
302 #define ST0_UX                  0x00000020
303 #define ST0_SX                  0x00000040
304 #define ST0_KX                  0x00000080
305 #define ST0_DE                  0x00010000
306 #define ST0_CE                  0x00020000
307
308 /*
309  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
310  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
311  * processors.
312  */
313 #define ST0_CO                  0x08000000
314
315 /*
316  * Bitfields in the R[23]000 cp0 status register.
317  */
318 #define ST0_IEC                 0x00000001
319 #define ST0_KUC                 0x00000002
320 #define ST0_IEP                 0x00000004
321 #define ST0_KUP                 0x00000008
322 #define ST0_IEO                 0x00000010
323 #define ST0_KUO                 0x00000020
324 /* bits 6 & 7 are reserved on R[23]000 */
325 #define ST0_ISC                 0x00010000
326 #define ST0_SWC                 0x00020000
327 #define ST0_CM                  0x00080000
328
329 /*
330  * Bits specific to the R4640/R4650
331  */
332 #define ST0_UM                  (_ULCAST_(1) <<  4)
333 #define ST0_IL                  (_ULCAST_(1) << 23)
334 #define ST0_DL                  (_ULCAST_(1) << 24)
335
336 /*
337  * Enable the MIPS MDMX and DSP ASEs
338  */
339 #define ST0_MX                  0x01000000
340
341 /*
342  * Bitfields in the TX39 family CP0 Configuration Register 3
343  */
344 #define TX39_CONF_ICS_SHIFT     19
345 #define TX39_CONF_ICS_MASK      0x00380000
346 #define TX39_CONF_ICS_1KB       0x00000000
347 #define TX39_CONF_ICS_2KB       0x00080000
348 #define TX39_CONF_ICS_4KB       0x00100000
349 #define TX39_CONF_ICS_8KB       0x00180000
350 #define TX39_CONF_ICS_16KB      0x00200000
351
352 #define TX39_CONF_DCS_SHIFT     16
353 #define TX39_CONF_DCS_MASK      0x00070000
354 #define TX39_CONF_DCS_1KB       0x00000000
355 #define TX39_CONF_DCS_2KB       0x00010000
356 #define TX39_CONF_DCS_4KB       0x00020000
357 #define TX39_CONF_DCS_8KB       0x00030000
358 #define TX39_CONF_DCS_16KB      0x00040000
359
360 #define TX39_CONF_CWFON         0x00004000
361 #define TX39_CONF_WBON          0x00002000
362 #define TX39_CONF_RF_SHIFT      10
363 #define TX39_CONF_RF_MASK       0x00000c00
364 #define TX39_CONF_DOZE          0x00000200
365 #define TX39_CONF_HALT          0x00000100
366 #define TX39_CONF_LOCK          0x00000080
367 #define TX39_CONF_ICE           0x00000020
368 #define TX39_CONF_DCE           0x00000010
369 #define TX39_CONF_IRSIZE_SHIFT  2
370 #define TX39_CONF_IRSIZE_MASK   0x0000000c
371 #define TX39_CONF_DRSIZE_SHIFT  0
372 #define TX39_CONF_DRSIZE_MASK   0x00000003
373
374 /*
375  * Status register bits available in all MIPS CPUs.
376  */
377 #define ST0_IM                  0x0000ff00
378 #define  STATUSB_IP0            8
379 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
380 #define  STATUSB_IP1            9
381 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
382 #define  STATUSB_IP2            10
383 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
384 #define  STATUSB_IP3            11
385 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
386 #define  STATUSB_IP4            12
387 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
388 #define  STATUSB_IP5            13
389 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
390 #define  STATUSB_IP6            14
391 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
392 #define  STATUSB_IP7            15
393 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
394 #define  STATUSB_IP8            0
395 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
396 #define  STATUSB_IP9            1
397 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
398 #define  STATUSB_IP10           2
399 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
400 #define  STATUSB_IP11           3
401 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
402 #define  STATUSB_IP12           4
403 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
404 #define  STATUSB_IP13           5
405 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
406 #define  STATUSB_IP14           6
407 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
408 #define  STATUSB_IP15           7
409 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
410 #define ST0_CH                  0x00040000
411 #define ST0_SR                  0x00100000
412 #define ST0_TS                  0x00200000
413 #define ST0_BEV                 0x00400000
414 #define ST0_RE                  0x02000000
415 #define ST0_FR                  0x04000000
416 #define ST0_CU                  0xf0000000
417 #define ST0_CU0                 0x10000000
418 #define ST0_CU1                 0x20000000
419 #define ST0_CU2                 0x40000000
420 #define ST0_CU3                 0x80000000
421 #define ST0_XX                  0x80000000      /* MIPS IV naming */
422
423 /*
424  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
425  *
426  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
427  */
428 #define INTCTLB_IPPCI           26
429 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
430 #define INTCTLB_IPTI            29
431 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
432
433 /*
434  * Bitfields and bit numbers in the coprocessor 0 cause register.
435  *
436  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
437  */
438 #define  CAUSEB_EXCCODE         2
439 #define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
440 #define  CAUSEB_IP              8
441 #define  CAUSEF_IP              (_ULCAST_(255) <<  8)
442 #define  CAUSEB_IP0             8
443 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
444 #define  CAUSEB_IP1             9
445 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
446 #define  CAUSEB_IP2             10
447 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
448 #define  CAUSEB_IP3             11
449 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
450 #define  CAUSEB_IP4             12
451 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
452 #define  CAUSEB_IP5             13
453 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
454 #define  CAUSEB_IP6             14
455 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
456 #define  CAUSEB_IP7             15
457 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
458 #define  CAUSEB_IV              23
459 #define  CAUSEF_IV              (_ULCAST_(1)   << 23)
460 #define  CAUSEB_CE              28
461 #define  CAUSEF_CE              (_ULCAST_(3)   << 28)
462 #define  CAUSEB_TI              30
463 #define  CAUSEF_TI              (_ULCAST_(1)   << 30)
464 #define  CAUSEB_BD              31
465 #define  CAUSEF_BD              (_ULCAST_(1)   << 31)
466
467 /*
468  * Bits in the coprocessor 0 config register.
469  */
470 /* Generic bits.  */
471 #define CONF_CM_CACHABLE_NO_WA          0
472 #define CONF_CM_CACHABLE_WA             1
473 #define CONF_CM_UNCACHED                2
474 #define CONF_CM_CACHABLE_NONCOHERENT    3
475 #define CONF_CM_CACHABLE_CE             4
476 #define CONF_CM_CACHABLE_COW            5
477 #define CONF_CM_CACHABLE_CUW            6
478 #define CONF_CM_CACHABLE_ACCELERATED    7
479 #define CONF_CM_CMASK                   7
480 #define CONF_BE                 (_ULCAST_(1) << 15)
481
482 /* Bits common to various processors.  */
483 #define CONF_CU                 (_ULCAST_(1) <<  3)
484 #define CONF_DB                 (_ULCAST_(1) <<  4)
485 #define CONF_IB                 (_ULCAST_(1) <<  5)
486 #define CONF_DC                 (_ULCAST_(7) <<  6)
487 #define CONF_IC                 (_ULCAST_(7) <<  9)
488 #define CONF_EB                 (_ULCAST_(1) << 13)
489 #define CONF_EM                 (_ULCAST_(1) << 14)
490 #define CONF_SM                 (_ULCAST_(1) << 16)
491 #define CONF_SC                 (_ULCAST_(1) << 17)
492 #define CONF_EW                 (_ULCAST_(3) << 18)
493 #define CONF_EP                 (_ULCAST_(15)<< 24)
494 #define CONF_EC                 (_ULCAST_(7) << 28)
495 #define CONF_CM                 (_ULCAST_(1) << 31)
496
497 /* Bits specific to the R4xx0.  */
498 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
499 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
500 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
501
502 /* Bits specific to the R5000.  */
503 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
504 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
505
506 /* Bits specific to the RM7000.  */
507 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
508 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
509 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
510 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
511 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
512 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
513
514 /* Bits specific to the R10000.  */
515 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
516 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
517 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
518 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
519 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
520 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
521 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
522 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
523 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
524 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
525 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
526
527 /* Bits specific to the VR41xx.  */
528 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
529 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
530 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
531 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
532 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
533
534 /* Bits specific to the R30xx.  */
535 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
536 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
537 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
538 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
539 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
540 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
541 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
542 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
543 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
544
545 /* Bits specific to the TX49.  */
546 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
547 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
548 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
549 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
550
551 /* Bits specific to the MIPS32/64 PRA.  */
552 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
553 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
554 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
555 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
556
557 /*
558  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
559  */
560 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
561 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
562 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
563 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
564 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
565 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
566 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
567 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
568 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
569 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
570 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
571 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
572 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
573 #define MIPS_CONF1_TLBS         (_ULCAST_(63)<< 25)
574
575 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
576 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
577 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
578 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
579 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
580 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
581 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
582 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
583
584 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
585 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
586 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
587 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
588 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
589 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
590 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
591 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
592 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
593
594 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
595 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
596 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
597
598 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
599
600 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
601
602
603 /*
604  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
605  */
606 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
607 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
608 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
609 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
610 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
611 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
612 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
613
614 #ifndef __ASSEMBLY__
615
616 /*
617  * Functions to access the R10000 performance counters.  These are basically
618  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
619  * performance counter number encoded into bits 1 ... 5 of the instruction.
620  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
621  * disassembler these will look like an access to sel 0 or 1.
622  */
623 #define read_r10k_perf_cntr(counter)                            \
624 ({                                                              \
625         unsigned int __res;                                     \
626         __asm__ __volatile__(                                   \
627         "mfpc\t%0, %1"                                          \
628         : "=r" (__res)                                          \
629         : "i" (counter));                                       \
630                                                                 \
631         __res;                                                  \
632 })
633
634 #define write_r10k_perf_cntr(counter,val)                       \
635 do {                                                            \
636         __asm__ __volatile__(                                   \
637         "mtpc\t%0, %1"                                          \
638         :                                                       \
639         : "r" (val), "i" (counter));                            \
640 } while (0)
641
642 #define read_r10k_perf_event(counter)                           \
643 ({                                                              \
644         unsigned int __res;                                     \
645         __asm__ __volatile__(                                   \
646         "mfps\t%0, %1"                                          \
647         : "=r" (__res)                                          \
648         : "i" (counter));                                       \
649                                                                 \
650         __res;                                                  \
651 })
652
653 #define write_r10k_perf_cntl(counter,val)                       \
654 do {                                                            \
655         __asm__ __volatile__(                                   \
656         "mtps\t%0, %1"                                          \
657         :                                                       \
658         : "r" (val), "i" (counter));                            \
659 } while (0)
660
661
662 /*
663  * Macros to access the system control coprocessor
664  */
665
666 #define __read_32bit_c0_register(source, sel)                           \
667 ({ int __res;                                                           \
668         if (sel == 0)                                                   \
669                 __asm__ __volatile__(                                   \
670                         "mfc0\t%0, " #source "\n\t"                     \
671                         : "=r" (__res));                                \
672         else                                                            \
673                 __asm__ __volatile__(                                   \
674                         ".set\tmips32\n\t"                              \
675                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
676                         ".set\tmips0\n\t"                               \
677                         : "=r" (__res));                                \
678         __res;                                                          \
679 })
680
681 #define __read_64bit_c0_register(source, sel)                           \
682 ({ unsigned long long __res;                                            \
683         if (sizeof(unsigned long) == 4)                                 \
684                 __res = __read_64bit_c0_split(source, sel);             \
685         else if (sel == 0)                                              \
686                 __asm__ __volatile__(                                   \
687                         ".set\tmips3\n\t"                               \
688                         "dmfc0\t%0, " #source "\n\t"                    \
689                         ".set\tmips0"                                   \
690                         : "=r" (__res));                                \
691         else                                                            \
692                 __asm__ __volatile__(                                   \
693                         ".set\tmips64\n\t"                              \
694                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
695                         ".set\tmips0"                                   \
696                         : "=r" (__res));                                \
697         __res;                                                          \
698 })
699
700 #define __write_32bit_c0_register(register, sel, value)                 \
701 do {                                                                    \
702         if (sel == 0)                                                   \
703                 __asm__ __volatile__(                                   \
704                         "mtc0\t%z0, " #register "\n\t"                  \
705                         : : "Jr" ((unsigned int)(value)));              \
706         else                                                            \
707                 __asm__ __volatile__(                                   \
708                         ".set\tmips32\n\t"                              \
709                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
710                         ".set\tmips0"                                   \
711                         : : "Jr" ((unsigned int)(value)));              \
712 } while (0)
713
714 #define __write_64bit_c0_register(register, sel, value)                 \
715 do {                                                                    \
716         if (sizeof(unsigned long) == 4)                                 \
717                 __write_64bit_c0_split(register, sel, value);           \
718         else if (sel == 0)                                              \
719                 __asm__ __volatile__(                                   \
720                         ".set\tmips3\n\t"                               \
721                         "dmtc0\t%z0, " #register "\n\t"                 \
722                         ".set\tmips0"                                   \
723                         : : "Jr" (value));                              \
724         else                                                            \
725                 __asm__ __volatile__(                                   \
726                         ".set\tmips64\n\t"                              \
727                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
728                         ".set\tmips0"                                   \
729                         : : "Jr" (value));                              \
730 } while (0)
731
732 #define __read_ulong_c0_register(reg, sel)                              \
733         ((sizeof(unsigned long) == 4) ?                                 \
734         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
735         (unsigned long) __read_64bit_c0_register(reg, sel))
736
737 #define __write_ulong_c0_register(reg, sel, val)                        \
738 do {                                                                    \
739         if (sizeof(unsigned long) == 4)                                 \
740                 __write_32bit_c0_register(reg, sel, val);               \
741         else                                                            \
742                 __write_64bit_c0_register(reg, sel, val);               \
743 } while (0)
744
745 /*
746  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
747  */
748 #define __read_32bit_c0_ctrl_register(source)                           \
749 ({ int __res;                                                           \
750         __asm__ __volatile__(                                           \
751                 "cfc0\t%0, " #source "\n\t"                             \
752                 : "=r" (__res));                                        \
753         __res;                                                          \
754 })
755
756 #define __write_32bit_c0_ctrl_register(register, value)                 \
757 do {                                                                    \
758         __asm__ __volatile__(                                           \
759                 "ctc0\t%z0, " #register "\n\t"                          \
760                 : : "Jr" ((unsigned int)(value)));                      \
761 } while (0)
762
763 /*
764  * These versions are only needed for systems with more than 38 bits of
765  * physical address space running the 32-bit kernel.  That's none atm :-)
766  */
767 #define __read_64bit_c0_split(source, sel)                              \
768 ({                                                                      \
769         unsigned long long __val;                                       \
770         unsigned long __flags;                                          \
771                                                                         \
772         local_irq_save(__flags);                                        \
773         if (sel == 0)                                                   \
774                 __asm__ __volatile__(                                   \
775                         ".set\tmips64\n\t"                              \
776                         "dmfc0\t%M0, " #source "\n\t"                   \
777                         "dsll\t%L0, %M0, 32\n\t"                        \
778                         "dsra\t%M0, %M0, 32\n\t"                        \
779                         "dsra\t%L0, %L0, 32\n\t"                        \
780                         ".set\tmips0"                                   \
781                         : "=r" (__val));                                \
782         else                                                            \
783                 __asm__ __volatile__(                                   \
784                         ".set\tmips64\n\t"                              \
785                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
786                         "dsll\t%L0, %M0, 32\n\t"                        \
787                         "dsra\t%M0, %M0, 32\n\t"                        \
788                         "dsra\t%L0, %L0, 32\n\t"                        \
789                         ".set\tmips0"                                   \
790                         : "=r" (__val));                                \
791         local_irq_restore(__flags);                                     \
792                                                                         \
793         __val;                                                          \
794 })
795
796 #define __write_64bit_c0_split(source, sel, val)                        \
797 do {                                                                    \
798         unsigned long __flags;                                          \
799                                                                         \
800         local_irq_save(__flags);                                        \
801         if (sel == 0)                                                   \
802                 __asm__ __volatile__(                                   \
803                         ".set\tmips64\n\t"                              \
804                         "dsll\t%L0, %L0, 32\n\t"                        \
805                         "dsrl\t%L0, %L0, 32\n\t"                        \
806                         "dsll\t%M0, %M0, 32\n\t"                        \
807                         "or\t%L0, %L0, %M0\n\t"                         \
808                         "dmtc0\t%L0, " #source "\n\t"                   \
809                         ".set\tmips0"                                   \
810                         : : "r" (val));                                 \
811         else                                                            \
812                 __asm__ __volatile__(                                   \
813                         ".set\tmips64\n\t"                              \
814                         "dsll\t%L0, %L0, 32\n\t"                        \
815                         "dsrl\t%L0, %L0, 32\n\t"                        \
816                         "dsll\t%M0, %M0, 32\n\t"                        \
817                         "or\t%L0, %L0, %M0\n\t"                         \
818                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
819                         ".set\tmips0"                                   \
820                         : : "r" (val));                                 \
821         local_irq_restore(__flags);                                     \
822 } while (0)
823
824 #define read_c0_index()         __read_32bit_c0_register($0, 0)
825 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
826
827 #define read_c0_random()        __read_32bit_c0_register($1, 0)
828 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
829
830 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
831 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
832
833 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
834 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
835
836 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
837 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
838
839 #define read_c0_context()       __read_ulong_c0_register($4, 0)
840 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
841
842 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
843 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
844
845 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
846 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
847
848 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
849 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
850
851 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
852 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
853
854 #define read_c0_info()          __read_32bit_c0_register($7, 0)
855
856 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
857 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
858
859 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
860 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
861
862 #define read_c0_count()         __read_32bit_c0_register($9, 0)
863 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
864
865 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
866 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
867
868 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
869 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
870
871 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
872 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
873
874 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
875 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
876
877 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
878 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
879
880 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
881 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
882
883 #define read_c0_status()        __read_32bit_c0_register($12, 0)
884 #ifdef CONFIG_MIPS_MT_SMTC
885 #define write_c0_status(val)                                            \
886 do {                                                                    \
887         __write_32bit_c0_register($12, 0, val);                         \
888         __ehb();                                                        \
889 } while (0)
890 #else
891 /*
892  * Legacy non-SMTC code, which may be hazardous
893  * but which might not support EHB
894  */
895 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
896 #endif /* CONFIG_MIPS_MT_SMTC */
897
898 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
899 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
900
901 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
902 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
903
904 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
905
906 #define read_c0_config()        __read_32bit_c0_register($16, 0)
907 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
908 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
909 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
910 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
911 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
912 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
913 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
914 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
915 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
916 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
917 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
918 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
919 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
920 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
921 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
922
923 /*
924  * The WatchLo register.  There may be upto 8 of them.
925  */
926 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
927 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
928 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
929 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
930 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
931 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
932 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
933 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
934 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
935 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
936 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
937 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
938 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
939 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
940 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
941 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
942
943 /*
944  * The WatchHi register.  There may be upto 8 of them.
945  */
946 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
947 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
948 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
949 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
950 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
951 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
952 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
953 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
954
955 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
956 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
957 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
958 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
959 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
960 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
961 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
962 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
963
964 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
965 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
966
967 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
968 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
969
970 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
971 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
972
973 /* RM9000 PerfControl performance counter control register */
974 #define read_c0_perfcontrol()   __read_32bit_c0_register($22, 0)
975 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
976
977 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
978 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
979
980 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
981 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
982
983 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
984 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
985
986 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
987 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
988
989 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
990 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
991
992 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
993 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
994
995 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
996 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
997
998 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
999 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1000
1001 /*
1002  * MIPS32 / MIPS64 performance counters
1003  */
1004 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1005 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1006 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1007 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1008 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1009 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1010 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1011 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1012 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1013 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1014 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1015 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1016 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1017 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1018 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1019 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1020
1021 /* RM9000 PerfCount performance counter register */
1022 #define read_c0_perfcount()     __read_64bit_c0_register($25, 0)
1023 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
1024
1025 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1026 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1027
1028 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1029 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1030
1031 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1032
1033 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1034 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1035
1036 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1037 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1038
1039 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1040 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1041
1042 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1043 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1044
1045 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1046 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1047
1048 /* MIPSR2 */
1049 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1050 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1051
1052 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1053 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1054
1055 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1056 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1057
1058 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1059 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1060
1061 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1062 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1063
1064
1065 /* Cavium OCTEON (cnMIPS) */
1066 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1067 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1068
1069 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1070 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1071
1072 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1073 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1074 /*
1075  * The cacheerr registers are not standardized.  On OCTEON, they are
1076  * 64 bits wide.
1077  */
1078 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1079 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1080
1081 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1082 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1083
1084 /*
1085  * Macros to access the floating point coprocessor control registers
1086  */
1087 #define read_32bit_cp1_register(source)                         \
1088 ({ int __res;                                                   \
1089         __asm__ __volatile__(                                   \
1090         ".set\tpush\n\t"                                        \
1091         ".set\treorder\n\t"                                     \
1092         /* gas fails to assemble cfc1 for some archs (octeon).*/ \
1093         ".set\tmips1\n\t"                                       \
1094         "cfc1\t%0,"STR(source)"\n\t"                            \
1095         ".set\tpop"                                             \
1096         : "=r" (__res));                                        \
1097         __res;})
1098
1099 #define rddsp(mask)                                                     \
1100 ({                                                                      \
1101         unsigned int __res;                                             \
1102                                                                         \
1103         __asm__ __volatile__(                                           \
1104         "       .set    push                            \n"             \
1105         "       .set    noat                            \n"             \
1106         "       # rddsp $1, %x1                         \n"             \
1107         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1108         "       move    %0, $1                          \n"             \
1109         "       .set    pop                             \n"             \
1110         : "=r" (__res)                                                  \
1111         : "i" (mask));                                                  \
1112         __res;                                                          \
1113 })
1114
1115 #define wrdsp(val, mask)                                                \
1116 do {                                                                    \
1117         __asm__ __volatile__(                                           \
1118         "       .set    push                                    \n"     \
1119         "       .set    noat                                    \n"     \
1120         "       move    $1, %0                                  \n"     \
1121         "       # wrdsp $1, %x1                                 \n"     \
1122         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1123         "       .set    pop                                     \n"     \
1124         :                                                               \
1125         : "r" (val), "i" (mask));                                       \
1126 } while (0)
1127
1128 #if 0   /* Need DSP ASE capable assembler ... */
1129 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1130 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1131 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
1132 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
1133
1134 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
1135 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
1136 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
1137 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
1138
1139 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
1140 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
1141 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
1142 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
1143
1144 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
1145 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
1146 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
1147 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1148
1149 #else
1150
1151 #define mfhi0()                                                         \
1152 ({                                                                      \
1153         unsigned long __treg;                                           \
1154                                                                         \
1155         __asm__ __volatile__(                                           \
1156         "       .set    push                    \n"                     \
1157         "       .set    noat                    \n"                     \
1158         "       # mfhi  %0, $ac0                \n"                     \
1159         "       .word   0x00000810              \n"                     \
1160         "       move    %0, $1                  \n"                     \
1161         "       .set    pop                     \n"                     \
1162         : "=r" (__treg));                                               \
1163         __treg;                                                         \
1164 })
1165
1166 #define mfhi1()                                                         \
1167 ({                                                                      \
1168         unsigned long __treg;                                           \
1169                                                                         \
1170         __asm__ __volatile__(                                           \
1171         "       .set    push                    \n"                     \
1172         "       .set    noat                    \n"                     \
1173         "       # mfhi  %0, $ac1                \n"                     \
1174         "       .word   0x00200810              \n"                     \
1175         "       move    %0, $1                  \n"                     \
1176         "       .set    pop                     \n"                     \
1177         : "=r" (__treg));                                               \
1178         __treg;                                                         \
1179 })
1180
1181 #define mfhi2()                                                         \
1182 ({                                                                      \
1183         unsigned long __treg;                                           \
1184                                                                         \
1185         __asm__ __volatile__(                                           \
1186         "       .set    push                    \n"                     \
1187         "       .set    noat                    \n"                     \
1188         "       # mfhi  %0, $ac2                \n"                     \
1189         "       .word   0x00400810              \n"                     \
1190         "       move    %0, $1                  \n"                     \
1191         "       .set    pop                     \n"                     \
1192         : "=r" (__treg));                                               \
1193         __treg;                                                         \
1194 })
1195
1196 #define mfhi3()                                                         \
1197 ({                                                                      \
1198         unsigned long __treg;                                           \
1199                                                                         \
1200         __asm__ __volatile__(                                           \
1201         "       .set    push                    \n"                     \
1202         "       .set    noat                    \n"                     \
1203         "       # mfhi  %0, $ac3                \n"                     \
1204         "       .word   0x00600810              \n"                     \
1205         "       move    %0, $1                  \n"                     \
1206         "       .set    pop                     \n"                     \
1207         : "=r" (__treg));                                               \
1208         __treg;                                                         \
1209 })
1210
1211 #define mflo0()                                                         \
1212 ({                                                                      \
1213         unsigned long __treg;                                           \
1214                                                                         \
1215         __asm__ __volatile__(                                           \
1216         "       .set    push                    \n"                     \
1217         "       .set    noat                    \n"                     \
1218         "       # mflo  %0, $ac0                \n"                     \
1219         "       .word   0x00000812              \n"                     \
1220         "       move    %0, $1                  \n"                     \
1221         "       .set    pop                     \n"                     \
1222         : "=r" (__treg));                                               \
1223         __treg;                                                         \
1224 })
1225
1226 #define mflo1()                                                         \
1227 ({                                                                      \
1228         unsigned long __treg;                                           \
1229                                                                         \
1230         __asm__ __volatile__(                                           \
1231         "       .set    push                    \n"                     \
1232         "       .set    noat                    \n"                     \
1233         "       # mflo  %0, $ac1                \n"                     \
1234         "       .word   0x00200812              \n"                     \
1235         "       move    %0, $1                  \n"                     \
1236         "       .set    pop                     \n"                     \
1237         : "=r" (__treg));                                               \
1238         __treg;                                                         \
1239 })
1240
1241 #define mflo2()                                                         \
1242 ({                                                                      \
1243         unsigned long __treg;                                           \
1244                                                                         \
1245         __asm__ __volatile__(                                           \
1246         "       .set    push                    \n"                     \
1247         "       .set    noat                    \n"                     \
1248         "       # mflo  %0, $ac2                \n"                     \
1249         "       .word   0x00400812              \n"                     \
1250         "       move    %0, $1                  \n"                     \
1251         "       .set    pop                     \n"                     \
1252         : "=r" (__treg));                                               \
1253         __treg;                                                         \
1254 })
1255
1256 #define mflo3()                                                         \
1257 ({                                                                      \
1258         unsigned long __treg;                                           \
1259                                                                         \
1260         __asm__ __volatile__(                                           \
1261         "       .set    push                    \n"                     \
1262         "       .set    noat                    \n"                     \
1263         "       # mflo  %0, $ac3                \n"                     \
1264         "       .word   0x00600812              \n"                     \
1265         "       move    %0, $1                  \n"                     \
1266         "       .set    pop                     \n"                     \
1267         : "=r" (__treg));                                               \
1268         __treg;                                                         \
1269 })
1270
1271 #define mthi0(x)                                                        \
1272 do {                                                                    \
1273         __asm__ __volatile__(                                           \
1274         "       .set    push                                    \n"     \
1275         "       .set    noat                                    \n"     \
1276         "       move    $1, %0                                  \n"     \
1277         "       # mthi  $1, $ac0                                \n"     \
1278         "       .word   0x00200011                              \n"     \
1279         "       .set    pop                                     \n"     \
1280         :                                                               \
1281         : "r" (x));                                                     \
1282 } while (0)
1283
1284 #define mthi1(x)                                                        \
1285 do {                                                                    \
1286         __asm__ __volatile__(                                           \
1287         "       .set    push                                    \n"     \
1288         "       .set    noat                                    \n"     \
1289         "       move    $1, %0                                  \n"     \
1290         "       # mthi  $1, $ac1                                \n"     \
1291         "       .word   0x00200811                              \n"     \
1292         "       .set    pop                                     \n"     \
1293         :                                                               \
1294         : "r" (x));                                                     \
1295 } while (0)
1296
1297 #define mthi2(x)                                                        \
1298 do {                                                                    \
1299         __asm__ __volatile__(                                           \
1300         "       .set    push                                    \n"     \
1301         "       .set    noat                                    \n"     \
1302         "       move    $1, %0                                  \n"     \
1303         "       # mthi  $1, $ac2                                \n"     \
1304         "       .word   0x00201011                              \n"     \
1305         "       .set    pop                                     \n"     \
1306         :                                                               \
1307         : "r" (x));                                                     \
1308 } while (0)
1309
1310 #define mthi3(x)                                                        \
1311 do {                                                                    \
1312         __asm__ __volatile__(                                           \
1313         "       .set    push                                    \n"     \
1314         "       .set    noat                                    \n"     \
1315         "       move    $1, %0                                  \n"     \
1316         "       # mthi  $1, $ac3                                \n"     \
1317         "       .word   0x00201811                              \n"     \
1318         "       .set    pop                                     \n"     \
1319         :                                                               \
1320         : "r" (x));                                                     \
1321 } while (0)
1322
1323 #define mtlo0(x)                                                        \
1324 do {                                                                    \
1325         __asm__ __volatile__(                                           \
1326         "       .set    push                                    \n"     \
1327         "       .set    noat                                    \n"     \
1328         "       move    $1, %0                                  \n"     \
1329         "       # mtlo  $1, $ac0                                \n"     \
1330         "       .word   0x00200013                              \n"     \
1331         "       .set    pop                                     \n"     \
1332         :                                                               \
1333         : "r" (x));                                                     \
1334 } while (0)
1335
1336 #define mtlo1(x)                                                        \
1337 do {                                                                    \
1338         __asm__ __volatile__(                                           \
1339         "       .set    push                                    \n"     \
1340         "       .set    noat                                    \n"     \
1341         "       move    $1, %0                                  \n"     \
1342         "       # mtlo  $1, $ac1                                \n"     \
1343         "       .word   0x00200813                              \n"     \
1344         "       .set    pop                                     \n"     \
1345         :                                                               \
1346         : "r" (x));                                                     \
1347 } while (0)
1348
1349 #define mtlo2(x)                                                        \
1350 do {                                                                    \
1351         __asm__ __volatile__(                                           \
1352         "       .set    push                                    \n"     \
1353         "       .set    noat                                    \n"     \
1354         "       move    $1, %0                                  \n"     \
1355         "       # mtlo  $1, $ac2                                \n"     \
1356         "       .word   0x00201013                              \n"     \
1357         "       .set    pop                                     \n"     \
1358         :                                                               \
1359         : "r" (x));                                                     \
1360 } while (0)
1361
1362 #define mtlo3(x)                                                        \
1363 do {                                                                    \
1364         __asm__ __volatile__(                                           \
1365         "       .set    push                                    \n"     \
1366         "       .set    noat                                    \n"     \
1367         "       move    $1, %0                                  \n"     \
1368         "       # mtlo  $1, $ac3                                \n"     \
1369         "       .word   0x00201813                              \n"     \
1370         "       .set    pop                                     \n"     \
1371         :                                                               \
1372         : "r" (x));                                                     \
1373 } while (0)
1374
1375 #endif
1376
1377 /*
1378  * TLB operations.
1379  *
1380  * It is responsibility of the caller to take care of any TLB hazards.
1381  */
1382 static inline void tlb_probe(void)
1383 {
1384         __asm__ __volatile__(
1385                 ".set noreorder\n\t"
1386                 "tlbp\n\t"
1387                 ".set reorder");
1388 }
1389
1390 static inline void tlb_read(void)
1391 {
1392 #if MIPS34K_MISSED_ITLB_WAR
1393         int res = 0;
1394
1395         __asm__ __volatile__(
1396         "       .set    push                                    \n"
1397         "       .set    noreorder                               \n"
1398         "       .set    noat                                    \n"
1399         "       .set    mips32r2                                \n"
1400         "       .word   0x41610001              # dvpe $1       \n"
1401         "       move    %0, $1                                  \n"
1402         "       ehb                                             \n"
1403         "       .set    pop                                     \n"
1404         : "=r" (res));
1405
1406         instruction_hazard();
1407 #endif
1408
1409         __asm__ __volatile__(
1410                 ".set noreorder\n\t"
1411                 "tlbr\n\t"
1412                 ".set reorder");
1413
1414 #if MIPS34K_MISSED_ITLB_WAR
1415         if ((res & _ULCAST_(1)))
1416                 __asm__ __volatile__(
1417                 "       .set    push                            \n"
1418                 "       .set    noreorder                       \n"
1419                 "       .set    noat                            \n"
1420                 "       .set    mips32r2                        \n"
1421                 "       .word   0x41600021      # evpe          \n"
1422                 "       ehb                                     \n"
1423                 "       .set    pop                             \n");
1424 #endif
1425 }
1426
1427 static inline void tlb_write_indexed(void)
1428 {
1429         __asm__ __volatile__(
1430                 ".set noreorder\n\t"
1431                 "tlbwi\n\t"
1432                 ".set reorder");
1433 }
1434
1435 static inline void tlb_write_random(void)
1436 {
1437         __asm__ __volatile__(
1438                 ".set noreorder\n\t"
1439                 "tlbwr\n\t"
1440                 ".set reorder");
1441 }
1442
1443 /*
1444  * Manipulate bits in a c0 register.
1445  */
1446 #ifndef CONFIG_MIPS_MT_SMTC
1447 /*
1448  * SMTC Linux requires shutting-down microthread scheduling
1449  * during CP0 register read-modify-write sequences.
1450  */
1451 #define __BUILD_SET_C0(name)                                    \
1452 static inline unsigned int                                      \
1453 set_c0_##name(unsigned int set)                                 \
1454 {                                                               \
1455         unsigned int res, new;                                  \
1456                                                                 \
1457         res = read_c0_##name();                                 \
1458         new = res | set;                                        \
1459         write_c0_##name(new);                                   \
1460                                                                 \
1461         return res;                                             \
1462 }                                                               \
1463                                                                 \
1464 static inline unsigned int                                      \
1465 clear_c0_##name(unsigned int clear)                             \
1466 {                                                               \
1467         unsigned int res, new;                                  \
1468                                                                 \
1469         res = read_c0_##name();                                 \
1470         new = res & ~clear;                                     \
1471         write_c0_##name(new);                                   \
1472                                                                 \
1473         return res;                                             \
1474 }                                                               \
1475                                                                 \
1476 static inline unsigned int                                      \
1477 change_c0_##name(unsigned int change, unsigned int val)         \
1478 {                                                               \
1479         unsigned int res, new;                                  \
1480                                                                 \
1481         res = read_c0_##name();                                 \
1482         new = res & ~change;                                    \
1483         new |= (val & change);                                  \
1484         write_c0_##name(new);                                   \
1485                                                                 \
1486         return res;                                             \
1487 }
1488
1489 #else /* SMTC versions that manage MT scheduling */
1490
1491 #include <linux/irqflags.h>
1492
1493 /*
1494  * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
1495  * header file recursion.
1496  */
1497 static inline unsigned int __dmt(void)
1498 {
1499         int res;
1500
1501         __asm__ __volatile__(
1502         "       .set    push                                            \n"
1503         "       .set    mips32r2                                        \n"
1504         "       .set    noat                                            \n"
1505         "       .word   0x41610BC1                      # dmt $1        \n"
1506         "       ehb                                                     \n"
1507         "       move    %0, $1                                          \n"
1508         "       .set    pop                                             \n"
1509         : "=r" (res));
1510
1511         instruction_hazard();
1512
1513         return res;
1514 }
1515
1516 #define __VPECONTROL_TE_SHIFT   15
1517 #define __VPECONTROL_TE         (1UL << __VPECONTROL_TE_SHIFT)
1518
1519 #define __EMT_ENABLE            __VPECONTROL_TE
1520
1521 static inline void __emt(unsigned int previous)
1522 {
1523         if ((previous & __EMT_ENABLE))
1524                 __asm__ __volatile__(
1525                 "       .set    mips32r2                                \n"
1526                 "       .word   0x41600be1              # emt           \n"
1527                 "       ehb                                             \n"
1528                 "       .set    mips0                                   \n");
1529 }
1530
1531 static inline void __ehb(void)
1532 {
1533         __asm__ __volatile__(
1534         "       .set    mips32r2                                        \n"
1535         "       ehb                                                     \n"             "       .set    mips0                                           \n");
1536 }
1537
1538 /*
1539  * Note that local_irq_save/restore affect TC-specific IXMT state,
1540  * not Status.IE as in non-SMTC kernel.
1541  */
1542
1543 #define __BUILD_SET_C0(name)                                    \
1544 static inline unsigned int                                      \
1545 set_c0_##name(unsigned int set)                                 \
1546 {                                                               \
1547         unsigned int res;                                       \
1548         unsigned int new;                                       \
1549         unsigned int omt;                                       \
1550         unsigned long flags;                                    \
1551                                                                 \
1552         local_irq_save(flags);                                  \
1553         omt = __dmt();                                          \
1554         res = read_c0_##name();                                 \
1555         new = res | set;                                        \
1556         write_c0_##name(new);                                   \
1557         __emt(omt);                                             \
1558         local_irq_restore(flags);                               \
1559                                                                 \
1560         return res;                                             \
1561 }                                                               \
1562                                                                 \
1563 static inline unsigned int                                      \
1564 clear_c0_##name(unsigned int clear)                             \
1565 {                                                               \
1566         unsigned int res;                                       \
1567         unsigned int new;                                       \
1568         unsigned int omt;                                       \
1569         unsigned long flags;                                    \
1570                                                                 \
1571         local_irq_save(flags);                                  \
1572         omt = __dmt();                                          \
1573         res = read_c0_##name();                                 \
1574         new = res & ~clear;                                     \
1575         write_c0_##name(new);                                   \
1576         __emt(omt);                                             \
1577         local_irq_restore(flags);                               \
1578                                                                 \
1579         return res;                                             \
1580 }                                                               \
1581                                                                 \
1582 static inline unsigned int                                      \
1583 change_c0_##name(unsigned int change, unsigned int newbits)     \
1584 {                                                               \
1585         unsigned int res;                                       \
1586         unsigned int new;                                       \
1587         unsigned int omt;                                       \
1588         unsigned long flags;                                    \
1589                                                                 \
1590         local_irq_save(flags);                                  \
1591                                                                 \
1592         omt = __dmt();                                          \
1593         res = read_c0_##name();                                 \
1594         new = res & ~change;                                    \
1595         new |= (newbits & change);                              \
1596         write_c0_##name(new);                                   \
1597         __emt(omt);                                             \
1598         local_irq_restore(flags);                               \
1599                                                                 \
1600         return res;                                             \
1601 }
1602 #endif
1603
1604 __BUILD_SET_C0(status)
1605 __BUILD_SET_C0(cause)
1606 __BUILD_SET_C0(config)
1607 __BUILD_SET_C0(intcontrol)
1608 __BUILD_SET_C0(intctl)
1609 __BUILD_SET_C0(srsmap)
1610
1611 #endif /* !__ASSEMBLY__ */
1612
1613 #endif /* _ASM_MIPSREGS_H */