Merge branch 'master' into export-slabh
[kernel.git] / drivers / gpu / drm / radeon / r300.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "radeon_reg.h"
33 #include "radeon.h"
34 #include "radeon_asic.h"
35 #include "radeon_drm.h"
36 #include "r100_track.h"
37 #include "r300d.h"
38 #include "rv350d.h"
39 #include "r300_reg_safe.h"
40
41 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
42  *
43  * GPU Errata:
44  * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
45  *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
46  *   However, scheduling such write to the ring seems harmless, i suspect
47  *   the CP read collide with the flush somehow, or maybe the MC, hard to
48  *   tell. (Jerome Glisse)
49  */
50
51 /*
52  * rv370,rv380 PCIE GART
53  */
54 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
55
56 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
57 {
58         uint32_t tmp;
59         int i;
60
61         /* Workaround HW bug do flush 2 times */
62         for (i = 0; i < 2; i++) {
63                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
64                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
65                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
66                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
67         }
68         mb();
69 }
70
71 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
72 {
73         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
74
75         if (i < 0 || i > rdev->gart.num_gpu_pages) {
76                 return -EINVAL;
77         }
78         addr = (lower_32_bits(addr) >> 8) |
79                ((upper_32_bits(addr) & 0xff) << 24) |
80                0xc;
81         /* on x86 we want this to be CPU endian, on powerpc
82          * on powerpc without HW swappers, it'll get swapped on way
83          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
84         writel(addr, ((void __iomem *)ptr) + (i * 4));
85         return 0;
86 }
87
88 int rv370_pcie_gart_init(struct radeon_device *rdev)
89 {
90         int r;
91
92         if (rdev->gart.table.vram.robj) {
93                 WARN(1, "RV370 PCIE GART already initialized.\n");
94                 return 0;
95         }
96         /* Initialize common gart structure */
97         r = radeon_gart_init(rdev);
98         if (r)
99                 return r;
100         r = rv370_debugfs_pcie_gart_info_init(rdev);
101         if (r)
102                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
103         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
104         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
105         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
106         return radeon_gart_table_vram_alloc(rdev);
107 }
108
109 int rv370_pcie_gart_enable(struct radeon_device *rdev)
110 {
111         uint32_t table_addr;
112         uint32_t tmp;
113         int r;
114
115         if (rdev->gart.table.vram.robj == NULL) {
116                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
117                 return -EINVAL;
118         }
119         r = radeon_gart_table_vram_pin(rdev);
120         if (r)
121                 return r;
122         radeon_gart_restore(rdev);
123         /* discard memory request outside of configured range */
124         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
125         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
126         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
127         tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
128         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
129         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
130         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
131         table_addr = rdev->gart.table_addr;
132         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
133         /* FIXME: setup default page */
134         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
135         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
136         /* Clear error */
137         WREG32_PCIE(0x18, 0);
138         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
139         tmp |= RADEON_PCIE_TX_GART_EN;
140         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
141         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
142         rv370_pcie_gart_tlb_flush(rdev);
143         DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
144                  (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
145         rdev->gart.ready = true;
146         return 0;
147 }
148
149 void rv370_pcie_gart_disable(struct radeon_device *rdev)
150 {
151         u32 tmp;
152         int r;
153
154         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
155         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
156         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
157         if (rdev->gart.table.vram.robj) {
158                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
159                 if (likely(r == 0)) {
160                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
161                         radeon_bo_unpin(rdev->gart.table.vram.robj);
162                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
163                 }
164         }
165 }
166
167 void rv370_pcie_gart_fini(struct radeon_device *rdev)
168 {
169         radeon_gart_fini(rdev);
170         rv370_pcie_gart_disable(rdev);
171         radeon_gart_table_vram_free(rdev);
172 }
173
174 void r300_fence_ring_emit(struct radeon_device *rdev,
175                           struct radeon_fence *fence)
176 {
177         /* Who ever call radeon_fence_emit should call ring_lock and ask
178          * for enough space (today caller are ib schedule and buffer move) */
179         /* Write SC register so SC & US assert idle */
180         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
181         radeon_ring_write(rdev, 0);
182         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
183         radeon_ring_write(rdev, 0);
184         /* Flush 3D cache */
185         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
186         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
187         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
188         radeon_ring_write(rdev, R300_ZC_FLUSH);
189         /* Wait until IDLE & CLEAN */
190         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
191         radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
192                                  RADEON_WAIT_2D_IDLECLEAN |
193                                  RADEON_WAIT_DMA_GUI_IDLE));
194         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
195         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
196                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
197         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
198         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
199         /* Emit fence sequence & fire IRQ */
200         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
201         radeon_ring_write(rdev, fence->seq);
202         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
203         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
204 }
205
206 void r300_ring_start(struct radeon_device *rdev)
207 {
208         unsigned gb_tile_config;
209         int r;
210
211         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
212         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
213         switch(rdev->num_gb_pipes) {
214         case 2:
215                 gb_tile_config |= R300_PIPE_COUNT_R300;
216                 break;
217         case 3:
218                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
219                 break;
220         case 4:
221                 gb_tile_config |= R300_PIPE_COUNT_R420;
222                 break;
223         case 1:
224         default:
225                 gb_tile_config |= R300_PIPE_COUNT_RV350;
226                 break;
227         }
228
229         r = radeon_ring_lock(rdev, 64);
230         if (r) {
231                 return;
232         }
233         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
234         radeon_ring_write(rdev,
235                           RADEON_ISYNC_ANY2D_IDLE3D |
236                           RADEON_ISYNC_ANY3D_IDLE2D |
237                           RADEON_ISYNC_WAIT_IDLEGUI |
238                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
239         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
240         radeon_ring_write(rdev, gb_tile_config);
241         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
242         radeon_ring_write(rdev,
243                           RADEON_WAIT_2D_IDLECLEAN |
244                           RADEON_WAIT_3D_IDLECLEAN);
245         radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
246         radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
247         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
248         radeon_ring_write(rdev, 0);
249         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
250         radeon_ring_write(rdev, 0);
251         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
252         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
253         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
254         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
255         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
256         radeon_ring_write(rdev,
257                           RADEON_WAIT_2D_IDLECLEAN |
258                           RADEON_WAIT_3D_IDLECLEAN);
259         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
260         radeon_ring_write(rdev, 0);
261         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
262         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
263         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
264         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
265         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
266         radeon_ring_write(rdev,
267                           ((6 << R300_MS_X0_SHIFT) |
268                            (6 << R300_MS_Y0_SHIFT) |
269                            (6 << R300_MS_X1_SHIFT) |
270                            (6 << R300_MS_Y1_SHIFT) |
271                            (6 << R300_MS_X2_SHIFT) |
272                            (6 << R300_MS_Y2_SHIFT) |
273                            (6 << R300_MSBD0_Y_SHIFT) |
274                            (6 << R300_MSBD0_X_SHIFT)));
275         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
276         radeon_ring_write(rdev,
277                           ((6 << R300_MS_X3_SHIFT) |
278                            (6 << R300_MS_Y3_SHIFT) |
279                            (6 << R300_MS_X4_SHIFT) |
280                            (6 << R300_MS_Y4_SHIFT) |
281                            (6 << R300_MS_X5_SHIFT) |
282                            (6 << R300_MS_Y5_SHIFT) |
283                            (6 << R300_MSBD1_SHIFT)));
284         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
285         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
286         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
287         radeon_ring_write(rdev,
288                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
289         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
290         radeon_ring_write(rdev,
291                           R300_GEOMETRY_ROUND_NEAREST |
292                           R300_COLOR_ROUND_NEAREST);
293         radeon_ring_unlock_commit(rdev);
294 }
295
296 void r300_errata(struct radeon_device *rdev)
297 {
298         rdev->pll_errata = 0;
299
300         if (rdev->family == CHIP_R300 &&
301             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
302                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
303         }
304 }
305
306 int r300_mc_wait_for_idle(struct radeon_device *rdev)
307 {
308         unsigned i;
309         uint32_t tmp;
310
311         for (i = 0; i < rdev->usec_timeout; i++) {
312                 /* read MC_STATUS */
313                 tmp = RREG32(RADEON_MC_STATUS);
314                 if (tmp & R300_MC_IDLE) {
315                         return 0;
316                 }
317                 DRM_UDELAY(1);
318         }
319         return -1;
320 }
321
322 void r300_gpu_init(struct radeon_device *rdev)
323 {
324         uint32_t gb_tile_config, tmp;
325
326         r100_hdp_reset(rdev);
327         /* FIXME: rv380 one pipes ? */
328         if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
329                 /* r300,r350 */
330                 rdev->num_gb_pipes = 2;
331         } else {
332                 /* rv350,rv370,rv380 */
333                 rdev->num_gb_pipes = 1;
334         }
335         rdev->num_z_pipes = 1;
336         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
337         switch (rdev->num_gb_pipes) {
338         case 2:
339                 gb_tile_config |= R300_PIPE_COUNT_R300;
340                 break;
341         case 3:
342                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
343                 break;
344         case 4:
345                 gb_tile_config |= R300_PIPE_COUNT_R420;
346                 break;
347         default:
348         case 1:
349                 gb_tile_config |= R300_PIPE_COUNT_RV350;
350                 break;
351         }
352         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
353
354         if (r100_gui_wait_for_idle(rdev)) {
355                 printk(KERN_WARNING "Failed to wait GUI idle while "
356                        "programming pipes. Bad things might happen.\n");
357         }
358
359         tmp = RREG32(R300_DST_PIPE_CONFIG);
360         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
361
362         WREG32(R300_RB2D_DSTCACHE_MODE,
363                R300_DC_AUTOFLUSH_ENABLE |
364                R300_DC_DC_DISABLE_IGNORE_PE);
365
366         if (r100_gui_wait_for_idle(rdev)) {
367                 printk(KERN_WARNING "Failed to wait GUI idle while "
368                        "programming pipes. Bad things might happen.\n");
369         }
370         if (r300_mc_wait_for_idle(rdev)) {
371                 printk(KERN_WARNING "Failed to wait MC idle while "
372                        "programming pipes. Bad things might happen.\n");
373         }
374         DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
375                  rdev->num_gb_pipes, rdev->num_z_pipes);
376 }
377
378 int r300_ga_reset(struct radeon_device *rdev)
379 {
380         uint32_t tmp;
381         bool reinit_cp;
382         int i;
383
384         reinit_cp = rdev->cp.ready;
385         rdev->cp.ready = false;
386         for (i = 0; i < rdev->usec_timeout; i++) {
387                 WREG32(RADEON_CP_CSQ_MODE, 0);
388                 WREG32(RADEON_CP_CSQ_CNTL, 0);
389                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
390                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
391                 udelay(200);
392                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
393                 /* Wait to prevent race in RBBM_STATUS */
394                 mdelay(1);
395                 tmp = RREG32(RADEON_RBBM_STATUS);
396                 if (tmp & ((1 << 20) | (1 << 26))) {
397                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
398                         /* GA still busy soft reset it */
399                         WREG32(0x429C, 0x200);
400                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
401                         WREG32(R300_RE_SCISSORS_TL, 0);
402                         WREG32(R300_RE_SCISSORS_BR, 0);
403                         WREG32(0x24AC, 0);
404                 }
405                 /* Wait to prevent race in RBBM_STATUS */
406                 mdelay(1);
407                 tmp = RREG32(RADEON_RBBM_STATUS);
408                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
409                         break;
410                 }
411         }
412         for (i = 0; i < rdev->usec_timeout; i++) {
413                 tmp = RREG32(RADEON_RBBM_STATUS);
414                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
415                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
416                                  tmp);
417                         if (reinit_cp) {
418                                 return r100_cp_init(rdev, rdev->cp.ring_size);
419                         }
420                         return 0;
421                 }
422                 DRM_UDELAY(1);
423         }
424         tmp = RREG32(RADEON_RBBM_STATUS);
425         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
426         return -1;
427 }
428
429 int r300_gpu_reset(struct radeon_device *rdev)
430 {
431         uint32_t status;
432
433         /* reset order likely matter */
434         status = RREG32(RADEON_RBBM_STATUS);
435         /* reset HDP */
436         r100_hdp_reset(rdev);
437         /* reset rb2d */
438         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
439                 r100_rb2d_reset(rdev);
440         }
441         /* reset GA */
442         if (status & ((1 << 20) | (1 << 26))) {
443                 r300_ga_reset(rdev);
444         }
445         /* reset CP */
446         status = RREG32(RADEON_RBBM_STATUS);
447         if (status & (1 << 16)) {
448                 r100_cp_reset(rdev);
449         }
450         /* Check if GPU is idle */
451         status = RREG32(RADEON_RBBM_STATUS);
452         if (status & RADEON_RBBM_ACTIVE) {
453                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
454                 return -1;
455         }
456         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
457         return 0;
458 }
459
460
461 /*
462  * r300,r350,rv350,rv380 VRAM info
463  */
464 void r300_mc_init(struct radeon_device *rdev)
465 {
466         u64 base;
467         u32 tmp;
468
469         /* DDR for all card after R300 & IGP */
470         rdev->mc.vram_is_ddr = true;
471         tmp = RREG32(RADEON_MEM_CNTL);
472         tmp &= R300_MEM_NUM_CHANNELS_MASK;
473         switch (tmp) {
474         case 0: rdev->mc.vram_width = 64; break;
475         case 1: rdev->mc.vram_width = 128; break;
476         case 2: rdev->mc.vram_width = 256; break;
477         default:  rdev->mc.vram_width = 128; break;
478         }
479         r100_vram_init_sizes(rdev);
480         base = rdev->mc.aper_base;
481         if (rdev->flags & RADEON_IS_IGP)
482                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
483         radeon_vram_location(rdev, &rdev->mc, base);
484         if (!(rdev->flags & RADEON_IS_AGP))
485                 radeon_gtt_location(rdev, &rdev->mc);
486         radeon_update_bandwidth_info(rdev);
487 }
488
489 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
490 {
491         uint32_t link_width_cntl, mask;
492
493         if (rdev->flags & RADEON_IS_IGP)
494                 return;
495
496         if (!(rdev->flags & RADEON_IS_PCIE))
497                 return;
498
499         /* FIXME wait for idle */
500
501         switch (lanes) {
502         case 0:
503                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
504                 break;
505         case 1:
506                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
507                 break;
508         case 2:
509                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
510                 break;
511         case 4:
512                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
513                 break;
514         case 8:
515                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
516                 break;
517         case 12:
518                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
519                 break;
520         case 16:
521         default:
522                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
523                 break;
524         }
525
526         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
527
528         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
529             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
530                 return;
531
532         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
533                              RADEON_PCIE_LC_RECONFIG_NOW |
534                              RADEON_PCIE_LC_RECONFIG_LATER |
535                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
536         link_width_cntl |= mask;
537         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
538         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
539                                                      RADEON_PCIE_LC_RECONFIG_NOW));
540
541         /* wait for lane set to complete */
542         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
543         while (link_width_cntl == 0xffffffff)
544                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
545
546 }
547
548 int rv370_get_pcie_lanes(struct radeon_device *rdev)
549 {
550         u32 link_width_cntl;
551
552         if (rdev->flags & RADEON_IS_IGP)
553                 return 0;
554
555         if (!(rdev->flags & RADEON_IS_PCIE))
556                 return 0;
557
558         /* FIXME wait for idle */
559
560         if (rdev->family < CHIP_R600)
561                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
562         else
563                 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
564
565         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
566         case RADEON_PCIE_LC_LINK_WIDTH_X0:
567                 return 0;
568         case RADEON_PCIE_LC_LINK_WIDTH_X1:
569                 return 1;
570         case RADEON_PCIE_LC_LINK_WIDTH_X2:
571                 return 2;
572         case RADEON_PCIE_LC_LINK_WIDTH_X4:
573                 return 4;
574         case RADEON_PCIE_LC_LINK_WIDTH_X8:
575                 return 8;
576         case RADEON_PCIE_LC_LINK_WIDTH_X16:
577         default:
578                 return 16;
579         }
580 }
581
582 #if defined(CONFIG_DEBUG_FS)
583 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
584 {
585         struct drm_info_node *node = (struct drm_info_node *) m->private;
586         struct drm_device *dev = node->minor->dev;
587         struct radeon_device *rdev = dev->dev_private;
588         uint32_t tmp;
589
590         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
591         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
592         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
593         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
594         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
595         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
596         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
597         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
598         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
599         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
600         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
601         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
602         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
603         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
604         return 0;
605 }
606
607 static struct drm_info_list rv370_pcie_gart_info_list[] = {
608         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
609 };
610 #endif
611
612 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
613 {
614 #if defined(CONFIG_DEBUG_FS)
615         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
616 #else
617         return 0;
618 #endif
619 }
620
621 static int r300_packet0_check(struct radeon_cs_parser *p,
622                 struct radeon_cs_packet *pkt,
623                 unsigned idx, unsigned reg)
624 {
625         struct radeon_cs_reloc *reloc;
626         struct r100_cs_track *track;
627         volatile uint32_t *ib;
628         uint32_t tmp, tile_flags = 0;
629         unsigned i;
630         int r;
631         u32 idx_value;
632
633         ib = p->ib->ptr;
634         track = (struct r100_cs_track *)p->track;
635         idx_value = radeon_get_ib_value(p, idx);
636
637         switch(reg) {
638         case AVIVO_D1MODE_VLINE_START_END:
639         case RADEON_CRTC_GUI_TRIG_VLINE:
640                 r = r100_cs_packet_parse_vline(p);
641                 if (r) {
642                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
643                                         idx, reg);
644                         r100_cs_dump_packet(p, pkt);
645                         return r;
646                 }
647                 break;
648         case RADEON_DST_PITCH_OFFSET:
649         case RADEON_SRC_PITCH_OFFSET:
650                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
651                 if (r)
652                         return r;
653                 break;
654         case R300_RB3D_COLOROFFSET0:
655         case R300_RB3D_COLOROFFSET1:
656         case R300_RB3D_COLOROFFSET2:
657         case R300_RB3D_COLOROFFSET3:
658                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
659                 r = r100_cs_packet_next_reloc(p, &reloc);
660                 if (r) {
661                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
662                                         idx, reg);
663                         r100_cs_dump_packet(p, pkt);
664                         return r;
665                 }
666                 track->cb[i].robj = reloc->robj;
667                 track->cb[i].offset = idx_value;
668                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
669                 break;
670         case R300_ZB_DEPTHOFFSET:
671                 r = r100_cs_packet_next_reloc(p, &reloc);
672                 if (r) {
673                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
674                                         idx, reg);
675                         r100_cs_dump_packet(p, pkt);
676                         return r;
677                 }
678                 track->zb.robj = reloc->robj;
679                 track->zb.offset = idx_value;
680                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
681                 break;
682         case R300_TX_OFFSET_0:
683         case R300_TX_OFFSET_0+4:
684         case R300_TX_OFFSET_0+8:
685         case R300_TX_OFFSET_0+12:
686         case R300_TX_OFFSET_0+16:
687         case R300_TX_OFFSET_0+20:
688         case R300_TX_OFFSET_0+24:
689         case R300_TX_OFFSET_0+28:
690         case R300_TX_OFFSET_0+32:
691         case R300_TX_OFFSET_0+36:
692         case R300_TX_OFFSET_0+40:
693         case R300_TX_OFFSET_0+44:
694         case R300_TX_OFFSET_0+48:
695         case R300_TX_OFFSET_0+52:
696         case R300_TX_OFFSET_0+56:
697         case R300_TX_OFFSET_0+60:
698                 i = (reg - R300_TX_OFFSET_0) >> 2;
699                 r = r100_cs_packet_next_reloc(p, &reloc);
700                 if (r) {
701                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
702                                         idx, reg);
703                         r100_cs_dump_packet(p, pkt);
704                         return r;
705                 }
706
707                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
708                         tile_flags |= R300_TXO_MACRO_TILE;
709                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
710                         tile_flags |= R300_TXO_MICRO_TILE;
711                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
712                         tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
713
714                 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
715                 tmp |= tile_flags;
716                 ib[idx] = tmp;
717                 track->textures[i].robj = reloc->robj;
718                 break;
719         /* Tracked registers */
720         case 0x2084:
721                 /* VAP_VF_CNTL */
722                 track->vap_vf_cntl = idx_value;
723                 break;
724         case 0x20B4:
725                 /* VAP_VTX_SIZE */
726                 track->vtx_size = idx_value & 0x7F;
727                 break;
728         case 0x2134:
729                 /* VAP_VF_MAX_VTX_INDX */
730                 track->max_indx = idx_value & 0x00FFFFFFUL;
731                 break;
732         case 0x43E4:
733                 /* SC_SCISSOR1 */
734                 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
735                 if (p->rdev->family < CHIP_RV515) {
736                         track->maxy -= 1440;
737                 }
738                 break;
739         case 0x4E00:
740                 /* RB3D_CCTL */
741                 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
742                 break;
743         case 0x4E38:
744         case 0x4E3C:
745         case 0x4E40:
746         case 0x4E44:
747                 /* RB3D_COLORPITCH0 */
748                 /* RB3D_COLORPITCH1 */
749                 /* RB3D_COLORPITCH2 */
750                 /* RB3D_COLORPITCH3 */
751                 r = r100_cs_packet_next_reloc(p, &reloc);
752                 if (r) {
753                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
754                                   idx, reg);
755                         r100_cs_dump_packet(p, pkt);
756                         return r;
757                 }
758
759                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
760                         tile_flags |= R300_COLOR_TILE_ENABLE;
761                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
762                         tile_flags |= R300_COLOR_MICROTILE_ENABLE;
763                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
764                         tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
765
766                 tmp = idx_value & ~(0x7 << 16);
767                 tmp |= tile_flags;
768                 ib[idx] = tmp;
769
770                 i = (reg - 0x4E38) >> 2;
771                 track->cb[i].pitch = idx_value & 0x3FFE;
772                 switch (((idx_value >> 21) & 0xF)) {
773                 case 9:
774                 case 11:
775                 case 12:
776                         track->cb[i].cpp = 1;
777                         break;
778                 case 3:
779                 case 4:
780                 case 13:
781                 case 15:
782                         track->cb[i].cpp = 2;
783                         break;
784                 case 6:
785                         track->cb[i].cpp = 4;
786                         break;
787                 case 10:
788                         track->cb[i].cpp = 8;
789                         break;
790                 case 7:
791                         track->cb[i].cpp = 16;
792                         break;
793                 default:
794                         DRM_ERROR("Invalid color buffer format (%d) !\n",
795                                   ((idx_value >> 21) & 0xF));
796                         return -EINVAL;
797                 }
798                 break;
799         case 0x4F00:
800                 /* ZB_CNTL */
801                 if (idx_value & 2) {
802                         track->z_enabled = true;
803                 } else {
804                         track->z_enabled = false;
805                 }
806                 break;
807         case 0x4F10:
808                 /* ZB_FORMAT */
809                 switch ((idx_value & 0xF)) {
810                 case 0:
811                 case 1:
812                         track->zb.cpp = 2;
813                         break;
814                 case 2:
815                         track->zb.cpp = 4;
816                         break;
817                 default:
818                         DRM_ERROR("Invalid z buffer format (%d) !\n",
819                                   (idx_value & 0xF));
820                         return -EINVAL;
821                 }
822                 break;
823         case 0x4F24:
824                 /* ZB_DEPTHPITCH */
825                 r = r100_cs_packet_next_reloc(p, &reloc);
826                 if (r) {
827                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
828                                   idx, reg);
829                         r100_cs_dump_packet(p, pkt);
830                         return r;
831                 }
832
833                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
834                         tile_flags |= R300_DEPTHMACROTILE_ENABLE;
835                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
836                         tile_flags |= R300_DEPTHMICROTILE_TILED;
837                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
838                         tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
839
840                 tmp = idx_value & ~(0x7 << 16);
841                 tmp |= tile_flags;
842                 ib[idx] = tmp;
843
844                 track->zb.pitch = idx_value & 0x3FFC;
845                 break;
846         case 0x4104:
847                 for (i = 0; i < 16; i++) {
848                         bool enabled;
849
850                         enabled = !!(idx_value & (1 << i));
851                         track->textures[i].enabled = enabled;
852                 }
853                 break;
854         case 0x44C0:
855         case 0x44C4:
856         case 0x44C8:
857         case 0x44CC:
858         case 0x44D0:
859         case 0x44D4:
860         case 0x44D8:
861         case 0x44DC:
862         case 0x44E0:
863         case 0x44E4:
864         case 0x44E8:
865         case 0x44EC:
866         case 0x44F0:
867         case 0x44F4:
868         case 0x44F8:
869         case 0x44FC:
870                 /* TX_FORMAT1_[0-15] */
871                 i = (reg - 0x44C0) >> 2;
872                 tmp = (idx_value >> 25) & 0x3;
873                 track->textures[i].tex_coord_type = tmp;
874                 switch ((idx_value & 0x1F)) {
875                 case R300_TX_FORMAT_X8:
876                 case R300_TX_FORMAT_Y4X4:
877                 case R300_TX_FORMAT_Z3Y3X2:
878                         track->textures[i].cpp = 1;
879                         break;
880                 case R300_TX_FORMAT_X16:
881                 case R300_TX_FORMAT_Y8X8:
882                 case R300_TX_FORMAT_Z5Y6X5:
883                 case R300_TX_FORMAT_Z6Y5X5:
884                 case R300_TX_FORMAT_W4Z4Y4X4:
885                 case R300_TX_FORMAT_W1Z5Y5X5:
886                 case R300_TX_FORMAT_D3DMFT_CxV8U8:
887                 case R300_TX_FORMAT_B8G8_B8G8:
888                 case R300_TX_FORMAT_G8R8_G8B8:
889                         track->textures[i].cpp = 2;
890                         break;
891                 case R300_TX_FORMAT_Y16X16:
892                 case R300_TX_FORMAT_Z11Y11X10:
893                 case R300_TX_FORMAT_Z10Y11X11:
894                 case R300_TX_FORMAT_W8Z8Y8X8:
895                 case R300_TX_FORMAT_W2Z10Y10X10:
896                 case 0x17:
897                 case R300_TX_FORMAT_FL_I32:
898                 case 0x1e:
899                         track->textures[i].cpp = 4;
900                         break;
901                 case R300_TX_FORMAT_W16Z16Y16X16:
902                 case R300_TX_FORMAT_FL_R16G16B16A16:
903                 case R300_TX_FORMAT_FL_I32A32:
904                         track->textures[i].cpp = 8;
905                         break;
906                 case R300_TX_FORMAT_FL_R32G32B32A32:
907                         track->textures[i].cpp = 16;
908                         break;
909                 case R300_TX_FORMAT_DXT1:
910                         track->textures[i].cpp = 1;
911                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
912                         break;
913                 case R300_TX_FORMAT_ATI2N:
914                         if (p->rdev->family < CHIP_R420) {
915                                 DRM_ERROR("Invalid texture format %u\n",
916                                           (idx_value & 0x1F));
917                                 return -EINVAL;
918                         }
919                         /* The same rules apply as for DXT3/5. */
920                         /* Pass through. */
921                 case R300_TX_FORMAT_DXT3:
922                 case R300_TX_FORMAT_DXT5:
923                         track->textures[i].cpp = 1;
924                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
925                         break;
926                 default:
927                         DRM_ERROR("Invalid texture format %u\n",
928                                   (idx_value & 0x1F));
929                         return -EINVAL;
930                         break;
931                 }
932                 break;
933         case 0x4400:
934         case 0x4404:
935         case 0x4408:
936         case 0x440C:
937         case 0x4410:
938         case 0x4414:
939         case 0x4418:
940         case 0x441C:
941         case 0x4420:
942         case 0x4424:
943         case 0x4428:
944         case 0x442C:
945         case 0x4430:
946         case 0x4434:
947         case 0x4438:
948         case 0x443C:
949                 /* TX_FILTER0_[0-15] */
950                 i = (reg - 0x4400) >> 2;
951                 tmp = idx_value & 0x7;
952                 if (tmp == 2 || tmp == 4 || tmp == 6) {
953                         track->textures[i].roundup_w = false;
954                 }
955                 tmp = (idx_value >> 3) & 0x7;
956                 if (tmp == 2 || tmp == 4 || tmp == 6) {
957                         track->textures[i].roundup_h = false;
958                 }
959                 break;
960         case 0x4500:
961         case 0x4504:
962         case 0x4508:
963         case 0x450C:
964         case 0x4510:
965         case 0x4514:
966         case 0x4518:
967         case 0x451C:
968         case 0x4520:
969         case 0x4524:
970         case 0x4528:
971         case 0x452C:
972         case 0x4530:
973         case 0x4534:
974         case 0x4538:
975         case 0x453C:
976                 /* TX_FORMAT2_[0-15] */
977                 i = (reg - 0x4500) >> 2;
978                 tmp = idx_value & 0x3FFF;
979                 track->textures[i].pitch = tmp + 1;
980                 if (p->rdev->family >= CHIP_RV515) {
981                         tmp = ((idx_value >> 15) & 1) << 11;
982                         track->textures[i].width_11 = tmp;
983                         tmp = ((idx_value >> 16) & 1) << 11;
984                         track->textures[i].height_11 = tmp;
985
986                         /* ATI1N */
987                         if (idx_value & (1 << 14)) {
988                                 /* The same rules apply as for DXT1. */
989                                 track->textures[i].compress_format =
990                                         R100_TRACK_COMP_DXT1;
991                         }
992                 } else if (idx_value & (1 << 14)) {
993                         DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
994                         return -EINVAL;
995                 }
996                 break;
997         case 0x4480:
998         case 0x4484:
999         case 0x4488:
1000         case 0x448C:
1001         case 0x4490:
1002         case 0x4494:
1003         case 0x4498:
1004         case 0x449C:
1005         case 0x44A0:
1006         case 0x44A4:
1007         case 0x44A8:
1008         case 0x44AC:
1009         case 0x44B0:
1010         case 0x44B4:
1011         case 0x44B8:
1012         case 0x44BC:
1013                 /* TX_FORMAT0_[0-15] */
1014                 i = (reg - 0x4480) >> 2;
1015                 tmp = idx_value & 0x7FF;
1016                 track->textures[i].width = tmp + 1;
1017                 tmp = (idx_value >> 11) & 0x7FF;
1018                 track->textures[i].height = tmp + 1;
1019                 tmp = (idx_value >> 26) & 0xF;
1020                 track->textures[i].num_levels = tmp;
1021                 tmp = idx_value & (1 << 31);
1022                 track->textures[i].use_pitch = !!tmp;
1023                 tmp = (idx_value >> 22) & 0xF;
1024                 track->textures[i].txdepth = tmp;
1025                 break;
1026         case R300_ZB_ZPASS_ADDR:
1027                 r = r100_cs_packet_next_reloc(p, &reloc);
1028                 if (r) {
1029                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1030                                         idx, reg);
1031                         r100_cs_dump_packet(p, pkt);
1032                         return r;
1033                 }
1034                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1035                 break;
1036         case 0x4e0c:
1037                 /* RB3D_COLOR_CHANNEL_MASK */
1038                 track->color_channel_mask = idx_value;
1039                 break;
1040         case 0x4d1c:
1041                 /* ZB_BW_CNTL */
1042                 track->fastfill = !!(idx_value & (1 << 2));
1043                 break;
1044         case 0x4e04:
1045                 /* RB3D_BLENDCNTL */
1046                 track->blend_read_enable = !!(idx_value & (1 << 2));
1047                 break;
1048         case 0x4be8:
1049                 /* valid register only on RV530 */
1050                 if (p->rdev->family == CHIP_RV530)
1051                         break;
1052                 /* fallthrough do not move */
1053         default:
1054                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1055                        reg, idx);
1056                 return -EINVAL;
1057         }
1058         return 0;
1059 }
1060
1061 static int r300_packet3_check(struct radeon_cs_parser *p,
1062                               struct radeon_cs_packet *pkt)
1063 {
1064         struct radeon_cs_reloc *reloc;
1065         struct r100_cs_track *track;
1066         volatile uint32_t *ib;
1067         unsigned idx;
1068         int r;
1069
1070         ib = p->ib->ptr;
1071         idx = pkt->idx + 1;
1072         track = (struct r100_cs_track *)p->track;
1073         switch(pkt->opcode) {
1074         case PACKET3_3D_LOAD_VBPNTR:
1075                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1076                 if (r)
1077                         return r;
1078                 break;
1079         case PACKET3_INDX_BUFFER:
1080                 r = r100_cs_packet_next_reloc(p, &reloc);
1081                 if (r) {
1082                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1083                         r100_cs_dump_packet(p, pkt);
1084                         return r;
1085                 }
1086                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1087                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1088                 if (r) {
1089                         return r;
1090                 }
1091                 break;
1092         /* Draw packet */
1093         case PACKET3_3D_DRAW_IMMD:
1094                 /* Number of dwords is vtx_size * (num_vertices - 1)
1095                  * PRIM_WALK must be equal to 3 vertex data in embedded
1096                  * in cmd stream */
1097                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1098                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1099                         return -EINVAL;
1100                 }
1101                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1102                 track->immd_dwords = pkt->count - 1;
1103                 r = r100_cs_track_check(p->rdev, track);
1104                 if (r) {
1105                         return r;
1106                 }
1107                 break;
1108         case PACKET3_3D_DRAW_IMMD_2:
1109                 /* Number of dwords is vtx_size * (num_vertices - 1)
1110                  * PRIM_WALK must be equal to 3 vertex data in embedded
1111                  * in cmd stream */
1112                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1113                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1114                         return -EINVAL;
1115                 }
1116                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1117                 track->immd_dwords = pkt->count;
1118                 r = r100_cs_track_check(p->rdev, track);
1119                 if (r) {
1120                         return r;
1121                 }
1122                 break;
1123         case PACKET3_3D_DRAW_VBUF:
1124                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1125                 r = r100_cs_track_check(p->rdev, track);
1126                 if (r) {
1127                         return r;
1128                 }
1129                 break;
1130         case PACKET3_3D_DRAW_VBUF_2:
1131                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1132                 r = r100_cs_track_check(p->rdev, track);
1133                 if (r) {
1134                         return r;
1135                 }
1136                 break;
1137         case PACKET3_3D_DRAW_INDX:
1138                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1139                 r = r100_cs_track_check(p->rdev, track);
1140                 if (r) {
1141                         return r;
1142                 }
1143                 break;
1144         case PACKET3_3D_DRAW_INDX_2:
1145                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1146                 r = r100_cs_track_check(p->rdev, track);
1147                 if (r) {
1148                         return r;
1149                 }
1150                 break;
1151         case PACKET3_NOP:
1152                 break;
1153         default:
1154                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1155                 return -EINVAL;
1156         }
1157         return 0;
1158 }
1159
1160 int r300_cs_parse(struct radeon_cs_parser *p)
1161 {
1162         struct radeon_cs_packet pkt;
1163         struct r100_cs_track *track;
1164         int r;
1165
1166         track = kzalloc(sizeof(*track), GFP_KERNEL);
1167         r100_cs_track_clear(p->rdev, track);
1168         p->track = track;
1169         do {
1170                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1171                 if (r) {
1172                         return r;
1173                 }
1174                 p->idx += pkt.count + 2;
1175                 switch (pkt.type) {
1176                 case PACKET_TYPE0:
1177                         r = r100_cs_parse_packet0(p, &pkt,
1178                                                   p->rdev->config.r300.reg_safe_bm,
1179                                                   p->rdev->config.r300.reg_safe_bm_size,
1180                                                   &r300_packet0_check);
1181                         break;
1182                 case PACKET_TYPE2:
1183                         break;
1184                 case PACKET_TYPE3:
1185                         r = r300_packet3_check(p, &pkt);
1186                         break;
1187                 default:
1188                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1189                         return -EINVAL;
1190                 }
1191                 if (r) {
1192                         return r;
1193                 }
1194         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1195         return 0;
1196 }
1197
1198 void r300_set_reg_safe(struct radeon_device *rdev)
1199 {
1200         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1201         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1202 }
1203
1204 void r300_mc_program(struct radeon_device *rdev)
1205 {
1206         struct r100_mc_save save;
1207         int r;
1208
1209         r = r100_debugfs_mc_info_init(rdev);
1210         if (r) {
1211                 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1212         }
1213
1214         /* Stops all mc clients */
1215         r100_mc_stop(rdev, &save);
1216         if (rdev->flags & RADEON_IS_AGP) {
1217                 WREG32(R_00014C_MC_AGP_LOCATION,
1218                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1219                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1220                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1221                 WREG32(R_00015C_AGP_BASE_2,
1222                         upper_32_bits(rdev->mc.agp_base) & 0xff);
1223         } else {
1224                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1225                 WREG32(R_000170_AGP_BASE, 0);
1226                 WREG32(R_00015C_AGP_BASE_2, 0);
1227         }
1228         /* Wait for mc idle */
1229         if (r300_mc_wait_for_idle(rdev))
1230                 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1231         /* Program MC, should be a 32bits limited address space */
1232         WREG32(R_000148_MC_FB_LOCATION,
1233                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1234                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1235         r100_mc_resume(rdev, &save);
1236 }
1237
1238 void r300_clock_startup(struct radeon_device *rdev)
1239 {
1240         u32 tmp;
1241
1242         if (radeon_dynclks != -1 && radeon_dynclks)
1243                 radeon_legacy_set_clock_gating(rdev, 1);
1244         /* We need to force on some of the block */
1245         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1246         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1247         if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1248                 tmp |= S_00000D_FORCE_VAP(1);
1249         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1250 }
1251
1252 static int r300_startup(struct radeon_device *rdev)
1253 {
1254         int r;
1255
1256         /* set common regs */
1257         r100_set_common_regs(rdev);
1258         /* program mc */
1259         r300_mc_program(rdev);
1260         /* Resume clock */
1261         r300_clock_startup(rdev);
1262         /* Initialize GPU configuration (# pipes, ...) */
1263         r300_gpu_init(rdev);
1264         /* Initialize GART (initialize after TTM so we can allocate
1265          * memory through TTM but finalize after TTM) */
1266         if (rdev->flags & RADEON_IS_PCIE) {
1267                 r = rv370_pcie_gart_enable(rdev);
1268                 if (r)
1269                         return r;
1270         }
1271
1272         if (rdev->family == CHIP_R300 ||
1273             rdev->family == CHIP_R350 ||
1274             rdev->family == CHIP_RV350)
1275                 r100_enable_bm(rdev);
1276
1277         if (rdev->flags & RADEON_IS_PCI) {
1278                 r = r100_pci_gart_enable(rdev);
1279                 if (r)
1280                         return r;
1281         }
1282         /* Enable IRQ */
1283         r100_irq_set(rdev);
1284         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1285         /* 1M ring buffer */
1286         r = r100_cp_init(rdev, 1024 * 1024);
1287         if (r) {
1288                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1289                 return r;
1290         }
1291         r = r100_wb_init(rdev);
1292         if (r)
1293                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1294         r = r100_ib_init(rdev);
1295         if (r) {
1296                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1297                 return r;
1298         }
1299         return 0;
1300 }
1301
1302 int r300_resume(struct radeon_device *rdev)
1303 {
1304         /* Make sur GART are not working */
1305         if (rdev->flags & RADEON_IS_PCIE)
1306                 rv370_pcie_gart_disable(rdev);
1307         if (rdev->flags & RADEON_IS_PCI)
1308                 r100_pci_gart_disable(rdev);
1309         /* Resume clock before doing reset */
1310         r300_clock_startup(rdev);
1311         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1312         if (radeon_gpu_reset(rdev)) {
1313                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1314                         RREG32(R_000E40_RBBM_STATUS),
1315                         RREG32(R_0007C0_CP_STAT));
1316         }
1317         /* post */
1318         radeon_combios_asic_init(rdev->ddev);
1319         /* Resume clock after posting */
1320         r300_clock_startup(rdev);
1321         /* Initialize surface registers */
1322         radeon_surface_init(rdev);
1323         return r300_startup(rdev);
1324 }
1325
1326 int r300_suspend(struct radeon_device *rdev)
1327 {
1328         r100_cp_disable(rdev);
1329         r100_wb_disable(rdev);
1330         r100_irq_disable(rdev);
1331         if (rdev->flags & RADEON_IS_PCIE)
1332                 rv370_pcie_gart_disable(rdev);
1333         if (rdev->flags & RADEON_IS_PCI)
1334                 r100_pci_gart_disable(rdev);
1335         return 0;
1336 }
1337
1338 void r300_fini(struct radeon_device *rdev)
1339 {
1340         radeon_pm_fini(rdev);
1341         r100_cp_fini(rdev);
1342         r100_wb_fini(rdev);
1343         r100_ib_fini(rdev);
1344         radeon_gem_fini(rdev);
1345         if (rdev->flags & RADEON_IS_PCIE)
1346                 rv370_pcie_gart_fini(rdev);
1347         if (rdev->flags & RADEON_IS_PCI)
1348                 r100_pci_gart_fini(rdev);
1349         radeon_agp_fini(rdev);
1350         radeon_irq_kms_fini(rdev);
1351         radeon_fence_driver_fini(rdev);
1352         radeon_bo_fini(rdev);
1353         radeon_atombios_fini(rdev);
1354         kfree(rdev->bios);
1355         rdev->bios = NULL;
1356 }
1357
1358 int r300_init(struct radeon_device *rdev)
1359 {
1360         int r;
1361
1362         /* Disable VGA */
1363         r100_vga_render_disable(rdev);
1364         /* Initialize scratch registers */
1365         radeon_scratch_init(rdev);
1366         /* Initialize surface registers */
1367         radeon_surface_init(rdev);
1368         /* TODO: disable VGA need to use VGA request */
1369         /* BIOS*/
1370         if (!radeon_get_bios(rdev)) {
1371                 if (ASIC_IS_AVIVO(rdev))
1372                         return -EINVAL;
1373         }
1374         if (rdev->is_atom_bios) {
1375                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1376                 return -EINVAL;
1377         } else {
1378                 r = radeon_combios_init(rdev);
1379                 if (r)
1380                         return r;
1381         }
1382         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1383         if (radeon_gpu_reset(rdev)) {
1384                 dev_warn(rdev->dev,
1385                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1386                         RREG32(R_000E40_RBBM_STATUS),
1387                         RREG32(R_0007C0_CP_STAT));
1388         }
1389         /* check if cards are posted or not */
1390         if (radeon_boot_test_post_card(rdev) == false)
1391                 return -EINVAL;
1392         /* Set asic errata */
1393         r300_errata(rdev);
1394         /* Initialize clocks */
1395         radeon_get_clock_info(rdev->ddev);
1396         /* Initialize power management */
1397         radeon_pm_init(rdev);
1398         /* initialize AGP */
1399         if (rdev->flags & RADEON_IS_AGP) {
1400                 r = radeon_agp_init(rdev);
1401                 if (r) {
1402                         radeon_agp_disable(rdev);
1403                 }
1404         }
1405         /* initialize memory controller */
1406         r300_mc_init(rdev);
1407         /* Fence driver */
1408         r = radeon_fence_driver_init(rdev);
1409         if (r)
1410                 return r;
1411         r = radeon_irq_kms_init(rdev);
1412         if (r)
1413                 return r;
1414         /* Memory manager */
1415         r = radeon_bo_init(rdev);
1416         if (r)
1417                 return r;
1418         if (rdev->flags & RADEON_IS_PCIE) {
1419                 r = rv370_pcie_gart_init(rdev);
1420                 if (r)
1421                         return r;
1422         }
1423         if (rdev->flags & RADEON_IS_PCI) {
1424                 r = r100_pci_gart_init(rdev);
1425                 if (r)
1426                         return r;
1427         }
1428         r300_set_reg_safe(rdev);
1429         rdev->accel_working = true;
1430         r = r300_startup(rdev);
1431         if (r) {
1432                 /* Somethings want wront with the accel init stop accel */
1433                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1434                 r100_cp_fini(rdev);
1435                 r100_wb_fini(rdev);
1436                 r100_ib_fini(rdev);
1437                 radeon_irq_kms_fini(rdev);
1438                 if (rdev->flags & RADEON_IS_PCIE)
1439                         rv370_pcie_gart_fini(rdev);
1440                 if (rdev->flags & RADEON_IS_PCI)
1441                         r100_pci_gart_fini(rdev);
1442                 radeon_agp_fini(rdev);
1443                 rdev->accel_working = false;
1444         }
1445         return 0;
1446 }