Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi...
[kernel.git] / drivers / gpu / drm / radeon / r600.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include <linux/firmware.h>
30 #include <linux/platform_device.h>
31 #include "drmP.h"
32 #include "radeon_drm.h"
33 #include "radeon.h"
34 #include "radeon_mode.h"
35 #include "r600d.h"
36 #include "atom.h"
37 #include "avivod.h"
38
39 #define PFP_UCODE_SIZE 576
40 #define PM4_UCODE_SIZE 1792
41 #define RLC_UCODE_SIZE 768
42 #define R700_PFP_UCODE_SIZE 848
43 #define R700_PM4_UCODE_SIZE 1360
44 #define R700_RLC_UCODE_SIZE 1024
45
46 /* Firmware Names */
47 MODULE_FIRMWARE("radeon/R600_pfp.bin");
48 MODULE_FIRMWARE("radeon/R600_me.bin");
49 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
50 MODULE_FIRMWARE("radeon/RV610_me.bin");
51 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
52 MODULE_FIRMWARE("radeon/RV630_me.bin");
53 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
54 MODULE_FIRMWARE("radeon/RV620_me.bin");
55 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
56 MODULE_FIRMWARE("radeon/RV635_me.bin");
57 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV670_me.bin");
59 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
60 MODULE_FIRMWARE("radeon/RS780_me.bin");
61 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV770_me.bin");
63 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV730_me.bin");
65 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV710_me.bin");
67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
69
70 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
71
72 /* r600,rv610,rv630,rv620,rv635,rv670 */
73 int r600_mc_wait_for_idle(struct radeon_device *rdev);
74 void r600_gpu_init(struct radeon_device *rdev);
75 void r600_fini(struct radeon_device *rdev);
76
77 /* hpd for digital panel detect/disconnect */
78 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
79 {
80         bool connected = false;
81
82         if (ASIC_IS_DCE3(rdev)) {
83                 switch (hpd) {
84                 case RADEON_HPD_1:
85                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
86                                 connected = true;
87                         break;
88                 case RADEON_HPD_2:
89                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
90                                 connected = true;
91                         break;
92                 case RADEON_HPD_3:
93                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
94                                 connected = true;
95                         break;
96                 case RADEON_HPD_4:
97                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
98                                 connected = true;
99                         break;
100                         /* DCE 3.2 */
101                 case RADEON_HPD_5:
102                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
103                                 connected = true;
104                         break;
105                 case RADEON_HPD_6:
106                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
107                                 connected = true;
108                         break;
109                 default:
110                         break;
111                 }
112         } else {
113                 switch (hpd) {
114                 case RADEON_HPD_1:
115                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
116                                 connected = true;
117                         break;
118                 case RADEON_HPD_2:
119                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
120                                 connected = true;
121                         break;
122                 case RADEON_HPD_3:
123                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
124                                 connected = true;
125                         break;
126                 default:
127                         break;
128                 }
129         }
130         return connected;
131 }
132
133 void r600_hpd_set_polarity(struct radeon_device *rdev,
134                            enum radeon_hpd_id hpd)
135 {
136         u32 tmp;
137         bool connected = r600_hpd_sense(rdev, hpd);
138
139         if (ASIC_IS_DCE3(rdev)) {
140                 switch (hpd) {
141                 case RADEON_HPD_1:
142                         tmp = RREG32(DC_HPD1_INT_CONTROL);
143                         if (connected)
144                                 tmp &= ~DC_HPDx_INT_POLARITY;
145                         else
146                                 tmp |= DC_HPDx_INT_POLARITY;
147                         WREG32(DC_HPD1_INT_CONTROL, tmp);
148                         break;
149                 case RADEON_HPD_2:
150                         tmp = RREG32(DC_HPD2_INT_CONTROL);
151                         if (connected)
152                                 tmp &= ~DC_HPDx_INT_POLARITY;
153                         else
154                                 tmp |= DC_HPDx_INT_POLARITY;
155                         WREG32(DC_HPD2_INT_CONTROL, tmp);
156                         break;
157                 case RADEON_HPD_3:
158                         tmp = RREG32(DC_HPD3_INT_CONTROL);
159                         if (connected)
160                                 tmp &= ~DC_HPDx_INT_POLARITY;
161                         else
162                                 tmp |= DC_HPDx_INT_POLARITY;
163                         WREG32(DC_HPD3_INT_CONTROL, tmp);
164                         break;
165                 case RADEON_HPD_4:
166                         tmp = RREG32(DC_HPD4_INT_CONTROL);
167                         if (connected)
168                                 tmp &= ~DC_HPDx_INT_POLARITY;
169                         else
170                                 tmp |= DC_HPDx_INT_POLARITY;
171                         WREG32(DC_HPD4_INT_CONTROL, tmp);
172                         break;
173                 case RADEON_HPD_5:
174                         tmp = RREG32(DC_HPD5_INT_CONTROL);
175                         if (connected)
176                                 tmp &= ~DC_HPDx_INT_POLARITY;
177                         else
178                                 tmp |= DC_HPDx_INT_POLARITY;
179                         WREG32(DC_HPD5_INT_CONTROL, tmp);
180                         break;
181                         /* DCE 3.2 */
182                 case RADEON_HPD_6:
183                         tmp = RREG32(DC_HPD6_INT_CONTROL);
184                         if (connected)
185                                 tmp &= ~DC_HPDx_INT_POLARITY;
186                         else
187                                 tmp |= DC_HPDx_INT_POLARITY;
188                         WREG32(DC_HPD6_INT_CONTROL, tmp);
189                         break;
190                 default:
191                         break;
192                 }
193         } else {
194                 switch (hpd) {
195                 case RADEON_HPD_1:
196                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
197                         if (connected)
198                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
199                         else
200                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
201                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
202                         break;
203                 case RADEON_HPD_2:
204                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
205                         if (connected)
206                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
207                         else
208                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
209                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
210                         break;
211                 case RADEON_HPD_3:
212                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
213                         if (connected)
214                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
215                         else
216                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
217                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
218                         break;
219                 default:
220                         break;
221                 }
222         }
223 }
224
225 void r600_hpd_init(struct radeon_device *rdev)
226 {
227         struct drm_device *dev = rdev->ddev;
228         struct drm_connector *connector;
229
230         if (ASIC_IS_DCE3(rdev)) {
231                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
232                 if (ASIC_IS_DCE32(rdev))
233                         tmp |= DC_HPDx_EN;
234
235                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
236                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
237                         switch (radeon_connector->hpd.hpd) {
238                         case RADEON_HPD_1:
239                                 WREG32(DC_HPD1_CONTROL, tmp);
240                                 rdev->irq.hpd[0] = true;
241                                 break;
242                         case RADEON_HPD_2:
243                                 WREG32(DC_HPD2_CONTROL, tmp);
244                                 rdev->irq.hpd[1] = true;
245                                 break;
246                         case RADEON_HPD_3:
247                                 WREG32(DC_HPD3_CONTROL, tmp);
248                                 rdev->irq.hpd[2] = true;
249                                 break;
250                         case RADEON_HPD_4:
251                                 WREG32(DC_HPD4_CONTROL, tmp);
252                                 rdev->irq.hpd[3] = true;
253                                 break;
254                                 /* DCE 3.2 */
255                         case RADEON_HPD_5:
256                                 WREG32(DC_HPD5_CONTROL, tmp);
257                                 rdev->irq.hpd[4] = true;
258                                 break;
259                         case RADEON_HPD_6:
260                                 WREG32(DC_HPD6_CONTROL, tmp);
261                                 rdev->irq.hpd[5] = true;
262                                 break;
263                         default:
264                                 break;
265                         }
266                 }
267         } else {
268                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
269                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
270                         switch (radeon_connector->hpd.hpd) {
271                         case RADEON_HPD_1:
272                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
273                                 rdev->irq.hpd[0] = true;
274                                 break;
275                         case RADEON_HPD_2:
276                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
277                                 rdev->irq.hpd[1] = true;
278                                 break;
279                         case RADEON_HPD_3:
280                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
281                                 rdev->irq.hpd[2] = true;
282                                 break;
283                         default:
284                                 break;
285                         }
286                 }
287         }
288         if (rdev->irq.installed)
289                 r600_irq_set(rdev);
290 }
291
292 void r600_hpd_fini(struct radeon_device *rdev)
293 {
294         struct drm_device *dev = rdev->ddev;
295         struct drm_connector *connector;
296
297         if (ASIC_IS_DCE3(rdev)) {
298                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
299                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
300                         switch (radeon_connector->hpd.hpd) {
301                         case RADEON_HPD_1:
302                                 WREG32(DC_HPD1_CONTROL, 0);
303                                 rdev->irq.hpd[0] = false;
304                                 break;
305                         case RADEON_HPD_2:
306                                 WREG32(DC_HPD2_CONTROL, 0);
307                                 rdev->irq.hpd[1] = false;
308                                 break;
309                         case RADEON_HPD_3:
310                                 WREG32(DC_HPD3_CONTROL, 0);
311                                 rdev->irq.hpd[2] = false;
312                                 break;
313                         case RADEON_HPD_4:
314                                 WREG32(DC_HPD4_CONTROL, 0);
315                                 rdev->irq.hpd[3] = false;
316                                 break;
317                                 /* DCE 3.2 */
318                         case RADEON_HPD_5:
319                                 WREG32(DC_HPD5_CONTROL, 0);
320                                 rdev->irq.hpd[4] = false;
321                                 break;
322                         case RADEON_HPD_6:
323                                 WREG32(DC_HPD6_CONTROL, 0);
324                                 rdev->irq.hpd[5] = false;
325                                 break;
326                         default:
327                                 break;
328                         }
329                 }
330         } else {
331                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
332                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
333                         switch (radeon_connector->hpd.hpd) {
334                         case RADEON_HPD_1:
335                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
336                                 rdev->irq.hpd[0] = false;
337                                 break;
338                         case RADEON_HPD_2:
339                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
340                                 rdev->irq.hpd[1] = false;
341                                 break;
342                         case RADEON_HPD_3:
343                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
344                                 rdev->irq.hpd[2] = false;
345                                 break;
346                         default:
347                                 break;
348                         }
349                 }
350         }
351 }
352
353 /*
354  * R600 PCIE GART
355  */
356 int r600_gart_clear_page(struct radeon_device *rdev, int i)
357 {
358         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
359         u64 pte;
360
361         if (i < 0 || i > rdev->gart.num_gpu_pages)
362                 return -EINVAL;
363         pte = 0;
364         writeq(pte, ((void __iomem *)ptr) + (i * 8));
365         return 0;
366 }
367
368 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
369 {
370         unsigned i;
371         u32 tmp;
372
373         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
374         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
375         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
376         for (i = 0; i < rdev->usec_timeout; i++) {
377                 /* read MC_STATUS */
378                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
379                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
380                 if (tmp == 2) {
381                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
382                         return;
383                 }
384                 if (tmp) {
385                         return;
386                 }
387                 udelay(1);
388         }
389 }
390
391 int r600_pcie_gart_init(struct radeon_device *rdev)
392 {
393         int r;
394
395         if (rdev->gart.table.vram.robj) {
396                 WARN(1, "R600 PCIE GART already initialized.\n");
397                 return 0;
398         }
399         /* Initialize common gart structure */
400         r = radeon_gart_init(rdev);
401         if (r)
402                 return r;
403         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
404         return radeon_gart_table_vram_alloc(rdev);
405 }
406
407 int r600_pcie_gart_enable(struct radeon_device *rdev)
408 {
409         u32 tmp;
410         int r, i;
411
412         if (rdev->gart.table.vram.robj == NULL) {
413                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
414                 return -EINVAL;
415         }
416         r = radeon_gart_table_vram_pin(rdev);
417         if (r)
418                 return r;
419
420         /* Setup L2 cache */
421         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
422                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
423                                 EFFECTIVE_L2_QUEUE_SIZE(7));
424         WREG32(VM_L2_CNTL2, 0);
425         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
426         /* Setup TLB control */
427         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
428                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
429                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
430                 ENABLE_WAIT_L2_QUERY;
431         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
432         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
433         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
434         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
435         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
436         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
437         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
438         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
439         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
440         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
441         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
442         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
443         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
444         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
445         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
446         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
447         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
448         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
449                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
450         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
451                         (u32)(rdev->dummy_page.addr >> 12));
452         for (i = 1; i < 7; i++)
453                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
454
455         r600_pcie_gart_tlb_flush(rdev);
456         rdev->gart.ready = true;
457         return 0;
458 }
459
460 void r600_pcie_gart_disable(struct radeon_device *rdev)
461 {
462         u32 tmp;
463         int i, r;
464
465         /* Disable all tables */
466         for (i = 0; i < 7; i++)
467                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
468
469         /* Disable L2 cache */
470         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
471                                 EFFECTIVE_L2_QUEUE_SIZE(7));
472         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
473         /* Setup L1 TLB control */
474         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
475                 ENABLE_WAIT_L2_QUERY;
476         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
477         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
478         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
479         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
480         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
481         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
482         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
483         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
484         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
485         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
486         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
487         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
488         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
489         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
490         if (rdev->gart.table.vram.robj) {
491                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
492                 if (likely(r == 0)) {
493                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
494                         radeon_bo_unpin(rdev->gart.table.vram.robj);
495                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
496                 }
497         }
498 }
499
500 void r600_pcie_gart_fini(struct radeon_device *rdev)
501 {
502         r600_pcie_gart_disable(rdev);
503         radeon_gart_table_vram_free(rdev);
504         radeon_gart_fini(rdev);
505 }
506
507 void r600_agp_enable(struct radeon_device *rdev)
508 {
509         u32 tmp;
510         int i;
511
512         /* Setup L2 cache */
513         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
514                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
515                                 EFFECTIVE_L2_QUEUE_SIZE(7));
516         WREG32(VM_L2_CNTL2, 0);
517         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
518         /* Setup TLB control */
519         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
520                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
521                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
522                 ENABLE_WAIT_L2_QUERY;
523         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
524         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
525         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
526         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
527         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
528         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
529         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
530         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
531         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
532         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
533         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
534         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
535         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
536         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
537         for (i = 0; i < 7; i++)
538                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
539 }
540
541 int r600_mc_wait_for_idle(struct radeon_device *rdev)
542 {
543         unsigned i;
544         u32 tmp;
545
546         for (i = 0; i < rdev->usec_timeout; i++) {
547                 /* read MC_STATUS */
548                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
549                 if (!tmp)
550                         return 0;
551                 udelay(1);
552         }
553         return -1;
554 }
555
556 static void r600_mc_program(struct radeon_device *rdev)
557 {
558         struct rv515_mc_save save;
559         u32 tmp;
560         int i, j;
561
562         /* Initialize HDP */
563         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
564                 WREG32((0x2c14 + j), 0x00000000);
565                 WREG32((0x2c18 + j), 0x00000000);
566                 WREG32((0x2c1c + j), 0x00000000);
567                 WREG32((0x2c20 + j), 0x00000000);
568                 WREG32((0x2c24 + j), 0x00000000);
569         }
570         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
571
572         rv515_mc_stop(rdev, &save);
573         if (r600_mc_wait_for_idle(rdev)) {
574                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
575         }
576         /* Lockout access through VGA aperture (doesn't exist before R600) */
577         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
578         /* Update configuration */
579         if (rdev->flags & RADEON_IS_AGP) {
580                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
581                         /* VRAM before AGP */
582                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
583                                 rdev->mc.vram_start >> 12);
584                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
585                                 rdev->mc.gtt_end >> 12);
586                 } else {
587                         /* VRAM after AGP */
588                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
589                                 rdev->mc.gtt_start >> 12);
590                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
591                                 rdev->mc.vram_end >> 12);
592                 }
593         } else {
594                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
595                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
596         }
597         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
598         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
599         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
600         WREG32(MC_VM_FB_LOCATION, tmp);
601         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
602         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
603         WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
604         if (rdev->flags & RADEON_IS_AGP) {
605                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
606                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
607                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
608         } else {
609                 WREG32(MC_VM_AGP_BASE, 0);
610                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
611                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
612         }
613         if (r600_mc_wait_for_idle(rdev)) {
614                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
615         }
616         rv515_mc_resume(rdev, &save);
617         /* we need to own VRAM, so turn off the VGA renderer here
618          * to stop it overwriting our objects */
619         rv515_vga_render_disable(rdev);
620 }
621
622 int r600_mc_init(struct radeon_device *rdev)
623 {
624         fixed20_12 a;
625         u32 tmp;
626         int chansize, numchan;
627
628         /* Get VRAM informations */
629         rdev->mc.vram_is_ddr = true;
630         tmp = RREG32(RAMCFG);
631         if (tmp & CHANSIZE_OVERRIDE) {
632                 chansize = 16;
633         } else if (tmp & CHANSIZE_MASK) {
634                 chansize = 64;
635         } else {
636                 chansize = 32;
637         }
638         tmp = RREG32(CHMAP);
639         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
640         case 0:
641         default:
642                 numchan = 1;
643                 break;
644         case 1:
645                 numchan = 2;
646                 break;
647         case 2:
648                 numchan = 4;
649                 break;
650         case 3:
651                 numchan = 8;
652                 break;
653         }
654         rdev->mc.vram_width = numchan * chansize;
655         /* Could aper size report 0 ? */
656         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
657         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
658         /* Setup GPU memory space */
659         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
660         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
661
662         if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
663                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
664
665         if (rdev->mc.real_vram_size > rdev->mc.aper_size)
666                 rdev->mc.real_vram_size = rdev->mc.aper_size;
667
668         if (rdev->flags & RADEON_IS_AGP) {
669                 /* gtt_size is setup by radeon_agp_init */
670                 rdev->mc.gtt_location = rdev->mc.agp_base;
671                 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
672                 /* Try to put vram before or after AGP because we
673                  * we want SYSTEM_APERTURE to cover both VRAM and
674                  * AGP so that GPU can catch out of VRAM/AGP access
675                  */
676                 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
677                         /* Enough place before */
678                         rdev->mc.vram_location = rdev->mc.gtt_location -
679                                                         rdev->mc.mc_vram_size;
680                 } else if (tmp > rdev->mc.mc_vram_size) {
681                         /* Enough place after */
682                         rdev->mc.vram_location = rdev->mc.gtt_location +
683                                                         rdev->mc.gtt_size;
684                 } else {
685                         /* Try to setup VRAM then AGP might not
686                          * not work on some card
687                          */
688                         rdev->mc.vram_location = 0x00000000UL;
689                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
690                 }
691         } else {
692                 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
693                 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
694                                                         0xFFFF) << 24;
695                 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
696                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
697                         /* Enough place after vram */
698                         rdev->mc.gtt_location = tmp;
699                 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
700                         /* Enough place before vram */
701                         rdev->mc.gtt_location = 0;
702                 } else {
703                         /* Not enough place after or before shrink
704                          * gart size
705                          */
706                         if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
707                                 rdev->mc.gtt_location = 0;
708                                 rdev->mc.gtt_size = rdev->mc.vram_location;
709                         } else {
710                                 rdev->mc.gtt_location = tmp;
711                                 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
712                         }
713                 }
714                 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
715         }
716         rdev->mc.vram_start = rdev->mc.vram_location;
717         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
718         rdev->mc.gtt_start = rdev->mc.gtt_location;
719         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
720         /* FIXME: we should enforce default clock in case GPU is not in
721          * default setup
722          */
723         a.full = rfixed_const(100);
724         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
725         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
726
727         if (rdev->flags & RADEON_IS_IGP)
728                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
729
730         return 0;
731 }
732
733 /* We doesn't check that the GPU really needs a reset we simply do the
734  * reset, it's up to the caller to determine if the GPU needs one. We
735  * might add an helper function to check that.
736  */
737 int r600_gpu_soft_reset(struct radeon_device *rdev)
738 {
739         struct rv515_mc_save save;
740         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
741                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
742                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
743                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
744                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
745                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
746                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
747                                 S_008010_GUI_ACTIVE(1);
748         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
749                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
750                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
751                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
752                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
753                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
754                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
755                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
756         u32 srbm_reset = 0;
757         u32 tmp;
758
759         dev_info(rdev->dev, "GPU softreset \n");
760         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
761                 RREG32(R_008010_GRBM_STATUS));
762         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
763                 RREG32(R_008014_GRBM_STATUS2));
764         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
765                 RREG32(R_000E50_SRBM_STATUS));
766         rv515_mc_stop(rdev, &save);
767         if (r600_mc_wait_for_idle(rdev)) {
768                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
769         }
770         /* Disable CP parsing/prefetching */
771         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
772         /* Check if any of the rendering block is busy and reset it */
773         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
774             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
775                 tmp = S_008020_SOFT_RESET_CR(1) |
776                         S_008020_SOFT_RESET_DB(1) |
777                         S_008020_SOFT_RESET_CB(1) |
778                         S_008020_SOFT_RESET_PA(1) |
779                         S_008020_SOFT_RESET_SC(1) |
780                         S_008020_SOFT_RESET_SMX(1) |
781                         S_008020_SOFT_RESET_SPI(1) |
782                         S_008020_SOFT_RESET_SX(1) |
783                         S_008020_SOFT_RESET_SH(1) |
784                         S_008020_SOFT_RESET_TC(1) |
785                         S_008020_SOFT_RESET_TA(1) |
786                         S_008020_SOFT_RESET_VC(1) |
787                         S_008020_SOFT_RESET_VGT(1);
788                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
789                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
790                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
791                 udelay(50);
792                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
793                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
794         }
795         /* Reset CP (we always reset CP) */
796         tmp = S_008020_SOFT_RESET_CP(1);
797         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
798         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
799         (void)RREG32(R_008020_GRBM_SOFT_RESET);
800         udelay(50);
801         WREG32(R_008020_GRBM_SOFT_RESET, 0);
802         (void)RREG32(R_008020_GRBM_SOFT_RESET);
803         /* Reset others GPU block if necessary */
804         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
805                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
806         if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
807                 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
808         if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
809                 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
810         if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
811                 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
812         if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
813                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
814         if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
815                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
816         if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
817                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
818         if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
819                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
820         if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
821                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
822         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
823                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
824         if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
825                 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
826         if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
827                 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
828         dev_info(rdev->dev, "  R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
829         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
830         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
831         udelay(50);
832         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
833         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
834         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
835         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
836         udelay(50);
837         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
838         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
839         /* Wait a little for things to settle down */
840         udelay(50);
841         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
842                 RREG32(R_008010_GRBM_STATUS));
843         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
844                 RREG32(R_008014_GRBM_STATUS2));
845         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
846                 RREG32(R_000E50_SRBM_STATUS));
847         /* After reset we need to reinit the asic as GPU often endup in an
848          * incoherent state.
849          */
850         atom_asic_init(rdev->mode_info.atom_context);
851         rv515_mc_resume(rdev, &save);
852         return 0;
853 }
854
855 int r600_gpu_reset(struct radeon_device *rdev)
856 {
857         return r600_gpu_soft_reset(rdev);
858 }
859
860 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
861                                              u32 num_backends,
862                                              u32 backend_disable_mask)
863 {
864         u32 backend_map = 0;
865         u32 enabled_backends_mask;
866         u32 enabled_backends_count;
867         u32 cur_pipe;
868         u32 swizzle_pipe[R6XX_MAX_PIPES];
869         u32 cur_backend;
870         u32 i;
871
872         if (num_tile_pipes > R6XX_MAX_PIPES)
873                 num_tile_pipes = R6XX_MAX_PIPES;
874         if (num_tile_pipes < 1)
875                 num_tile_pipes = 1;
876         if (num_backends > R6XX_MAX_BACKENDS)
877                 num_backends = R6XX_MAX_BACKENDS;
878         if (num_backends < 1)
879                 num_backends = 1;
880
881         enabled_backends_mask = 0;
882         enabled_backends_count = 0;
883         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
884                 if (((backend_disable_mask >> i) & 1) == 0) {
885                         enabled_backends_mask |= (1 << i);
886                         ++enabled_backends_count;
887                 }
888                 if (enabled_backends_count == num_backends)
889                         break;
890         }
891
892         if (enabled_backends_count == 0) {
893                 enabled_backends_mask = 1;
894                 enabled_backends_count = 1;
895         }
896
897         if (enabled_backends_count != num_backends)
898                 num_backends = enabled_backends_count;
899
900         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
901         switch (num_tile_pipes) {
902         case 1:
903                 swizzle_pipe[0] = 0;
904                 break;
905         case 2:
906                 swizzle_pipe[0] = 0;
907                 swizzle_pipe[1] = 1;
908                 break;
909         case 3:
910                 swizzle_pipe[0] = 0;
911                 swizzle_pipe[1] = 1;
912                 swizzle_pipe[2] = 2;
913                 break;
914         case 4:
915                 swizzle_pipe[0] = 0;
916                 swizzle_pipe[1] = 1;
917                 swizzle_pipe[2] = 2;
918                 swizzle_pipe[3] = 3;
919                 break;
920         case 5:
921                 swizzle_pipe[0] = 0;
922                 swizzle_pipe[1] = 1;
923                 swizzle_pipe[2] = 2;
924                 swizzle_pipe[3] = 3;
925                 swizzle_pipe[4] = 4;
926                 break;
927         case 6:
928                 swizzle_pipe[0] = 0;
929                 swizzle_pipe[1] = 2;
930                 swizzle_pipe[2] = 4;
931                 swizzle_pipe[3] = 5;
932                 swizzle_pipe[4] = 1;
933                 swizzle_pipe[5] = 3;
934                 break;
935         case 7:
936                 swizzle_pipe[0] = 0;
937                 swizzle_pipe[1] = 2;
938                 swizzle_pipe[2] = 4;
939                 swizzle_pipe[3] = 6;
940                 swizzle_pipe[4] = 1;
941                 swizzle_pipe[5] = 3;
942                 swizzle_pipe[6] = 5;
943                 break;
944         case 8:
945                 swizzle_pipe[0] = 0;
946                 swizzle_pipe[1] = 2;
947                 swizzle_pipe[2] = 4;
948                 swizzle_pipe[3] = 6;
949                 swizzle_pipe[4] = 1;
950                 swizzle_pipe[5] = 3;
951                 swizzle_pipe[6] = 5;
952                 swizzle_pipe[7] = 7;
953                 break;
954         }
955
956         cur_backend = 0;
957         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
958                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
959                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
960
961                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
962
963                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
964         }
965
966         return backend_map;
967 }
968
969 int r600_count_pipe_bits(uint32_t val)
970 {
971         int i, ret = 0;
972
973         for (i = 0; i < 32; i++) {
974                 ret += val & 1;
975                 val >>= 1;
976         }
977         return ret;
978 }
979
980 void r600_gpu_init(struct radeon_device *rdev)
981 {
982         u32 tiling_config;
983         u32 ramcfg;
984         u32 tmp;
985         int i, j;
986         u32 sq_config;
987         u32 sq_gpr_resource_mgmt_1 = 0;
988         u32 sq_gpr_resource_mgmt_2 = 0;
989         u32 sq_thread_resource_mgmt = 0;
990         u32 sq_stack_resource_mgmt_1 = 0;
991         u32 sq_stack_resource_mgmt_2 = 0;
992
993         /* FIXME: implement */
994         switch (rdev->family) {
995         case CHIP_R600:
996                 rdev->config.r600.max_pipes = 4;
997                 rdev->config.r600.max_tile_pipes = 8;
998                 rdev->config.r600.max_simds = 4;
999                 rdev->config.r600.max_backends = 4;
1000                 rdev->config.r600.max_gprs = 256;
1001                 rdev->config.r600.max_threads = 192;
1002                 rdev->config.r600.max_stack_entries = 256;
1003                 rdev->config.r600.max_hw_contexts = 8;
1004                 rdev->config.r600.max_gs_threads = 16;
1005                 rdev->config.r600.sx_max_export_size = 128;
1006                 rdev->config.r600.sx_max_export_pos_size = 16;
1007                 rdev->config.r600.sx_max_export_smx_size = 128;
1008                 rdev->config.r600.sq_num_cf_insts = 2;
1009                 break;
1010         case CHIP_RV630:
1011         case CHIP_RV635:
1012                 rdev->config.r600.max_pipes = 2;
1013                 rdev->config.r600.max_tile_pipes = 2;
1014                 rdev->config.r600.max_simds = 3;
1015                 rdev->config.r600.max_backends = 1;
1016                 rdev->config.r600.max_gprs = 128;
1017                 rdev->config.r600.max_threads = 192;
1018                 rdev->config.r600.max_stack_entries = 128;
1019                 rdev->config.r600.max_hw_contexts = 8;
1020                 rdev->config.r600.max_gs_threads = 4;
1021                 rdev->config.r600.sx_max_export_size = 128;
1022                 rdev->config.r600.sx_max_export_pos_size = 16;
1023                 rdev->config.r600.sx_max_export_smx_size = 128;
1024                 rdev->config.r600.sq_num_cf_insts = 2;
1025                 break;
1026         case CHIP_RV610:
1027         case CHIP_RV620:
1028         case CHIP_RS780:
1029         case CHIP_RS880:
1030                 rdev->config.r600.max_pipes = 1;
1031                 rdev->config.r600.max_tile_pipes = 1;
1032                 rdev->config.r600.max_simds = 2;
1033                 rdev->config.r600.max_backends = 1;
1034                 rdev->config.r600.max_gprs = 128;
1035                 rdev->config.r600.max_threads = 192;
1036                 rdev->config.r600.max_stack_entries = 128;
1037                 rdev->config.r600.max_hw_contexts = 4;
1038                 rdev->config.r600.max_gs_threads = 4;
1039                 rdev->config.r600.sx_max_export_size = 128;
1040                 rdev->config.r600.sx_max_export_pos_size = 16;
1041                 rdev->config.r600.sx_max_export_smx_size = 128;
1042                 rdev->config.r600.sq_num_cf_insts = 1;
1043                 break;
1044         case CHIP_RV670:
1045                 rdev->config.r600.max_pipes = 4;
1046                 rdev->config.r600.max_tile_pipes = 4;
1047                 rdev->config.r600.max_simds = 4;
1048                 rdev->config.r600.max_backends = 4;
1049                 rdev->config.r600.max_gprs = 192;
1050                 rdev->config.r600.max_threads = 192;
1051                 rdev->config.r600.max_stack_entries = 256;
1052                 rdev->config.r600.max_hw_contexts = 8;
1053                 rdev->config.r600.max_gs_threads = 16;
1054                 rdev->config.r600.sx_max_export_size = 128;
1055                 rdev->config.r600.sx_max_export_pos_size = 16;
1056                 rdev->config.r600.sx_max_export_smx_size = 128;
1057                 rdev->config.r600.sq_num_cf_insts = 2;
1058                 break;
1059         default:
1060                 break;
1061         }
1062
1063         /* Initialize HDP */
1064         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1065                 WREG32((0x2c14 + j), 0x00000000);
1066                 WREG32((0x2c18 + j), 0x00000000);
1067                 WREG32((0x2c1c + j), 0x00000000);
1068                 WREG32((0x2c20 + j), 0x00000000);
1069                 WREG32((0x2c24 + j), 0x00000000);
1070         }
1071
1072         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1073
1074         /* Setup tiling */
1075         tiling_config = 0;
1076         ramcfg = RREG32(RAMCFG);
1077         switch (rdev->config.r600.max_tile_pipes) {
1078         case 1:
1079                 tiling_config |= PIPE_TILING(0);
1080                 break;
1081         case 2:
1082                 tiling_config |= PIPE_TILING(1);
1083                 break;
1084         case 4:
1085                 tiling_config |= PIPE_TILING(2);
1086                 break;
1087         case 8:
1088                 tiling_config |= PIPE_TILING(3);
1089                 break;
1090         default:
1091                 break;
1092         }
1093         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1094         tiling_config |= GROUP_SIZE(0);
1095         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1096         if (tmp > 3) {
1097                 tiling_config |= ROW_TILING(3);
1098                 tiling_config |= SAMPLE_SPLIT(3);
1099         } else {
1100                 tiling_config |= ROW_TILING(tmp);
1101                 tiling_config |= SAMPLE_SPLIT(tmp);
1102         }
1103         tiling_config |= BANK_SWAPS(1);
1104         tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1105                                                 rdev->config.r600.max_backends,
1106                                                 (0xff << rdev->config.r600.max_backends) & 0xff);
1107         tiling_config |= BACKEND_MAP(tmp);
1108         WREG32(GB_TILING_CONFIG, tiling_config);
1109         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1110         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1111
1112         tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1113         WREG32(CC_RB_BACKEND_DISABLE, tmp);
1114
1115         /* Setup pipes */
1116         tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1117         tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1118         WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
1119         WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
1120
1121         tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
1122         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1123         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1124
1125         /* Setup some CP states */
1126         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1127         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1128
1129         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1130                              SYNC_WALKER | SYNC_ALIGNER));
1131         /* Setup various GPU states */
1132         if (rdev->family == CHIP_RV670)
1133                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1134
1135         tmp = RREG32(SX_DEBUG_1);
1136         tmp |= SMX_EVENT_RELEASE;
1137         if ((rdev->family > CHIP_R600))
1138                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1139         WREG32(SX_DEBUG_1, tmp);
1140
1141         if (((rdev->family) == CHIP_R600) ||
1142             ((rdev->family) == CHIP_RV630) ||
1143             ((rdev->family) == CHIP_RV610) ||
1144             ((rdev->family) == CHIP_RV620) ||
1145             ((rdev->family) == CHIP_RS780) ||
1146             ((rdev->family) == CHIP_RS880)) {
1147                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1148         } else {
1149                 WREG32(DB_DEBUG, 0);
1150         }
1151         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1152                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1153
1154         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1155         WREG32(VGT_NUM_INSTANCES, 0);
1156
1157         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1158         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1159
1160         tmp = RREG32(SQ_MS_FIFO_SIZES);
1161         if (((rdev->family) == CHIP_RV610) ||
1162             ((rdev->family) == CHIP_RV620) ||
1163             ((rdev->family) == CHIP_RS780) ||
1164             ((rdev->family) == CHIP_RS880)) {
1165                 tmp = (CACHE_FIFO_SIZE(0xa) |
1166                        FETCH_FIFO_HIWATER(0xa) |
1167                        DONE_FIFO_HIWATER(0xe0) |
1168                        ALU_UPDATE_FIFO_HIWATER(0x8));
1169         } else if (((rdev->family) == CHIP_R600) ||
1170                    ((rdev->family) == CHIP_RV630)) {
1171                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1172                 tmp |= DONE_FIFO_HIWATER(0x4);
1173         }
1174         WREG32(SQ_MS_FIFO_SIZES, tmp);
1175
1176         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1177          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1178          */
1179         sq_config = RREG32(SQ_CONFIG);
1180         sq_config &= ~(PS_PRIO(3) |
1181                        VS_PRIO(3) |
1182                        GS_PRIO(3) |
1183                        ES_PRIO(3));
1184         sq_config |= (DX9_CONSTS |
1185                       VC_ENABLE |
1186                       PS_PRIO(0) |
1187                       VS_PRIO(1) |
1188                       GS_PRIO(2) |
1189                       ES_PRIO(3));
1190
1191         if ((rdev->family) == CHIP_R600) {
1192                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1193                                           NUM_VS_GPRS(124) |
1194                                           NUM_CLAUSE_TEMP_GPRS(4));
1195                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1196                                           NUM_ES_GPRS(0));
1197                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1198                                            NUM_VS_THREADS(48) |
1199                                            NUM_GS_THREADS(4) |
1200                                            NUM_ES_THREADS(4));
1201                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1202                                             NUM_VS_STACK_ENTRIES(128));
1203                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1204                                             NUM_ES_STACK_ENTRIES(0));
1205         } else if (((rdev->family) == CHIP_RV610) ||
1206                    ((rdev->family) == CHIP_RV620) ||
1207                    ((rdev->family) == CHIP_RS780) ||
1208                    ((rdev->family) == CHIP_RS880)) {
1209                 /* no vertex cache */
1210                 sq_config &= ~VC_ENABLE;
1211
1212                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1213                                           NUM_VS_GPRS(44) |
1214                                           NUM_CLAUSE_TEMP_GPRS(2));
1215                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1216                                           NUM_ES_GPRS(17));
1217                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1218                                            NUM_VS_THREADS(78) |
1219                                            NUM_GS_THREADS(4) |
1220                                            NUM_ES_THREADS(31));
1221                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1222                                             NUM_VS_STACK_ENTRIES(40));
1223                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1224                                             NUM_ES_STACK_ENTRIES(16));
1225         } else if (((rdev->family) == CHIP_RV630) ||
1226                    ((rdev->family) == CHIP_RV635)) {
1227                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1228                                           NUM_VS_GPRS(44) |
1229                                           NUM_CLAUSE_TEMP_GPRS(2));
1230                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1231                                           NUM_ES_GPRS(18));
1232                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1233                                            NUM_VS_THREADS(78) |
1234                                            NUM_GS_THREADS(4) |
1235                                            NUM_ES_THREADS(31));
1236                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1237                                             NUM_VS_STACK_ENTRIES(40));
1238                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1239                                             NUM_ES_STACK_ENTRIES(16));
1240         } else if ((rdev->family) == CHIP_RV670) {
1241                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1242                                           NUM_VS_GPRS(44) |
1243                                           NUM_CLAUSE_TEMP_GPRS(2));
1244                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1245                                           NUM_ES_GPRS(17));
1246                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1247                                            NUM_VS_THREADS(78) |
1248                                            NUM_GS_THREADS(4) |
1249                                            NUM_ES_THREADS(31));
1250                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1251                                             NUM_VS_STACK_ENTRIES(64));
1252                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1253                                             NUM_ES_STACK_ENTRIES(64));
1254         }
1255
1256         WREG32(SQ_CONFIG, sq_config);
1257         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1258         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1259         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1260         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1261         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1262
1263         if (((rdev->family) == CHIP_RV610) ||
1264             ((rdev->family) == CHIP_RV620) ||
1265             ((rdev->family) == CHIP_RS780) ||
1266             ((rdev->family) == CHIP_RS880)) {
1267                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1268         } else {
1269                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1270         }
1271
1272         /* More default values. 2D/3D driver should adjust as needed */
1273         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1274                                          S1_X(0x4) | S1_Y(0xc)));
1275         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1276                                          S1_X(0x2) | S1_Y(0x2) |
1277                                          S2_X(0xa) | S2_Y(0x6) |
1278                                          S3_X(0x6) | S3_Y(0xa)));
1279         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1280                                              S1_X(0x4) | S1_Y(0xc) |
1281                                              S2_X(0x1) | S2_Y(0x6) |
1282                                              S3_X(0xa) | S3_Y(0xe)));
1283         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1284                                              S5_X(0x0) | S5_Y(0x0) |
1285                                              S6_X(0xb) | S6_Y(0x4) |
1286                                              S7_X(0x7) | S7_Y(0x8)));
1287
1288         WREG32(VGT_STRMOUT_EN, 0);
1289         tmp = rdev->config.r600.max_pipes * 16;
1290         switch (rdev->family) {
1291         case CHIP_RV610:
1292         case CHIP_RV620:
1293         case CHIP_RS780:
1294         case CHIP_RS880:
1295                 tmp += 32;
1296                 break;
1297         case CHIP_RV670:
1298                 tmp += 128;
1299                 break;
1300         default:
1301                 break;
1302         }
1303         if (tmp > 256) {
1304                 tmp = 256;
1305         }
1306         WREG32(VGT_ES_PER_GS, 128);
1307         WREG32(VGT_GS_PER_ES, tmp);
1308         WREG32(VGT_GS_PER_VS, 2);
1309         WREG32(VGT_GS_VERTEX_REUSE, 16);
1310
1311         /* more default values. 2D/3D driver should adjust as needed */
1312         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1313         WREG32(VGT_STRMOUT_EN, 0);
1314         WREG32(SX_MISC, 0);
1315         WREG32(PA_SC_MODE_CNTL, 0);
1316         WREG32(PA_SC_AA_CONFIG, 0);
1317         WREG32(PA_SC_LINE_STIPPLE, 0);
1318         WREG32(SPI_INPUT_Z, 0);
1319         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1320         WREG32(CB_COLOR7_FRAG, 0);
1321
1322         /* Clear render buffer base addresses */
1323         WREG32(CB_COLOR0_BASE, 0);
1324         WREG32(CB_COLOR1_BASE, 0);
1325         WREG32(CB_COLOR2_BASE, 0);
1326         WREG32(CB_COLOR3_BASE, 0);
1327         WREG32(CB_COLOR4_BASE, 0);
1328         WREG32(CB_COLOR5_BASE, 0);
1329         WREG32(CB_COLOR6_BASE, 0);
1330         WREG32(CB_COLOR7_BASE, 0);
1331         WREG32(CB_COLOR7_FRAG, 0);
1332
1333         switch (rdev->family) {
1334         case CHIP_RV610:
1335         case CHIP_RV620:
1336         case CHIP_RS780:
1337         case CHIP_RS880:
1338                 tmp = TC_L2_SIZE(8);
1339                 break;
1340         case CHIP_RV630:
1341         case CHIP_RV635:
1342                 tmp = TC_L2_SIZE(4);
1343                 break;
1344         case CHIP_R600:
1345                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1346                 break;
1347         default:
1348                 tmp = TC_L2_SIZE(0);
1349                 break;
1350         }
1351         WREG32(TC_CNTL, tmp);
1352
1353         tmp = RREG32(HDP_HOST_PATH_CNTL);
1354         WREG32(HDP_HOST_PATH_CNTL, tmp);
1355
1356         tmp = RREG32(ARB_POP);
1357         tmp |= ENABLE_TC128;
1358         WREG32(ARB_POP, tmp);
1359
1360         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1361         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1362                                NUM_CLIP_SEQ(3)));
1363         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1364 }
1365
1366
1367 /*
1368  * Indirect registers accessor
1369  */
1370 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1371 {
1372         u32 r;
1373
1374         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1375         (void)RREG32(PCIE_PORT_INDEX);
1376         r = RREG32(PCIE_PORT_DATA);
1377         return r;
1378 }
1379
1380 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1381 {
1382         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1383         (void)RREG32(PCIE_PORT_INDEX);
1384         WREG32(PCIE_PORT_DATA, (v));
1385         (void)RREG32(PCIE_PORT_DATA);
1386 }
1387
1388 /*
1389  * CP & Ring
1390  */
1391 void r600_cp_stop(struct radeon_device *rdev)
1392 {
1393         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1394 }
1395
1396 int r600_init_microcode(struct radeon_device *rdev)
1397 {
1398         struct platform_device *pdev;
1399         const char *chip_name;
1400         const char *rlc_chip_name;
1401         size_t pfp_req_size, me_req_size, rlc_req_size;
1402         char fw_name[30];
1403         int err;
1404
1405         DRM_DEBUG("\n");
1406
1407         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1408         err = IS_ERR(pdev);
1409         if (err) {
1410                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1411                 return -EINVAL;
1412         }
1413
1414         switch (rdev->family) {
1415         case CHIP_R600:
1416                 chip_name = "R600";
1417                 rlc_chip_name = "R600";
1418                 break;
1419         case CHIP_RV610:
1420                 chip_name = "RV610";
1421                 rlc_chip_name = "R600";
1422                 break;
1423         case CHIP_RV630:
1424                 chip_name = "RV630";
1425                 rlc_chip_name = "R600";
1426                 break;
1427         case CHIP_RV620:
1428                 chip_name = "RV620";
1429                 rlc_chip_name = "R600";
1430                 break;
1431         case CHIP_RV635:
1432                 chip_name = "RV635";
1433                 rlc_chip_name = "R600";
1434                 break;
1435         case CHIP_RV670:
1436                 chip_name = "RV670";
1437                 rlc_chip_name = "R600";
1438                 break;
1439         case CHIP_RS780:
1440         case CHIP_RS880:
1441                 chip_name = "RS780";
1442                 rlc_chip_name = "R600";
1443                 break;
1444         case CHIP_RV770:
1445                 chip_name = "RV770";
1446                 rlc_chip_name = "R700";
1447                 break;
1448         case CHIP_RV730:
1449         case CHIP_RV740:
1450                 chip_name = "RV730";
1451                 rlc_chip_name = "R700";
1452                 break;
1453         case CHIP_RV710:
1454                 chip_name = "RV710";
1455                 rlc_chip_name = "R700";
1456                 break;
1457         default: BUG();
1458         }
1459
1460         if (rdev->family >= CHIP_RV770) {
1461                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1462                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1463                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1464         } else {
1465                 pfp_req_size = PFP_UCODE_SIZE * 4;
1466                 me_req_size = PM4_UCODE_SIZE * 12;
1467                 rlc_req_size = RLC_UCODE_SIZE * 4;
1468         }
1469
1470         DRM_INFO("Loading %s Microcode\n", chip_name);
1471
1472         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1473         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1474         if (err)
1475                 goto out;
1476         if (rdev->pfp_fw->size != pfp_req_size) {
1477                 printk(KERN_ERR
1478                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1479                        rdev->pfp_fw->size, fw_name);
1480                 err = -EINVAL;
1481                 goto out;
1482         }
1483
1484         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1485         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1486         if (err)
1487                 goto out;
1488         if (rdev->me_fw->size != me_req_size) {
1489                 printk(KERN_ERR
1490                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1491                        rdev->me_fw->size, fw_name);
1492                 err = -EINVAL;
1493         }
1494
1495         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1496         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1497         if (err)
1498                 goto out;
1499         if (rdev->rlc_fw->size != rlc_req_size) {
1500                 printk(KERN_ERR
1501                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1502                        rdev->rlc_fw->size, fw_name);
1503                 err = -EINVAL;
1504         }
1505
1506 out:
1507         platform_device_unregister(pdev);
1508
1509         if (err) {
1510                 if (err != -EINVAL)
1511                         printk(KERN_ERR
1512                                "r600_cp: Failed to load firmware \"%s\"\n",
1513                                fw_name);
1514                 release_firmware(rdev->pfp_fw);
1515                 rdev->pfp_fw = NULL;
1516                 release_firmware(rdev->me_fw);
1517                 rdev->me_fw = NULL;
1518                 release_firmware(rdev->rlc_fw);
1519                 rdev->rlc_fw = NULL;
1520         }
1521         return err;
1522 }
1523
1524 static int r600_cp_load_microcode(struct radeon_device *rdev)
1525 {
1526         const __be32 *fw_data;
1527         int i;
1528
1529         if (!rdev->me_fw || !rdev->pfp_fw)
1530                 return -EINVAL;
1531
1532         r600_cp_stop(rdev);
1533
1534         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1535
1536         /* Reset cp */
1537         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1538         RREG32(GRBM_SOFT_RESET);
1539         mdelay(15);
1540         WREG32(GRBM_SOFT_RESET, 0);
1541
1542         WREG32(CP_ME_RAM_WADDR, 0);
1543
1544         fw_data = (const __be32 *)rdev->me_fw->data;
1545         WREG32(CP_ME_RAM_WADDR, 0);
1546         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1547                 WREG32(CP_ME_RAM_DATA,
1548                        be32_to_cpup(fw_data++));
1549
1550         fw_data = (const __be32 *)rdev->pfp_fw->data;
1551         WREG32(CP_PFP_UCODE_ADDR, 0);
1552         for (i = 0; i < PFP_UCODE_SIZE; i++)
1553                 WREG32(CP_PFP_UCODE_DATA,
1554                        be32_to_cpup(fw_data++));
1555
1556         WREG32(CP_PFP_UCODE_ADDR, 0);
1557         WREG32(CP_ME_RAM_WADDR, 0);
1558         WREG32(CP_ME_RAM_RADDR, 0);
1559         return 0;
1560 }
1561
1562 int r600_cp_start(struct radeon_device *rdev)
1563 {
1564         int r;
1565         uint32_t cp_me;
1566
1567         r = radeon_ring_lock(rdev, 7);
1568         if (r) {
1569                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1570                 return r;
1571         }
1572         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1573         radeon_ring_write(rdev, 0x1);
1574         if (rdev->family < CHIP_RV770) {
1575                 radeon_ring_write(rdev, 0x3);
1576                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1577         } else {
1578                 radeon_ring_write(rdev, 0x0);
1579                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1580         }
1581         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1582         radeon_ring_write(rdev, 0);
1583         radeon_ring_write(rdev, 0);
1584         radeon_ring_unlock_commit(rdev);
1585
1586         cp_me = 0xff;
1587         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1588         return 0;
1589 }
1590
1591 int r600_cp_resume(struct radeon_device *rdev)
1592 {
1593         u32 tmp;
1594         u32 rb_bufsz;
1595         int r;
1596
1597         /* Reset cp */
1598         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1599         RREG32(GRBM_SOFT_RESET);
1600         mdelay(15);
1601         WREG32(GRBM_SOFT_RESET, 0);
1602
1603         /* Set ring buffer size */
1604         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1605         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1606 #ifdef __BIG_ENDIAN
1607         tmp |= BUF_SWAP_32BIT;
1608 #endif
1609         WREG32(CP_RB_CNTL, tmp);
1610         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1611
1612         /* Set the write pointer delay */
1613         WREG32(CP_RB_WPTR_DELAY, 0);
1614
1615         /* Initialize the ring buffer's read and write pointers */
1616         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1617         WREG32(CP_RB_RPTR_WR, 0);
1618         WREG32(CP_RB_WPTR, 0);
1619         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1620         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1621         mdelay(1);
1622         WREG32(CP_RB_CNTL, tmp);
1623
1624         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1625         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1626
1627         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1628         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1629
1630         r600_cp_start(rdev);
1631         rdev->cp.ready = true;
1632         r = radeon_ring_test(rdev);
1633         if (r) {
1634                 rdev->cp.ready = false;
1635                 return r;
1636         }
1637         return 0;
1638 }
1639
1640 void r600_cp_commit(struct radeon_device *rdev)
1641 {
1642         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1643         (void)RREG32(CP_RB_WPTR);
1644 }
1645
1646 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1647 {
1648         u32 rb_bufsz;
1649
1650         /* Align ring size */
1651         rb_bufsz = drm_order(ring_size / 8);
1652         ring_size = (1 << (rb_bufsz + 1)) * 4;
1653         rdev->cp.ring_size = ring_size;
1654         rdev->cp.align_mask = 16 - 1;
1655 }
1656
1657 void r600_cp_fini(struct radeon_device *rdev)
1658 {
1659         r600_cp_stop(rdev);
1660         radeon_ring_fini(rdev);
1661 }
1662
1663
1664 /*
1665  * GPU scratch registers helpers function.
1666  */
1667 void r600_scratch_init(struct radeon_device *rdev)
1668 {
1669         int i;
1670
1671         rdev->scratch.num_reg = 7;
1672         for (i = 0; i < rdev->scratch.num_reg; i++) {
1673                 rdev->scratch.free[i] = true;
1674                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1675         }
1676 }
1677
1678 int r600_ring_test(struct radeon_device *rdev)
1679 {
1680         uint32_t scratch;
1681         uint32_t tmp = 0;
1682         unsigned i;
1683         int r;
1684
1685         r = radeon_scratch_get(rdev, &scratch);
1686         if (r) {
1687                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1688                 return r;
1689         }
1690         WREG32(scratch, 0xCAFEDEAD);
1691         r = radeon_ring_lock(rdev, 3);
1692         if (r) {
1693                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1694                 radeon_scratch_free(rdev, scratch);
1695                 return r;
1696         }
1697         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1698         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1699         radeon_ring_write(rdev, 0xDEADBEEF);
1700         radeon_ring_unlock_commit(rdev);
1701         for (i = 0; i < rdev->usec_timeout; i++) {
1702                 tmp = RREG32(scratch);
1703                 if (tmp == 0xDEADBEEF)
1704                         break;
1705                 DRM_UDELAY(1);
1706         }
1707         if (i < rdev->usec_timeout) {
1708                 DRM_INFO("ring test succeeded in %d usecs\n", i);
1709         } else {
1710                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1711                           scratch, tmp);
1712                 r = -EINVAL;
1713         }
1714         radeon_scratch_free(rdev, scratch);
1715         return r;
1716 }
1717
1718 void r600_wb_disable(struct radeon_device *rdev)
1719 {
1720         int r;
1721
1722         WREG32(SCRATCH_UMSK, 0);
1723         if (rdev->wb.wb_obj) {
1724                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1725                 if (unlikely(r != 0))
1726                         return;
1727                 radeon_bo_kunmap(rdev->wb.wb_obj);
1728                 radeon_bo_unpin(rdev->wb.wb_obj);
1729                 radeon_bo_unreserve(rdev->wb.wb_obj);
1730         }
1731 }
1732
1733 void r600_wb_fini(struct radeon_device *rdev)
1734 {
1735         r600_wb_disable(rdev);
1736         if (rdev->wb.wb_obj) {
1737                 radeon_bo_unref(&rdev->wb.wb_obj);
1738                 rdev->wb.wb = NULL;
1739                 rdev->wb.wb_obj = NULL;
1740         }
1741 }
1742
1743 int r600_wb_enable(struct radeon_device *rdev)
1744 {
1745         int r;
1746
1747         if (rdev->wb.wb_obj == NULL) {
1748                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1749                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1750                 if (r) {
1751                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1752                         return r;
1753                 }
1754                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1755                 if (unlikely(r != 0)) {
1756                         r600_wb_fini(rdev);
1757                         return r;
1758                 }
1759                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1760                                 &rdev->wb.gpu_addr);
1761                 if (r) {
1762                         radeon_bo_unreserve(rdev->wb.wb_obj);
1763                         dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1764                         r600_wb_fini(rdev);
1765                         return r;
1766                 }
1767                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1768                 radeon_bo_unreserve(rdev->wb.wb_obj);
1769                 if (r) {
1770                         dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1771                         r600_wb_fini(rdev);
1772                         return r;
1773                 }
1774         }
1775         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1776         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1777         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1778         WREG32(SCRATCH_UMSK, 0xff);
1779         return 0;
1780 }
1781
1782 void r600_fence_ring_emit(struct radeon_device *rdev,
1783                           struct radeon_fence *fence)
1784 {
1785         /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
1786         /* Emit fence sequence & fire IRQ */
1787         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1788         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1789         radeon_ring_write(rdev, fence->seq);
1790         radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
1791         radeon_ring_write(rdev, 1);
1792         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1793         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1794         radeon_ring_write(rdev, RB_INT_STAT);
1795 }
1796
1797 int r600_copy_blit(struct radeon_device *rdev,
1798                    uint64_t src_offset, uint64_t dst_offset,
1799                    unsigned num_pages, struct radeon_fence *fence)
1800 {
1801         int r;
1802
1803         mutex_lock(&rdev->r600_blit.mutex);
1804         rdev->r600_blit.vb_ib = NULL;
1805         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1806         if (r) {
1807                 if (rdev->r600_blit.vb_ib)
1808                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1809                 mutex_unlock(&rdev->r600_blit.mutex);
1810                 return r;
1811         }
1812         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1813         r600_blit_done_copy(rdev, fence);
1814         mutex_unlock(&rdev->r600_blit.mutex);
1815         return 0;
1816 }
1817
1818 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1819                          uint32_t tiling_flags, uint32_t pitch,
1820                          uint32_t offset, uint32_t obj_size)
1821 {
1822         /* FIXME: implement */
1823         return 0;
1824 }
1825
1826 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1827 {
1828         /* FIXME: implement */
1829 }
1830
1831
1832 bool r600_card_posted(struct radeon_device *rdev)
1833 {
1834         uint32_t reg;
1835
1836         /* first check CRTCs */
1837         reg = RREG32(D1CRTC_CONTROL) |
1838                 RREG32(D2CRTC_CONTROL);
1839         if (reg & CRTC_EN)
1840                 return true;
1841
1842         /* then check MEM_SIZE, in case the crtcs are off */
1843         if (RREG32(CONFIG_MEMSIZE))
1844                 return true;
1845
1846         return false;
1847 }
1848
1849 int r600_startup(struct radeon_device *rdev)
1850 {
1851         int r;
1852
1853         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1854                 r = r600_init_microcode(rdev);
1855                 if (r) {
1856                         DRM_ERROR("Failed to load firmware!\n");
1857                         return r;
1858                 }
1859         }
1860
1861         r600_mc_program(rdev);
1862         if (rdev->flags & RADEON_IS_AGP) {
1863                 r600_agp_enable(rdev);
1864         } else {
1865                 r = r600_pcie_gart_enable(rdev);
1866                 if (r)
1867                         return r;
1868         }
1869         r600_gpu_init(rdev);
1870         r = r600_blit_init(rdev);
1871         if (r) {
1872                 r600_blit_fini(rdev);
1873                 rdev->asic->copy = NULL;
1874                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1875         }
1876         /* pin copy shader into vram */
1877         if (rdev->r600_blit.shader_obj) {
1878                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1879                 if (unlikely(r != 0))
1880                         return r;
1881                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1882                                 &rdev->r600_blit.shader_gpu_addr);
1883                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1884                 if (r) {
1885                         dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1886                         return r;
1887                 }
1888         }
1889         /* Enable IRQ */
1890         r = r600_irq_init(rdev);
1891         if (r) {
1892                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1893                 radeon_irq_kms_fini(rdev);
1894                 return r;
1895         }
1896         r600_irq_set(rdev);
1897
1898         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1899         if (r)
1900                 return r;
1901         r = r600_cp_load_microcode(rdev);
1902         if (r)
1903                 return r;
1904         r = r600_cp_resume(rdev);
1905         if (r)
1906                 return r;
1907         /* write back buffer are not vital so don't worry about failure */
1908         r600_wb_enable(rdev);
1909         return 0;
1910 }
1911
1912 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1913 {
1914         uint32_t temp;
1915
1916         temp = RREG32(CONFIG_CNTL);
1917         if (state == false) {
1918                 temp &= ~(1<<0);
1919                 temp |= (1<<1);
1920         } else {
1921                 temp &= ~(1<<1);
1922         }
1923         WREG32(CONFIG_CNTL, temp);
1924 }
1925
1926 int r600_resume(struct radeon_device *rdev)
1927 {
1928         int r;
1929
1930         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1931          * posting will perform necessary task to bring back GPU into good
1932          * shape.
1933          */
1934         /* post card */
1935         atom_asic_init(rdev->mode_info.atom_context);
1936         /* Initialize clocks */
1937         r = radeon_clocks_init(rdev);
1938         if (r) {
1939                 return r;
1940         }
1941
1942         r = r600_startup(rdev);
1943         if (r) {
1944                 DRM_ERROR("r600 startup failed on resume\n");
1945                 return r;
1946         }
1947
1948         r = r600_ib_test(rdev);
1949         if (r) {
1950                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1951                 return r;
1952         }
1953
1954         r = r600_audio_init(rdev);
1955         if (r) {
1956                 DRM_ERROR("radeon: audio resume failed\n");
1957                 return r;
1958         }
1959
1960         return r;
1961 }
1962
1963 int r600_suspend(struct radeon_device *rdev)
1964 {
1965         int r;
1966
1967         r600_audio_fini(rdev);
1968         /* FIXME: we should wait for ring to be empty */
1969         r600_cp_stop(rdev);
1970         rdev->cp.ready = false;
1971         r600_irq_suspend(rdev);
1972         r600_wb_disable(rdev);
1973         r600_pcie_gart_disable(rdev);
1974         /* unpin shaders bo */
1975         if (rdev->r600_blit.shader_obj) {
1976                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1977                 if (!r) {
1978                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
1979                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1980                 }
1981         }
1982         return 0;
1983 }
1984
1985 /* Plan is to move initialization in that function and use
1986  * helper function so that radeon_device_init pretty much
1987  * do nothing more than calling asic specific function. This
1988  * should also allow to remove a bunch of callback function
1989  * like vram_info.
1990  */
1991 int r600_init(struct radeon_device *rdev)
1992 {
1993         int r;
1994
1995         r = radeon_dummy_page_init(rdev);
1996         if (r)
1997                 return r;
1998         if (r600_debugfs_mc_info_init(rdev)) {
1999                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2000         }
2001         /* This don't do much */
2002         r = radeon_gem_init(rdev);
2003         if (r)
2004                 return r;
2005         /* Read BIOS */
2006         if (!radeon_get_bios(rdev)) {
2007                 if (ASIC_IS_AVIVO(rdev))
2008                         return -EINVAL;
2009         }
2010         /* Must be an ATOMBIOS */
2011         if (!rdev->is_atom_bios) {
2012                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2013                 return -EINVAL;
2014         }
2015         r = radeon_atombios_init(rdev);
2016         if (r)
2017                 return r;
2018         /* Post card if necessary */
2019         if (!r600_card_posted(rdev)) {
2020                 if (!rdev->bios) {
2021                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2022                         return -EINVAL;
2023                 }
2024                 DRM_INFO("GPU not posted. posting now...\n");
2025                 atom_asic_init(rdev->mode_info.atom_context);
2026         }
2027         /* Initialize scratch registers */
2028         r600_scratch_init(rdev);
2029         /* Initialize surface registers */
2030         radeon_surface_init(rdev);
2031         /* Initialize clocks */
2032         radeon_get_clock_info(rdev->ddev);
2033         r = radeon_clocks_init(rdev);
2034         if (r)
2035                 return r;
2036         /* Initialize power management */
2037         radeon_pm_init(rdev);
2038         /* Fence driver */
2039         r = radeon_fence_driver_init(rdev);
2040         if (r)
2041                 return r;
2042         if (rdev->flags & RADEON_IS_AGP) {
2043                 r = radeon_agp_init(rdev);
2044                 if (r)
2045                         radeon_agp_disable(rdev);
2046         }
2047         r = r600_mc_init(rdev);
2048         if (r)
2049                 return r;
2050         /* Memory manager */
2051         r = radeon_bo_init(rdev);
2052         if (r)
2053                 return r;
2054
2055         r = radeon_irq_kms_init(rdev);
2056         if (r)
2057                 return r;
2058
2059         rdev->cp.ring_obj = NULL;
2060         r600_ring_init(rdev, 1024 * 1024);
2061
2062         rdev->ih.ring_obj = NULL;
2063         r600_ih_ring_init(rdev, 64 * 1024);
2064
2065         r = r600_pcie_gart_init(rdev);
2066         if (r)
2067                 return r;
2068
2069         rdev->accel_working = true;
2070         r = r600_startup(rdev);
2071         if (r) {
2072                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2073                 r600_cp_fini(rdev);
2074                 r600_wb_fini(rdev);
2075                 r600_irq_fini(rdev);
2076                 radeon_irq_kms_fini(rdev);
2077                 r600_pcie_gart_fini(rdev);
2078                 rdev->accel_working = false;
2079         }
2080         if (rdev->accel_working) {
2081                 r = radeon_ib_pool_init(rdev);
2082                 if (r) {
2083                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2084                         rdev->accel_working = false;
2085                 } else {
2086                         r = r600_ib_test(rdev);
2087                         if (r) {
2088                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2089                                 rdev->accel_working = false;
2090                         }
2091                 }
2092         }
2093
2094         r = r600_audio_init(rdev);
2095         if (r)
2096                 return r; /* TODO error handling */
2097         return 0;
2098 }
2099
2100 void r600_fini(struct radeon_device *rdev)
2101 {
2102         r600_audio_fini(rdev);
2103         r600_blit_fini(rdev);
2104         r600_cp_fini(rdev);
2105         r600_wb_fini(rdev);
2106         r600_irq_fini(rdev);
2107         radeon_irq_kms_fini(rdev);
2108         r600_pcie_gart_fini(rdev);
2109         radeon_agp_fini(rdev);
2110         radeon_gem_fini(rdev);
2111         radeon_fence_driver_fini(rdev);
2112         radeon_clocks_fini(rdev);
2113         radeon_bo_fini(rdev);
2114         radeon_atombios_fini(rdev);
2115         kfree(rdev->bios);
2116         rdev->bios = NULL;
2117         radeon_dummy_page_fini(rdev);
2118 }
2119
2120
2121 /*
2122  * CS stuff
2123  */
2124 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2125 {
2126         /* FIXME: implement */
2127         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2128         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2129         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2130         radeon_ring_write(rdev, ib->length_dw);
2131 }
2132
2133 int r600_ib_test(struct radeon_device *rdev)
2134 {
2135         struct radeon_ib *ib;
2136         uint32_t scratch;
2137         uint32_t tmp = 0;
2138         unsigned i;
2139         int r;
2140
2141         r = radeon_scratch_get(rdev, &scratch);
2142         if (r) {
2143                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2144                 return r;
2145         }
2146         WREG32(scratch, 0xCAFEDEAD);
2147         r = radeon_ib_get(rdev, &ib);
2148         if (r) {
2149                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2150                 return r;
2151         }
2152         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2153         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2154         ib->ptr[2] = 0xDEADBEEF;
2155         ib->ptr[3] = PACKET2(0);
2156         ib->ptr[4] = PACKET2(0);
2157         ib->ptr[5] = PACKET2(0);
2158         ib->ptr[6] = PACKET2(0);
2159         ib->ptr[7] = PACKET2(0);
2160         ib->ptr[8] = PACKET2(0);
2161         ib->ptr[9] = PACKET2(0);
2162         ib->ptr[10] = PACKET2(0);
2163         ib->ptr[11] = PACKET2(0);
2164         ib->ptr[12] = PACKET2(0);
2165         ib->ptr[13] = PACKET2(0);
2166         ib->ptr[14] = PACKET2(0);
2167         ib->ptr[15] = PACKET2(0);
2168         ib->length_dw = 16;
2169         r = radeon_ib_schedule(rdev, ib);
2170         if (r) {
2171                 radeon_scratch_free(rdev, scratch);
2172                 radeon_ib_free(rdev, &ib);
2173                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2174                 return r;
2175         }
2176         r = radeon_fence_wait(ib->fence, false);
2177         if (r) {
2178                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2179                 return r;
2180         }
2181         for (i = 0; i < rdev->usec_timeout; i++) {
2182                 tmp = RREG32(scratch);
2183                 if (tmp == 0xDEADBEEF)
2184                         break;
2185                 DRM_UDELAY(1);
2186         }
2187         if (i < rdev->usec_timeout) {
2188                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2189         } else {
2190                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2191                           scratch, tmp);
2192                 r = -EINVAL;
2193         }
2194         radeon_scratch_free(rdev, scratch);
2195         radeon_ib_free(rdev, &ib);
2196         return r;
2197 }
2198
2199 /*
2200  * Interrupts
2201  *
2202  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2203  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2204  * writing to the ring and the GPU consuming, the GPU writes to the ring
2205  * and host consumes.  As the host irq handler processes interrupts, it
2206  * increments the rptr.  When the rptr catches up with the wptr, all the
2207  * current interrupts have been processed.
2208  */
2209
2210 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2211 {
2212         u32 rb_bufsz;
2213
2214         /* Align ring size */
2215         rb_bufsz = drm_order(ring_size / 4);
2216         ring_size = (1 << rb_bufsz) * 4;
2217         rdev->ih.ring_size = ring_size;
2218         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2219         rdev->ih.rptr = 0;
2220 }
2221
2222 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2223 {
2224         int r;
2225
2226         /* Allocate ring buffer */
2227         if (rdev->ih.ring_obj == NULL) {
2228                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2229                                      true,
2230                                      RADEON_GEM_DOMAIN_GTT,
2231                                      &rdev->ih.ring_obj);
2232                 if (r) {
2233                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2234                         return r;
2235                 }
2236                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2237                 if (unlikely(r != 0))
2238                         return r;
2239                 r = radeon_bo_pin(rdev->ih.ring_obj,
2240                                   RADEON_GEM_DOMAIN_GTT,
2241                                   &rdev->ih.gpu_addr);
2242                 if (r) {
2243                         radeon_bo_unreserve(rdev->ih.ring_obj);
2244                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2245                         return r;
2246                 }
2247                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2248                                    (void **)&rdev->ih.ring);
2249                 radeon_bo_unreserve(rdev->ih.ring_obj);
2250                 if (r) {
2251                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2252                         return r;
2253                 }
2254         }
2255         return 0;
2256 }
2257
2258 static void r600_ih_ring_fini(struct radeon_device *rdev)
2259 {
2260         int r;
2261         if (rdev->ih.ring_obj) {
2262                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2263                 if (likely(r == 0)) {
2264                         radeon_bo_kunmap(rdev->ih.ring_obj);
2265                         radeon_bo_unpin(rdev->ih.ring_obj);
2266                         radeon_bo_unreserve(rdev->ih.ring_obj);
2267                 }
2268                 radeon_bo_unref(&rdev->ih.ring_obj);
2269                 rdev->ih.ring = NULL;
2270                 rdev->ih.ring_obj = NULL;
2271         }
2272 }
2273
2274 static void r600_rlc_stop(struct radeon_device *rdev)
2275 {
2276
2277         if (rdev->family >= CHIP_RV770) {
2278                 /* r7xx asics need to soft reset RLC before halting */
2279                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2280                 RREG32(SRBM_SOFT_RESET);
2281                 udelay(15000);
2282                 WREG32(SRBM_SOFT_RESET, 0);
2283                 RREG32(SRBM_SOFT_RESET);
2284         }
2285
2286         WREG32(RLC_CNTL, 0);
2287 }
2288
2289 static void r600_rlc_start(struct radeon_device *rdev)
2290 {
2291         WREG32(RLC_CNTL, RLC_ENABLE);
2292 }
2293
2294 static int r600_rlc_init(struct radeon_device *rdev)
2295 {
2296         u32 i;
2297         const __be32 *fw_data;
2298
2299         if (!rdev->rlc_fw)
2300                 return -EINVAL;
2301
2302         r600_rlc_stop(rdev);
2303
2304         WREG32(RLC_HB_BASE, 0);
2305         WREG32(RLC_HB_CNTL, 0);
2306         WREG32(RLC_HB_RPTR, 0);
2307         WREG32(RLC_HB_WPTR, 0);
2308         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2309         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2310         WREG32(RLC_MC_CNTL, 0);
2311         WREG32(RLC_UCODE_CNTL, 0);
2312
2313         fw_data = (const __be32 *)rdev->rlc_fw->data;
2314         if (rdev->family >= CHIP_RV770) {
2315                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2316                         WREG32(RLC_UCODE_ADDR, i);
2317                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2318                 }
2319         } else {
2320                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2321                         WREG32(RLC_UCODE_ADDR, i);
2322                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2323                 }
2324         }
2325         WREG32(RLC_UCODE_ADDR, 0);
2326
2327         r600_rlc_start(rdev);
2328
2329         return 0;
2330 }
2331
2332 static void r600_enable_interrupts(struct radeon_device *rdev)
2333 {
2334         u32 ih_cntl = RREG32(IH_CNTL);
2335         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2336
2337         ih_cntl |= ENABLE_INTR;
2338         ih_rb_cntl |= IH_RB_ENABLE;
2339         WREG32(IH_CNTL, ih_cntl);
2340         WREG32(IH_RB_CNTL, ih_rb_cntl);
2341         rdev->ih.enabled = true;
2342 }
2343
2344 static void r600_disable_interrupts(struct radeon_device *rdev)
2345 {
2346         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2347         u32 ih_cntl = RREG32(IH_CNTL);
2348
2349         ih_rb_cntl &= ~IH_RB_ENABLE;
2350         ih_cntl &= ~ENABLE_INTR;
2351         WREG32(IH_RB_CNTL, ih_rb_cntl);
2352         WREG32(IH_CNTL, ih_cntl);
2353         /* set rptr, wptr to 0 */
2354         WREG32(IH_RB_RPTR, 0);
2355         WREG32(IH_RB_WPTR, 0);
2356         rdev->ih.enabled = false;
2357         rdev->ih.wptr = 0;
2358         rdev->ih.rptr = 0;
2359 }
2360
2361 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2362 {
2363         u32 tmp;
2364
2365         WREG32(CP_INT_CNTL, 0);
2366         WREG32(GRBM_INT_CNTL, 0);
2367         WREG32(DxMODE_INT_MASK, 0);
2368         if (ASIC_IS_DCE3(rdev)) {
2369                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2370                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2371                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2372                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2373                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2374                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2375                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2376                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2377                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2378                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2379                 if (ASIC_IS_DCE32(rdev)) {
2380                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2381                         WREG32(DC_HPD5_INT_CONTROL, 0);
2382                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2383                         WREG32(DC_HPD6_INT_CONTROL, 0);
2384                 }
2385         } else {
2386                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2387                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2388                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2389                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0);
2390                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2391                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0);
2392                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2393                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0);
2394         }
2395 }
2396
2397 int r600_irq_init(struct radeon_device *rdev)
2398 {
2399         int ret = 0;
2400         int rb_bufsz;
2401         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2402
2403         /* allocate ring */
2404         ret = r600_ih_ring_alloc(rdev);
2405         if (ret)
2406                 return ret;
2407
2408         /* disable irqs */
2409         r600_disable_interrupts(rdev);
2410
2411         /* init rlc */
2412         ret = r600_rlc_init(rdev);
2413         if (ret) {
2414                 r600_ih_ring_fini(rdev);
2415                 return ret;
2416         }
2417
2418         /* setup interrupt control */
2419         /* set dummy read address to ring address */
2420         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2421         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2422         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2423          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2424          */
2425         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2426         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2427         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2428         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2429
2430         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2431         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2432
2433         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2434                       IH_WPTR_OVERFLOW_CLEAR |
2435                       (rb_bufsz << 1));
2436         /* WPTR writeback, not yet */
2437         /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2438         WREG32(IH_RB_WPTR_ADDR_LO, 0);
2439         WREG32(IH_RB_WPTR_ADDR_HI, 0);
2440
2441         WREG32(IH_RB_CNTL, ih_rb_cntl);
2442
2443         /* set rptr, wptr to 0 */
2444         WREG32(IH_RB_RPTR, 0);
2445         WREG32(IH_RB_WPTR, 0);
2446
2447         /* Default settings for IH_CNTL (disabled at first) */
2448         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2449         /* RPTR_REARM only works if msi's are enabled */
2450         if (rdev->msi_enabled)
2451                 ih_cntl |= RPTR_REARM;
2452
2453 #ifdef __BIG_ENDIAN
2454         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2455 #endif
2456         WREG32(IH_CNTL, ih_cntl);
2457
2458         /* force the active interrupt state to all disabled */
2459         r600_disable_interrupt_state(rdev);
2460
2461         /* enable irqs */
2462         r600_enable_interrupts(rdev);
2463
2464         return ret;
2465 }
2466
2467 void r600_irq_suspend(struct radeon_device *rdev)
2468 {
2469         r600_disable_interrupts(rdev);
2470         r600_rlc_stop(rdev);
2471 }
2472
2473 void r600_irq_fini(struct radeon_device *rdev)
2474 {
2475         r600_irq_suspend(rdev);
2476         r600_ih_ring_fini(rdev);
2477 }
2478
2479 int r600_irq_set(struct radeon_device *rdev)
2480 {
2481         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2482         u32 mode_int = 0;
2483         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2484
2485         if (!rdev->irq.installed) {
2486                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2487                 return -EINVAL;
2488         }
2489         /* don't enable anything if the ih is disabled */
2490         if (!rdev->ih.enabled) {
2491                 r600_disable_interrupts(rdev);
2492                 /* force the active interrupt state to all disabled */
2493                 r600_disable_interrupt_state(rdev);
2494                 return 0;
2495         }
2496
2497         if (ASIC_IS_DCE3(rdev)) {
2498                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2499                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2500                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2501                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2502                 if (ASIC_IS_DCE32(rdev)) {
2503                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2504                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2505                 }
2506         } else {
2507                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2508                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2509                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2510         }
2511
2512         if (rdev->irq.sw_int) {
2513                 DRM_DEBUG("r600_irq_set: sw int\n");
2514                 cp_int_cntl |= RB_INT_ENABLE;
2515         }
2516         if (rdev->irq.crtc_vblank_int[0]) {
2517                 DRM_DEBUG("r600_irq_set: vblank 0\n");
2518                 mode_int |= D1MODE_VBLANK_INT_MASK;
2519         }
2520         if (rdev->irq.crtc_vblank_int[1]) {
2521                 DRM_DEBUG("r600_irq_set: vblank 1\n");
2522                 mode_int |= D2MODE_VBLANK_INT_MASK;
2523         }
2524         if (rdev->irq.hpd[0]) {
2525                 DRM_DEBUG("r600_irq_set: hpd 1\n");
2526                 hpd1 |= DC_HPDx_INT_EN;
2527         }
2528         if (rdev->irq.hpd[1]) {
2529                 DRM_DEBUG("r600_irq_set: hpd 2\n");
2530                 hpd2 |= DC_HPDx_INT_EN;
2531         }
2532         if (rdev->irq.hpd[2]) {
2533                 DRM_DEBUG("r600_irq_set: hpd 3\n");
2534                 hpd3 |= DC_HPDx_INT_EN;
2535         }
2536         if (rdev->irq.hpd[3]) {
2537                 DRM_DEBUG("r600_irq_set: hpd 4\n");
2538                 hpd4 |= DC_HPDx_INT_EN;
2539         }
2540         if (rdev->irq.hpd[4]) {
2541                 DRM_DEBUG("r600_irq_set: hpd 5\n");
2542                 hpd5 |= DC_HPDx_INT_EN;
2543         }
2544         if (rdev->irq.hpd[5]) {
2545                 DRM_DEBUG("r600_irq_set: hpd 6\n");
2546                 hpd6 |= DC_HPDx_INT_EN;
2547         }
2548
2549         WREG32(CP_INT_CNTL, cp_int_cntl);
2550         WREG32(DxMODE_INT_MASK, mode_int);
2551         if (ASIC_IS_DCE3(rdev)) {
2552                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2553                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2554                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2555                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2556                 if (ASIC_IS_DCE32(rdev)) {
2557                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2558                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2559                 }
2560         } else {
2561                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2562                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2563                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2564         }
2565
2566         return 0;
2567 }
2568
2569 static inline void r600_irq_ack(struct radeon_device *rdev,
2570                                 u32 *disp_int,
2571                                 u32 *disp_int_cont,
2572                                 u32 *disp_int_cont2)
2573 {
2574         u32 tmp;
2575
2576         if (ASIC_IS_DCE3(rdev)) {
2577                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2578                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2579                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2580         } else {
2581                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2582                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2583                 *disp_int_cont2 = 0;
2584         }
2585
2586         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2587                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2588         if (*disp_int & LB_D1_VLINE_INTERRUPT)
2589                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2590         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2591                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2592         if (*disp_int & LB_D2_VLINE_INTERRUPT)
2593                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2594         if (*disp_int & DC_HPD1_INTERRUPT) {
2595                 if (ASIC_IS_DCE3(rdev)) {
2596                         tmp = RREG32(DC_HPD1_INT_CONTROL);
2597                         tmp |= DC_HPDx_INT_ACK;
2598                         WREG32(DC_HPD1_INT_CONTROL, tmp);
2599                 } else {
2600                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2601                         tmp |= DC_HPDx_INT_ACK;
2602                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2603                 }
2604         }
2605         if (*disp_int & DC_HPD2_INTERRUPT) {
2606                 if (ASIC_IS_DCE3(rdev)) {
2607                         tmp = RREG32(DC_HPD2_INT_CONTROL);
2608                         tmp |= DC_HPDx_INT_ACK;
2609                         WREG32(DC_HPD2_INT_CONTROL, tmp);
2610                 } else {
2611                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2612                         tmp |= DC_HPDx_INT_ACK;
2613                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2614                 }
2615         }
2616         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2617                 if (ASIC_IS_DCE3(rdev)) {
2618                         tmp = RREG32(DC_HPD3_INT_CONTROL);
2619                         tmp |= DC_HPDx_INT_ACK;
2620                         WREG32(DC_HPD3_INT_CONTROL, tmp);
2621                 } else {
2622                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2623                         tmp |= DC_HPDx_INT_ACK;
2624                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2625                 }
2626         }
2627         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2628                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2629                 tmp |= DC_HPDx_INT_ACK;
2630                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2631         }
2632         if (ASIC_IS_DCE32(rdev)) {
2633                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2634                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2635                         tmp |= DC_HPDx_INT_ACK;
2636                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2637                 }
2638                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2639                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2640                         tmp |= DC_HPDx_INT_ACK;
2641                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2642                 }
2643         }
2644 }
2645
2646 void r600_irq_disable(struct radeon_device *rdev)
2647 {
2648         u32 disp_int, disp_int_cont, disp_int_cont2;
2649
2650         r600_disable_interrupts(rdev);
2651         /* Wait and acknowledge irq */
2652         mdelay(1);
2653         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2654         r600_disable_interrupt_state(rdev);
2655 }
2656
2657 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2658 {
2659         u32 wptr, tmp;
2660
2661         /* XXX use writeback */
2662         wptr = RREG32(IH_RB_WPTR);
2663
2664         if (wptr & RB_OVERFLOW) {
2665                 /* When a ring buffer overflow happen start parsing interrupt
2666                  * from the last not overwritten vector (wptr + 16). Hopefully
2667                  * this should allow us to catchup.
2668                  */
2669                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2670                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2671                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2672                 tmp = RREG32(IH_RB_CNTL);
2673                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2674                 WREG32(IH_RB_CNTL, tmp);
2675         }
2676         return (wptr & rdev->ih.ptr_mask);
2677 }
2678
2679 /*        r600 IV Ring
2680  * Each IV ring entry is 128 bits:
2681  * [7:0]    - interrupt source id
2682  * [31:8]   - reserved
2683  * [59:32]  - interrupt source data
2684  * [127:60]  - reserved
2685  *
2686  * The basic interrupt vector entries
2687  * are decoded as follows:
2688  * src_id  src_data  description
2689  *      1         0  D1 Vblank
2690  *      1         1  D1 Vline
2691  *      5         0  D2 Vblank
2692  *      5         1  D2 Vline
2693  *     19         0  FP Hot plug detection A
2694  *     19         1  FP Hot plug detection B
2695  *     19         2  DAC A auto-detection
2696  *     19         3  DAC B auto-detection
2697  *    176         -  CP_INT RB
2698  *    177         -  CP_INT IB1
2699  *    178         -  CP_INT IB2
2700  *    181         -  EOP Interrupt
2701  *    233         -  GUI Idle
2702  *
2703  * Note, these are based on r600 and may need to be
2704  * adjusted or added to on newer asics
2705  */
2706
2707 int r600_irq_process(struct radeon_device *rdev)
2708 {
2709         u32 wptr = r600_get_ih_wptr(rdev);
2710         u32 rptr = rdev->ih.rptr;
2711         u32 src_id, src_data;
2712         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2713         unsigned long flags;
2714         bool queue_hotplug = false;
2715
2716         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2717         if (!rdev->ih.enabled)
2718                 return IRQ_NONE;
2719
2720         spin_lock_irqsave(&rdev->ih.lock, flags);
2721
2722         if (rptr == wptr) {
2723                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2724                 return IRQ_NONE;
2725         }
2726         if (rdev->shutdown) {
2727                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2728                 return IRQ_NONE;
2729         }
2730
2731 restart_ih:
2732         /* display interrupts */
2733         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2734
2735         rdev->ih.wptr = wptr;
2736         while (rptr != wptr) {
2737                 /* wptr/rptr are in bytes! */
2738                 ring_index = rptr / 4;
2739                 src_id =  rdev->ih.ring[ring_index] & 0xff;
2740                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2741
2742                 switch (src_id) {
2743                 case 1: /* D1 vblank/vline */
2744                         switch (src_data) {
2745                         case 0: /* D1 vblank */
2746                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2747                                         drm_handle_vblank(rdev->ddev, 0);
2748                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2749                                         DRM_DEBUG("IH: D1 vblank\n");
2750                                 }
2751                                 break;
2752                         case 1: /* D1 vline */
2753                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2754                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
2755                                         DRM_DEBUG("IH: D1 vline\n");
2756                                 }
2757                                 break;
2758                         default:
2759                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2760                                 break;
2761                         }
2762                         break;
2763                 case 5: /* D2 vblank/vline */
2764                         switch (src_data) {
2765                         case 0: /* D2 vblank */
2766                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2767                                         drm_handle_vblank(rdev->ddev, 1);
2768                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2769                                         DRM_DEBUG("IH: D2 vblank\n");
2770                                 }
2771                                 break;
2772                         case 1: /* D1 vline */
2773                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2774                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
2775                                         DRM_DEBUG("IH: D2 vline\n");
2776                                 }
2777                                 break;
2778                         default:
2779                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2780                                 break;
2781                         }
2782                         break;
2783                 case 19: /* HPD/DAC hotplug */
2784                         switch (src_data) {
2785                         case 0:
2786                                 if (disp_int & DC_HPD1_INTERRUPT) {
2787                                         disp_int &= ~DC_HPD1_INTERRUPT;
2788                                         queue_hotplug = true;
2789                                         DRM_DEBUG("IH: HPD1\n");
2790                                 }
2791                                 break;
2792                         case 1:
2793                                 if (disp_int & DC_HPD2_INTERRUPT) {
2794                                         disp_int &= ~DC_HPD2_INTERRUPT;
2795                                         queue_hotplug = true;
2796                                         DRM_DEBUG("IH: HPD2\n");
2797                                 }
2798                                 break;
2799                         case 4:
2800                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2801                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
2802                                         queue_hotplug = true;
2803                                         DRM_DEBUG("IH: HPD3\n");
2804                                 }
2805                                 break;
2806                         case 5:
2807                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2808                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
2809                                         queue_hotplug = true;
2810                                         DRM_DEBUG("IH: HPD4\n");
2811                                 }
2812                                 break;
2813                         case 10:
2814                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
2815                                         disp_int_cont &= ~DC_HPD5_INTERRUPT;
2816                                         queue_hotplug = true;
2817                                         DRM_DEBUG("IH: HPD5\n");
2818                                 }
2819                                 break;
2820                         case 12:
2821                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
2822                                         disp_int_cont &= ~DC_HPD6_INTERRUPT;
2823                                         queue_hotplug = true;
2824                                         DRM_DEBUG("IH: HPD6\n");
2825                                 }
2826                                 break;
2827                         default:
2828                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2829                                 break;
2830                         }
2831                         break;
2832                 case 176: /* CP_INT in ring buffer */
2833                 case 177: /* CP_INT in IB1 */
2834                 case 178: /* CP_INT in IB2 */
2835                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2836                         radeon_fence_process(rdev);
2837                         break;
2838                 case 181: /* CP EOP event */
2839                         DRM_DEBUG("IH: CP EOP\n");
2840                         break;
2841                 default:
2842                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2843                         break;
2844                 }
2845
2846                 /* wptr/rptr are in bytes! */
2847                 rptr += 16;
2848                 rptr &= rdev->ih.ptr_mask;
2849         }
2850         /* make sure wptr hasn't changed while processing */
2851         wptr = r600_get_ih_wptr(rdev);
2852         if (wptr != rdev->ih.wptr)
2853                 goto restart_ih;
2854         if (queue_hotplug)
2855                 queue_work(rdev->wq, &rdev->hotplug_work);
2856         rdev->ih.rptr = rptr;
2857         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2858         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2859         return IRQ_HANDLED;
2860 }
2861
2862 /*
2863  * Debugfs info
2864  */
2865 #if defined(CONFIG_DEBUG_FS)
2866
2867 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
2868 {
2869         struct drm_info_node *node = (struct drm_info_node *) m->private;
2870         struct drm_device *dev = node->minor->dev;
2871         struct radeon_device *rdev = dev->dev_private;
2872         unsigned count, i, j;
2873
2874         radeon_ring_free_size(rdev);
2875         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
2876         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
2877         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2878         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2879         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2880         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
2881         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2882         seq_printf(m, "%u dwords in ring\n", count);
2883         i = rdev->cp.rptr;
2884         for (j = 0; j <= count; j++) {
2885                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2886                 i = (i + 1) & rdev->cp.ptr_mask;
2887         }
2888         return 0;
2889 }
2890
2891 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2892 {
2893         struct drm_info_node *node = (struct drm_info_node *) m->private;
2894         struct drm_device *dev = node->minor->dev;
2895         struct radeon_device *rdev = dev->dev_private;
2896
2897         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2898         DREG32_SYS(m, rdev, VM_L2_STATUS);
2899         return 0;
2900 }
2901
2902 static struct drm_info_list r600_mc_info_list[] = {
2903         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2904         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2905 };
2906 #endif
2907
2908 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2909 {
2910 #if defined(CONFIG_DEBUG_FS)
2911         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2912 #else
2913         return 0;
2914 #endif
2915 }
2916
2917 /**
2918  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2919  * rdev: radeon device structure
2920  * bo: buffer object struct which userspace is waiting for idle
2921  *
2922  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2923  * through ring buffer, this leads to corruption in rendering, see
2924  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2925  * directly perform HDP flush by writing register through MMIO.
2926  */
2927 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2928 {
2929         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2930 }