Merge branch 'master' into export-slabh
[kernel.git] / drivers / gpu / drm / radeon / rs400.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include <drm/drmP.h>
31 #include "radeon.h"
32 #include "radeon_asic.h"
33 #include "rs400d.h"
34
35 /* This files gather functions specifics to : rs400,rs480 */
36 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
37
38 void rs400_gart_adjust_size(struct radeon_device *rdev)
39 {
40         /* Check gart size */
41         switch (rdev->mc.gtt_size/(1024*1024)) {
42         case 32:
43         case 64:
44         case 128:
45         case 256:
46         case 512:
47         case 1024:
48         case 2048:
49                 break;
50         default:
51                 DRM_ERROR("Unable to use IGP GART size %uM\n",
52                           (unsigned)(rdev->mc.gtt_size >> 20));
53                 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
54                 DRM_ERROR("Forcing to 32M GART size\n");
55                 rdev->mc.gtt_size = 32 * 1024 * 1024;
56                 return;
57         }
58         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
59                 /* FIXME: RS400 & RS480 seems to have issue with GART size
60                  * if 4G of system memory (needs more testing) */
61                 rdev->mc.gtt_size = 32 * 1024 * 1024;
62                 DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
63         }
64 }
65
66 void rs400_gart_tlb_flush(struct radeon_device *rdev)
67 {
68         uint32_t tmp;
69         unsigned int timeout = rdev->usec_timeout;
70
71         WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
72         do {
73                 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
74                 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
75                         break;
76                 DRM_UDELAY(1);
77                 timeout--;
78         } while (timeout > 0);
79         WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
80 }
81
82 int rs400_gart_init(struct radeon_device *rdev)
83 {
84         int r;
85
86         if (rdev->gart.table.ram.ptr) {
87                 WARN(1, "RS400 GART already initialized.\n");
88                 return 0;
89         }
90         /* Check gart size */
91         switch(rdev->mc.gtt_size / (1024 * 1024)) {
92         case 32:
93         case 64:
94         case 128:
95         case 256:
96         case 512:
97         case 1024:
98         case 2048:
99                 break;
100         default:
101                 return -EINVAL;
102         }
103         /* Initialize common gart structure */
104         r = radeon_gart_init(rdev);
105         if (r)
106                 return r;
107         if (rs400_debugfs_pcie_gart_info_init(rdev))
108                 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
109         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
110         return radeon_gart_table_ram_alloc(rdev);
111 }
112
113 int rs400_gart_enable(struct radeon_device *rdev)
114 {
115         uint32_t size_reg;
116         uint32_t tmp;
117
118         radeon_gart_restore(rdev);
119         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
120         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
121         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
122         /* Check gart size */
123         switch(rdev->mc.gtt_size / (1024 * 1024)) {
124         case 32:
125                 size_reg = RS480_VA_SIZE_32MB;
126                 break;
127         case 64:
128                 size_reg = RS480_VA_SIZE_64MB;
129                 break;
130         case 128:
131                 size_reg = RS480_VA_SIZE_128MB;
132                 break;
133         case 256:
134                 size_reg = RS480_VA_SIZE_256MB;
135                 break;
136         case 512:
137                 size_reg = RS480_VA_SIZE_512MB;
138                 break;
139         case 1024:
140                 size_reg = RS480_VA_SIZE_1GB;
141                 break;
142         case 2048:
143                 size_reg = RS480_VA_SIZE_2GB;
144                 break;
145         default:
146                 return -EINVAL;
147         }
148         /* It should be fine to program it to max value */
149         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
150                 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
151                 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
152         } else {
153                 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
154                 WREG32(RS480_AGP_BASE_2, 0);
155         }
156         tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
157         tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
158         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
159                 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
160                 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
161                 WREG32(RADEON_BUS_CNTL, tmp);
162         } else {
163                 WREG32(RADEON_MC_AGP_LOCATION, tmp);
164                 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
165                 WREG32(RADEON_BUS_CNTL, tmp);
166         }
167         /* Table should be in 32bits address space so ignore bits above. */
168         tmp = (u32)rdev->gart.table_addr & 0xfffff000;
169         tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
170
171         WREG32_MC(RS480_GART_BASE, tmp);
172         /* TODO: more tweaking here */
173         WREG32_MC(RS480_GART_FEATURE_ID,
174                   (RS480_TLB_ENABLE |
175                    RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
176         /* Disable snooping */
177         WREG32_MC(RS480_AGP_MODE_CNTL,
178                   (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
179         /* Disable AGP mode */
180         /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
181          * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
182         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
183                 WREG32_MC(RS480_MC_MISC_CNTL,
184                           (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
185         } else {
186                 WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
187         }
188         /* Enable gart */
189         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
190         rs400_gart_tlb_flush(rdev);
191         rdev->gart.ready = true;
192         return 0;
193 }
194
195 void rs400_gart_disable(struct radeon_device *rdev)
196 {
197         uint32_t tmp;
198
199         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
200         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
201         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
202         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
203 }
204
205 void rs400_gart_fini(struct radeon_device *rdev)
206 {
207         radeon_gart_fini(rdev);
208         rs400_gart_disable(rdev);
209         radeon_gart_table_ram_free(rdev);
210 }
211
212 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
213 {
214         uint32_t entry;
215
216         if (i < 0 || i > rdev->gart.num_gpu_pages) {
217                 return -EINVAL;
218         }
219
220         entry = (lower_32_bits(addr) & PAGE_MASK) |
221                 ((upper_32_bits(addr) & 0xff) << 4) |
222                 0xc;
223         entry = cpu_to_le32(entry);
224         rdev->gart.table.ram.ptr[i] = entry;
225         return 0;
226 }
227
228 int rs400_mc_wait_for_idle(struct radeon_device *rdev)
229 {
230         unsigned i;
231         uint32_t tmp;
232
233         for (i = 0; i < rdev->usec_timeout; i++) {
234                 /* read MC_STATUS */
235                 tmp = RREG32(0x0150);
236                 if (tmp & (1 << 2)) {
237                         return 0;
238                 }
239                 DRM_UDELAY(1);
240         }
241         return -1;
242 }
243
244 void rs400_gpu_init(struct radeon_device *rdev)
245 {
246         /* FIXME: HDP same place on rs400 ? */
247         r100_hdp_reset(rdev);
248         /* FIXME: is this correct ? */
249         r420_pipes_init(rdev);
250         if (rs400_mc_wait_for_idle(rdev)) {
251                 printk(KERN_WARNING "rs400: Failed to wait MC idle while "
252                        "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
253         }
254 }
255
256 void rs400_mc_init(struct radeon_device *rdev)
257 {
258         u64 base;
259
260         rs400_gart_adjust_size(rdev);
261         rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
262         /* DDR for all card after R300 & IGP */
263         rdev->mc.vram_is_ddr = true;
264         rdev->mc.vram_width = 128;
265         r100_vram_init_sizes(rdev);
266         base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
267         radeon_vram_location(rdev, &rdev->mc, base);
268         radeon_gtt_location(rdev, &rdev->mc);
269         radeon_update_bandwidth_info(rdev);
270 }
271
272 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
273 {
274         uint32_t r;
275
276         WREG32(RS480_NB_MC_INDEX, reg & 0xff);
277         r = RREG32(RS480_NB_MC_DATA);
278         WREG32(RS480_NB_MC_INDEX, 0xff);
279         return r;
280 }
281
282 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
283 {
284         WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
285         WREG32(RS480_NB_MC_DATA, (v));
286         WREG32(RS480_NB_MC_INDEX, 0xff);
287 }
288
289 #if defined(CONFIG_DEBUG_FS)
290 static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
291 {
292         struct drm_info_node *node = (struct drm_info_node *) m->private;
293         struct drm_device *dev = node->minor->dev;
294         struct radeon_device *rdev = dev->dev_private;
295         uint32_t tmp;
296
297         tmp = RREG32(RADEON_HOST_PATH_CNTL);
298         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
299         tmp = RREG32(RADEON_BUS_CNTL);
300         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
301         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
302         seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
303         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
304                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
305                 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
306                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
307                 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
308                 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
309                 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
310                 tmp = RREG32_MC(0x100);
311                 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
312                 tmp = RREG32(0x134);
313                 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
314         } else {
315                 tmp = RREG32(RADEON_AGP_BASE);
316                 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
317                 tmp = RREG32(RS480_AGP_BASE_2);
318                 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
319                 tmp = RREG32(RADEON_MC_AGP_LOCATION);
320                 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
321         }
322         tmp = RREG32_MC(RS480_GART_BASE);
323         seq_printf(m, "GART_BASE 0x%08x\n", tmp);
324         tmp = RREG32_MC(RS480_GART_FEATURE_ID);
325         seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
326         tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
327         seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
328         tmp = RREG32_MC(RS480_MC_MISC_CNTL);
329         seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
330         tmp = RREG32_MC(0x5F);
331         seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
332         tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
333         seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
334         tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
335         seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
336         tmp = RREG32_MC(0x3B);
337         seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
338         tmp = RREG32_MC(0x3C);
339         seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
340         tmp = RREG32_MC(0x30);
341         seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
342         tmp = RREG32_MC(0x31);
343         seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
344         tmp = RREG32_MC(0x32);
345         seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
346         tmp = RREG32_MC(0x33);
347         seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
348         tmp = RREG32_MC(0x34);
349         seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
350         tmp = RREG32_MC(0x35);
351         seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
352         tmp = RREG32_MC(0x36);
353         seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
354         tmp = RREG32_MC(0x37);
355         seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
356         return 0;
357 }
358
359 static struct drm_info_list rs400_gart_info_list[] = {
360         {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
361 };
362 #endif
363
364 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
365 {
366 #if defined(CONFIG_DEBUG_FS)
367         return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
368 #else
369         return 0;
370 #endif
371 }
372
373 void rs400_mc_program(struct radeon_device *rdev)
374 {
375         struct r100_mc_save save;
376
377         /* Stops all mc clients */
378         r100_mc_stop(rdev, &save);
379
380         /* Wait for mc idle */
381         if (rs400_mc_wait_for_idle(rdev))
382                 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
383         WREG32(R_000148_MC_FB_LOCATION,
384                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
385                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
386
387         r100_mc_resume(rdev, &save);
388 }
389
390 static int rs400_startup(struct radeon_device *rdev)
391 {
392         int r;
393
394         r100_set_common_regs(rdev);
395
396         rs400_mc_program(rdev);
397         /* Resume clock */
398         r300_clock_startup(rdev);
399         /* Initialize GPU configuration (# pipes, ...) */
400         rs400_gpu_init(rdev);
401         r100_enable_bm(rdev);
402         /* Initialize GART (initialize after TTM so we can allocate
403          * memory through TTM but finalize after TTM) */
404         r = rs400_gart_enable(rdev);
405         if (r)
406                 return r;
407         /* Enable IRQ */
408         r100_irq_set(rdev);
409         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
410         /* 1M ring buffer */
411         r = r100_cp_init(rdev, 1024 * 1024);
412         if (r) {
413                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
414                 return r;
415         }
416         r = r100_wb_init(rdev);
417         if (r)
418                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
419         r = r100_ib_init(rdev);
420         if (r) {
421                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
422                 return r;
423         }
424         return 0;
425 }
426
427 int rs400_resume(struct radeon_device *rdev)
428 {
429         /* Make sur GART are not working */
430         rs400_gart_disable(rdev);
431         /* Resume clock before doing reset */
432         r300_clock_startup(rdev);
433         /* setup MC before calling post tables */
434         rs400_mc_program(rdev);
435         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
436         if (radeon_gpu_reset(rdev)) {
437                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
438                         RREG32(R_000E40_RBBM_STATUS),
439                         RREG32(R_0007C0_CP_STAT));
440         }
441         /* post */
442         radeon_combios_asic_init(rdev->ddev);
443         /* Resume clock after posting */
444         r300_clock_startup(rdev);
445         /* Initialize surface registers */
446         radeon_surface_init(rdev);
447         return rs400_startup(rdev);
448 }
449
450 int rs400_suspend(struct radeon_device *rdev)
451 {
452         r100_cp_disable(rdev);
453         r100_wb_disable(rdev);
454         r100_irq_disable(rdev);
455         rs400_gart_disable(rdev);
456         return 0;
457 }
458
459 void rs400_fini(struct radeon_device *rdev)
460 {
461         radeon_pm_fini(rdev);
462         r100_cp_fini(rdev);
463         r100_wb_fini(rdev);
464         r100_ib_fini(rdev);
465         radeon_gem_fini(rdev);
466         rs400_gart_fini(rdev);
467         radeon_irq_kms_fini(rdev);
468         radeon_fence_driver_fini(rdev);
469         radeon_bo_fini(rdev);
470         radeon_atombios_fini(rdev);
471         kfree(rdev->bios);
472         rdev->bios = NULL;
473 }
474
475 int rs400_init(struct radeon_device *rdev)
476 {
477         int r;
478
479         /* Disable VGA */
480         r100_vga_render_disable(rdev);
481         /* Initialize scratch registers */
482         radeon_scratch_init(rdev);
483         /* Initialize surface registers */
484         radeon_surface_init(rdev);
485         /* TODO: disable VGA need to use VGA request */
486         /* BIOS*/
487         if (!radeon_get_bios(rdev)) {
488                 if (ASIC_IS_AVIVO(rdev))
489                         return -EINVAL;
490         }
491         if (rdev->is_atom_bios) {
492                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
493                 return -EINVAL;
494         } else {
495                 r = radeon_combios_init(rdev);
496                 if (r)
497                         return r;
498         }
499         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
500         if (radeon_gpu_reset(rdev)) {
501                 dev_warn(rdev->dev,
502                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
503                         RREG32(R_000E40_RBBM_STATUS),
504                         RREG32(R_0007C0_CP_STAT));
505         }
506         /* check if cards are posted or not */
507         if (radeon_boot_test_post_card(rdev) == false)
508                 return -EINVAL;
509
510         /* Initialize clocks */
511         radeon_get_clock_info(rdev->ddev);
512         /* Initialize power management */
513         radeon_pm_init(rdev);
514         /* initialize memory controller */
515         rs400_mc_init(rdev);
516         /* Fence driver */
517         r = radeon_fence_driver_init(rdev);
518         if (r)
519                 return r;
520         r = radeon_irq_kms_init(rdev);
521         if (r)
522                 return r;
523         /* Memory manager */
524         r = radeon_bo_init(rdev);
525         if (r)
526                 return r;
527         r = rs400_gart_init(rdev);
528         if (r)
529                 return r;
530         r300_set_reg_safe(rdev);
531         rdev->accel_working = true;
532         r = rs400_startup(rdev);
533         if (r) {
534                 /* Somethings want wront with the accel init stop accel */
535                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
536                 r100_cp_fini(rdev);
537                 r100_wb_fini(rdev);
538                 r100_ib_fini(rdev);
539                 rs400_gart_fini(rdev);
540                 radeon_irq_kms_fini(rdev);
541                 rdev->accel_working = false;
542         }
543         return 0;
544 }