Merge branch 'master' into export-slabh
[kernel.git] / drivers / gpu / drm / radeon / rv515.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "rv515d.h"
32 #include "radeon.h"
33 #include "radeon_asic.h"
34 #include "atom.h"
35 #include "rv515_reg_safe.h"
36
37 /* This files gather functions specifics to: rv515 */
38 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
39 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
40 void rv515_gpu_init(struct radeon_device *rdev);
41 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
42
43 void rv515_debugfs(struct radeon_device *rdev)
44 {
45         if (r100_debugfs_rbbm_init(rdev)) {
46                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
47         }
48         if (rv515_debugfs_pipes_info_init(rdev)) {
49                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
50         }
51         if (rv515_debugfs_ga_info_init(rdev)) {
52                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
53         }
54 }
55
56 void rv515_ring_start(struct radeon_device *rdev)
57 {
58         int r;
59
60         r = radeon_ring_lock(rdev, 64);
61         if (r) {
62                 return;
63         }
64         radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
65         radeon_ring_write(rdev,
66                           ISYNC_ANY2D_IDLE3D |
67                           ISYNC_ANY3D_IDLE2D |
68                           ISYNC_WAIT_IDLEGUI |
69                           ISYNC_CPSCRATCH_IDLEGUI);
70         radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
71         radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
72         radeon_ring_write(rdev, PACKET0(0x170C, 0));
73         radeon_ring_write(rdev, 1 << 31);
74         radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
75         radeon_ring_write(rdev, 0);
76         radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
77         radeon_ring_write(rdev, 0);
78         radeon_ring_write(rdev, PACKET0(0x42C8, 0));
79         radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
80         radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
81         radeon_ring_write(rdev, 0);
82         radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
83         radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
84         radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
85         radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
86         radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
87         radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
88         radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
89         radeon_ring_write(rdev, 0);
90         radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
91         radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
92         radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
93         radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
94         radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
95         radeon_ring_write(rdev,
96                           ((6 << MS_X0_SHIFT) |
97                            (6 << MS_Y0_SHIFT) |
98                            (6 << MS_X1_SHIFT) |
99                            (6 << MS_Y1_SHIFT) |
100                            (6 << MS_X2_SHIFT) |
101                            (6 << MS_Y2_SHIFT) |
102                            (6 << MSBD0_Y_SHIFT) |
103                            (6 << MSBD0_X_SHIFT)));
104         radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
105         radeon_ring_write(rdev,
106                           ((6 << MS_X3_SHIFT) |
107                            (6 << MS_Y3_SHIFT) |
108                            (6 << MS_X4_SHIFT) |
109                            (6 << MS_Y4_SHIFT) |
110                            (6 << MS_X5_SHIFT) |
111                            (6 << MS_Y5_SHIFT) |
112                            (6 << MSBD1_SHIFT)));
113         radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
114         radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
115         radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
116         radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
117         radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
118         radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
119         radeon_ring_write(rdev, PACKET0(0x20C8, 0));
120         radeon_ring_write(rdev, 0);
121         radeon_ring_unlock_commit(rdev);
122 }
123
124 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
125 {
126         unsigned i;
127         uint32_t tmp;
128
129         for (i = 0; i < rdev->usec_timeout; i++) {
130                 /* read MC_STATUS */
131                 tmp = RREG32_MC(MC_STATUS);
132                 if (tmp & MC_STATUS_IDLE) {
133                         return 0;
134                 }
135                 DRM_UDELAY(1);
136         }
137         return -1;
138 }
139
140 void rv515_vga_render_disable(struct radeon_device *rdev)
141 {
142         WREG32(R_000300_VGA_RENDER_CONTROL,
143                 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
144 }
145
146 void rv515_gpu_init(struct radeon_device *rdev)
147 {
148         unsigned pipe_select_current, gb_pipe_select, tmp;
149
150         r100_hdp_reset(rdev);
151         r100_rb2d_reset(rdev);
152
153         if (r100_gui_wait_for_idle(rdev)) {
154                 printk(KERN_WARNING "Failed to wait GUI idle while "
155                        "reseting GPU. Bad things might happen.\n");
156         }
157
158         rv515_vga_render_disable(rdev);
159
160         r420_pipes_init(rdev);
161         gb_pipe_select = RREG32(0x402C);
162         tmp = RREG32(0x170C);
163         pipe_select_current = (tmp >> 2) & 3;
164         tmp = (1 << pipe_select_current) |
165               (((gb_pipe_select >> 8) & 0xF) << 4);
166         WREG32_PLL(0x000D, tmp);
167         if (r100_gui_wait_for_idle(rdev)) {
168                 printk(KERN_WARNING "Failed to wait GUI idle while "
169                        "reseting GPU. Bad things might happen.\n");
170         }
171         if (rv515_mc_wait_for_idle(rdev)) {
172                 printk(KERN_WARNING "Failed to wait MC idle while "
173                        "programming pipes. Bad things might happen.\n");
174         }
175 }
176
177 int rv515_ga_reset(struct radeon_device *rdev)
178 {
179         uint32_t tmp;
180         bool reinit_cp;
181         int i;
182
183         reinit_cp = rdev->cp.ready;
184         rdev->cp.ready = false;
185         for (i = 0; i < rdev->usec_timeout; i++) {
186                 WREG32(CP_CSQ_MODE, 0);
187                 WREG32(CP_CSQ_CNTL, 0);
188                 WREG32(RBBM_SOFT_RESET, 0x32005);
189                 (void)RREG32(RBBM_SOFT_RESET);
190                 udelay(200);
191                 WREG32(RBBM_SOFT_RESET, 0);
192                 /* Wait to prevent race in RBBM_STATUS */
193                 mdelay(1);
194                 tmp = RREG32(RBBM_STATUS);
195                 if (tmp & ((1 << 20) | (1 << 26))) {
196                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
197                         /* GA still busy soft reset it */
198                         WREG32(0x429C, 0x200);
199                         WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
200                         WREG32(0x43E0, 0);
201                         WREG32(0x43E4, 0);
202                         WREG32(0x24AC, 0);
203                 }
204                 /* Wait to prevent race in RBBM_STATUS */
205                 mdelay(1);
206                 tmp = RREG32(RBBM_STATUS);
207                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
208                         break;
209                 }
210         }
211         for (i = 0; i < rdev->usec_timeout; i++) {
212                 tmp = RREG32(RBBM_STATUS);
213                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
214                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
215                                  tmp);
216                         DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
217                         DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
218                         DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
219                         if (reinit_cp) {
220                                 return r100_cp_init(rdev, rdev->cp.ring_size);
221                         }
222                         return 0;
223                 }
224                 DRM_UDELAY(1);
225         }
226         tmp = RREG32(RBBM_STATUS);
227         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
228         return -1;
229 }
230
231 int rv515_gpu_reset(struct radeon_device *rdev)
232 {
233         uint32_t status;
234
235         /* reset order likely matter */
236         status = RREG32(RBBM_STATUS);
237         /* reset HDP */
238         r100_hdp_reset(rdev);
239         /* reset rb2d */
240         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
241                 r100_rb2d_reset(rdev);
242         }
243         /* reset GA */
244         if (status & ((1 << 20) | (1 << 26))) {
245                 rv515_ga_reset(rdev);
246         }
247         /* reset CP */
248         status = RREG32(RBBM_STATUS);
249         if (status & (1 << 16)) {
250                 r100_cp_reset(rdev);
251         }
252         /* Check if GPU is idle */
253         status = RREG32(RBBM_STATUS);
254         if (status & (1 << 31)) {
255                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
256                 return -1;
257         }
258         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
259         return 0;
260 }
261
262 static void rv515_vram_get_type(struct radeon_device *rdev)
263 {
264         uint32_t tmp;
265
266         rdev->mc.vram_width = 128;
267         rdev->mc.vram_is_ddr = true;
268         tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
269         switch (tmp) {
270         case 0:
271                 rdev->mc.vram_width = 64;
272                 break;
273         case 1:
274                 rdev->mc.vram_width = 128;
275                 break;
276         default:
277                 rdev->mc.vram_width = 128;
278                 break;
279         }
280 }
281
282 void rv515_mc_init(struct radeon_device *rdev)
283 {
284
285         rv515_vram_get_type(rdev);
286         r100_vram_init_sizes(rdev);
287         radeon_vram_location(rdev, &rdev->mc, 0);
288         if (!(rdev->flags & RADEON_IS_AGP))
289                 radeon_gtt_location(rdev, &rdev->mc);
290         radeon_update_bandwidth_info(rdev);
291 }
292
293 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
294 {
295         uint32_t r;
296
297         WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
298         r = RREG32(MC_IND_DATA);
299         WREG32(MC_IND_INDEX, 0);
300         return r;
301 }
302
303 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
304 {
305         WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
306         WREG32(MC_IND_DATA, (v));
307         WREG32(MC_IND_INDEX, 0);
308 }
309
310 #if defined(CONFIG_DEBUG_FS)
311 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
312 {
313         struct drm_info_node *node = (struct drm_info_node *) m->private;
314         struct drm_device *dev = node->minor->dev;
315         struct radeon_device *rdev = dev->dev_private;
316         uint32_t tmp;
317
318         tmp = RREG32(GB_PIPE_SELECT);
319         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
320         tmp = RREG32(SU_REG_DEST);
321         seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
322         tmp = RREG32(GB_TILE_CONFIG);
323         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
324         tmp = RREG32(DST_PIPE_CONFIG);
325         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
326         return 0;
327 }
328
329 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
330 {
331         struct drm_info_node *node = (struct drm_info_node *) m->private;
332         struct drm_device *dev = node->minor->dev;
333         struct radeon_device *rdev = dev->dev_private;
334         uint32_t tmp;
335
336         tmp = RREG32(0x2140);
337         seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
338         radeon_gpu_reset(rdev);
339         tmp = RREG32(0x425C);
340         seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
341         return 0;
342 }
343
344 static struct drm_info_list rv515_pipes_info_list[] = {
345         {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
346 };
347
348 static struct drm_info_list rv515_ga_info_list[] = {
349         {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
350 };
351 #endif
352
353 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
354 {
355 #if defined(CONFIG_DEBUG_FS)
356         return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
357 #else
358         return 0;
359 #endif
360 }
361
362 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
363 {
364 #if defined(CONFIG_DEBUG_FS)
365         return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
366 #else
367         return 0;
368 #endif
369 }
370
371 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
372 {
373         save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
374         save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
375         save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
376         save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
377         save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
378         save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
379
380         /* Stop all video */
381         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
382         WREG32(R_000300_VGA_RENDER_CONTROL, 0);
383         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
384         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
385         WREG32(R_006080_D1CRTC_CONTROL, 0);
386         WREG32(R_006880_D2CRTC_CONTROL, 0);
387         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
388         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
389         WREG32(R_000330_D1VGA_CONTROL, 0);
390         WREG32(R_000338_D2VGA_CONTROL, 0);
391 }
392
393 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
394 {
395         WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
396         WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
397         WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
398         WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
399         WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
400         /* Unlock host access */
401         WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
402         mdelay(1);
403         /* Restore video state */
404         WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
405         WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
406         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
407         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
408         WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
409         WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
410         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
411         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
412         WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
413 }
414
415 void rv515_mc_program(struct radeon_device *rdev)
416 {
417         struct rv515_mc_save save;
418
419         /* Stops all mc clients */
420         rv515_mc_stop(rdev, &save);
421
422         /* Wait for mc idle */
423         if (rv515_mc_wait_for_idle(rdev))
424                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
425         /* Write VRAM size in case we are limiting it */
426         WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
427         /* Program MC, should be a 32bits limited address space */
428         WREG32_MC(R_000001_MC_FB_LOCATION,
429                         S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
430                         S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
431         WREG32(R_000134_HDP_FB_LOCATION,
432                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
433         if (rdev->flags & RADEON_IS_AGP) {
434                 WREG32_MC(R_000002_MC_AGP_LOCATION,
435                         S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
436                         S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
437                 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
438                 WREG32_MC(R_000004_MC_AGP_BASE_2,
439                         S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
440         } else {
441                 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
442                 WREG32_MC(R_000003_MC_AGP_BASE, 0);
443                 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
444         }
445
446         rv515_mc_resume(rdev, &save);
447 }
448
449 void rv515_clock_startup(struct radeon_device *rdev)
450 {
451         if (radeon_dynclks != -1 && radeon_dynclks)
452                 radeon_atom_set_clock_gating(rdev, 1);
453         /* We need to force on some of the block */
454         WREG32_PLL(R_00000F_CP_DYN_CNTL,
455                 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
456         WREG32_PLL(R_000011_E2_DYN_CNTL,
457                 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
458         WREG32_PLL(R_000013_IDCT_DYN_CNTL,
459                 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
460 }
461
462 static int rv515_startup(struct radeon_device *rdev)
463 {
464         int r;
465
466         rv515_mc_program(rdev);
467         /* Resume clock */
468         rv515_clock_startup(rdev);
469         /* Initialize GPU configuration (# pipes, ...) */
470         rv515_gpu_init(rdev);
471         /* Initialize GART (initialize after TTM so we can allocate
472          * memory through TTM but finalize after TTM) */
473         if (rdev->flags & RADEON_IS_PCIE) {
474                 r = rv370_pcie_gart_enable(rdev);
475                 if (r)
476                         return r;
477         }
478         /* Enable IRQ */
479         rs600_irq_set(rdev);
480         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
481         /* 1M ring buffer */
482         r = r100_cp_init(rdev, 1024 * 1024);
483         if (r) {
484                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
485                 return r;
486         }
487         r = r100_wb_init(rdev);
488         if (r)
489                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
490         r = r100_ib_init(rdev);
491         if (r) {
492                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
493                 return r;
494         }
495         return 0;
496 }
497
498 int rv515_resume(struct radeon_device *rdev)
499 {
500         /* Make sur GART are not working */
501         if (rdev->flags & RADEON_IS_PCIE)
502                 rv370_pcie_gart_disable(rdev);
503         /* Resume clock before doing reset */
504         rv515_clock_startup(rdev);
505         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
506         if (radeon_gpu_reset(rdev)) {
507                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
508                         RREG32(R_000E40_RBBM_STATUS),
509                         RREG32(R_0007C0_CP_STAT));
510         }
511         /* post */
512         atom_asic_init(rdev->mode_info.atom_context);
513         /* Resume clock after posting */
514         rv515_clock_startup(rdev);
515         /* Initialize surface registers */
516         radeon_surface_init(rdev);
517         return rv515_startup(rdev);
518 }
519
520 int rv515_suspend(struct radeon_device *rdev)
521 {
522         r100_cp_disable(rdev);
523         r100_wb_disable(rdev);
524         rs600_irq_disable(rdev);
525         if (rdev->flags & RADEON_IS_PCIE)
526                 rv370_pcie_gart_disable(rdev);
527         return 0;
528 }
529
530 void rv515_set_safe_registers(struct radeon_device *rdev)
531 {
532         rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
533         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
534 }
535
536 void rv515_fini(struct radeon_device *rdev)
537 {
538         radeon_pm_fini(rdev);
539         r100_cp_fini(rdev);
540         r100_wb_fini(rdev);
541         r100_ib_fini(rdev);
542         radeon_gem_fini(rdev);
543         rv370_pcie_gart_fini(rdev);
544         radeon_agp_fini(rdev);
545         radeon_irq_kms_fini(rdev);
546         radeon_fence_driver_fini(rdev);
547         radeon_bo_fini(rdev);
548         radeon_atombios_fini(rdev);
549         kfree(rdev->bios);
550         rdev->bios = NULL;
551 }
552
553 int rv515_init(struct radeon_device *rdev)
554 {
555         int r;
556
557         /* Initialize scratch registers */
558         radeon_scratch_init(rdev);
559         /* Initialize surface registers */
560         radeon_surface_init(rdev);
561         /* TODO: disable VGA need to use VGA request */
562         /* BIOS*/
563         if (!radeon_get_bios(rdev)) {
564                 if (ASIC_IS_AVIVO(rdev))
565                         return -EINVAL;
566         }
567         if (rdev->is_atom_bios) {
568                 r = radeon_atombios_init(rdev);
569                 if (r)
570                         return r;
571         } else {
572                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
573                 return -EINVAL;
574         }
575         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
576         if (radeon_gpu_reset(rdev)) {
577                 dev_warn(rdev->dev,
578                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
579                         RREG32(R_000E40_RBBM_STATUS),
580                         RREG32(R_0007C0_CP_STAT));
581         }
582         /* check if cards are posted or not */
583         if (radeon_boot_test_post_card(rdev) == false)
584                 return -EINVAL;
585         /* Initialize clocks */
586         radeon_get_clock_info(rdev->ddev);
587         /* Initialize power management */
588         radeon_pm_init(rdev);
589         /* initialize AGP */
590         if (rdev->flags & RADEON_IS_AGP) {
591                 r = radeon_agp_init(rdev);
592                 if (r) {
593                         radeon_agp_disable(rdev);
594                 }
595         }
596         /* initialize memory controller */
597         rv515_mc_init(rdev);
598         rv515_debugfs(rdev);
599         /* Fence driver */
600         r = radeon_fence_driver_init(rdev);
601         if (r)
602                 return r;
603         r = radeon_irq_kms_init(rdev);
604         if (r)
605                 return r;
606         /* Memory manager */
607         r = radeon_bo_init(rdev);
608         if (r)
609                 return r;
610         r = rv370_pcie_gart_init(rdev);
611         if (r)
612                 return r;
613         rv515_set_safe_registers(rdev);
614         rdev->accel_working = true;
615         r = rv515_startup(rdev);
616         if (r) {
617                 /* Somethings want wront with the accel init stop accel */
618                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
619                 r100_cp_fini(rdev);
620                 r100_wb_fini(rdev);
621                 r100_ib_fini(rdev);
622                 radeon_irq_kms_fini(rdev);
623                 rv370_pcie_gart_fini(rdev);
624                 radeon_agp_fini(rdev);
625                 rdev->accel_working = false;
626         }
627         return 0;
628 }
629
630 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
631 {
632         int index_reg = 0x6578 + crtc->crtc_offset;
633         int data_reg = 0x657c + crtc->crtc_offset;
634
635         WREG32(0x659C + crtc->crtc_offset, 0x0);
636         WREG32(0x6594 + crtc->crtc_offset, 0x705);
637         WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
638         WREG32(0x65D8 + crtc->crtc_offset, 0x0);
639         WREG32(0x65B0 + crtc->crtc_offset, 0x0);
640         WREG32(0x65C0 + crtc->crtc_offset, 0x0);
641         WREG32(0x65D4 + crtc->crtc_offset, 0x0);
642         WREG32(index_reg, 0x0);
643         WREG32(data_reg, 0x841880A8);
644         WREG32(index_reg, 0x1);
645         WREG32(data_reg, 0x84208680);
646         WREG32(index_reg, 0x2);
647         WREG32(data_reg, 0xBFF880B0);
648         WREG32(index_reg, 0x100);
649         WREG32(data_reg, 0x83D88088);
650         WREG32(index_reg, 0x101);
651         WREG32(data_reg, 0x84608680);
652         WREG32(index_reg, 0x102);
653         WREG32(data_reg, 0xBFF080D0);
654         WREG32(index_reg, 0x200);
655         WREG32(data_reg, 0x83988068);
656         WREG32(index_reg, 0x201);
657         WREG32(data_reg, 0x84A08680);
658         WREG32(index_reg, 0x202);
659         WREG32(data_reg, 0xBFF080F8);
660         WREG32(index_reg, 0x300);
661         WREG32(data_reg, 0x83588058);
662         WREG32(index_reg, 0x301);
663         WREG32(data_reg, 0x84E08660);
664         WREG32(index_reg, 0x302);
665         WREG32(data_reg, 0xBFF88120);
666         WREG32(index_reg, 0x400);
667         WREG32(data_reg, 0x83188040);
668         WREG32(index_reg, 0x401);
669         WREG32(data_reg, 0x85008660);
670         WREG32(index_reg, 0x402);
671         WREG32(data_reg, 0xBFF88150);
672         WREG32(index_reg, 0x500);
673         WREG32(data_reg, 0x82D88030);
674         WREG32(index_reg, 0x501);
675         WREG32(data_reg, 0x85408640);
676         WREG32(index_reg, 0x502);
677         WREG32(data_reg, 0xBFF88180);
678         WREG32(index_reg, 0x600);
679         WREG32(data_reg, 0x82A08018);
680         WREG32(index_reg, 0x601);
681         WREG32(data_reg, 0x85808620);
682         WREG32(index_reg, 0x602);
683         WREG32(data_reg, 0xBFF081B8);
684         WREG32(index_reg, 0x700);
685         WREG32(data_reg, 0x82608010);
686         WREG32(index_reg, 0x701);
687         WREG32(data_reg, 0x85A08600);
688         WREG32(index_reg, 0x702);
689         WREG32(data_reg, 0x800081F0);
690         WREG32(index_reg, 0x800);
691         WREG32(data_reg, 0x8228BFF8);
692         WREG32(index_reg, 0x801);
693         WREG32(data_reg, 0x85E085E0);
694         WREG32(index_reg, 0x802);
695         WREG32(data_reg, 0xBFF88228);
696         WREG32(index_reg, 0x10000);
697         WREG32(data_reg, 0x82A8BF00);
698         WREG32(index_reg, 0x10001);
699         WREG32(data_reg, 0x82A08CC0);
700         WREG32(index_reg, 0x10002);
701         WREG32(data_reg, 0x8008BEF8);
702         WREG32(index_reg, 0x10100);
703         WREG32(data_reg, 0x81F0BF28);
704         WREG32(index_reg, 0x10101);
705         WREG32(data_reg, 0x83608CA0);
706         WREG32(index_reg, 0x10102);
707         WREG32(data_reg, 0x8018BED0);
708         WREG32(index_reg, 0x10200);
709         WREG32(data_reg, 0x8148BF38);
710         WREG32(index_reg, 0x10201);
711         WREG32(data_reg, 0x84408C80);
712         WREG32(index_reg, 0x10202);
713         WREG32(data_reg, 0x8008BEB8);
714         WREG32(index_reg, 0x10300);
715         WREG32(data_reg, 0x80B0BF78);
716         WREG32(index_reg, 0x10301);
717         WREG32(data_reg, 0x85008C20);
718         WREG32(index_reg, 0x10302);
719         WREG32(data_reg, 0x8020BEA0);
720         WREG32(index_reg, 0x10400);
721         WREG32(data_reg, 0x8028BF90);
722         WREG32(index_reg, 0x10401);
723         WREG32(data_reg, 0x85E08BC0);
724         WREG32(index_reg, 0x10402);
725         WREG32(data_reg, 0x8018BE90);
726         WREG32(index_reg, 0x10500);
727         WREG32(data_reg, 0xBFB8BFB0);
728         WREG32(index_reg, 0x10501);
729         WREG32(data_reg, 0x86C08B40);
730         WREG32(index_reg, 0x10502);
731         WREG32(data_reg, 0x8010BE90);
732         WREG32(index_reg, 0x10600);
733         WREG32(data_reg, 0xBF58BFC8);
734         WREG32(index_reg, 0x10601);
735         WREG32(data_reg, 0x87A08AA0);
736         WREG32(index_reg, 0x10602);
737         WREG32(data_reg, 0x8010BE98);
738         WREG32(index_reg, 0x10700);
739         WREG32(data_reg, 0xBF10BFF0);
740         WREG32(index_reg, 0x10701);
741         WREG32(data_reg, 0x886089E0);
742         WREG32(index_reg, 0x10702);
743         WREG32(data_reg, 0x8018BEB0);
744         WREG32(index_reg, 0x10800);
745         WREG32(data_reg, 0xBED8BFE8);
746         WREG32(index_reg, 0x10801);
747         WREG32(data_reg, 0x89408940);
748         WREG32(index_reg, 0x10802);
749         WREG32(data_reg, 0xBFE8BED8);
750         WREG32(index_reg, 0x20000);
751         WREG32(data_reg, 0x80008000);
752         WREG32(index_reg, 0x20001);
753         WREG32(data_reg, 0x90008000);
754         WREG32(index_reg, 0x20002);
755         WREG32(data_reg, 0x80008000);
756         WREG32(index_reg, 0x20003);
757         WREG32(data_reg, 0x80008000);
758         WREG32(index_reg, 0x20100);
759         WREG32(data_reg, 0x80108000);
760         WREG32(index_reg, 0x20101);
761         WREG32(data_reg, 0x8FE0BF70);
762         WREG32(index_reg, 0x20102);
763         WREG32(data_reg, 0xBFE880C0);
764         WREG32(index_reg, 0x20103);
765         WREG32(data_reg, 0x80008000);
766         WREG32(index_reg, 0x20200);
767         WREG32(data_reg, 0x8018BFF8);
768         WREG32(index_reg, 0x20201);
769         WREG32(data_reg, 0x8F80BF08);
770         WREG32(index_reg, 0x20202);
771         WREG32(data_reg, 0xBFD081A0);
772         WREG32(index_reg, 0x20203);
773         WREG32(data_reg, 0xBFF88000);
774         WREG32(index_reg, 0x20300);
775         WREG32(data_reg, 0x80188000);
776         WREG32(index_reg, 0x20301);
777         WREG32(data_reg, 0x8EE0BEC0);
778         WREG32(index_reg, 0x20302);
779         WREG32(data_reg, 0xBFB082A0);
780         WREG32(index_reg, 0x20303);
781         WREG32(data_reg, 0x80008000);
782         WREG32(index_reg, 0x20400);
783         WREG32(data_reg, 0x80188000);
784         WREG32(index_reg, 0x20401);
785         WREG32(data_reg, 0x8E00BEA0);
786         WREG32(index_reg, 0x20402);
787         WREG32(data_reg, 0xBF8883C0);
788         WREG32(index_reg, 0x20403);
789         WREG32(data_reg, 0x80008000);
790         WREG32(index_reg, 0x20500);
791         WREG32(data_reg, 0x80188000);
792         WREG32(index_reg, 0x20501);
793         WREG32(data_reg, 0x8D00BE90);
794         WREG32(index_reg, 0x20502);
795         WREG32(data_reg, 0xBF588500);
796         WREG32(index_reg, 0x20503);
797         WREG32(data_reg, 0x80008008);
798         WREG32(index_reg, 0x20600);
799         WREG32(data_reg, 0x80188000);
800         WREG32(index_reg, 0x20601);
801         WREG32(data_reg, 0x8BC0BE98);
802         WREG32(index_reg, 0x20602);
803         WREG32(data_reg, 0xBF308660);
804         WREG32(index_reg, 0x20603);
805         WREG32(data_reg, 0x80008008);
806         WREG32(index_reg, 0x20700);
807         WREG32(data_reg, 0x80108000);
808         WREG32(index_reg, 0x20701);
809         WREG32(data_reg, 0x8A80BEB0);
810         WREG32(index_reg, 0x20702);
811         WREG32(data_reg, 0xBF0087C0);
812         WREG32(index_reg, 0x20703);
813         WREG32(data_reg, 0x80008008);
814         WREG32(index_reg, 0x20800);
815         WREG32(data_reg, 0x80108000);
816         WREG32(index_reg, 0x20801);
817         WREG32(data_reg, 0x8920BED0);
818         WREG32(index_reg, 0x20802);
819         WREG32(data_reg, 0xBED08920);
820         WREG32(index_reg, 0x20803);
821         WREG32(data_reg, 0x80008010);
822         WREG32(index_reg, 0x30000);
823         WREG32(data_reg, 0x90008000);
824         WREG32(index_reg, 0x30001);
825         WREG32(data_reg, 0x80008000);
826         WREG32(index_reg, 0x30100);
827         WREG32(data_reg, 0x8FE0BF90);
828         WREG32(index_reg, 0x30101);
829         WREG32(data_reg, 0xBFF880A0);
830         WREG32(index_reg, 0x30200);
831         WREG32(data_reg, 0x8F60BF40);
832         WREG32(index_reg, 0x30201);
833         WREG32(data_reg, 0xBFE88180);
834         WREG32(index_reg, 0x30300);
835         WREG32(data_reg, 0x8EC0BF00);
836         WREG32(index_reg, 0x30301);
837         WREG32(data_reg, 0xBFC88280);
838         WREG32(index_reg, 0x30400);
839         WREG32(data_reg, 0x8DE0BEE0);
840         WREG32(index_reg, 0x30401);
841         WREG32(data_reg, 0xBFA083A0);
842         WREG32(index_reg, 0x30500);
843         WREG32(data_reg, 0x8CE0BED0);
844         WREG32(index_reg, 0x30501);
845         WREG32(data_reg, 0xBF7884E0);
846         WREG32(index_reg, 0x30600);
847         WREG32(data_reg, 0x8BA0BED8);
848         WREG32(index_reg, 0x30601);
849         WREG32(data_reg, 0xBF508640);
850         WREG32(index_reg, 0x30700);
851         WREG32(data_reg, 0x8A60BEE8);
852         WREG32(index_reg, 0x30701);
853         WREG32(data_reg, 0xBF2087A0);
854         WREG32(index_reg, 0x30800);
855         WREG32(data_reg, 0x8900BF00);
856         WREG32(index_reg, 0x30801);
857         WREG32(data_reg, 0xBF008900);
858 }
859
860 struct rv515_watermark {
861         u32        lb_request_fifo_depth;
862         fixed20_12 num_line_pair;
863         fixed20_12 estimated_width;
864         fixed20_12 worst_case_latency;
865         fixed20_12 consumption_rate;
866         fixed20_12 active_time;
867         fixed20_12 dbpp;
868         fixed20_12 priority_mark_max;
869         fixed20_12 priority_mark;
870         fixed20_12 sclk;
871 };
872
873 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
874                                   struct radeon_crtc *crtc,
875                                   struct rv515_watermark *wm)
876 {
877         struct drm_display_mode *mode = &crtc->base.mode;
878         fixed20_12 a, b, c;
879         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
880         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
881
882         if (!crtc->base.enabled) {
883                 /* FIXME: wouldn't it better to set priority mark to maximum */
884                 wm->lb_request_fifo_depth = 4;
885                 return;
886         }
887
888         if (crtc->vsc.full > rfixed_const(2))
889                 wm->num_line_pair.full = rfixed_const(2);
890         else
891                 wm->num_line_pair.full = rfixed_const(1);
892
893         b.full = rfixed_const(mode->crtc_hdisplay);
894         c.full = rfixed_const(256);
895         a.full = rfixed_div(b, c);
896         request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
897         request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
898         if (a.full < rfixed_const(4)) {
899                 wm->lb_request_fifo_depth = 4;
900         } else {
901                 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
902         }
903
904         /* Determine consumption rate
905          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
906          *  vtaps = number of vertical taps,
907          *  vsc = vertical scaling ratio, defined as source/destination
908          *  hsc = horizontal scaling ration, defined as source/destination
909          */
910         a.full = rfixed_const(mode->clock);
911         b.full = rfixed_const(1000);
912         a.full = rfixed_div(a, b);
913         pclk.full = rfixed_div(b, a);
914         if (crtc->rmx_type != RMX_OFF) {
915                 b.full = rfixed_const(2);
916                 if (crtc->vsc.full > b.full)
917                         b.full = crtc->vsc.full;
918                 b.full = rfixed_mul(b, crtc->hsc);
919                 c.full = rfixed_const(2);
920                 b.full = rfixed_div(b, c);
921                 consumption_time.full = rfixed_div(pclk, b);
922         } else {
923                 consumption_time.full = pclk.full;
924         }
925         a.full = rfixed_const(1);
926         wm->consumption_rate.full = rfixed_div(a, consumption_time);
927
928
929         /* Determine line time
930          *  LineTime = total time for one line of displayhtotal
931          *  LineTime = total number of horizontal pixels
932          *  pclk = pixel clock period(ns)
933          */
934         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
935         line_time.full = rfixed_mul(a, pclk);
936
937         /* Determine active time
938          *  ActiveTime = time of active region of display within one line,
939          *  hactive = total number of horizontal active pixels
940          *  htotal = total number of horizontal pixels
941          */
942         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
943         b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
944         wm->active_time.full = rfixed_mul(line_time, b);
945         wm->active_time.full = rfixed_div(wm->active_time, a);
946
947         /* Determine chunk time
948          * ChunkTime = the time it takes the DCP to send one chunk of data
949          * to the LB which consists of pipeline delay and inter chunk gap
950          * sclk = system clock(Mhz)
951          */
952         a.full = rfixed_const(600 * 1000);
953         chunk_time.full = rfixed_div(a, rdev->pm.sclk);
954         read_delay_latency.full = rfixed_const(1000);
955
956         /* Determine the worst case latency
957          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
958          * WorstCaseLatency = worst case time from urgent to when the MC starts
959          *                    to return data
960          * READ_DELAY_IDLE_MAX = constant of 1us
961          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
962          *             which consists of pipeline delay and inter chunk gap
963          */
964         if (rfixed_trunc(wm->num_line_pair) > 1) {
965                 a.full = rfixed_const(3);
966                 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
967                 wm->worst_case_latency.full += read_delay_latency.full;
968         } else {
969                 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
970         }
971
972         /* Determine the tolerable latency
973          * TolerableLatency = Any given request has only 1 line time
974          *                    for the data to be returned
975          * LBRequestFifoDepth = Number of chunk requests the LB can
976          *                      put into the request FIFO for a display
977          *  LineTime = total time for one line of display
978          *  ChunkTime = the time it takes the DCP to send one chunk
979          *              of data to the LB which consists of
980          *  pipeline delay and inter chunk gap
981          */
982         if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
983                 tolerable_latency.full = line_time.full;
984         } else {
985                 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
986                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
987                 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
988                 tolerable_latency.full = line_time.full - tolerable_latency.full;
989         }
990         /* We assume worst case 32bits (4 bytes) */
991         wm->dbpp.full = rfixed_const(2 * 16);
992
993         /* Determine the maximum priority mark
994          *  width = viewport width in pixels
995          */
996         a.full = rfixed_const(16);
997         wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
998         wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
999         wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
1000
1001         /* Determine estimated width */
1002         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1003         estimated_width.full = rfixed_div(estimated_width, consumption_time);
1004         if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1005                 wm->priority_mark.full = wm->priority_mark_max.full;
1006         } else {
1007                 a.full = rfixed_const(16);
1008                 wm->priority_mark.full = rfixed_div(estimated_width, a);
1009                 wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
1010                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1011         }
1012 }
1013
1014 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1015 {
1016         struct drm_display_mode *mode0 = NULL;
1017         struct drm_display_mode *mode1 = NULL;
1018         struct rv515_watermark wm0;
1019         struct rv515_watermark wm1;
1020         u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt;
1021         fixed20_12 priority_mark02, priority_mark12, fill_rate;
1022         fixed20_12 a, b;
1023
1024         if (rdev->mode_info.crtcs[0]->base.enabled)
1025                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1026         if (rdev->mode_info.crtcs[1]->base.enabled)
1027                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1028         rs690_line_buffer_adjust(rdev, mode0, mode1);
1029
1030         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
1031         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
1032
1033         tmp = wm0.lb_request_fifo_depth;
1034         tmp |= wm1.lb_request_fifo_depth << 16;
1035         WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1036
1037         if (mode0 && mode1) {
1038                 if (rfixed_trunc(wm0.dbpp) > 64)
1039                         a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1040                 else
1041                         a.full = wm0.num_line_pair.full;
1042                 if (rfixed_trunc(wm1.dbpp) > 64)
1043                         b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1044                 else
1045                         b.full = wm1.num_line_pair.full;
1046                 a.full += b.full;
1047                 fill_rate.full = rfixed_div(wm0.sclk, a);
1048                 if (wm0.consumption_rate.full > fill_rate.full) {
1049                         b.full = wm0.consumption_rate.full - fill_rate.full;
1050                         b.full = rfixed_mul(b, wm0.active_time);
1051                         a.full = rfixed_const(16);
1052                         b.full = rfixed_div(b, a);
1053                         a.full = rfixed_mul(wm0.worst_case_latency,
1054                                                 wm0.consumption_rate);
1055                         priority_mark02.full = a.full + b.full;
1056                 } else {
1057                         a.full = rfixed_mul(wm0.worst_case_latency,
1058                                                 wm0.consumption_rate);
1059                         b.full = rfixed_const(16 * 1000);
1060                         priority_mark02.full = rfixed_div(a, b);
1061                 }
1062                 if (wm1.consumption_rate.full > fill_rate.full) {
1063                         b.full = wm1.consumption_rate.full - fill_rate.full;
1064                         b.full = rfixed_mul(b, wm1.active_time);
1065                         a.full = rfixed_const(16);
1066                         b.full = rfixed_div(b, a);
1067                         a.full = rfixed_mul(wm1.worst_case_latency,
1068                                                 wm1.consumption_rate);
1069                         priority_mark12.full = a.full + b.full;
1070                 } else {
1071                         a.full = rfixed_mul(wm1.worst_case_latency,
1072                                                 wm1.consumption_rate);
1073                         b.full = rfixed_const(16 * 1000);
1074                         priority_mark12.full = rfixed_div(a, b);
1075                 }
1076                 if (wm0.priority_mark.full > priority_mark02.full)
1077                         priority_mark02.full = wm0.priority_mark.full;
1078                 if (rfixed_trunc(priority_mark02) < 0)
1079                         priority_mark02.full = 0;
1080                 if (wm0.priority_mark_max.full > priority_mark02.full)
1081                         priority_mark02.full = wm0.priority_mark_max.full;
1082                 if (wm1.priority_mark.full > priority_mark12.full)
1083                         priority_mark12.full = wm1.priority_mark.full;
1084                 if (rfixed_trunc(priority_mark12) < 0)
1085                         priority_mark12.full = 0;
1086                 if (wm1.priority_mark_max.full > priority_mark12.full)
1087                         priority_mark12.full = wm1.priority_mark_max.full;
1088                 d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
1089                 d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
1090                 if (rdev->disp_priority == 2) {
1091                         d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1092                         d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1093                 }
1094                 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1095                 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1096                 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1097                 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1098         } else if (mode0) {
1099                 if (rfixed_trunc(wm0.dbpp) > 64)
1100                         a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1101                 else
1102                         a.full = wm0.num_line_pair.full;
1103                 fill_rate.full = rfixed_div(wm0.sclk, a);
1104                 if (wm0.consumption_rate.full > fill_rate.full) {
1105                         b.full = wm0.consumption_rate.full - fill_rate.full;
1106                         b.full = rfixed_mul(b, wm0.active_time);
1107                         a.full = rfixed_const(16);
1108                         b.full = rfixed_div(b, a);
1109                         a.full = rfixed_mul(wm0.worst_case_latency,
1110                                                 wm0.consumption_rate);
1111                         priority_mark02.full = a.full + b.full;
1112                 } else {
1113                         a.full = rfixed_mul(wm0.worst_case_latency,
1114                                                 wm0.consumption_rate);
1115                         b.full = rfixed_const(16);
1116                         priority_mark02.full = rfixed_div(a, b);
1117                 }
1118                 if (wm0.priority_mark.full > priority_mark02.full)
1119                         priority_mark02.full = wm0.priority_mark.full;
1120                 if (rfixed_trunc(priority_mark02) < 0)
1121                         priority_mark02.full = 0;
1122                 if (wm0.priority_mark_max.full > priority_mark02.full)
1123                         priority_mark02.full = wm0.priority_mark_max.full;
1124                 d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
1125                 if (rdev->disp_priority == 2)
1126                         d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1127                 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1128                 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1129                 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1130                 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1131         } else {
1132                 if (rfixed_trunc(wm1.dbpp) > 64)
1133                         a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1134                 else
1135                         a.full = wm1.num_line_pair.full;
1136                 fill_rate.full = rfixed_div(wm1.sclk, a);
1137                 if (wm1.consumption_rate.full > fill_rate.full) {
1138                         b.full = wm1.consumption_rate.full - fill_rate.full;
1139                         b.full = rfixed_mul(b, wm1.active_time);
1140                         a.full = rfixed_const(16);
1141                         b.full = rfixed_div(b, a);
1142                         a.full = rfixed_mul(wm1.worst_case_latency,
1143                                                 wm1.consumption_rate);
1144                         priority_mark12.full = a.full + b.full;
1145                 } else {
1146                         a.full = rfixed_mul(wm1.worst_case_latency,
1147                                                 wm1.consumption_rate);
1148                         b.full = rfixed_const(16 * 1000);
1149                         priority_mark12.full = rfixed_div(a, b);
1150                 }
1151                 if (wm1.priority_mark.full > priority_mark12.full)
1152                         priority_mark12.full = wm1.priority_mark.full;
1153                 if (rfixed_trunc(priority_mark12) < 0)
1154                         priority_mark12.full = 0;
1155                 if (wm1.priority_mark_max.full > priority_mark12.full)
1156                         priority_mark12.full = wm1.priority_mark_max.full;
1157                 d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
1158                 if (rdev->disp_priority == 2)
1159                         d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1160                 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1161                 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1162                 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1163                 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1164         }
1165 }
1166
1167 void rv515_bandwidth_update(struct radeon_device *rdev)
1168 {
1169         uint32_t tmp;
1170         struct drm_display_mode *mode0 = NULL;
1171         struct drm_display_mode *mode1 = NULL;
1172
1173         radeon_update_display_priority(rdev);
1174
1175         if (rdev->mode_info.crtcs[0]->base.enabled)
1176                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1177         if (rdev->mode_info.crtcs[1]->base.enabled)
1178                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1179         /*
1180          * Set display0/1 priority up in the memory controller for
1181          * modes if the user specifies HIGH for displaypriority
1182          * option.
1183          */
1184         if ((rdev->disp_priority == 2) &&
1185             (rdev->family == CHIP_RV515)) {
1186                 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1187                 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1188                 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1189                 if (mode1)
1190                         tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1191                 if (mode0)
1192                         tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1193                 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1194         }
1195         rv515_bandwidth_avivo_update(rdev);
1196 }