Merge branch 'master' into export-slabh
[kernel.git] / drivers / gpu / drm / radeon / rv770.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/firmware.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
31 #include "drmP.h"
32 #include "radeon.h"
33 #include "radeon_asic.h"
34 #include "radeon_drm.h"
35 #include "rv770d.h"
36 #include "atom.h"
37 #include "avivod.h"
38
39 #define R700_PFP_UCODE_SIZE 848
40 #define R700_PM4_UCODE_SIZE 1360
41
42 static void rv770_gpu_init(struct radeon_device *rdev);
43 void rv770_fini(struct radeon_device *rdev);
44
45
46 /*
47  * GART
48  */
49 int rv770_pcie_gart_enable(struct radeon_device *rdev)
50 {
51         u32 tmp;
52         int r, i;
53
54         if (rdev->gart.table.vram.robj == NULL) {
55                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
56                 return -EINVAL;
57         }
58         r = radeon_gart_table_vram_pin(rdev);
59         if (r)
60                 return r;
61         radeon_gart_restore(rdev);
62         /* Setup L2 cache */
63         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
64                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
65                                 EFFECTIVE_L2_QUEUE_SIZE(7));
66         WREG32(VM_L2_CNTL2, 0);
67         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
68         /* Setup TLB control */
69         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
70                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
71                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
72                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
73         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
74         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
75         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
76         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
77         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
78         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
79         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
80         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
81         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
82         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
83         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
84                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
85         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
86                         (u32)(rdev->dummy_page.addr >> 12));
87         for (i = 1; i < 7; i++)
88                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
89
90         r600_pcie_gart_tlb_flush(rdev);
91         rdev->gart.ready = true;
92         return 0;
93 }
94
95 void rv770_pcie_gart_disable(struct radeon_device *rdev)
96 {
97         u32 tmp;
98         int i, r;
99
100         /* Disable all tables */
101         for (i = 0; i < 7; i++)
102                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
103
104         /* Setup L2 cache */
105         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
106                                 EFFECTIVE_L2_QUEUE_SIZE(7));
107         WREG32(VM_L2_CNTL2, 0);
108         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
109         /* Setup TLB control */
110         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
111         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
112         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
113         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
114         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
115         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
116         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
117         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
118         if (rdev->gart.table.vram.robj) {
119                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
120                 if (likely(r == 0)) {
121                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
122                         radeon_bo_unpin(rdev->gart.table.vram.robj);
123                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
124                 }
125         }
126 }
127
128 void rv770_pcie_gart_fini(struct radeon_device *rdev)
129 {
130         radeon_gart_fini(rdev);
131         rv770_pcie_gart_disable(rdev);
132         radeon_gart_table_vram_free(rdev);
133 }
134
135
136 void rv770_agp_enable(struct radeon_device *rdev)
137 {
138         u32 tmp;
139         int i;
140
141         /* Setup L2 cache */
142         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
143                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
144                                 EFFECTIVE_L2_QUEUE_SIZE(7));
145         WREG32(VM_L2_CNTL2, 0);
146         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
147         /* Setup TLB control */
148         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
149                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
150                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
151                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
152         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
153         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
154         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
155         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
156         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
157         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
158         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
159         for (i = 0; i < 7; i++)
160                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
161 }
162
163 static void rv770_mc_program(struct radeon_device *rdev)
164 {
165         struct rv515_mc_save save;
166         u32 tmp;
167         int i, j;
168
169         /* Initialize HDP */
170         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
171                 WREG32((0x2c14 + j), 0x00000000);
172                 WREG32((0x2c18 + j), 0x00000000);
173                 WREG32((0x2c1c + j), 0x00000000);
174                 WREG32((0x2c20 + j), 0x00000000);
175                 WREG32((0x2c24 + j), 0x00000000);
176         }
177         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
178
179         rv515_mc_stop(rdev, &save);
180         if (r600_mc_wait_for_idle(rdev)) {
181                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
182         }
183         /* Lockout access through VGA aperture*/
184         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
185         /* Update configuration */
186         if (rdev->flags & RADEON_IS_AGP) {
187                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
188                         /* VRAM before AGP */
189                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
190                                 rdev->mc.vram_start >> 12);
191                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
192                                 rdev->mc.gtt_end >> 12);
193                 } else {
194                         /* VRAM after AGP */
195                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
196                                 rdev->mc.gtt_start >> 12);
197                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
198                                 rdev->mc.vram_end >> 12);
199                 }
200         } else {
201                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
202                         rdev->mc.vram_start >> 12);
203                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
204                         rdev->mc.vram_end >> 12);
205         }
206         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
207         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
208         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
209         WREG32(MC_VM_FB_LOCATION, tmp);
210         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
211         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
212         WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
213         if (rdev->flags & RADEON_IS_AGP) {
214                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
215                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
216                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
217         } else {
218                 WREG32(MC_VM_AGP_BASE, 0);
219                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
220                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
221         }
222         if (r600_mc_wait_for_idle(rdev)) {
223                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
224         }
225         rv515_mc_resume(rdev, &save);
226         /* we need to own VRAM, so turn off the VGA renderer here
227          * to stop it overwriting our objects */
228         rv515_vga_render_disable(rdev);
229 }
230
231
232 /*
233  * CP.
234  */
235 void r700_cp_stop(struct radeon_device *rdev)
236 {
237         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
238 }
239
240
241 static int rv770_cp_load_microcode(struct radeon_device *rdev)
242 {
243         const __be32 *fw_data;
244         int i;
245
246         if (!rdev->me_fw || !rdev->pfp_fw)
247                 return -EINVAL;
248
249         r700_cp_stop(rdev);
250         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
251
252         /* Reset cp */
253         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
254         RREG32(GRBM_SOFT_RESET);
255         mdelay(15);
256         WREG32(GRBM_SOFT_RESET, 0);
257
258         fw_data = (const __be32 *)rdev->pfp_fw->data;
259         WREG32(CP_PFP_UCODE_ADDR, 0);
260         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
261                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
262         WREG32(CP_PFP_UCODE_ADDR, 0);
263
264         fw_data = (const __be32 *)rdev->me_fw->data;
265         WREG32(CP_ME_RAM_WADDR, 0);
266         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
267                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
268
269         WREG32(CP_PFP_UCODE_ADDR, 0);
270         WREG32(CP_ME_RAM_WADDR, 0);
271         WREG32(CP_ME_RAM_RADDR, 0);
272         return 0;
273 }
274
275
276 /*
277  * Core functions
278  */
279 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
280                                              u32 num_tile_pipes,
281                                              u32 num_backends,
282                                              u32 backend_disable_mask)
283 {
284         u32 backend_map = 0;
285         u32 enabled_backends_mask;
286         u32 enabled_backends_count;
287         u32 cur_pipe;
288         u32 swizzle_pipe[R7XX_MAX_PIPES];
289         u32 cur_backend;
290         u32 i;
291         bool force_no_swizzle;
292
293         if (num_tile_pipes > R7XX_MAX_PIPES)
294                 num_tile_pipes = R7XX_MAX_PIPES;
295         if (num_tile_pipes < 1)
296                 num_tile_pipes = 1;
297         if (num_backends > R7XX_MAX_BACKENDS)
298                 num_backends = R7XX_MAX_BACKENDS;
299         if (num_backends < 1)
300                 num_backends = 1;
301
302         enabled_backends_mask = 0;
303         enabled_backends_count = 0;
304         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
305                 if (((backend_disable_mask >> i) & 1) == 0) {
306                         enabled_backends_mask |= (1 << i);
307                         ++enabled_backends_count;
308                 }
309                 if (enabled_backends_count == num_backends)
310                         break;
311         }
312
313         if (enabled_backends_count == 0) {
314                 enabled_backends_mask = 1;
315                 enabled_backends_count = 1;
316         }
317
318         if (enabled_backends_count != num_backends)
319                 num_backends = enabled_backends_count;
320
321         switch (rdev->family) {
322         case CHIP_RV770:
323         case CHIP_RV730:
324                 force_no_swizzle = false;
325                 break;
326         case CHIP_RV710:
327         case CHIP_RV740:
328         default:
329                 force_no_swizzle = true;
330                 break;
331         }
332
333         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
334         switch (num_tile_pipes) {
335         case 1:
336                 swizzle_pipe[0] = 0;
337                 break;
338         case 2:
339                 swizzle_pipe[0] = 0;
340                 swizzle_pipe[1] = 1;
341                 break;
342         case 3:
343                 if (force_no_swizzle) {
344                         swizzle_pipe[0] = 0;
345                         swizzle_pipe[1] = 1;
346                         swizzle_pipe[2] = 2;
347                 } else {
348                         swizzle_pipe[0] = 0;
349                         swizzle_pipe[1] = 2;
350                         swizzle_pipe[2] = 1;
351                 }
352                 break;
353         case 4:
354                 if (force_no_swizzle) {
355                         swizzle_pipe[0] = 0;
356                         swizzle_pipe[1] = 1;
357                         swizzle_pipe[2] = 2;
358                         swizzle_pipe[3] = 3;
359                 } else {
360                         swizzle_pipe[0] = 0;
361                         swizzle_pipe[1] = 2;
362                         swizzle_pipe[2] = 3;
363                         swizzle_pipe[3] = 1;
364                 }
365                 break;
366         case 5:
367                 if (force_no_swizzle) {
368                         swizzle_pipe[0] = 0;
369                         swizzle_pipe[1] = 1;
370                         swizzle_pipe[2] = 2;
371                         swizzle_pipe[3] = 3;
372                         swizzle_pipe[4] = 4;
373                 } else {
374                         swizzle_pipe[0] = 0;
375                         swizzle_pipe[1] = 2;
376                         swizzle_pipe[2] = 4;
377                         swizzle_pipe[3] = 1;
378                         swizzle_pipe[4] = 3;
379                 }
380                 break;
381         case 6:
382                 if (force_no_swizzle) {
383                         swizzle_pipe[0] = 0;
384                         swizzle_pipe[1] = 1;
385                         swizzle_pipe[2] = 2;
386                         swizzle_pipe[3] = 3;
387                         swizzle_pipe[4] = 4;
388                         swizzle_pipe[5] = 5;
389                 } else {
390                         swizzle_pipe[0] = 0;
391                         swizzle_pipe[1] = 2;
392                         swizzle_pipe[2] = 4;
393                         swizzle_pipe[3] = 5;
394                         swizzle_pipe[4] = 3;
395                         swizzle_pipe[5] = 1;
396                 }
397                 break;
398         case 7:
399                 if (force_no_swizzle) {
400                         swizzle_pipe[0] = 0;
401                         swizzle_pipe[1] = 1;
402                         swizzle_pipe[2] = 2;
403                         swizzle_pipe[3] = 3;
404                         swizzle_pipe[4] = 4;
405                         swizzle_pipe[5] = 5;
406                         swizzle_pipe[6] = 6;
407                 } else {
408                         swizzle_pipe[0] = 0;
409                         swizzle_pipe[1] = 2;
410                         swizzle_pipe[2] = 4;
411                         swizzle_pipe[3] = 6;
412                         swizzle_pipe[4] = 3;
413                         swizzle_pipe[5] = 1;
414                         swizzle_pipe[6] = 5;
415                 }
416                 break;
417         case 8:
418                 if (force_no_swizzle) {
419                         swizzle_pipe[0] = 0;
420                         swizzle_pipe[1] = 1;
421                         swizzle_pipe[2] = 2;
422                         swizzle_pipe[3] = 3;
423                         swizzle_pipe[4] = 4;
424                         swizzle_pipe[5] = 5;
425                         swizzle_pipe[6] = 6;
426                         swizzle_pipe[7] = 7;
427                 } else {
428                         swizzle_pipe[0] = 0;
429                         swizzle_pipe[1] = 2;
430                         swizzle_pipe[2] = 4;
431                         swizzle_pipe[3] = 6;
432                         swizzle_pipe[4] = 3;
433                         swizzle_pipe[5] = 1;
434                         swizzle_pipe[6] = 7;
435                         swizzle_pipe[7] = 5;
436                 }
437                 break;
438         }
439
440         cur_backend = 0;
441         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
442                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
443                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
444
445                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
446
447                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
448         }
449
450         return backend_map;
451 }
452
453 static void rv770_gpu_init(struct radeon_device *rdev)
454 {
455         int i, j, num_qd_pipes;
456         u32 ta_aux_cntl;
457         u32 sx_debug_1;
458         u32 smx_dc_ctl0;
459         u32 db_debug3;
460         u32 num_gs_verts_per_thread;
461         u32 vgt_gs_per_es;
462         u32 gs_prim_buffer_depth = 0;
463         u32 sq_ms_fifo_sizes;
464         u32 sq_config;
465         u32 sq_thread_resource_mgmt;
466         u32 hdp_host_path_cntl;
467         u32 sq_dyn_gpr_size_simd_ab_0;
468         u32 backend_map;
469         u32 gb_tiling_config = 0;
470         u32 cc_rb_backend_disable = 0;
471         u32 cc_gc_shader_pipe_config = 0;
472         u32 mc_arb_ramcfg;
473         u32 db_debug4;
474
475         /* setup chip specs */
476         switch (rdev->family) {
477         case CHIP_RV770:
478                 rdev->config.rv770.max_pipes = 4;
479                 rdev->config.rv770.max_tile_pipes = 8;
480                 rdev->config.rv770.max_simds = 10;
481                 rdev->config.rv770.max_backends = 4;
482                 rdev->config.rv770.max_gprs = 256;
483                 rdev->config.rv770.max_threads = 248;
484                 rdev->config.rv770.max_stack_entries = 512;
485                 rdev->config.rv770.max_hw_contexts = 8;
486                 rdev->config.rv770.max_gs_threads = 16 * 2;
487                 rdev->config.rv770.sx_max_export_size = 128;
488                 rdev->config.rv770.sx_max_export_pos_size = 16;
489                 rdev->config.rv770.sx_max_export_smx_size = 112;
490                 rdev->config.rv770.sq_num_cf_insts = 2;
491
492                 rdev->config.rv770.sx_num_of_sets = 7;
493                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
494                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
495                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
496                 break;
497         case CHIP_RV730:
498                 rdev->config.rv770.max_pipes = 2;
499                 rdev->config.rv770.max_tile_pipes = 4;
500                 rdev->config.rv770.max_simds = 8;
501                 rdev->config.rv770.max_backends = 2;
502                 rdev->config.rv770.max_gprs = 128;
503                 rdev->config.rv770.max_threads = 248;
504                 rdev->config.rv770.max_stack_entries = 256;
505                 rdev->config.rv770.max_hw_contexts = 8;
506                 rdev->config.rv770.max_gs_threads = 16 * 2;
507                 rdev->config.rv770.sx_max_export_size = 256;
508                 rdev->config.rv770.sx_max_export_pos_size = 32;
509                 rdev->config.rv770.sx_max_export_smx_size = 224;
510                 rdev->config.rv770.sq_num_cf_insts = 2;
511
512                 rdev->config.rv770.sx_num_of_sets = 7;
513                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
514                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
515                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
516                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
517                         rdev->config.rv770.sx_max_export_pos_size -= 16;
518                         rdev->config.rv770.sx_max_export_smx_size += 16;
519                 }
520                 break;
521         case CHIP_RV710:
522                 rdev->config.rv770.max_pipes = 2;
523                 rdev->config.rv770.max_tile_pipes = 2;
524                 rdev->config.rv770.max_simds = 2;
525                 rdev->config.rv770.max_backends = 1;
526                 rdev->config.rv770.max_gprs = 256;
527                 rdev->config.rv770.max_threads = 192;
528                 rdev->config.rv770.max_stack_entries = 256;
529                 rdev->config.rv770.max_hw_contexts = 4;
530                 rdev->config.rv770.max_gs_threads = 8 * 2;
531                 rdev->config.rv770.sx_max_export_size = 128;
532                 rdev->config.rv770.sx_max_export_pos_size = 16;
533                 rdev->config.rv770.sx_max_export_smx_size = 112;
534                 rdev->config.rv770.sq_num_cf_insts = 1;
535
536                 rdev->config.rv770.sx_num_of_sets = 7;
537                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
538                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
539                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
540                 break;
541         case CHIP_RV740:
542                 rdev->config.rv770.max_pipes = 4;
543                 rdev->config.rv770.max_tile_pipes = 4;
544                 rdev->config.rv770.max_simds = 8;
545                 rdev->config.rv770.max_backends = 4;
546                 rdev->config.rv770.max_gprs = 256;
547                 rdev->config.rv770.max_threads = 248;
548                 rdev->config.rv770.max_stack_entries = 512;
549                 rdev->config.rv770.max_hw_contexts = 8;
550                 rdev->config.rv770.max_gs_threads = 16 * 2;
551                 rdev->config.rv770.sx_max_export_size = 256;
552                 rdev->config.rv770.sx_max_export_pos_size = 32;
553                 rdev->config.rv770.sx_max_export_smx_size = 224;
554                 rdev->config.rv770.sq_num_cf_insts = 2;
555
556                 rdev->config.rv770.sx_num_of_sets = 7;
557                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
558                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
559                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
560
561                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
562                         rdev->config.rv770.sx_max_export_pos_size -= 16;
563                         rdev->config.rv770.sx_max_export_smx_size += 16;
564                 }
565                 break;
566         default:
567                 break;
568         }
569
570         /* Initialize HDP */
571         j = 0;
572         for (i = 0; i < 32; i++) {
573                 WREG32((0x2c14 + j), 0x00000000);
574                 WREG32((0x2c18 + j), 0x00000000);
575                 WREG32((0x2c1c + j), 0x00000000);
576                 WREG32((0x2c20 + j), 0x00000000);
577                 WREG32((0x2c24 + j), 0x00000000);
578                 j += 0x18;
579         }
580
581         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
582
583         /* setup tiling, simd, pipe config */
584         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
585
586         switch (rdev->config.rv770.max_tile_pipes) {
587         case 1:
588         default:
589                 gb_tiling_config |= PIPE_TILING(0);
590                 break;
591         case 2:
592                 gb_tiling_config |= PIPE_TILING(1);
593                 break;
594         case 4:
595                 gb_tiling_config |= PIPE_TILING(2);
596                 break;
597         case 8:
598                 gb_tiling_config |= PIPE_TILING(3);
599                 break;
600         }
601         rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
602
603         if (rdev->family == CHIP_RV770)
604                 gb_tiling_config |= BANK_TILING(1);
605         else
606                 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
607         rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
608
609         gb_tiling_config |= GROUP_SIZE(0);
610         rdev->config.rv770.tiling_group_size = 256;
611
612         if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
613                 gb_tiling_config |= ROW_TILING(3);
614                 gb_tiling_config |= SAMPLE_SPLIT(3);
615         } else {
616                 gb_tiling_config |=
617                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
618                 gb_tiling_config |=
619                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
620         }
621
622         gb_tiling_config |= BANK_SWAPS(1);
623
624         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
625         cc_rb_backend_disable |=
626                 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
627
628         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
629         cc_gc_shader_pipe_config |=
630                 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
631         cc_gc_shader_pipe_config |=
632                 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
633
634         if (rdev->family == CHIP_RV740)
635                 backend_map = 0x28;
636         else
637                 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
638                                                                 rdev->config.rv770.max_tile_pipes,
639                                                                 (R7XX_MAX_BACKENDS -
640                                                                  r600_count_pipe_bits((cc_rb_backend_disable &
641                                                                                        R7XX_MAX_BACKENDS_MASK) >> 16)),
642                                                                 (cc_rb_backend_disable >> 16));
643         gb_tiling_config |= BACKEND_MAP(backend_map);
644
645
646         WREG32(GB_TILING_CONFIG, gb_tiling_config);
647         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
648         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
649
650         WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
651         WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
652         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
653         WREG32(CC_SYS_RB_BACKEND_DISABLE,  cc_rb_backend_disable);
654
655         WREG32(CGTS_SYS_TCC_DISABLE, 0);
656         WREG32(CGTS_TCC_DISABLE, 0);
657         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
658         WREG32(CGTS_USER_TCC_DISABLE, 0);
659
660         num_qd_pipes =
661                 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
662         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
663         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
664
665         /* set HW defaults for 3D engine */
666         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
667                                      ROQ_IB2_START(0x2b)));
668
669         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
670
671         ta_aux_cntl = RREG32(TA_CNTL_AUX);
672         WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
673
674         sx_debug_1 = RREG32(SX_DEBUG_1);
675         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
676         WREG32(SX_DEBUG_1, sx_debug_1);
677
678         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
679         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
680         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
681         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
682
683         if (rdev->family != CHIP_RV740)
684                 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
685                                        GS_FLUSH_CTL(4) |
686                                        ACK_FLUSH_CTL(3) |
687                                        SYNC_FLUSH_CTL));
688
689         db_debug3 = RREG32(DB_DEBUG3);
690         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
691         switch (rdev->family) {
692         case CHIP_RV770:
693         case CHIP_RV740:
694                 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
695                 break;
696         case CHIP_RV710:
697         case CHIP_RV730:
698         default:
699                 db_debug3 |= DB_CLK_OFF_DELAY(2);
700                 break;
701         }
702         WREG32(DB_DEBUG3, db_debug3);
703
704         if (rdev->family != CHIP_RV770) {
705                 db_debug4 = RREG32(DB_DEBUG4);
706                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
707                 WREG32(DB_DEBUG4, db_debug4);
708         }
709
710         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
711                                         POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
712                                         SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
713
714         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
715                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
716                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
717
718         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
719
720         WREG32(VGT_NUM_INSTANCES, 1);
721
722         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
723
724         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
725
726         WREG32(CP_PERFMON_CNTL, 0);
727
728         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
729                             DONE_FIFO_HIWATER(0xe0) |
730                             ALU_UPDATE_FIFO_HIWATER(0x8));
731         switch (rdev->family) {
732         case CHIP_RV770:
733         case CHIP_RV730:
734         case CHIP_RV710:
735                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
736                 break;
737         case CHIP_RV740:
738         default:
739                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
740                 break;
741         }
742         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
743
744         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
745          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
746          */
747         sq_config = RREG32(SQ_CONFIG);
748         sq_config &= ~(PS_PRIO(3) |
749                        VS_PRIO(3) |
750                        GS_PRIO(3) |
751                        ES_PRIO(3));
752         sq_config |= (DX9_CONSTS |
753                       VC_ENABLE |
754                       EXPORT_SRC_C |
755                       PS_PRIO(0) |
756                       VS_PRIO(1) |
757                       GS_PRIO(2) |
758                       ES_PRIO(3));
759         if (rdev->family == CHIP_RV710)
760                 /* no vertex cache */
761                 sq_config &= ~VC_ENABLE;
762
763         WREG32(SQ_CONFIG, sq_config);
764
765         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
766                                          NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
767                                          NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
768
769         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
770                                          NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
771
772         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
773                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
774                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
775         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
776                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
777         else
778                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
779         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
780
781         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
782                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
783
784         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
785                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
786
787         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
788                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
789                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
790                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
791
792         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
793         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
794         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
795         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
796         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
797         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
798         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
799         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
800
801         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
802                                           FORCE_EOV_MAX_REZ_CNT(255)));
803
804         if (rdev->family == CHIP_RV710)
805                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
806                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
807         else
808                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
809                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
810
811         switch (rdev->family) {
812         case CHIP_RV770:
813         case CHIP_RV730:
814         case CHIP_RV740:
815                 gs_prim_buffer_depth = 384;
816                 break;
817         case CHIP_RV710:
818                 gs_prim_buffer_depth = 128;
819                 break;
820         default:
821                 break;
822         }
823
824         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
825         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
826         /* Max value for this is 256 */
827         if (vgt_gs_per_es > 256)
828                 vgt_gs_per_es = 256;
829
830         WREG32(VGT_ES_PER_GS, 128);
831         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
832         WREG32(VGT_GS_PER_VS, 2);
833
834         /* more default values. 2D/3D driver should adjust as needed */
835         WREG32(VGT_GS_VERTEX_REUSE, 16);
836         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
837         WREG32(VGT_STRMOUT_EN, 0);
838         WREG32(SX_MISC, 0);
839         WREG32(PA_SC_MODE_CNTL, 0);
840         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
841         WREG32(PA_SC_AA_CONFIG, 0);
842         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
843         WREG32(PA_SC_LINE_STIPPLE, 0);
844         WREG32(SPI_INPUT_Z, 0);
845         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
846         WREG32(CB_COLOR7_FRAG, 0);
847
848         /* clear render buffer base addresses */
849         WREG32(CB_COLOR0_BASE, 0);
850         WREG32(CB_COLOR1_BASE, 0);
851         WREG32(CB_COLOR2_BASE, 0);
852         WREG32(CB_COLOR3_BASE, 0);
853         WREG32(CB_COLOR4_BASE, 0);
854         WREG32(CB_COLOR5_BASE, 0);
855         WREG32(CB_COLOR6_BASE, 0);
856         WREG32(CB_COLOR7_BASE, 0);
857
858         WREG32(TCP_CNTL, 0);
859
860         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
861         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
862
863         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
864
865         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
866                                           NUM_CLIP_SEQ(3)));
867
868 }
869
870 int rv770_mc_init(struct radeon_device *rdev)
871 {
872         u32 tmp;
873         int chansize, numchan;
874
875         /* Get VRAM informations */
876         rdev->mc.vram_is_ddr = true;
877         tmp = RREG32(MC_ARB_RAMCFG);
878         if (tmp & CHANSIZE_OVERRIDE) {
879                 chansize = 16;
880         } else if (tmp & CHANSIZE_MASK) {
881                 chansize = 64;
882         } else {
883                 chansize = 32;
884         }
885         tmp = RREG32(MC_SHARED_CHMAP);
886         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
887         case 0:
888         default:
889                 numchan = 1;
890                 break;
891         case 1:
892                 numchan = 2;
893                 break;
894         case 2:
895                 numchan = 4;
896                 break;
897         case 3:
898                 numchan = 8;
899                 break;
900         }
901         rdev->mc.vram_width = numchan * chansize;
902         /* Could aper size report 0 ? */
903         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
904         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
905         /* Setup GPU memory space */
906         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
907         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
908         rdev->mc.visible_vram_size = rdev->mc.aper_size;
909         /* FIXME remove this once we support unmappable VRAM */
910         if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
911                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
912                 rdev->mc.real_vram_size = rdev->mc.aper_size;
913         }
914         r600_vram_gtt_location(rdev, &rdev->mc);
915         radeon_update_bandwidth_info(rdev);
916
917         return 0;
918 }
919
920 int rv770_gpu_reset(struct radeon_device *rdev)
921 {
922         /* FIXME: implement any rv770 specific bits */
923         return r600_gpu_reset(rdev);
924 }
925
926 static int rv770_startup(struct radeon_device *rdev)
927 {
928         int r;
929
930         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
931                 r = r600_init_microcode(rdev);
932                 if (r) {
933                         DRM_ERROR("Failed to load firmware!\n");
934                         return r;
935                 }
936         }
937
938         rv770_mc_program(rdev);
939         if (rdev->flags & RADEON_IS_AGP) {
940                 rv770_agp_enable(rdev);
941         } else {
942                 r = rv770_pcie_gart_enable(rdev);
943                 if (r)
944                         return r;
945         }
946         rv770_gpu_init(rdev);
947         r = r600_blit_init(rdev);
948         if (r) {
949                 r600_blit_fini(rdev);
950                 rdev->asic->copy = NULL;
951                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
952         }
953         /* pin copy shader into vram */
954         if (rdev->r600_blit.shader_obj) {
955                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
956                 if (unlikely(r != 0))
957                         return r;
958                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
959                                 &rdev->r600_blit.shader_gpu_addr);
960                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
961                 if (r) {
962                         DRM_ERROR("failed to pin blit object %d\n", r);
963                         return r;
964                 }
965         }
966         /* Enable IRQ */
967         r = r600_irq_init(rdev);
968         if (r) {
969                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
970                 radeon_irq_kms_fini(rdev);
971                 return r;
972         }
973         r600_irq_set(rdev);
974
975         r = radeon_ring_init(rdev, rdev->cp.ring_size);
976         if (r)
977                 return r;
978         r = rv770_cp_load_microcode(rdev);
979         if (r)
980                 return r;
981         r = r600_cp_resume(rdev);
982         if (r)
983                 return r;
984         /* write back buffer are not vital so don't worry about failure */
985         r600_wb_enable(rdev);
986         return 0;
987 }
988
989 int rv770_resume(struct radeon_device *rdev)
990 {
991         int r;
992
993         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
994          * posting will perform necessary task to bring back GPU into good
995          * shape.
996          */
997         /* post card */
998         atom_asic_init(rdev->mode_info.atom_context);
999         /* Initialize clocks */
1000         r = radeon_clocks_init(rdev);
1001         if (r) {
1002                 return r;
1003         }
1004
1005         r = rv770_startup(rdev);
1006         if (r) {
1007                 DRM_ERROR("r600 startup failed on resume\n");
1008                 return r;
1009         }
1010
1011         r = r600_ib_test(rdev);
1012         if (r) {
1013                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1014                 return r;
1015         }
1016
1017         r = r600_audio_init(rdev);
1018         if (r) {
1019                 dev_err(rdev->dev, "radeon: audio init failed\n");
1020                 return r;
1021         }
1022
1023         return r;
1024
1025 }
1026
1027 int rv770_suspend(struct radeon_device *rdev)
1028 {
1029         int r;
1030
1031         r600_audio_fini(rdev);
1032         /* FIXME: we should wait for ring to be empty */
1033         r700_cp_stop(rdev);
1034         rdev->cp.ready = false;
1035         r600_irq_suspend(rdev);
1036         r600_wb_disable(rdev);
1037         rv770_pcie_gart_disable(rdev);
1038         /* unpin shaders bo */
1039         if (rdev->r600_blit.shader_obj) {
1040                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1041                 if (likely(r == 0)) {
1042                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
1043                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1044                 }
1045         }
1046         return 0;
1047 }
1048
1049 /* Plan is to move initialization in that function and use
1050  * helper function so that radeon_device_init pretty much
1051  * do nothing more than calling asic specific function. This
1052  * should also allow to remove a bunch of callback function
1053  * like vram_info.
1054  */
1055 int rv770_init(struct radeon_device *rdev)
1056 {
1057         int r;
1058
1059         r = radeon_dummy_page_init(rdev);
1060         if (r)
1061                 return r;
1062         /* This don't do much */
1063         r = radeon_gem_init(rdev);
1064         if (r)
1065                 return r;
1066         /* Read BIOS */
1067         if (!radeon_get_bios(rdev)) {
1068                 if (ASIC_IS_AVIVO(rdev))
1069                         return -EINVAL;
1070         }
1071         /* Must be an ATOMBIOS */
1072         if (!rdev->is_atom_bios) {
1073                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1074                 return -EINVAL;
1075         }
1076         r = radeon_atombios_init(rdev);
1077         if (r)
1078                 return r;
1079         /* Post card if necessary */
1080         if (!r600_card_posted(rdev)) {
1081                 if (!rdev->bios) {
1082                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1083                         return -EINVAL;
1084                 }
1085                 DRM_INFO("GPU not posted. posting now...\n");
1086                 atom_asic_init(rdev->mode_info.atom_context);
1087         }
1088         /* Initialize scratch registers */
1089         r600_scratch_init(rdev);
1090         /* Initialize surface registers */
1091         radeon_surface_init(rdev);
1092         /* Initialize clocks */
1093         radeon_get_clock_info(rdev->ddev);
1094         r = radeon_clocks_init(rdev);
1095         if (r)
1096                 return r;
1097         /* Initialize power management */
1098         radeon_pm_init(rdev);
1099         /* Fence driver */
1100         r = radeon_fence_driver_init(rdev);
1101         if (r)
1102                 return r;
1103         /* initialize AGP */
1104         if (rdev->flags & RADEON_IS_AGP) {
1105                 r = radeon_agp_init(rdev);
1106                 if (r)
1107                         radeon_agp_disable(rdev);
1108         }
1109         r = rv770_mc_init(rdev);
1110         if (r)
1111                 return r;
1112         /* Memory manager */
1113         r = radeon_bo_init(rdev);
1114         if (r)
1115                 return r;
1116
1117         r = radeon_irq_kms_init(rdev);
1118         if (r)
1119                 return r;
1120
1121         rdev->cp.ring_obj = NULL;
1122         r600_ring_init(rdev, 1024 * 1024);
1123
1124         rdev->ih.ring_obj = NULL;
1125         r600_ih_ring_init(rdev, 64 * 1024);
1126
1127         r = r600_pcie_gart_init(rdev);
1128         if (r)
1129                 return r;
1130
1131         rdev->accel_working = true;
1132         r = rv770_startup(rdev);
1133         if (r) {
1134                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1135                 r600_cp_fini(rdev);
1136                 r600_wb_fini(rdev);
1137                 r600_irq_fini(rdev);
1138                 radeon_irq_kms_fini(rdev);
1139                 rv770_pcie_gart_fini(rdev);
1140                 rdev->accel_working = false;
1141         }
1142         if (rdev->accel_working) {
1143                 r = radeon_ib_pool_init(rdev);
1144                 if (r) {
1145                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1146                         rdev->accel_working = false;
1147                 } else {
1148                         r = r600_ib_test(rdev);
1149                         if (r) {
1150                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1151                                 rdev->accel_working = false;
1152                         }
1153                 }
1154         }
1155
1156         r = r600_audio_init(rdev);
1157         if (r) {
1158                 dev_err(rdev->dev, "radeon: audio init failed\n");
1159                 return r;
1160         }
1161
1162         return 0;
1163 }
1164
1165 void rv770_fini(struct radeon_device *rdev)
1166 {
1167         radeon_pm_fini(rdev);
1168         r600_blit_fini(rdev);
1169         r600_cp_fini(rdev);
1170         r600_wb_fini(rdev);
1171         r600_irq_fini(rdev);
1172         radeon_irq_kms_fini(rdev);
1173         rv770_pcie_gart_fini(rdev);
1174         radeon_gem_fini(rdev);
1175         radeon_fence_driver_fini(rdev);
1176         radeon_clocks_fini(rdev);
1177         radeon_agp_fini(rdev);
1178         radeon_bo_fini(rdev);
1179         radeon_atombios_fini(rdev);
1180         kfree(rdev->bios);
1181         rdev->bios = NULL;
1182         radeon_dummy_page_fini(rdev);
1183 }