Implement enable/reset of 3D engine
[kernel.git] / drivers / mfd / glamo / glamo-core.c
1 /* Smedia Glamo 336x/337x driver
2  *
3  * (C) 2007 by Openmoko, Inc.
4  * Author: Harald Welte <laforge@openmoko.org>
5  * All rights reserved.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
27 #include <linux/mm.h>
28 #include <linux/tty.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/fb.h>
32 #include <linux/init.h>
33 #include <linux/irq.h>
34 #include <linux/interrupt.h>
35 #include <linux/workqueue.h>
36 #include <linux/wait.h>
37 #include <linux/platform_device.h>
38 #include <linux/kernel_stat.h>
39 #include <linux/spinlock.h>
40 #include <linux/glamofb.h>
41 #include <linux/mmc/mmc.h>
42 #include <linux/mmc/host.h>
43
44 #include <asm/io.h>
45 #include <asm/uaccess.h>
46 #include <asm/div64.h>
47
48 //#include <mach/regs-irq.h>
49
50 #ifdef CONFIG_PM
51 #include <linux/pm.h>
52 #endif
53
54 #include "glamo-regs.h"
55 #include "glamo-core.h"
56
57 #define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
58
59 #define GLAMO_MEM_REFRESH_COUNT 0x100
60
61
62 /*
63  * Glamo internal settings
64  *
65  * We run the memory interface from the faster PLLB on 2.6.28 kernels and
66  * above.  Couple of GTA02 users report trouble with memory bus when they
67  * upgraded from 2.6.24.  So this parameter allows reversion to 2.6.24
68  * scheme if their Glamo chip needs it.
69  *
70  * you can override the faster default on kernel commandline using
71  *
72  *   glamo3362.slow_memory=1
73  *
74  * for example
75  */
76
77 static int slow_memory = 0;
78 module_param(slow_memory, int, 0644);
79
80 struct reg_range {
81         int start;
82         int count;
83         char *name;
84         char dump;
85 };
86 struct reg_range reg_range[] = {
87         { 0x0000, 0x76,         "General",      1 },
88         { 0x0200, 0x16,         "Host Bus",     1 },
89         { 0x0300, 0x38,         "Memory",       1 },
90 /*      { 0x0400, 0x100,        "Sensor",       0 }, */
91 /*              { 0x0500, 0x300,        "ISP",          0 }, */
92 /*              { 0x0800, 0x400,        "JPEG",         0 }, */
93 /*              { 0x0c00, 0xcc,         "MPEG",         0 }, */
94         { 0x1100, 0xb2,         "LCD 1",        1 },
95         { 0x1200, 0x64,         "LCD 2",        1 },
96         { 0x1400, 0x40,         "MMC",          1 },
97 /*              { 0x1500, 0x080,        "MPU 0",        0 },
98         { 0x1580, 0x080,        "MPU 1",        0 },
99         { 0x1600, 0x080,        "Cmd Queue",    0 },
100         { 0x1680, 0x080,        "RISC CPU",     0 },
101         { 0x1700, 0x400,        "2D Unit",      0 },
102         { 0x1b00, 0x900,        "3D Unit",      0 }, */
103 };
104
105 static struct glamo_core *glamo_handle;
106
107 static inline void __reg_write(struct glamo_core *glamo,
108                                 u_int16_t reg, u_int16_t val)
109 {
110         writew(val, glamo->base + reg);
111 }
112
113 static inline u_int16_t __reg_read(struct glamo_core *glamo,
114                                    u_int16_t reg)
115 {
116         return readw(glamo->base + reg);
117 }
118
119 static void __reg_set_bit_mask(struct glamo_core *glamo,
120                                 u_int16_t reg, u_int16_t mask,
121                                 u_int16_t val)
122 {
123         u_int16_t tmp;
124
125         val &= mask;
126
127         tmp = __reg_read(glamo, reg);
128         tmp &= ~mask;
129         tmp |= val;
130         __reg_write(glamo, reg, tmp);
131 }
132
133 static void reg_set_bit_mask(struct glamo_core *glamo,
134                                 u_int16_t reg, u_int16_t mask,
135                                 u_int16_t val)
136 {
137         spin_lock(&glamo->lock);
138         __reg_set_bit_mask(glamo, reg, mask, val);
139         spin_unlock(&glamo->lock);
140 }
141
142 static inline void __reg_set_bit(struct glamo_core *glamo,
143                                  u_int16_t reg, u_int16_t bit)
144 {
145         __reg_set_bit_mask(glamo, reg, bit, 0xffff);
146 }
147
148 static inline void __reg_clear_bit(struct glamo_core *glamo,
149                                    u_int16_t reg, u_int16_t bit)
150 {
151         __reg_set_bit_mask(glamo, reg, bit, 0);
152 }
153
154 static inline void glamo_vmem_write(struct glamo_core *glamo, u_int32_t addr,
155                                     u_int16_t *src, int len)
156 {
157         if (addr & 0x0001 || (unsigned long)src & 0x0001 || len & 0x0001) {
158                 dev_err(&glamo->pdev->dev, "unaligned write(0x%08x, 0x%p, "
159                         "0x%x)!!\n", addr, src, len);
160         }
161
162 }
163
164 static inline void glamo_vmem_read(struct glamo_core *glamo, u_int16_t *buf,
165                                    u_int32_t addr, int len)
166 {
167         if (addr & 0x0001 || (unsigned long) buf & 0x0001 || len & 0x0001) {
168                 dev_err(&glamo->pdev->dev, "unaligned read(0x%p, 0x08%x, "
169                         "0x%x)!!\n", buf, addr, len);
170         }
171
172
173 }
174
175 /***********************************************************************
176  * resources of sibling devices
177  ***********************************************************************/
178 static struct resource glamo_graphics_resources[] = {
179         {
180                 .name   = "glamo-cmdq-regs",
181                 .start  = GLAMO_REGOFS_CMDQUEUE,
182                 .end    = GLAMO_REGOFS_RISC - 1,
183                 .flags  = IORESOURCE_MEM,
184         }, {
185                 .name   = "glamo-command-queue",
186                 .start  = GLAMO_MEM_BASE + GLAMO_OFFSET_CMDQ,
187                 .end    = GLAMO_MEM_BASE + GLAMO_OFFSET_CMDQ +
188                           GLAMO_CMDQ_SIZE - 1,
189                 .flags  = IORESOURCE_MEM,
190         }, {
191                 .name   = "glamo-fb-mem",
192                 .start  = GLAMO_MEM_BASE + GLAMO_OFFSET_FB,
193                 .end    = GLAMO_MEM_BASE + GLAMO_OFFSET_FB +
194                           GLAMO_FB_SIZE - 1,
195                 .flags  = IORESOURCE_MEM,
196         }, {
197                 .name   = "glamo-fb-regs",
198                 .start  = GLAMO_REGOFS_LCD,
199                 .end    = GLAMO_REGOFS_MMC - 1,
200                 .flags  = IORESOURCE_MEM,
201         }, {
202                 .name   = "glamo-2d-regs",
203                 .start  = GLAMO_REGOFS_2D,
204                 .end    = GLAMO_REGOFS_3D- 1,
205                 .flags  = IORESOURCE_MEM,
206         }
207 };
208
209 static struct platform_device glamo_graphics_dev = {
210         .name           = "glamo-fb",
211         .resource       = glamo_graphics_resources,
212         .num_resources  = ARRAY_SIZE(glamo_graphics_resources),
213 };
214
215 static struct platform_device glamo_spigpio_dev = {
216         .name           = "glamo-spi-gpio",
217 };
218
219
220 static struct resource glamo_mmc_resources[] = {
221         {
222                 /* FIXME: those need to be incremented by parent base */
223                 .start  = GLAMO_REGOFS_MMC,
224                 .end    = GLAMO_REGOFS_MPROC0 - 1,
225                 .flags  = IORESOURCE_MEM
226         }, {
227                 .start  = IRQ_GLAMO_MMC,
228                 .end    = IRQ_GLAMO_MMC,
229                 .flags  = IORESOURCE_IRQ,
230         }, { /* our data buffer for MMC transfers */
231                 .start  = GLAMO_MEM_BASE + GLAMO_OFFSET_MMC,
232                 .end    = GLAMO_MEM_BASE + GLAMO_OFFSET_MMC +
233                           GLAMO_MMC_BUFFER_SIZE - 1,
234                 .flags  = IORESOURCE_MEM
235         },
236 };
237
238 struct glamo_mci_pdata glamo_mci_def_pdata = {
239         .gpio_detect            = 0,
240         .glamo_can_set_mci_power        = NULL, /* filled in from MFD platform data */
241         .ocr_avail      = MMC_VDD_20_21 |
242                           MMC_VDD_21_22 |
243                           MMC_VDD_22_23 |
244                           MMC_VDD_23_24 |
245                           MMC_VDD_24_25 |
246                           MMC_VDD_25_26 |
247                           MMC_VDD_26_27 |
248                           MMC_VDD_27_28 |
249                           MMC_VDD_28_29 |
250                           MMC_VDD_29_30 |
251                           MMC_VDD_30_31 |
252                           MMC_VDD_32_33,
253         .glamo_irq_is_wired     = NULL, /* filled in from MFD platform data */
254         .mci_suspending = NULL, /* filled in from MFD platform data */
255         .mci_all_dependencies_resumed = NULL, /* filled in from MFD platform data */
256 };
257 EXPORT_SYMBOL_GPL(glamo_mci_def_pdata);
258
259
260
261 static void mangle_mem_resources(struct resource *res, int num_res,
262                                  struct resource *parent)
263 {
264         int i;
265
266         for (i = 0; i < num_res; i++) {
267                 if (res[i].flags != IORESOURCE_MEM)
268                         continue;
269                 res[i].start += parent->start;
270                 res[i].end += parent->start;
271                 res[i].parent = parent;
272         }
273 }
274
275 /***********************************************************************
276  * IRQ demultiplexer
277  ***********************************************************************/
278 #define irq2glamo(x)    (x - IRQ_GLAMO(0))
279
280 static void glamo_ack_irq(unsigned int irq)
281 {
282         /* clear interrupt source */
283         __reg_write(glamo_handle, GLAMO_REG_IRQ_CLEAR,
284                     1 << irq2glamo(irq));
285 }
286
287 static void glamo_mask_irq(unsigned int irq)
288 {
289         u_int16_t tmp;
290
291         /* clear bit in enable register */
292         tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
293         tmp &= ~(1 << irq2glamo(irq));
294         __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
295 }
296
297 static void glamo_unmask_irq(unsigned int irq)
298 {
299         u_int16_t tmp;
300
301         /* set bit in enable register */
302         tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
303         tmp |= (1 << irq2glamo(irq));
304         __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
305 }
306
307 static struct irq_chip glamo_irq_chip = {
308         .ack    = glamo_ack_irq,
309         .mask   = glamo_mask_irq,
310         .unmask = glamo_unmask_irq,
311 };
312
313 static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
314 {
315         const unsigned int cpu = smp_processor_id();
316
317         desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
318
319         if (unlikely(desc->status & IRQ_INPROGRESS)) {
320                 desc->status |= (IRQ_PENDING | IRQ_MASKED);
321                 desc->chip->mask(irq);
322                 desc->chip->ack(irq);
323                 return;
324         }
325
326         kstat_cpu(cpu).irqs[irq]++;
327         desc->chip->ack(irq);
328         desc->status |= IRQ_INPROGRESS;
329
330         do {
331                 u_int16_t irqstatus;
332                 int i;
333
334                 if (unlikely((desc->status &
335                                 (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
336                                 (IRQ_PENDING | IRQ_MASKED))) {
337                         /* dealing with pending IRQ, unmasking */
338                         desc->chip->unmask(irq);
339                         desc->status &= ~IRQ_MASKED;
340                 }
341
342                 desc->status &= ~IRQ_PENDING;
343
344                 /* read IRQ status register */
345                 irqstatus = __reg_read(glamo_handle, GLAMO_REG_IRQ_STATUS);
346                 for (i = 0; i < 9; i++)
347                         if (irqstatus & (1 << i))
348                                 desc_handle_irq(IRQ_GLAMO(i),
349                                     irq_desc+IRQ_GLAMO(i));
350
351         } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
352
353         desc->status &= ~IRQ_INPROGRESS;
354 }
355
356
357 void glamo_clear_irq(struct glamo_core *glamo, unsigned int irq)
358 {
359         /* set interrupt source */
360         __reg_write(glamo, GLAMO_REG_IRQ_CLEAR, irq);
361 }
362
363
364 void glamo_enable_irq(struct glamo_core *glamo, unsigned int irq)
365 {
366         u_int16_t tmp;
367
368         /* set bit in enable register */
369         tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE);
370         tmp |= irq;
371         __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp);
372 }
373
374
375 static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
376                            const char *buf, size_t count)
377 {
378         unsigned long reg = simple_strtoul(buf, NULL, 10);
379         struct glamo_core *glamo = dev_get_drvdata(dev);
380
381         while (*buf && (*buf != ' '))
382                 buf++;
383         if (*buf != ' ')
384                 return -EINVAL;
385         while (*buf && (*buf == ' '))
386                 buf++;
387         if (!*buf)
388                 return -EINVAL;
389
390         printk(KERN_INFO"reg 0x%02lX <-- 0x%04lX\n",
391                reg, simple_strtoul(buf, NULL, 10));
392
393         __reg_write(glamo, reg, simple_strtoul(buf, NULL, 10));
394
395         return count;
396 }
397
398 static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
399                         char *buf)
400 {
401         struct glamo_core *glamo = dev_get_drvdata(dev);
402         int n, n1 = 0, r;
403         char * end = buf;
404
405         spin_lock(&glamo->lock);
406
407         for (r = 0; r < ARRAY_SIZE(reg_range); r++) {
408                 if (!reg_range[r].dump)
409                         continue;
410                 n1 = 0;
411                 end += sprintf(end, "\n%s\n", reg_range[r].name);
412                 for (n = reg_range[r].start;
413                      n < reg_range[r].start + reg_range[r].count; n += 2) {
414                         if (((n1++) & 7) == 0)
415                                 end += sprintf(end, "\n%04X:  ", n);
416                         end += sprintf(end, "%04x ", __reg_read(glamo, n));
417                 }
418                 end += sprintf(end, "\n");
419                 if (!attr) {
420                         printk("%s", buf);
421                         end = buf;
422                 }
423         }
424         spin_unlock(&glamo->lock);
425
426         return end - buf;
427 }
428
429 static DEVICE_ATTR(regs, 0644, regs_read, regs_write);
430 static struct attribute *glamo_sysfs_entries[] = {
431         &dev_attr_regs.attr,
432         NULL
433 };
434 static struct attribute_group glamo_attr_group = {
435         .name   = NULL,
436         .attrs  = glamo_sysfs_entries,
437 };
438
439
440
441 /***********************************************************************
442  * 'engine' support
443  ***********************************************************************/
444
445 int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
446 {
447         switch (engine) {
448         case GLAMO_ENGINE_LCD:
449                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
450                                    GLAMO_HOSTBUS2_MMIO_EN_LCD,
451                                    GLAMO_HOSTBUS2_MMIO_EN_LCD);
452                 __reg_write(glamo, GLAMO_REG_CLOCK_LCD,
453                             GLAMO_CLOCK_LCD_EN_M5CLK |
454                             GLAMO_CLOCK_LCD_EN_DHCLK |
455                             GLAMO_CLOCK_LCD_EN_DMCLK |
456                             GLAMO_CLOCK_LCD_EN_DCLK |
457                             GLAMO_CLOCK_LCD_DG_M5CLK |
458                             GLAMO_CLOCK_LCD_DG_DMCLK);
459                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
460                             GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
461                             GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
462                             GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0xffff);
463                 break;
464         case GLAMO_ENGINE_MMC:
465                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
466                                    GLAMO_HOSTBUS2_MMIO_EN_MMC,
467                                    GLAMO_HOSTBUS2_MMIO_EN_MMC);
468                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
469                                    GLAMO_CLOCK_MMC_EN_M9CLK |
470                                    GLAMO_CLOCK_MMC_EN_TCLK |
471                                    GLAMO_CLOCK_MMC_DG_M9CLK |
472                                    GLAMO_CLOCK_MMC_DG_TCLK, 0xffff);
473                 /* enable the TCLK divider clk input */
474                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
475                                                  GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
476                                                  GLAMO_CLOCK_GEN51_EN_DIV_TCLK);
477                 break;
478         case GLAMO_ENGINE_2D:
479                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
480                                    GLAMO_CLOCK_2D_EN_M7CLK |
481                                    GLAMO_CLOCK_2D_EN_GCLK |
482                                    GLAMO_CLOCK_2D_DG_M7CLK |
483                                    GLAMO_CLOCK_2D_DG_GCLK, 0xffff);
484                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
485                                    GLAMO_HOSTBUS2_MMIO_EN_2D,
486                                    GLAMO_HOSTBUS2_MMIO_EN_2D);
487                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
488                                    GLAMO_CLOCK_GEN51_EN_DIV_GCLK, 0xffff);
489                 break;
490         case GLAMO_ENGINE_3D:
491                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_3D,
492                                           GLAMO_CLOCK_3D_EN_M8CLK |
493                                           GLAMO_CLOCK_3D_EN_ECLK |
494                                           GLAMO_CLOCK_3D_EN_RCLK |
495                                           GLAMO_CLOCK_3D_DG_M8CLK |
496                                           GLAMO_CLOCK_3D_DG_RCLK |
497                                           GLAMO_CLOCK_3D_DG_ECLK, 0xffff);
498                 /* Enable 3D MMIO */
499                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
500                                           GLAMO_HOSTBUS2_MMIO_EN_3D,
501                                           GLAMO_HOSTBUS2_MMIO_EN_3D);
502                 break;
503         case GLAMO_ENGINE_CMDQ:
504                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
505                                    GLAMO_CLOCK_2D_EN_M6CLK, 0xffff);
506                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
507                                    GLAMO_HOSTBUS2_MMIO_EN_CQ,
508                                    GLAMO_HOSTBUS2_MMIO_EN_CQ);
509                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
510                                    GLAMO_CLOCK_GEN51_EN_DIV_MCLK, 0xffff);
511                 break;
512         /* FIXME: Implementation */
513         default:
514                 break;
515         }
516
517         glamo->engine_enabled_bitfield |= 1 << engine;
518
519         return 0;
520 }
521
522 int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
523 {
524         int ret;
525
526         spin_lock(&glamo->lock);
527
528         ret = __glamo_engine_enable(glamo, engine);
529
530         spin_unlock(&glamo->lock);
531
532         return ret;
533 }
534 EXPORT_SYMBOL_GPL(glamo_engine_enable);
535
536 int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
537 {
538         switch (engine) {
539         case GLAMO_ENGINE_LCD:
540                 /* remove pixel clock to LCM */
541                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
542                             GLAMO_CLOCK_LCD_EN_DCLK, 0);
543                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
544                             GLAMO_CLOCK_LCD_EN_DHCLK |
545                             GLAMO_CLOCK_LCD_EN_DMCLK, 0);
546                 /* kill memory clock */
547                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
548                             GLAMO_CLOCK_LCD_EN_M5CLK, 0);
549                 /* stop dividing the clocks */
550                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
551                             GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
552                             GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
553                             GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0);
554                 break;
555
556         case GLAMO_ENGINE_MMC:
557 //              __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
558 //                                                 GLAMO_CLOCK_MMC_EN_M9CLK |
559 //                                                 GLAMO_CLOCK_MMC_EN_TCLK |
560 //                                                 GLAMO_CLOCK_MMC_DG_M9CLK |
561 //                                                 GLAMO_CLOCK_MMC_DG_TCLK, 0);
562                 /* disable the TCLK divider clk input */
563 //              __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
564 //                                      GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 0);
565
566         default:
567                 break;
568         }
569
570         glamo->engine_enabled_bitfield &= ~(1 << engine);
571
572         return 0;
573 }
574 int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
575 {
576         int ret;
577
578         spin_lock(&glamo->lock);
579
580         ret = __glamo_engine_disable(glamo, engine);
581
582         spin_unlock(&glamo->lock);
583
584         return ret;
585 }
586 EXPORT_SYMBOL_GPL(glamo_engine_disable);
587
588 static const u_int16_t engine_clock_regs[__NUM_GLAMO_ENGINES] = {
589         [GLAMO_ENGINE_LCD]      = GLAMO_REG_CLOCK_LCD,
590         [GLAMO_ENGINE_MMC]      = GLAMO_REG_CLOCK_MMC,
591         [GLAMO_ENGINE_ISP]      = GLAMO_REG_CLOCK_ISP,
592         [GLAMO_ENGINE_JPEG]     = GLAMO_REG_CLOCK_JPEG,
593         [GLAMO_ENGINE_3D]       = GLAMO_REG_CLOCK_3D,
594         [GLAMO_ENGINE_2D]       = GLAMO_REG_CLOCK_2D,
595         [GLAMO_ENGINE_MPEG_ENC] = GLAMO_REG_CLOCK_MPEG,
596         [GLAMO_ENGINE_MPEG_DEC] = GLAMO_REG_CLOCK_MPEG,
597 };
598
599 void glamo_engine_clkreg_set(struct glamo_core *glamo,
600                              enum glamo_engine engine,
601                              u_int16_t mask, u_int16_t val)
602 {
603         reg_set_bit_mask(glamo, engine_clock_regs[engine], mask, val);
604 }
605 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_set);
606
607 u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
608                                   enum glamo_engine engine)
609 {
610         u_int16_t val;
611
612         spin_lock(&glamo->lock);
613         val = __reg_read(glamo, engine_clock_regs[engine]);
614         spin_unlock(&glamo->lock);
615
616         return val;
617 }
618 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get);
619
620 struct glamo_script reset_regs[] = {
621         [GLAMO_ENGINE_LCD] = {
622                 GLAMO_REG_CLOCK_LCD, GLAMO_CLOCK_LCD_RESET
623         },
624 #if 0
625         [GLAMO_ENGINE_HOST] = {
626                 GLAMO_REG_CLOCK_HOST, GLAMO_CLOCK_HOST_RESET
627         },
628         [GLAMO_ENGINE_MEM] = {
629                 GLAMO_REG_CLOCK_MEM, GLAMO_CLOCK_MEM_RESET
630         },
631 #endif
632         [GLAMO_ENGINE_MMC] = {
633                 GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
634         },
635         [GLAMO_ENGINE_2D] = {
636                 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
637         },
638         [GLAMO_ENGINE_3D] = {
639                 GLAMO_REG_CLOCK_3D, GLAMO_CLOCK_3D_BACK_RESET |
640                                     GLAMO_CLOCK_3D_FRONT_RESET
641         },
642         [GLAMO_ENGINE_JPEG] = {
643                 GLAMO_REG_CLOCK_JPEG, GLAMO_CLOCK_JPEG_RESET
644         },
645         /* The following is defined as "Reset command queue", nothing to do
646          * with the 2D engine. */
647         [GLAMO_ENGINE_CMDQ] = {
648                 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_CQ_RESET
649         },
650 };
651
652 void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
653 {
654         struct glamo_script *rst;
655
656         if (engine >= ARRAY_SIZE(reset_regs)) {
657                 dev_warn(&glamo->pdev->dev, "unknown engine %u ", engine);
658                 return;
659         }
660
661         rst = &reset_regs[engine];
662
663         spin_lock(&glamo->lock);
664         __reg_set_bit(glamo, rst->reg, rst->val);
665         __reg_clear_bit(glamo, rst->reg, rst->val);
666         spin_unlock(&glamo->lock);
667 }
668 EXPORT_SYMBOL_GPL(glamo_engine_reset);
669
670 void glamo_lcm_reset(int level)
671 {
672         if (!glamo_handle)
673                 return;
674
675         glamo_gpio_setpin(glamo_handle, GLAMO_GPIO4, level);
676         glamo_gpio_cfgpin(glamo_handle, GLAMO_GPIO4_OUTPUT);
677
678 }
679 EXPORT_SYMBOL_GPL(glamo_lcm_reset);
680
681 enum glamo_pll {
682         GLAMO_PLL1,
683         GLAMO_PLL2,
684 };
685
686 static int glamo_pll_rate(struct glamo_core *glamo,
687                           enum glamo_pll pll)
688 {
689         u_int16_t reg;
690         unsigned int div = 512;
691         /* FIXME: move osci into platform_data */
692         unsigned int osci = 32768;
693
694         if (osci == 32768)
695                 div = 1;
696
697         switch (pll) {
698         case GLAMO_PLL1:
699                 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
700                 break;
701         case GLAMO_PLL2:
702                 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
703                 break;
704         default:
705                 return -EINVAL;
706         }
707         return (osci/div)*reg;
708 }
709
710 int glamo_engine_reclock(struct glamo_core *glamo,
711                          enum glamo_engine engine,
712                          int ps)
713 {
714         int pll, khz;
715         u_int16_t reg, mask, val = 0;
716
717         if (!ps)
718                 return 0;
719
720         switch (engine) {
721         case GLAMO_ENGINE_LCD:
722                 pll = GLAMO_PLL1;
723                 reg = GLAMO_REG_CLOCK_GEN7;
724                 mask = 0xff;
725                 break;
726         default:
727                 dev_warn(&glamo->pdev->dev,
728                          "reclock of engine 0x%x not supported\n", engine);
729                 return -EINVAL;
730                 break;
731         }
732
733         pll = glamo_pll_rate(glamo, pll);
734         khz = 1000000000UL / ps;
735
736         if (khz)
737                 val = (pll / khz) / 1000;
738
739         dev_dbg(&glamo->pdev->dev,
740                         "PLL %d, kHZ %d, div %d\n", pll, khz, val);
741
742         if (val) {
743                 val--;
744                 reg_set_bit_mask(glamo, reg, mask, val);
745                 mdelay(5); /* wait some time to stabilize */
746
747                 return 0;
748         } else {
749                 return -EINVAL;
750         }
751 }
752 EXPORT_SYMBOL_GPL(glamo_engine_reclock);
753
754 /***********************************************************************
755  * script support
756  ***********************************************************************/
757
758 int glamo_run_script(struct glamo_core *glamo, struct glamo_script *script,
759                      int len, int may_sleep)
760 {
761         int i;
762
763         for (i = 0; i < len; i++) {
764                 struct glamo_script *line = &script[i];
765
766                 switch (line->reg) {
767                 case 0xffff:
768                         return 0;
769                 case 0xfffe:
770                         if (may_sleep)
771                                 msleep(line->val);
772                         else
773                                 mdelay(line->val * 4);
774                         break;
775                 case 0xfffd:
776                         /* spin until PLLs lock */
777                         while ((__reg_read(glamo, GLAMO_REG_PLL_GEN5) & 3) != 3)
778                                 ;
779                         break;
780
781                 /*
782                  * couple of people reported artefacts with 2.6.28 changes, this
783                  * allows reversion to 2.6.24 settings
784                  */
785
786                 case 0x200:
787                         switch (slow_memory) {
788                         /* choice 1 is the most conservative */
789                         case 1: /* 3 waits on Async BB R & W, Use PLL 1 for mem bus */
790                                 __reg_write(glamo, script[i].reg, 0xef0);
791                                 break;
792                         case 2: /* 2 waits on Async BB R & W, Use PLL 1 for mem bus */
793                                 __reg_write(glamo, script[i].reg, 0xea0);
794                                 break;
795                         case 3: /* 1 waits on Async BB R & W, Use PLL 1 for mem bus */
796                                 __reg_write(glamo, script[i].reg, 0xe50);
797                                 break;
798                         case 4: /* 0 waits on Async BB R & W, Use PLL 1 for mem bus */
799                                 __reg_write(glamo, script[i].reg, 0xe00);
800                                 break;
801
802                         /* using PLL2 for memory bus increases CPU bandwidth significantly */
803                         case 5: /* 3 waits on Async BB R & W, Use PLL 2 for mem bus */
804                                 __reg_write(glamo, script[i].reg, 0xef3);
805                                 break;
806                         case 6: /* 2 waits on Async BB R & W, Use PLL 2 for mem bus */
807                                 __reg_write(glamo, script[i].reg, 0xea3);
808                                 break;
809                         case 7: /* 1 waits on Async BB R & W, Use PLL 2 for mem bus */
810                                 __reg_write(glamo, script[i].reg, 0xe53);
811                                 break;
812                         /* default of 0 or >7 is fastest */
813                         default: /* 0 waits on Async BB R & W, Use PLL 2 for mem bus */
814                                 __reg_write(glamo, script[i].reg, 0xe03);
815                                 break;
816                         }
817                         break;
818
819                 default:
820                         __reg_write(glamo, script[i].reg, script[i].val);
821                         break;
822                 }
823         }
824
825         return 0;
826 }
827 EXPORT_SYMBOL(glamo_run_script);
828
829 static struct glamo_script glamo_init_script[] = {
830         { GLAMO_REG_CLOCK_HOST,         0x1000 },
831                 { 0xfffe, 2 },
832         { GLAMO_REG_CLOCK_MEMORY,       0x1000 },
833         { GLAMO_REG_CLOCK_MEMORY,       0x2000 },
834         { GLAMO_REG_CLOCK_LCD,          0x1000 },
835         { GLAMO_REG_CLOCK_MMC,          0x1000 },
836         { GLAMO_REG_CLOCK_ISP,          0x1000 },
837         { GLAMO_REG_CLOCK_ISP,          0x3000 },
838         { GLAMO_REG_CLOCK_JPEG,         0x1000 },
839         { GLAMO_REG_CLOCK_3D,           0x1000 },
840         { GLAMO_REG_CLOCK_3D,           0x3000 },
841         { GLAMO_REG_CLOCK_2D,           0x1000 },
842         { GLAMO_REG_CLOCK_2D,           0x3000 },
843         { GLAMO_REG_CLOCK_RISC1,        0x1000 },
844         { GLAMO_REG_CLOCK_MPEG,         0x3000 },
845         { GLAMO_REG_CLOCK_MPEG,         0x3000 },
846         { GLAMO_REG_CLOCK_MPROC,        0x1000 /*0x100f*/ },
847                 { 0xfffe, 2 },
848         { GLAMO_REG_CLOCK_HOST,         0x0000 },
849         { GLAMO_REG_CLOCK_MEMORY,       0x0000 },
850         { GLAMO_REG_CLOCK_LCD,          0x0000 },
851         { GLAMO_REG_CLOCK_MMC,          0x0000 },
852 #if 0
853 /* unused engines must be left in reset to stop MMC block read "blackouts" */
854         { GLAMO_REG_CLOCK_ISP,          0x0000 },
855         { GLAMO_REG_CLOCK_ISP,          0x0000 },
856         { GLAMO_REG_CLOCK_JPEG,         0x0000 },
857         { GLAMO_REG_CLOCK_3D,           0x0000 },
858         { GLAMO_REG_CLOCK_3D,           0x0000 },
859         { GLAMO_REG_CLOCK_2D,           0x0000 },
860         { GLAMO_REG_CLOCK_2D,           0x0000 },
861         { GLAMO_REG_CLOCK_RISC1,        0x0000 },
862         { GLAMO_REG_CLOCK_MPEG,         0x0000 },
863         { GLAMO_REG_CLOCK_MPEG,         0x0000 },
864 #endif
865         { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
866         { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
867         { 0xfffd, 0 },
868         /*
869          * b9 of this register MUST be zero to get any interrupts on INT#
870          * the other set bits enable all the engine interrupt sources
871          */
872         { GLAMO_REG_IRQ_ENABLE,         0x01ff },
873         { GLAMO_REG_CLOCK_GEN6,         0x2000 },
874         { GLAMO_REG_CLOCK_GEN7,         0x0101 },
875         { GLAMO_REG_CLOCK_GEN8,         0x0100 },
876         { GLAMO_REG_CLOCK_HOST,         0x000d },
877         /*
878          * b7..b4 = 0 = no wait states on read or write
879          * b0 = 1 select PLL2 for Host interface, b1 = enable it
880          */
881         { 0x200,        0x0e03 /* this is replaced by script parser */ },
882         { 0x202,        0x07ff },
883         { 0x212,        0x0000 },
884         { 0x214,        0x4000 },
885         { 0x216,        0xf00e },
886
887         /* S-Media recommended "set tiling mode to 512 mode for memory access
888          * more efficiency when 640x480" */
889         { GLAMO_REG_MEM_TYPE,           0x0c74 }, /* 8MB, 16 word pg wr+rd */
890         { GLAMO_REG_MEM_GEN,            0xafaf }, /* 63 grants min + max */
891
892         { GLAMO_REGOFS_HOSTBUS + 2,     0xffff }, /* enable  on MMIO*/
893
894         { GLAMO_REG_MEM_TIMING1,        0x0108 },
895         { GLAMO_REG_MEM_TIMING2,        0x0010 }, /* Taa = 3 MCLK */
896         { GLAMO_REG_MEM_TIMING3,        0x0000 },
897         { GLAMO_REG_MEM_TIMING4,        0x0000 }, /* CE1# delay fall/rise */
898         { GLAMO_REG_MEM_TIMING5,        0x0000 }, /* UB# LB# */
899         { GLAMO_REG_MEM_TIMING6,        0x0000 }, /* OE# */
900         { GLAMO_REG_MEM_TIMING7,        0x0000 }, /* WE# */
901         { GLAMO_REG_MEM_TIMING8,        0x1002 }, /* MCLK delay, was 0x1000 */
902         { GLAMO_REG_MEM_TIMING9,        0x6006 },
903         { GLAMO_REG_MEM_TIMING10,       0x00ff },
904         { GLAMO_REG_MEM_TIMING11,       0x0001 },
905         { GLAMO_REG_MEM_POWER1,         0x0020 },
906         { GLAMO_REG_MEM_POWER2,         0x0000 },
907         { GLAMO_REG_MEM_DRAM1,          0x0000 },
908                 { 0xfffe, 1 },
909         { GLAMO_REG_MEM_DRAM1,          0xc100 },
910                 { 0xfffe, 1 },
911         { GLAMO_REG_MEM_DRAM1,          0xe100 },
912         { GLAMO_REG_MEM_DRAM2,          0x01d6 },
913         { GLAMO_REG_CLOCK_MEMORY,       0x000b },
914         { GLAMO_REG_GPIO_GEN1,          0x000f },
915         { GLAMO_REG_GPIO_GEN2,          0x111e },
916         { GLAMO_REG_GPIO_GEN3,          0xccc3 },
917         { GLAMO_REG_GPIO_GEN4,          0x111e },
918         { GLAMO_REG_GPIO_GEN5,          0x000f },
919 };
920 #if 0
921 static struct glamo_script glamo_resume_script[] = {
922
923         { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
924         { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
925         { GLAMO_REG_DFT_GEN6, 1 },
926                 { 0xfffe, 100 },
927                 { 0xfffd, 0 },
928         { 0x200,        0x0e03 },
929
930         /*
931          * b9 of this register MUST be zero to get any interrupts on INT#
932          * the other set bits enable all the engine interrupt sources
933          */
934         { GLAMO_REG_IRQ_ENABLE,         0x01ff },
935         { GLAMO_REG_CLOCK_HOST,         0x0018 },
936         { GLAMO_REG_CLOCK_GEN5_1, 0x18b1 },
937
938         { GLAMO_REG_MEM_DRAM1,          0x0000 },
939                 { 0xfffe, 1 },
940         { GLAMO_REG_MEM_DRAM1,          0xc100 },
941                 { 0xfffe, 1 },
942         { GLAMO_REG_MEM_DRAM1,          0xe100 },
943         { GLAMO_REG_MEM_DRAM2,          0x01d6 },
944         { GLAMO_REG_CLOCK_MEMORY,       0x000b },
945 };
946 #endif
947
948 enum glamo_power {
949         GLAMO_POWER_ON,
950         GLAMO_POWER_SUSPEND,
951 };
952
953 static void glamo_power(struct glamo_core *glamo,
954                         enum glamo_power new_state)
955 {
956         int n;
957         unsigned long flags;
958
959         spin_lock_irqsave(&glamo->lock, flags);
960
961         dev_info(&glamo->pdev->dev, "***** glamo_power -> %d\n", new_state);
962
963         /*
964 Power management
965 static const REG_VALUE_MASK_TYPE reg_powerOn[] =
966 {
967     { REG_GEN_DFT6,     REG_BIT_ALL,    REG_DATA(1u << 0)           },
968     { REG_GEN_PLL3,     0u,             REG_DATA(1u << 13)          },
969     { REG_GEN_MEM_CLK,  REG_BIT_ALL,    REG_BIT_EN_MOCACLK          },
970     { REG_MEM_DRAM2,    0u,             REG_BIT_EN_DEEP_POWER_DOWN  },
971     { REG_MEM_DRAM1,    0u,             REG_BIT_SELF_REFRESH        }
972 };
973
974 static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
975 {
976     { REG_MEM_DRAM1,    REG_BIT_ALL,    REG_BIT_SELF_REFRESH    },
977     { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK      },
978     { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)      },
979     { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)       }
980 };
981
982 static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
983 {
984     { REG_MEM_DRAM2,    REG_BIT_ALL,    REG_BIT_EN_DEEP_POWER_DOWN  },
985     { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK          },
986     { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)          },
987     { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)           }
988 };
989 */
990
991         switch (new_state) {
992         case GLAMO_POWER_ON:
993
994                 /*
995                  * glamo state on resume is nondeterministic in some
996                  * fundamental way, it has also been observed that the
997                  * Glamo reset pin can get asserted by, eg, touching it with
998                  * a scope probe.  So the only answer is to roll with it and
999                  * force an external reset on the Glamo during resume.
1000                  */
1001
1002                 (glamo->pdata->glamo_external_reset)(0);
1003                 udelay(10);
1004                 (glamo->pdata->glamo_external_reset)(1);
1005                 mdelay(5);
1006
1007                 glamo_run_script(glamo, glamo_init_script,
1008                          ARRAY_SIZE(glamo_init_script), 0);
1009
1010                 break;
1011
1012         case GLAMO_POWER_SUSPEND:
1013
1014                 /* nuke interrupts */
1015                 __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, 0x200);
1016
1017                 /* stash a copy of which engines were running */
1018                 glamo->engine_enabled_bitfield_suspend =
1019                                                  glamo->engine_enabled_bitfield;
1020
1021                 /* take down each engine before we kill mem and pll */
1022                 for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
1023                         if (glamo->engine_enabled_bitfield & (1 << n))
1024                                 __glamo_engine_disable(glamo, n);
1025
1026                 /* enable self-refresh */
1027
1028                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
1029                                         GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
1030                                         GLAMO_MEM_DRAM1_EN_GATE_CKE |
1031                                         GLAMO_MEM_DRAM1_SELF_REFRESH |
1032                                         GLAMO_MEM_REFRESH_COUNT);
1033                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
1034                                         GLAMO_MEM_DRAM1_EN_MODEREG_SET |
1035                                         GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
1036                                         GLAMO_MEM_DRAM1_EN_GATE_CKE |
1037                                         GLAMO_MEM_DRAM1_SELF_REFRESH |
1038                                         GLAMO_MEM_REFRESH_COUNT);
1039
1040                 /* force RAM into deep powerdown */
1041
1042                 __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
1043                                         GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
1044                                         (7 << 6) | /* tRC */
1045                                         (1 << 4) | /* tRP */
1046                                         (1 << 2) | /* tRCD */
1047                                         2); /* CAS latency */
1048
1049                 /* disable clocks to memory */
1050                 __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
1051
1052                 /* all dividers from OSCI */
1053                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0x400, 0x400);
1054
1055                 /* PLL2 into bypass */
1056                 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 12, 1 << 12);
1057
1058                 __reg_write(glamo, 0x200, 0x0e00);
1059
1060
1061                 /* kill PLLS 1 then 2 */
1062                 __reg_write(glamo, GLAMO_REG_DFT_GEN5, 0x0001);
1063                 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 13, 1 << 13);
1064
1065                 break;
1066         }
1067
1068         spin_unlock_irqrestore(&glamo->lock, flags);
1069 }
1070
1071 #if 0
1072 #define MEMDETECT_RETRY 6
1073 static unsigned int detect_memsize(struct glamo_core *glamo)
1074 {
1075         int i;
1076
1077         /*static const u_int16_t pattern[] = {
1078                 0x1111, 0x8a8a, 0x2222, 0x7a7a,
1079                 0x3333, 0x6a6a, 0x4444, 0x5a5a,
1080                 0x5555, 0x4a4a, 0x6666, 0x3a3a,
1081                 0x7777, 0x2a2a, 0x8888, 0x1a1a
1082         }; */
1083
1084         for (i = 0; i < MEMDETECT_RETRY; i++) {
1085                 switch (glamo->type) {
1086                 case 3600:
1087                         __reg_write(glamo, GLAMO_REG_MEM_TYPE, 0x0072);
1088                         __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1089                         break;
1090                 case 3650:
1091                         switch (glamo->revision) {
1092                         case GLAMO_CORE_REV_A0:
1093                                 if (i & 1)
1094                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1095                                                     0x097a);
1096                                 else
1097                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1098                                                     0x0173);
1099
1100                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1101                                 msleep(1);
1102                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1103                                 break;
1104                         default:
1105                                 if (i & 1)
1106                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1107                                                     0x0972);
1108                                 else
1109                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1110                                                     0x0872);
1111
1112                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1113                                 msleep(1);
1114                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xe100);
1115                                 break;
1116                         }
1117                         break;
1118                 case 3700:
1119                         /* FIXME */
1120                 default:
1121                         break;
1122                 }
1123
1124 #if 0
1125                 /* FIXME: finish implementation */
1126                 for (j = 0; j < 8; j++) {
1127                         __
1128 #endif
1129         }
1130
1131         return 0;
1132 }
1133 #endif
1134
1135 /* Find out if we can support this version of the Glamo chip */
1136 static int glamo_supported(struct glamo_core *glamo)
1137 {
1138         u_int16_t dev_id, rev_id; /*, memsize; */
1139
1140         dev_id = __reg_read(glamo, GLAMO_REG_DEVICE_ID);
1141         rev_id = __reg_read(glamo, GLAMO_REG_REVISION_ID);
1142
1143         switch (dev_id) {
1144         case 0x3650:
1145                 switch (rev_id) {
1146                 case GLAMO_CORE_REV_A2:
1147                         break;
1148                 case GLAMO_CORE_REV_A0:
1149                 case GLAMO_CORE_REV_A1:
1150                 case GLAMO_CORE_REV_A3:
1151                         dev_warn(&glamo->pdev->dev, "untested core revision "
1152                                  "%04x, your mileage may vary\n", rev_id);
1153                         break;
1154                 default:
1155                         dev_warn(&glamo->pdev->dev, "unknown glamo revision "
1156                                  "%04x, your mileage may vary\n", rev_id);
1157                         /* maybe should abort ? */
1158                 }
1159                 break;
1160         case 0x3600:
1161         case 0x3700:
1162         default:
1163                 dev_err(&glamo->pdev->dev, "unsupported Glamo device %04x\n",
1164                         dev_id);
1165                 return 0;
1166         }
1167
1168         dev_dbg(&glamo->pdev->dev, "Detected Glamo core %04x Revision %04x "
1169                  "(%uHz CPU / %uHz Memory)\n", dev_id, rev_id,
1170                  glamo_pll_rate(glamo, GLAMO_PLL1),
1171                  glamo_pll_rate(glamo, GLAMO_PLL2));
1172
1173         return 1;
1174 }
1175
1176 static int __init glamo_probe(struct platform_device *pdev)
1177 {
1178         int rc = 0, irq;
1179         struct glamo_core *glamo;
1180         struct platform_device *glamo_mmc_dev;
1181
1182         if (glamo_handle) {
1183                 dev_err(&pdev->dev,
1184                         "This driver supports only one instance\n");
1185                 return -EBUSY;
1186         }
1187
1188         glamo = kmalloc(GFP_KERNEL, sizeof(*glamo));
1189         if (!glamo)
1190                 return -ENOMEM;
1191
1192         spin_lock_init(&glamo->lock);
1193         glamo_handle = glamo;
1194         glamo->pdev = pdev;
1195         glamo->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1196         glamo->irq = platform_get_irq(pdev, 0);
1197         glamo->pdata = pdev->dev.platform_data;
1198         if (!glamo->mem || !glamo->pdata) {
1199                 dev_err(&pdev->dev, "platform device with no MEM/PDATA ?\n");
1200                 rc = -ENOENT;
1201                 goto bail_free;
1202         }
1203
1204         /* register a number of sibling devices whoise IOMEM resources
1205          * are siblings of pdev's IOMEM resource */
1206 #if 0
1207         glamo_core_dev.dev.parent = &pdev.dev;
1208         mangle_mem_resources(glamo_core_dev.resources,
1209                              glamo_core_dev.num_resources, glamo->mem);
1210         glamo_core_dev.resources[1].start = glamo->irq;
1211         glamo_core_dev.resources[1].end = glamo->irq;
1212         platform_device_register(&glamo_core_dev);
1213 #endif
1214         /* only remap the generic, hostbus and memory controller registers */
1215         glamo->base = ioremap(glamo->mem->start, 0x4000 /*GLAMO_REGOFS_VIDCAP*/);
1216         if (!glamo->base) {
1217                 dev_err(&pdev->dev, "failed to ioremap() memory region\n");
1218                 goto bail_free;
1219         }
1220
1221         platform_set_drvdata(pdev, glamo);
1222
1223         (glamo->pdata->glamo_external_reset)(0);
1224         udelay(10);
1225         (glamo->pdata->glamo_external_reset)(1);
1226         mdelay(10);
1227
1228         /*
1229          * finally set the mfd interrupts up
1230          * can't do them earlier or sibling probes blow up
1231          */
1232
1233         for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1234                 set_irq_chip(irq, &glamo_irq_chip);
1235                 set_irq_handler(irq, handle_level_irq);
1236                 set_irq_flags(irq, IRQF_VALID);
1237         }
1238
1239         if (glamo->pdata->glamo_irq_is_wired &&
1240             !glamo->pdata->glamo_irq_is_wired()) {
1241                 set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
1242                 set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING);
1243                 dev_info(&pdev->dev, "Glamo interrupt registered\n");
1244                 glamo->irq_works = 1;
1245         } else {
1246                 dev_err(&pdev->dev, "Glamo interrupt not used\n");
1247                 glamo->irq_works = 0;
1248         }
1249
1250
1251         /* confirm it isn't insane version */
1252         if (!glamo_supported(glamo)) {
1253                 dev_err(&pdev->dev, "This Glamo is not supported\n");
1254                 goto bail_irq;
1255         }
1256
1257         /* sysfs */
1258         rc = sysfs_create_group(&pdev->dev.kobj, &glamo_attr_group);
1259         if (rc < 0) {
1260                 dev_err(&pdev->dev, "cannot create sysfs group\n");
1261                 goto bail_irq;
1262         }
1263
1264         /* init the chip with canned register set */
1265
1266         dev_dbg(&glamo->pdev->dev, "running init script\n");
1267         glamo_run_script(glamo, glamo_init_script,
1268                          ARRAY_SIZE(glamo_init_script), 1);
1269
1270         dev_info(&glamo->pdev->dev, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
1271                  glamo_pll_rate(glamo, GLAMO_PLL1),
1272                  glamo_pll_rate(glamo, GLAMO_PLL2));
1273
1274         /* bring MCI specific stuff over from our MFD platform data */
1275         glamo_mci_def_pdata.glamo_can_set_mci_power =
1276                                         glamo->pdata->glamo_can_set_mci_power;
1277         glamo_mci_def_pdata.glamo_mci_use_slow =
1278                                         glamo->pdata->glamo_mci_use_slow;
1279         glamo_mci_def_pdata.glamo_irq_is_wired =
1280                                         glamo->pdata->glamo_irq_is_wired;
1281
1282         /* start creating the siblings */
1283         glamo->pdata->glamo = glamo;
1284
1285         /* Command queue device (for DRM) */
1286         glamo_graphics_dev.dev.parent = &pdev->dev;
1287         glamo_graphics_dev.dev.platform_data = glamo->pdata;
1288         mangle_mem_resources(glamo_graphics_dev.resource,
1289                              glamo_graphics_dev.num_resources, glamo->mem);
1290         platform_device_register(&glamo_graphics_dev);
1291
1292         /* GPIO */
1293         glamo->pdata->spigpio_info->glamo = glamo;
1294         glamo_spigpio_dev.dev.parent = &pdev->dev;
1295         glamo_spigpio_dev.dev.platform_data = glamo->pdata->spigpio_info;
1296         platform_device_register(&glamo_spigpio_dev);
1297
1298         /* MMC */
1299         glamo_mmc_dev = glamo->pdata->mmc_dev;
1300         glamo_mmc_dev->name = "glamo-mci";
1301         glamo_mmc_dev->dev.parent = &pdev->dev;
1302         glamo_mmc_dev->resource = glamo_mmc_resources;
1303         glamo_mmc_dev->num_resources = ARRAY_SIZE(glamo_mmc_resources);
1304         glamo_mci_def_pdata.pglamo = glamo;
1305         mangle_mem_resources(glamo_mmc_dev->resource,
1306                              glamo_mmc_dev->num_resources, glamo->mem);
1307         platform_device_register(glamo_mmc_dev);
1308
1309         /* Only request the generic, hostbus and memory controller MMIO */
1310         glamo->mem = request_mem_region(glamo->mem->start,
1311                                         GLAMO_REGOFS_VIDCAP, "glamo-core");
1312         if (!glamo->mem) {
1313                 dev_err(&pdev->dev, "failed to request memory region\n");
1314                 goto bail_irq;
1315         }
1316
1317         return 0;
1318
1319 bail_irq:
1320         disable_irq(glamo->irq);
1321         set_irq_chained_handler(glamo->irq, NULL);
1322
1323         for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1324                 set_irq_flags(irq, 0);
1325                 set_irq_chip(irq, NULL);
1326         }
1327
1328         iounmap(glamo->base);
1329 bail_free:
1330         platform_set_drvdata(pdev, NULL);
1331         glamo_handle = NULL;
1332         kfree(glamo);
1333
1334         return rc;
1335 }
1336
1337 static int glamo_remove(struct platform_device *pdev)
1338 {
1339         struct glamo_core *glamo = platform_get_drvdata(pdev);
1340         int irq;
1341
1342         disable_irq(glamo->irq);
1343         set_irq_chained_handler(glamo->irq, NULL);
1344
1345         for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1346                 set_irq_flags(irq, 0);
1347                 set_irq_chip(irq, NULL);
1348         }
1349
1350         platform_set_drvdata(pdev, NULL);
1351         platform_device_unregister(glamo->pdata->mmc_dev);
1352         /* FIXME: Don't we need to unregister these as well?
1353          * platform_device_unregister(glamo->pdata->graphics_dev);
1354          * platform_device_unregister(glamo->pdata->gpio_dev); */
1355         iounmap(glamo->base);
1356         release_mem_region(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
1357         glamo_handle = NULL;
1358         kfree(glamo);
1359
1360         return 0;
1361 }
1362
1363 #ifdef CONFIG_PM
1364
1365 static int glamo_suspend(struct platform_device *pdev, pm_message_t state)
1366 {
1367         glamo_handle->suspending = 1;
1368         glamo_power(glamo_handle, GLAMO_POWER_SUSPEND);
1369
1370         return 0;
1371 }
1372
1373 static int glamo_resume(struct platform_device *pdev)
1374 {
1375         glamo_power(glamo_handle, GLAMO_POWER_ON);
1376         glamo_handle->suspending = 0;
1377
1378         return 0;
1379 }
1380
1381 #else
1382 #define glamo_suspend NULL
1383 #define glamo_resume  NULL
1384 #endif
1385
1386 static struct platform_driver glamo_driver = {
1387         .probe          = glamo_probe,
1388         .remove         = glamo_remove,
1389         .suspend        = glamo_suspend,
1390         .resume = glamo_resume,
1391         .driver         = {
1392                 .name   = "glamo3362",
1393                 .owner  = THIS_MODULE,
1394         },
1395 };
1396
1397 static int __devinit glamo_init(void)
1398 {
1399         return platform_driver_register(&glamo_driver);
1400 }
1401
1402 static void __exit glamo_cleanup(void)
1403 {
1404         platform_driver_unregister(&glamo_driver);
1405 }
1406
1407 module_init(glamo_init);
1408 module_exit(glamo_cleanup);
1409
1410 MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
1411 MODULE_DESCRIPTION("Smedia Glamo 336x/337x core/resource driver");
1412 MODULE_LICENSE("GPL");