1 /* Smedia Glamo 336x/337x driver
3 * (C) 2007 by Openmoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
28 #include <linux/tty.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/irq.h>
34 #include <linux/interrupt.h>
35 #include <linux/workqueue.h>
36 #include <linux/wait.h>
37 #include <linux/platform_device.h>
38 #include <linux/kernel_stat.h>
39 #include <linux/spinlock.h>
40 #include <linux/glamofb.h>
41 #include <linux/mmc/mmc.h>
42 #include <linux/mmc/host.h>
45 #include <asm/uaccess.h>
46 #include <asm/div64.h>
48 //#include <mach/regs-irq.h>
54 #include "glamo-regs.h"
55 #include "glamo-core.h"
57 #define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
59 #define GLAMO_MEM_REFRESH_COUNT 0x100
63 * Glamo internal settings
65 * We run the memory interface from the faster PLLB on 2.6.28 kernels and
66 * above. Couple of GTA02 users report trouble with memory bus when they
67 * upgraded from 2.6.24. So this parameter allows reversion to 2.6.24
68 * scheme if their Glamo chip needs it.
70 * you can override the faster default on kernel commandline using
72 * glamo3362.slow_memory=1
77 static int slow_memory = 0;
78 module_param(slow_memory, int, 0644);
86 struct reg_range reg_range[] = {
87 { 0x0000, 0x76, "General", 1 },
88 { 0x0200, 0x16, "Host Bus", 1 },
89 { 0x0300, 0x38, "Memory", 1 },
90 /* { 0x0400, 0x100, "Sensor", 0 }, */
91 /* { 0x0500, 0x300, "ISP", 0 }, */
92 /* { 0x0800, 0x400, "JPEG", 0 }, */
93 /* { 0x0c00, 0xcc, "MPEG", 0 }, */
94 { 0x1100, 0xb2, "LCD 1", 1 },
95 { 0x1200, 0x64, "LCD 2", 1 },
96 { 0x1400, 0x40, "MMC", 1 },
97 /* { 0x1500, 0x080, "MPU 0", 0 },
98 { 0x1580, 0x080, "MPU 1", 0 },
99 { 0x1600, 0x080, "Cmd Queue", 0 },
100 { 0x1680, 0x080, "RISC CPU", 0 },
101 { 0x1700, 0x400, "2D Unit", 0 },
102 { 0x1b00, 0x900, "3D Unit", 0 }, */
105 static struct glamo_core *glamo_handle;
107 static inline void __reg_write(struct glamo_core *glamo,
108 u_int16_t reg, u_int16_t val)
110 printk(KERN_CRIT "Core %i -> %x\n", val, reg);
111 writew(val, glamo->base + reg);
114 static inline u_int16_t __reg_read(struct glamo_core *glamo,
117 return readw(glamo->base + reg);
120 static void __reg_set_bit_mask(struct glamo_core *glamo,
121 u_int16_t reg, u_int16_t mask,
128 tmp = __reg_read(glamo, reg);
131 __reg_write(glamo, reg, tmp);
134 static void reg_set_bit_mask(struct glamo_core *glamo,
135 u_int16_t reg, u_int16_t mask,
138 spin_lock(&glamo->lock);
139 __reg_set_bit_mask(glamo, reg, mask, val);
140 spin_unlock(&glamo->lock);
143 static inline void __reg_set_bit(struct glamo_core *glamo,
144 u_int16_t reg, u_int16_t bit)
146 __reg_set_bit_mask(glamo, reg, bit, 0xffff);
149 static inline void __reg_clear_bit(struct glamo_core *glamo,
150 u_int16_t reg, u_int16_t bit)
152 __reg_set_bit_mask(glamo, reg, bit, 0);
155 static inline void glamo_vmem_write(struct glamo_core *glamo, u_int32_t addr,
156 u_int16_t *src, int len)
158 if (addr & 0x0001 || (unsigned long)src & 0x0001 || len & 0x0001) {
159 dev_err(&glamo->pdev->dev, "unaligned write(0x%08x, 0x%p, "
160 "0x%x)!!\n", addr, src, len);
165 static inline void glamo_vmem_read(struct glamo_core *glamo, u_int16_t *buf,
166 u_int32_t addr, int len)
168 if (addr & 0x0001 || (unsigned long) buf & 0x0001 || len & 0x0001) {
169 dev_err(&glamo->pdev->dev, "unaligned read(0x%p, 0x08%x, "
170 "0x%x)!!\n", buf, addr, len);
176 /***********************************************************************
177 * resources of sibling devices
178 ***********************************************************************/
179 static struct resource glamo_graphics_resources[] = {
181 .name = "glamo-cmdq-regs",
182 .start = GLAMO_REGOFS_CMDQUEUE,
183 .end = GLAMO_REGOFS_RISC - 1,
184 .flags = IORESOURCE_MEM,
186 .name = "glamo-command-queue",
187 .start = GLAMO_MEM_BASE + GLAMO_OFFSET_CMDQ,
188 .end = GLAMO_MEM_BASE + GLAMO_OFFSET_CMDQ +
190 .flags = IORESOURCE_MEM,
192 .name = "glamo-fb-mem",
193 .start = GLAMO_MEM_BASE + GLAMO_OFFSET_FB,
194 .end = GLAMO_MEM_BASE + GLAMO_OFFSET_FB +
196 .flags = IORESOURCE_MEM,
198 .name = "glamo-fb-regs",
199 .start = GLAMO_REGOFS_LCD,
200 .end = GLAMO_REGOFS_MMC - 1,
201 .flags = IORESOURCE_MEM,
205 static struct platform_device glamo_graphics_dev = {
207 .resource = glamo_graphics_resources,
208 .num_resources = ARRAY_SIZE(glamo_graphics_resources),
211 static struct platform_device glamo_spigpio_dev = {
212 .name = "glamo-spi-gpio",
216 static struct resource glamo_mmc_resources[] = {
218 /* FIXME: those need to be incremented by parent base */
219 .start = GLAMO_REGOFS_MMC,
220 .end = GLAMO_REGOFS_MPROC0 - 1,
221 .flags = IORESOURCE_MEM
223 .start = IRQ_GLAMO_MMC,
224 .end = IRQ_GLAMO_MMC,
225 .flags = IORESOURCE_IRQ,
226 }, { /* our data buffer for MMC transfers */
227 .start = GLAMO_MEM_BASE + GLAMO_OFFSET_MMC,
228 .end = GLAMO_MEM_BASE + GLAMO_OFFSET_MMC +
229 GLAMO_MMC_BUFFER_SIZE - 1,
230 .flags = IORESOURCE_MEM
234 struct glamo_mci_pdata glamo_mci_def_pdata = {
236 .glamo_can_set_mci_power = NULL, /* filled in from MFD platform data */
237 .ocr_avail = MMC_VDD_20_21 |
249 .glamo_irq_is_wired = NULL, /* filled in from MFD platform data */
250 .mci_suspending = NULL, /* filled in from MFD platform data */
251 .mci_all_dependencies_resumed = NULL, /* filled in from MFD platform data */
253 EXPORT_SYMBOL_GPL(glamo_mci_def_pdata);
257 static void mangle_mem_resources(struct resource *res, int num_res,
258 struct resource *parent)
262 for (i = 0; i < num_res; i++) {
263 if (res[i].flags != IORESOURCE_MEM)
265 res[i].start += parent->start;
266 res[i].end += parent->start;
267 res[i].parent = parent;
271 /***********************************************************************
273 ***********************************************************************/
274 #define irq2glamo(x) (x - IRQ_GLAMO(0))
276 static void glamo_ack_irq(unsigned int irq)
278 /* clear interrupt source */
279 __reg_write(glamo_handle, GLAMO_REG_IRQ_CLEAR,
280 1 << irq2glamo(irq));
283 static void glamo_mask_irq(unsigned int irq)
287 /* clear bit in enable register */
288 tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
289 tmp &= ~(1 << irq2glamo(irq));
290 __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
293 static void glamo_unmask_irq(unsigned int irq)
297 /* set bit in enable register */
298 tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
299 tmp |= (1 << irq2glamo(irq));
300 __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
303 static struct irq_chip glamo_irq_chip = {
304 .ack = glamo_ack_irq,
305 .mask = glamo_mask_irq,
306 .unmask = glamo_unmask_irq,
309 static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
311 const unsigned int cpu = smp_processor_id();
313 desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
315 if (unlikely(desc->status & IRQ_INPROGRESS)) {
316 desc->status |= (IRQ_PENDING | IRQ_MASKED);
317 desc->chip->mask(irq);
318 desc->chip->ack(irq);
322 kstat_cpu(cpu).irqs[irq]++;
323 desc->chip->ack(irq);
324 desc->status |= IRQ_INPROGRESS;
330 if (unlikely((desc->status &
331 (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
332 (IRQ_PENDING | IRQ_MASKED))) {
333 /* dealing with pending IRQ, unmasking */
334 desc->chip->unmask(irq);
335 desc->status &= ~IRQ_MASKED;
338 desc->status &= ~IRQ_PENDING;
340 /* read IRQ status register */
341 irqstatus = __reg_read(glamo_handle, GLAMO_REG_IRQ_STATUS);
342 for (i = 0; i < 9; i++)
343 if (irqstatus & (1 << i))
344 desc_handle_irq(IRQ_GLAMO(i),
345 irq_desc+IRQ_GLAMO(i));
347 } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
349 desc->status &= ~IRQ_INPROGRESS;
353 static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
354 const char *buf, size_t count)
356 unsigned long reg = simple_strtoul(buf, NULL, 10);
357 struct glamo_core *glamo = dev_get_drvdata(dev);
359 while (*buf && (*buf != ' '))
363 while (*buf && (*buf == ' '))
368 printk(KERN_INFO"reg 0x%02lX <-- 0x%04lX\n",
369 reg, simple_strtoul(buf, NULL, 10));
371 __reg_write(glamo, reg, simple_strtoul(buf, NULL, 10));
376 static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
379 struct glamo_core *glamo = dev_get_drvdata(dev);
383 spin_lock(&glamo->lock);
385 for (r = 0; r < ARRAY_SIZE(reg_range); r++) {
386 if (!reg_range[r].dump)
389 end += sprintf(end, "\n%s\n", reg_range[r].name);
390 for (n = reg_range[r].start;
391 n < reg_range[r].start + reg_range[r].count; n += 2) {
392 if (((n1++) & 7) == 0)
393 end += sprintf(end, "\n%04X: ", n);
394 end += sprintf(end, "%04x ", __reg_read(glamo, n));
396 end += sprintf(end, "\n");
402 spin_unlock(&glamo->lock);
407 static DEVICE_ATTR(regs, 0644, regs_read, regs_write);
408 static struct attribute *glamo_sysfs_entries[] = {
412 static struct attribute_group glamo_attr_group = {
414 .attrs = glamo_sysfs_entries,
419 /***********************************************************************
421 ***********************************************************************/
423 int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
426 case GLAMO_ENGINE_LCD:
427 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
428 GLAMO_HOSTBUS2_MMIO_EN_LCD,
429 GLAMO_HOSTBUS2_MMIO_EN_LCD);
430 __reg_write(glamo, GLAMO_REG_CLOCK_LCD,
431 GLAMO_CLOCK_LCD_EN_M5CLK |
432 GLAMO_CLOCK_LCD_EN_DHCLK |
433 GLAMO_CLOCK_LCD_EN_DMCLK |
434 GLAMO_CLOCK_LCD_EN_DCLK |
435 GLAMO_CLOCK_LCD_DG_M5CLK |
436 GLAMO_CLOCK_LCD_DG_DMCLK);
437 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
438 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
439 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
440 GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0xffff);
442 case GLAMO_ENGINE_MMC:
443 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
444 GLAMO_HOSTBUS2_MMIO_EN_MMC,
445 GLAMO_HOSTBUS2_MMIO_EN_MMC);
446 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
447 GLAMO_CLOCK_MMC_EN_M9CLK |
448 GLAMO_CLOCK_MMC_EN_TCLK |
449 GLAMO_CLOCK_MMC_DG_M9CLK |
450 GLAMO_CLOCK_MMC_DG_TCLK, 0xffff);
451 /* enable the TCLK divider clk input */
452 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
453 GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
454 GLAMO_CLOCK_GEN51_EN_DIV_TCLK);
456 case GLAMO_ENGINE_2D:
457 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
458 GLAMO_CLOCK_2D_EN_M7CLK |
459 GLAMO_CLOCK_2D_EN_GCLK |
460 GLAMO_CLOCK_2D_DG_M7CLK |
461 GLAMO_CLOCK_2D_DG_GCLK, 0xffff);
462 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
463 GLAMO_HOSTBUS2_MMIO_EN_2D,
464 GLAMO_HOSTBUS2_MMIO_EN_2D);
465 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
466 GLAMO_CLOCK_GEN51_EN_DIV_GCLK, 0xffff);
468 case GLAMO_ENGINE_CMDQ:
469 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
470 GLAMO_CLOCK_2D_EN_M6CLK, 0xffff);
471 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
472 GLAMO_HOSTBUS2_MMIO_EN_CQ,
473 GLAMO_HOSTBUS2_MMIO_EN_CQ);
474 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
475 GLAMO_CLOCK_GEN51_EN_DIV_MCLK, 0xffff);
477 /* FIXME: Implementation */
482 glamo->engine_enabled_bitfield |= 1 << engine;
487 int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
491 spin_lock(&glamo->lock);
493 ret = __glamo_engine_enable(glamo, engine);
495 spin_unlock(&glamo->lock);
499 EXPORT_SYMBOL_GPL(glamo_engine_enable);
501 int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
504 case GLAMO_ENGINE_LCD:
505 /* remove pixel clock to LCM */
506 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
507 GLAMO_CLOCK_LCD_EN_DCLK, 0);
508 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
509 GLAMO_CLOCK_LCD_EN_DHCLK |
510 GLAMO_CLOCK_LCD_EN_DMCLK, 0);
511 /* kill memory clock */
512 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
513 GLAMO_CLOCK_LCD_EN_M5CLK, 0);
514 /* stop dividing the clocks */
515 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
516 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
517 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
518 GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0);
521 case GLAMO_ENGINE_MMC:
522 // __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
523 // GLAMO_CLOCK_MMC_EN_M9CLK |
524 // GLAMO_CLOCK_MMC_EN_TCLK |
525 // GLAMO_CLOCK_MMC_DG_M9CLK |
526 // GLAMO_CLOCK_MMC_DG_TCLK, 0);
527 /* disable the TCLK divider clk input */
528 // __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
529 // GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 0);
535 glamo->engine_enabled_bitfield &= ~(1 << engine);
539 int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
543 spin_lock(&glamo->lock);
545 ret = __glamo_engine_disable(glamo, engine);
547 spin_unlock(&glamo->lock);
551 EXPORT_SYMBOL_GPL(glamo_engine_disable);
553 static const u_int16_t engine_clock_regs[__NUM_GLAMO_ENGINES] = {
554 [GLAMO_ENGINE_LCD] = GLAMO_REG_CLOCK_LCD,
555 [GLAMO_ENGINE_MMC] = GLAMO_REG_CLOCK_MMC,
556 [GLAMO_ENGINE_ISP] = GLAMO_REG_CLOCK_ISP,
557 [GLAMO_ENGINE_JPEG] = GLAMO_REG_CLOCK_JPEG,
558 [GLAMO_ENGINE_3D] = GLAMO_REG_CLOCK_3D,
559 [GLAMO_ENGINE_2D] = GLAMO_REG_CLOCK_2D,
560 [GLAMO_ENGINE_MPEG_ENC] = GLAMO_REG_CLOCK_MPEG,
561 [GLAMO_ENGINE_MPEG_DEC] = GLAMO_REG_CLOCK_MPEG,
564 void glamo_engine_clkreg_set(struct glamo_core *glamo,
565 enum glamo_engine engine,
566 u_int16_t mask, u_int16_t val)
568 reg_set_bit_mask(glamo, engine_clock_regs[engine], mask, val);
570 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_set);
572 u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
573 enum glamo_engine engine)
577 spin_lock(&glamo->lock);
578 val = __reg_read(glamo, engine_clock_regs[engine]);
579 spin_unlock(&glamo->lock);
583 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get);
585 struct glamo_script reset_regs[] = {
586 [GLAMO_ENGINE_LCD] = {
587 GLAMO_REG_CLOCK_LCD, GLAMO_CLOCK_LCD_RESET
590 [GLAMO_ENGINE_HOST] = {
591 GLAMO_REG_CLOCK_HOST, GLAMO_CLOCK_HOST_RESET
593 [GLAMO_ENGINE_MEM] = {
594 GLAMO_REG_CLOCK_MEM, GLAMO_CLOCK_MEM_RESET
597 [GLAMO_ENGINE_MMC] = {
598 GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
600 [GLAMO_ENGINE_2D] = {
601 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
603 [GLAMO_ENGINE_JPEG] = {
604 GLAMO_REG_CLOCK_JPEG, GLAMO_CLOCK_JPEG_RESET
606 /* The following is defined as "Reset command queue", nothing to do
607 * with the 2D engine. */
608 [GLAMO_ENGINE_CMDQ] = {
609 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_CQ_RESET
613 void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
615 struct glamo_script *rst;
617 if (engine >= ARRAY_SIZE(reset_regs)) {
618 dev_warn(&glamo->pdev->dev, "unknown engine %u ", engine);
622 rst = &reset_regs[engine];
624 spin_lock(&glamo->lock);
625 __reg_set_bit(glamo, rst->reg, rst->val);
626 __reg_clear_bit(glamo, rst->reg, rst->val);
627 spin_unlock(&glamo->lock);
629 EXPORT_SYMBOL_GPL(glamo_engine_reset);
631 void glamo_lcm_reset(int level)
636 glamo_gpio_setpin(glamo_handle, GLAMO_GPIO4, level);
637 glamo_gpio_cfgpin(glamo_handle, GLAMO_GPIO4_OUTPUT);
640 EXPORT_SYMBOL_GPL(glamo_lcm_reset);
647 static int glamo_pll_rate(struct glamo_core *glamo,
651 unsigned int div = 512;
652 /* FIXME: move osci into platform_data */
653 unsigned int osci = 32768;
660 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
663 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
668 return (osci/div)*reg;
671 int glamo_engine_reclock(struct glamo_core *glamo,
672 enum glamo_engine engine,
676 u_int16_t reg, mask, val = 0;
682 case GLAMO_ENGINE_LCD:
684 reg = GLAMO_REG_CLOCK_GEN7;
688 dev_warn(&glamo->pdev->dev,
689 "reclock of engine 0x%x not supported\n", engine);
694 pll = glamo_pll_rate(glamo, pll);
695 khz = 1000000000UL / ps;
698 val = (pll / khz) / 1000;
700 dev_dbg(&glamo->pdev->dev,
701 "PLL %d, kHZ %d, div %d\n", pll, khz, val);
705 reg_set_bit_mask(glamo, reg, mask, val);
706 mdelay(5); /* wait some time to stabilize */
713 EXPORT_SYMBOL_GPL(glamo_engine_reclock);
715 /***********************************************************************
717 ***********************************************************************/
719 int glamo_run_script(struct glamo_core *glamo, struct glamo_script *script,
720 int len, int may_sleep)
724 for (i = 0; i < len; i++) {
725 struct glamo_script *line = &script[i];
734 mdelay(line->val * 4);
737 /* spin until PLLs lock */
738 while ((__reg_read(glamo, GLAMO_REG_PLL_GEN5) & 3) != 3)
743 * couple of people reported artefacts with 2.6.28 changes, this
744 * allows reversion to 2.6.24 settings
748 switch (slow_memory) {
749 /* choice 1 is the most conservative */
750 case 1: /* 3 waits on Async BB R & W, Use PLL 1 for mem bus */
751 __reg_write(glamo, script[i].reg, 0xef0);
753 case 2: /* 2 waits on Async BB R & W, Use PLL 1 for mem bus */
754 __reg_write(glamo, script[i].reg, 0xea0);
756 case 3: /* 1 waits on Async BB R & W, Use PLL 1 for mem bus */
757 __reg_write(glamo, script[i].reg, 0xe50);
759 case 4: /* 0 waits on Async BB R & W, Use PLL 1 for mem bus */
760 __reg_write(glamo, script[i].reg, 0xe00);
763 /* using PLL2 for memory bus increases CPU bandwidth significantly */
764 case 5: /* 3 waits on Async BB R & W, Use PLL 2 for mem bus */
765 __reg_write(glamo, script[i].reg, 0xef3);
767 case 6: /* 2 waits on Async BB R & W, Use PLL 2 for mem bus */
768 __reg_write(glamo, script[i].reg, 0xea3);
770 case 7: /* 1 waits on Async BB R & W, Use PLL 2 for mem bus */
771 __reg_write(glamo, script[i].reg, 0xe53);
773 /* default of 0 or >7 is fastest */
774 default: /* 0 waits on Async BB R & W, Use PLL 2 for mem bus */
775 __reg_write(glamo, script[i].reg, 0xe03);
781 __reg_write(glamo, script[i].reg, script[i].val);
788 EXPORT_SYMBOL(glamo_run_script);
790 static struct glamo_script glamo_init_script[] = {
791 { GLAMO_REG_CLOCK_HOST, 0x1000 },
793 { GLAMO_REG_CLOCK_MEMORY, 0x1000 },
794 { GLAMO_REG_CLOCK_MEMORY, 0x2000 },
795 { GLAMO_REG_CLOCK_LCD, 0x1000 },
796 { GLAMO_REG_CLOCK_MMC, 0x1000 },
797 { GLAMO_REG_CLOCK_ISP, 0x1000 },
798 { GLAMO_REG_CLOCK_ISP, 0x3000 },
799 { GLAMO_REG_CLOCK_JPEG, 0x1000 },
800 { GLAMO_REG_CLOCK_3D, 0x1000 },
801 { GLAMO_REG_CLOCK_3D, 0x3000 },
802 { GLAMO_REG_CLOCK_2D, 0x1000 },
803 { GLAMO_REG_CLOCK_2D, 0x3000 },
804 { GLAMO_REG_CLOCK_RISC1, 0x1000 },
805 { GLAMO_REG_CLOCK_MPEG, 0x3000 },
806 { GLAMO_REG_CLOCK_MPEG, 0x3000 },
807 { GLAMO_REG_CLOCK_MPROC, 0x1000 /*0x100f*/ },
809 { GLAMO_REG_CLOCK_HOST, 0x0000 },
810 { GLAMO_REG_CLOCK_MEMORY, 0x0000 },
811 { GLAMO_REG_CLOCK_LCD, 0x0000 },
812 { GLAMO_REG_CLOCK_MMC, 0x0000 },
814 /* unused engines must be left in reset to stop MMC block read "blackouts" */
815 { GLAMO_REG_CLOCK_ISP, 0x0000 },
816 { GLAMO_REG_CLOCK_ISP, 0x0000 },
817 { GLAMO_REG_CLOCK_JPEG, 0x0000 },
818 { GLAMO_REG_CLOCK_3D, 0x0000 },
819 { GLAMO_REG_CLOCK_3D, 0x0000 },
820 { GLAMO_REG_CLOCK_2D, 0x0000 },
821 { GLAMO_REG_CLOCK_2D, 0x0000 },
822 { GLAMO_REG_CLOCK_RISC1, 0x0000 },
823 { GLAMO_REG_CLOCK_MPEG, 0x0000 },
824 { GLAMO_REG_CLOCK_MPEG, 0x0000 },
826 { GLAMO_REG_PLL_GEN1, 0x05db }, /* 48MHz */
827 { GLAMO_REG_PLL_GEN3, 0x0aba }, /* 90MHz */
830 * b9 of this register MUST be zero to get any interrupts on INT#
831 * the other set bits enable all the engine interrupt sources
833 { GLAMO_REG_IRQ_ENABLE, 0x01ff },
834 { GLAMO_REG_CLOCK_GEN6, 0x2000 },
835 { GLAMO_REG_CLOCK_GEN7, 0x0101 },
836 { GLAMO_REG_CLOCK_GEN8, 0x0100 },
837 { GLAMO_REG_CLOCK_HOST, 0x000d },
839 * b7..b4 = 0 = no wait states on read or write
840 * b0 = 1 select PLL2 for Host interface, b1 = enable it
842 { 0x200, 0x0e03 /* this is replaced by script parser */ },
848 /* S-Media recommended "set tiling mode to 512 mode for memory access
849 * more efficiency when 640x480" */
850 { GLAMO_REG_MEM_TYPE, 0x0c74 }, /* 8MB, 16 word pg wr+rd */
851 { GLAMO_REG_MEM_GEN, 0xafaf }, /* 63 grants min + max */
853 { GLAMO_REGOFS_HOSTBUS + 2, 0xffff }, /* enable on MMIO*/
855 { GLAMO_REG_MEM_TIMING1, 0x0108 },
856 { GLAMO_REG_MEM_TIMING2, 0x0010 }, /* Taa = 3 MCLK */
857 { GLAMO_REG_MEM_TIMING3, 0x0000 },
858 { GLAMO_REG_MEM_TIMING4, 0x0000 }, /* CE1# delay fall/rise */
859 { GLAMO_REG_MEM_TIMING5, 0x0000 }, /* UB# LB# */
860 { GLAMO_REG_MEM_TIMING6, 0x0000 }, /* OE# */
861 { GLAMO_REG_MEM_TIMING7, 0x0000 }, /* WE# */
862 { GLAMO_REG_MEM_TIMING8, 0x1002 }, /* MCLK delay, was 0x1000 */
863 { GLAMO_REG_MEM_TIMING9, 0x6006 },
864 { GLAMO_REG_MEM_TIMING10, 0x00ff },
865 { GLAMO_REG_MEM_TIMING11, 0x0001 },
866 { GLAMO_REG_MEM_POWER1, 0x0020 },
867 { GLAMO_REG_MEM_POWER2, 0x0000 },
868 { GLAMO_REG_MEM_DRAM1, 0x0000 },
870 { GLAMO_REG_MEM_DRAM1, 0xc100 },
872 { GLAMO_REG_MEM_DRAM1, 0xe100 },
873 { GLAMO_REG_MEM_DRAM2, 0x01d6 },
874 { GLAMO_REG_CLOCK_MEMORY, 0x000b },
875 { GLAMO_REG_GPIO_GEN1, 0x000f },
876 { GLAMO_REG_GPIO_GEN2, 0x111e },
877 { GLAMO_REG_GPIO_GEN3, 0xccc3 },
878 { GLAMO_REG_GPIO_GEN4, 0x111e },
879 { GLAMO_REG_GPIO_GEN5, 0x000f },
882 static struct glamo_script glamo_resume_script[] = {
884 { GLAMO_REG_PLL_GEN1, 0x05db }, /* 48MHz */
885 { GLAMO_REG_PLL_GEN3, 0x0aba }, /* 90MHz */
886 { GLAMO_REG_DFT_GEN6, 1 },
892 * b9 of this register MUST be zero to get any interrupts on INT#
893 * the other set bits enable all the engine interrupt sources
895 { GLAMO_REG_IRQ_ENABLE, 0x01ff },
896 { GLAMO_REG_CLOCK_HOST, 0x0018 },
897 { GLAMO_REG_CLOCK_GEN5_1, 0x18b1 },
899 { GLAMO_REG_MEM_DRAM1, 0x0000 },
901 { GLAMO_REG_MEM_DRAM1, 0xc100 },
903 { GLAMO_REG_MEM_DRAM1, 0xe100 },
904 { GLAMO_REG_MEM_DRAM2, 0x01d6 },
905 { GLAMO_REG_CLOCK_MEMORY, 0x000b },
914 static void glamo_power(struct glamo_core *glamo,
915 enum glamo_power new_state)
920 spin_lock_irqsave(&glamo->lock, flags);
922 dev_info(&glamo->pdev->dev, "***** glamo_power -> %d\n", new_state);
926 static const REG_VALUE_MASK_TYPE reg_powerOn[] =
928 { REG_GEN_DFT6, REG_BIT_ALL, REG_DATA(1u << 0) },
929 { REG_GEN_PLL3, 0u, REG_DATA(1u << 13) },
930 { REG_GEN_MEM_CLK, REG_BIT_ALL, REG_BIT_EN_MOCACLK },
931 { REG_MEM_DRAM2, 0u, REG_BIT_EN_DEEP_POWER_DOWN },
932 { REG_MEM_DRAM1, 0u, REG_BIT_SELF_REFRESH }
935 static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
937 { REG_MEM_DRAM1, REG_BIT_ALL, REG_BIT_SELF_REFRESH },
938 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
939 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
940 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
943 static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
945 { REG_MEM_DRAM2, REG_BIT_ALL, REG_BIT_EN_DEEP_POWER_DOWN },
946 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
947 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
948 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
956 * glamo state on resume is nondeterministic in some
957 * fundamental way, it has also been observed that the
958 * Glamo reset pin can get asserted by, eg, touching it with
959 * a scope probe. So the only answer is to roll with it and
960 * force an external reset on the Glamo during resume.
963 (glamo->pdata->glamo_external_reset)(0);
965 (glamo->pdata->glamo_external_reset)(1);
968 glamo_run_script(glamo, glamo_init_script,
969 ARRAY_SIZE(glamo_init_script), 0);
973 case GLAMO_POWER_SUSPEND:
975 /* nuke interrupts */
976 __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, 0x200);
978 /* stash a copy of which engines were running */
979 glamo->engine_enabled_bitfield_suspend =
980 glamo->engine_enabled_bitfield;
982 /* take down each engine before we kill mem and pll */
983 for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
984 if (glamo->engine_enabled_bitfield & (1 << n))
985 __glamo_engine_disable(glamo, n);
987 /* enable self-refresh */
989 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
990 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
991 GLAMO_MEM_DRAM1_EN_GATE_CKE |
992 GLAMO_MEM_DRAM1_SELF_REFRESH |
993 GLAMO_MEM_REFRESH_COUNT);
994 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
995 GLAMO_MEM_DRAM1_EN_MODEREG_SET |
996 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
997 GLAMO_MEM_DRAM1_EN_GATE_CKE |
998 GLAMO_MEM_DRAM1_SELF_REFRESH |
999 GLAMO_MEM_REFRESH_COUNT);
1001 /* force RAM into deep powerdown */
1003 __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
1004 GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
1005 (7 << 6) | /* tRC */
1006 (1 << 4) | /* tRP */
1007 (1 << 2) | /* tRCD */
1008 2); /* CAS latency */
1010 /* disable clocks to memory */
1011 __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
1013 /* all dividers from OSCI */
1014 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0x400, 0x400);
1016 /* PLL2 into bypass */
1017 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 12, 1 << 12);
1019 __reg_write(glamo, 0x200, 0x0e00);
1022 /* kill PLLS 1 then 2 */
1023 __reg_write(glamo, GLAMO_REG_DFT_GEN5, 0x0001);
1024 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 13, 1 << 13);
1029 spin_unlock_irqrestore(&glamo->lock, flags);
1033 #define MEMDETECT_RETRY 6
1034 static unsigned int detect_memsize(struct glamo_core *glamo)
1038 /*static const u_int16_t pattern[] = {
1039 0x1111, 0x8a8a, 0x2222, 0x7a7a,
1040 0x3333, 0x6a6a, 0x4444, 0x5a5a,
1041 0x5555, 0x4a4a, 0x6666, 0x3a3a,
1042 0x7777, 0x2a2a, 0x8888, 0x1a1a
1045 for (i = 0; i < MEMDETECT_RETRY; i++) {
1046 switch (glamo->type) {
1048 __reg_write(glamo, GLAMO_REG_MEM_TYPE, 0x0072);
1049 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1052 switch (glamo->revision) {
1053 case GLAMO_CORE_REV_A0:
1055 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1058 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1061 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1063 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1067 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1070 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1073 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1075 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xe100);
1086 /* FIXME: finish implementation */
1087 for (j = 0; j < 8; j++) {
1096 /* Find out if we can support this version of the Glamo chip */
1097 static int glamo_supported(struct glamo_core *glamo)
1099 u_int16_t dev_id, rev_id; /*, memsize; */
1101 dev_id = __reg_read(glamo, GLAMO_REG_DEVICE_ID);
1102 rev_id = __reg_read(glamo, GLAMO_REG_REVISION_ID);
1107 case GLAMO_CORE_REV_A2:
1109 case GLAMO_CORE_REV_A0:
1110 case GLAMO_CORE_REV_A1:
1111 case GLAMO_CORE_REV_A3:
1112 dev_warn(&glamo->pdev->dev, "untested core revision "
1113 "%04x, your mileage may vary\n", rev_id);
1116 dev_warn(&glamo->pdev->dev, "unknown glamo revision "
1117 "%04x, your mileage may vary\n", rev_id);
1118 /* maybe should abort ? */
1124 dev_err(&glamo->pdev->dev, "unsupported Glamo device %04x\n",
1129 dev_dbg(&glamo->pdev->dev, "Detected Glamo core %04x Revision %04x "
1130 "(%uHz CPU / %uHz Memory)\n", dev_id, rev_id,
1131 glamo_pll_rate(glamo, GLAMO_PLL1),
1132 glamo_pll_rate(glamo, GLAMO_PLL2));
1137 static int __init glamo_probe(struct platform_device *pdev)
1140 struct glamo_core *glamo;
1141 struct platform_device *glamo_mmc_dev;
1145 "This driver supports only one instance\n");
1149 glamo = kmalloc(GFP_KERNEL, sizeof(*glamo));
1153 spin_lock_init(&glamo->lock);
1154 glamo_handle = glamo;
1156 glamo->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1157 glamo->irq = platform_get_irq(pdev, 0);
1158 glamo->pdata = pdev->dev.platform_data;
1159 if (!glamo->mem || !glamo->pdata) {
1160 dev_err(&pdev->dev, "platform device with no MEM/PDATA ?\n");
1165 /* register a number of sibling devices whoise IOMEM resources
1166 * are siblings of pdev's IOMEM resource */
1168 glamo_core_dev.dev.parent = &pdev.dev;
1169 mangle_mem_resources(glamo_core_dev.resources,
1170 glamo_core_dev.num_resources, glamo->mem);
1171 glamo_core_dev.resources[1].start = glamo->irq;
1172 glamo_core_dev.resources[1].end = glamo->irq;
1173 platform_device_register(&glamo_core_dev);
1175 /* only remap the generic, hostbus and memory controller registers */
1176 glamo->base = ioremap(glamo->mem->start, 0x4000 /*GLAMO_REGOFS_VIDCAP*/);
1178 dev_err(&pdev->dev, "failed to ioremap() memory region\n");
1182 platform_set_drvdata(pdev, glamo);
1184 (glamo->pdata->glamo_external_reset)(0);
1186 (glamo->pdata->glamo_external_reset)(1);
1190 * finally set the mfd interrupts up
1191 * can't do them earlier or sibling probes blow up
1194 for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1195 set_irq_chip(irq, &glamo_irq_chip);
1196 set_irq_handler(irq, handle_level_irq);
1197 set_irq_flags(irq, IRQF_VALID);
1200 if (glamo->pdata->glamo_irq_is_wired &&
1201 !glamo->pdata->glamo_irq_is_wired()) {
1202 set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
1203 set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING);
1204 dev_info(&pdev->dev, "Glamo interrupt registered\n");
1205 glamo->irq_works = 1;
1207 dev_err(&pdev->dev, "Glamo interrupt not used\n");
1208 glamo->irq_works = 0;
1212 /* confirm it isn't insane version */
1213 if (!glamo_supported(glamo)) {
1214 dev_err(&pdev->dev, "This Glamo is not supported\n");
1219 rc = sysfs_create_group(&pdev->dev.kobj, &glamo_attr_group);
1221 dev_err(&pdev->dev, "cannot create sysfs group\n");
1225 /* init the chip with canned register set */
1227 dev_dbg(&glamo->pdev->dev, "running init script\n");
1228 glamo_run_script(glamo, glamo_init_script,
1229 ARRAY_SIZE(glamo_init_script), 1);
1231 dev_info(&glamo->pdev->dev, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
1232 glamo_pll_rate(glamo, GLAMO_PLL1),
1233 glamo_pll_rate(glamo, GLAMO_PLL2));
1235 /* bring MCI specific stuff over from our MFD platform data */
1236 glamo_mci_def_pdata.glamo_can_set_mci_power =
1237 glamo->pdata->glamo_can_set_mci_power;
1238 glamo_mci_def_pdata.glamo_mci_use_slow =
1239 glamo->pdata->glamo_mci_use_slow;
1240 glamo_mci_def_pdata.glamo_irq_is_wired =
1241 glamo->pdata->glamo_irq_is_wired;
1243 /* start creating the siblings */
1244 glamo->pdata->glamo = glamo;
1246 /* Command queue device (for DRM) */
1247 glamo_graphics_dev.dev.parent = &pdev->dev;
1248 glamo_graphics_dev.dev.platform_data = glamo->pdata;
1249 mangle_mem_resources(glamo_graphics_dev.resource,
1250 glamo_graphics_dev.num_resources, glamo->mem);
1251 platform_device_register(&glamo_graphics_dev);
1254 glamo->pdata->spigpio_info->glamo = glamo;
1255 glamo_spigpio_dev.dev.parent = &pdev->dev;
1256 glamo_spigpio_dev.dev.platform_data = glamo->pdata->spigpio_info;
1257 platform_device_register(&glamo_spigpio_dev);
1260 glamo_mmc_dev = glamo->pdata->mmc_dev;
1261 glamo_mmc_dev->name = "glamo-mci";
1262 glamo_mmc_dev->dev.parent = &pdev->dev;
1263 glamo_mmc_dev->resource = glamo_mmc_resources;
1264 glamo_mmc_dev->num_resources = ARRAY_SIZE(glamo_mmc_resources);
1265 glamo_mci_def_pdata.pglamo = glamo;
1266 mangle_mem_resources(glamo_mmc_dev->resource,
1267 glamo_mmc_dev->num_resources, glamo->mem);
1268 platform_device_register(glamo_mmc_dev);
1270 /* Only request the generic, hostbus and memory controller MMIO */
1271 glamo->mem = request_mem_region(glamo->mem->start,
1272 GLAMO_REGOFS_VIDCAP, "glamo-core");
1274 dev_err(&pdev->dev, "failed to request memory region\n");
1281 disable_irq(glamo->irq);
1282 set_irq_chained_handler(glamo->irq, NULL);
1284 for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1285 set_irq_flags(irq, 0);
1286 set_irq_chip(irq, NULL);
1289 iounmap(glamo->base);
1291 platform_set_drvdata(pdev, NULL);
1292 glamo_handle = NULL;
1298 static int glamo_remove(struct platform_device *pdev)
1300 struct glamo_core *glamo = platform_get_drvdata(pdev);
1303 disable_irq(glamo->irq);
1304 set_irq_chained_handler(glamo->irq, NULL);
1306 for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1307 set_irq_flags(irq, 0);
1308 set_irq_chip(irq, NULL);
1311 platform_set_drvdata(pdev, NULL);
1312 platform_device_unregister(glamo->pdata->mmc_dev);
1313 /* FIXME: Don't we need to unregister these as well?
1314 * platform_device_unregister(glamo->pdata->graphics_dev);
1315 * platform_device_unregister(glamo->pdata->gpio_dev); */
1316 iounmap(glamo->base);
1317 release_mem_region(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
1318 glamo_handle = NULL;
1326 static int glamo_suspend(struct platform_device *pdev, pm_message_t state)
1328 glamo_handle->suspending = 1;
1329 glamo_power(glamo_handle, GLAMO_POWER_SUSPEND);
1334 static int glamo_resume(struct platform_device *pdev)
1336 glamo_power(glamo_handle, GLAMO_POWER_ON);
1337 glamo_handle->suspending = 0;
1343 #define glamo_suspend NULL
1344 #define glamo_resume NULL
1347 static struct platform_driver glamo_driver = {
1348 .probe = glamo_probe,
1349 .remove = glamo_remove,
1350 .suspend = glamo_suspend,
1351 .resume = glamo_resume,
1353 .name = "glamo3362",
1354 .owner = THIS_MODULE,
1358 static int __devinit glamo_init(void)
1360 return platform_driver_register(&glamo_driver);
1363 static void __exit glamo_cleanup(void)
1365 platform_driver_unregister(&glamo_driver);
1368 module_init(glamo_init);
1369 module_exit(glamo_cleanup);
1371 MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
1372 MODULE_DESCRIPTION("Smedia Glamo 336x/337x core/resource driver");
1373 MODULE_LICENSE("GPL");