Set minimum and maximum dimensions in mode config
[kernel.git] / drivers / mfd / glamo / glamo-display.c
1 /*
2  * SMedia Glamo 336x/337x display
3  *
4  * Copyright (C) 2008-2009 Thomas White <taw@bitwiz.org.uk>
5  *
6  * Based on glamo-fb.c (C) 2007-2008 by Openmoko, Inc.
7  * Author: Harald Welte <laforge@openmoko.org>
8  * All rights reserved.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  *
25  *
26  * Based on intel_display.c and intel_crt.c from drivers/gpu/drm/i915
27  *  to which the following licence applies:
28  *
29  * Copyright © 2006-2007 Intel Corporation
30  *
31  * Permission is hereby granted, free of charge, to any person obtaining a
32  * copy of this software and associated documentation files (the "Software"),
33  * to deal in the Software without restriction, including without limitation
34  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
35  * and/or sell copies of the Software, and to permit persons to whom the
36  * Software is furnished to do so, subject to the following conditions:
37  *
38  * The above copyright notice and this permission notice (including the next
39  * paragraph) shall be included in all copies or substantial portions of the
40  * Software.
41  *
42  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
43  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
44  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
45  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
46  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
47  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
48  * DEALINGS IN THE SOFTWARE.
49  *
50  * Authors:
51  *      Eric Anholt <eric@anholt.net>
52  *
53  */
54
55 #define DEBUG 1
56
57 #include <drm/drmP.h>
58 #include <drm/glamo_drm.h>
59 #include <drm/drm_crtc_helper.h>
60 #include <drm/drm_crtc.h>
61
62 #include "glamo-core.h"
63 #include "glamo-drm-private.h"
64 #include "glamo-regs.h"
65 #include "glamo-kms-fb.h"
66 #include <linux/glamofb.h>
67
68
69 #define GLAMO_LCD_WIDTH_MASK 0x03FF
70 #define GLAMO_LCD_HEIGHT_MASK 0x03FF
71 #define GLAMO_LCD_PITCH_MASK 0x07FE
72 #define GLAMO_LCD_HV_TOTAL_MASK 0x03FF
73 #define GLAMO_LCD_HV_RETR_START_MASK 0x03FF
74 #define GLAMO_LCD_HV_RETR_END_MASK 0x03FF
75 #define GLAMO_LCD_HV_RETR_DISP_START_MASK 0x03FF
76 #define GLAMO_LCD_HV_RETR_DISP_END_MASK 0x03FF
77
78
79 struct glamofb_par {
80         struct drm_device *dev;
81         struct drm_display_mode *our_mode;
82         struct glamo_framebuffer *glamo_fb;
83         int crtc_count;
84         /* crtc currently bound to this */
85         uint32_t crtc_ids[2];
86 };
87
88
89 static int reg_read_lcd(struct glamodrm_handle *gdrm, u_int16_t reg)
90 {
91         int i = 0;
92
93         for (i = 0; i != 2; i++)
94                 nop();
95
96         return ioread16(gdrm->lcd_base + reg);
97 }
98
99
100 static void reg_write_lcd(struct glamodrm_handle *gdrm,
101                           u_int16_t reg, u_int16_t val)
102 {
103         int i = 0;
104
105         for (i = 0; i != 2; i++)
106                 nop();
107
108         iowrite16(val, gdrm->lcd_base + reg);
109 }
110
111
112 static void reg_set_bit_mask_lcd(struct glamodrm_handle *gdrm,
113                                  u_int16_t reg, u_int16_t mask,
114                                  u_int16_t val)
115 {
116         u_int16_t tmp;
117
118         val &= mask;
119
120         tmp = reg_read_lcd(gdrm, reg);
121         tmp &= ~mask;
122         tmp |= val;
123         reg_write_lcd(gdrm, reg, tmp);
124 }
125
126
127 /* Note that this has nothing at all to do with the engine command queue
128  * in glamo-cmdq.c */
129 static inline int glamo_lcd_cmdq_empty(struct glamodrm_handle *gdrm)
130 {
131         /* DGCMdQempty -- 1 == command queue is empty */
132         return reg_read_lcd(gdrm, GLAMO_REG_LCD_STATUS1) & (1 << 15);
133 }
134
135
136 /* call holding gfb->lock_cmd  when locking, until you unlock */
137 int glamo_lcd_cmd_mode(struct glamodrm_handle *gdrm, int on)
138 {
139         int timeout = 2000000;
140
141         if (gdrm->glamo_core->suspending) {
142                 dev_err(&gdrm->glamo_core->pdev->dev,
143                                 "IGNORING glamofb_cmd_mode while"
144                                 " suspended\n");
145                 return -EBUSY;
146         }
147
148         dev_dbg(gdrm->dev, "glamofb_cmd_mode(on=%d)\n", on);
149         if (on) {
150
151                 while ((!glamo_lcd_cmdq_empty(gdrm)) && (timeout--))
152                         /* yield() */;
153                 if (timeout < 0) {
154                         printk(KERN_ERR "*************"
155                                         " LCD command queue never got empty "
156                                         "*************\n");
157                         return -EIO;
158                 }
159
160                 /* display the entire frame then switch to command */
161                 reg_write_lcd(gdrm, GLAMO_REG_LCD_COMMAND1,
162                           GLAMO_LCD_CMD_TYPE_DISP |
163                           GLAMO_LCD_CMD_DATA_FIRE_VSYNC);
164
165                 /* wait until lcd idle */
166                 timeout = 2000000;
167                 while ((!reg_read_lcd(gdrm, GLAMO_REG_LCD_STATUS2) & (1 << 12))
168                           && (timeout--))
169                         /* yield() */;
170                 if (timeout < 0) {
171                         printk(KERN_ERR"*************"
172                                        " LCD never idle "
173                                        "*************\n");
174                         return -EIO;
175                 }
176
177                 mdelay(100);
178
179         } else {
180                 /* RGB interface needs vsync/hsync */
181                 int mode;
182                 mode = reg_read_lcd(gdrm, GLAMO_REG_LCD_MODE3);
183                 if ( mode & GLAMO_LCD_MODE3_RGB)
184                         reg_write_lcd(gdrm, GLAMO_REG_LCD_COMMAND1,
185                                   GLAMO_LCD_CMD_TYPE_DISP |
186                                   GLAMO_LCD_CMD_DATA_DISP_SYNC);
187
188                 reg_write_lcd(gdrm, GLAMO_REG_LCD_COMMAND1,
189                           GLAMO_LCD_CMD_TYPE_DISP |
190                           GLAMO_LCD_CMD_DATA_DISP_FIRE);
191         }
192
193         return 0;
194 }
195
196
197 static struct glamo_script lcd_init_script[] = {
198         { GLAMO_REG_LCD_MODE1, 0x0020 },
199         /* no display rotation, no hardware cursor, no dither, no gamma,
200          * no retrace flip, vsync low-active, hsync low active,
201          * no TVCLK, no partial display, hw dest color from fb,
202          * no partial display mode, LCD1, software flip,  */
203         { GLAMO_REG_LCD_MODE2, 0x9020 },
204           /* video flip, no ptr, no ptr, dhclk off,
205            * normal mode,  no cpuif,
206            * res, serial msb first, single fb, no fr ctrl,
207            * cpu if bits all zero, no crc
208            * 0000 0000 0010  0000 */
209         { GLAMO_REG_LCD_MODE3, 0x0b40 },
210           /* src data rgb565, res, 18bit rgb666
211            * 000 01 011 0100 0000 */
212         { GLAMO_REG_LCD_POLARITY, 0x440c },
213           /* DE high active, no cpu/lcd if, cs0 force low, a0 low active,
214            * np cpu if, 9bit serial data, sclk rising edge latch data
215            * 01 00 0 100 0 000 01 0 0 */
216         /* The following values assume 640*480@16bpp */
217         { GLAMO_REG_LCD_A_BASE1, 0x0000 }, /* display A base address 15:0 */
218         { GLAMO_REG_LCD_A_BASE2, 0x0000 }, /* display A base address 22:16 */
219         { GLAMO_REG_LCD_B_BASE1, 0x6000 }, /* display B base address 15:0 */
220         { GLAMO_REG_LCD_B_BASE2, 0x0009 }, /* display B base address 22:16 */
221         { GLAMO_REG_LCD_CURSOR_BASE1, 0xC000 }, /* cursor base address 15:0 */
222         { GLAMO_REG_LCD_CURSOR_BASE2, 0x0012 }, /* cursor base address 22:16 */
223         { GLAMO_REG_LCD_COMMAND2, 0x0000 }, /* display page A */
224 };
225
226
227 static int glamo_run_lcd_script(struct glamodrm_handle *gdrm,
228                                 struct glamo_script *script, int len)
229 {
230         int i;
231
232         for (i = 0; i < len; i++) {
233                 struct glamo_script *line = &script[i];
234
235                 if (line->reg == 0xffff)
236                         return 0;
237                 else if (line->reg == 0xfffe)
238                         msleep(line->val);
239                 else
240                         reg_write_lcd(gdrm, script[i].reg, script[i].val);
241         }
242
243         return 0;
244 }
245
246
247 #if 0
248 static void notify_blank(struct drm_crtc *crtc, int mode)
249 {
250         struct fb_event event;
251
252         event.info = info;
253         event.data = &blank_mode;
254         fb_notifier_call_chain(FB_EVENT_CONBLANK, &event);
255 }
256 #endif
257
258
259 extern void jbt6k74_action(int val);
260
261
262 /* Power on/off */
263 static void glamo_crtc_dpms(struct drm_crtc *crtc, int mode)
264 {
265         struct glamodrm_handle *gdrm;
266         struct glamo_crtc *glamo_crtc = to_glamo_crtc(crtc);
267
268         printk(KERN_CRIT "glamo_crtc_dpms(%u)\n", mode);
269         gdrm = glamo_crtc->gdrm;
270
271         switch (mode) {
272         case DRM_MODE_DPMS_OFF:
273                 /* LCM need notification before pixel clock is stopped */
274                 jbt6k74_action(0);
275
276                 /* disable the pixel clock */
277                 glamo_engine_clkreg_set(gdrm->glamo_core, GLAMO_ENGINE_LCD,
278                                         GLAMO_CLOCK_LCD_EN_DCLK, 0);
279                 glamo_crtc->blank_mode = mode;
280                 break;
281         case DRM_MODE_DPMS_ON:
282                 /* enable the pixel clock if off */
283                 if (glamo_crtc->blank_mode == DRM_MODE_DPMS_OFF)
284                         glamo_engine_clkreg_set(gdrm->glamo_core,
285                                                 GLAMO_ENGINE_LCD,
286                                                 GLAMO_CLOCK_LCD_EN_DCLK,
287                                                 GLAMO_CLOCK_LCD_EN_DCLK);
288                 jbt6k74_action(1);
289                 glamo_crtc->blank_mode = mode;
290                 break;
291         }
292 }
293
294
295 static bool glamo_crtc_mode_fixup(struct drm_crtc *crtc,
296                                   struct drm_display_mode *mode,
297                                   struct drm_display_mode *adjusted_mode)
298 {
299         printk(KERN_CRIT "glamo_crtc_mode_fixup\n");
300         return true;
301 }
302
303
304 static void glamo_crtc_mode_set(struct drm_crtc *crtc,
305                                 struct drm_display_mode *mode,
306                                 struct drm_display_mode *adjusted_mode,
307                                 int x, int y,
308                                 struct drm_framebuffer *old_fb)
309 {
310         struct glamodrm_handle *gdrm;
311         struct glamo_crtc *gcrtc;
312         int retr_start, retr_end, disp_start, disp_end;
313         int ps;
314
315         printk(KERN_CRIT "glamo_crtc_mode_set\n");
316
317         /* Dig out our handle */
318         gcrtc = to_glamo_crtc(crtc);
319         gdrm = gcrtc->gdrm;     /* Here it is! */
320
321         glamo_lcd_cmd_mode(gdrm, 1);
322         ps = mode->clock / 1000;        /* Hz -> kHz */
323         ps = 1000000000UL / ps;         /* kHz -> ps */
324         printk(KERN_INFO "[glamo-drm] Reclocking LCD engine to %i ps\n", ps);
325         glamo_engine_reclock(gdrm->glamo_core, GLAMO_ENGINE_LCD, ps);
326         gdrm->saved_clock = ps;
327
328         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_WIDTH,
329                              GLAMO_LCD_WIDTH_MASK, mode->hdisplay);
330         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HEIGHT,
331                              GLAMO_LCD_HEIGHT_MASK, mode->vdisplay);
332         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_PITCH,
333                              GLAMO_LCD_PITCH_MASK, mode->hdisplay*2);
334
335         /* Convert "X modeline timings" into "Glamo timings" */
336         retr_start = 0;
337         retr_end = retr_start + mode->hsync_end - mode->hsync_start;
338         disp_start = mode->htotal - mode->hsync_start;
339         disp_end = disp_start + mode->hdisplay;
340         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_TOTAL,
341                              GLAMO_LCD_HV_TOTAL_MASK, mode->htotal);
342         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_START,
343                              GLAMO_LCD_HV_RETR_START_MASK, retr_start);
344         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_END,
345                              GLAMO_LCD_HV_RETR_END_MASK, retr_end);
346         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_START,
347                              GLAMO_LCD_HV_RETR_DISP_START_MASK, disp_start);
348         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_END,
349                              GLAMO_LCD_HV_RETR_DISP_END_MASK, disp_end);
350
351         /* The same in the vertical direction */
352         retr_start = 0;
353         retr_end = retr_start + mode->vsync_end - mode->vsync_start;
354         disp_start = mode->vtotal - mode->vsync_start;
355         disp_end = disp_start + mode->vdisplay;
356         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_TOTAL,
357                              GLAMO_LCD_HV_TOTAL_MASK, mode->vtotal);
358         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_START,
359                              GLAMO_LCD_HV_RETR_START_MASK, retr_start);
360         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_END,
361                              GLAMO_LCD_HV_RETR_END_MASK, retr_end);
362         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_START,
363                              GLAMO_LCD_HV_RETR_DISP_START_MASK, disp_start);
364         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_END,
365                              GLAMO_LCD_HV_RETR_DISP_END_MASK, disp_end);
366
367         glamo_lcd_cmd_mode(gdrm, 0);
368 }
369
370
371 static void glamo_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
372                                      struct drm_framebuffer *old_fb)
373 {
374         printk(KERN_CRIT "glamo_crtc_mode_set_base\n");
375 }
376
377
378 static void glamo_crtc_prepare(struct drm_crtc *crtc)
379 {
380         printk(KERN_CRIT "glamo_crtc_prepare\n");
381 }
382
383
384 static void glamo_crtc_commit(struct drm_crtc *crtc)
385 {
386         printk(KERN_CRIT "glamo_crtc_commit\n");
387 }
388
389
390 static int glamo_crtc_cursor_set(struct drm_crtc *crtc,
391                                  struct drm_file *file_priv,
392                                  uint32_t handle,
393                                  uint32_t width, uint32_t height)
394 {
395         printk(KERN_CRIT "glamo_crtc_cursor_set\n");
396         return 0;
397 }
398
399
400 static int glamo_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
401 {
402         printk(KERN_CRIT "glamo_crtc_cursor_move\n");
403         return 0;
404 }
405
406
407 static void glamo_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
408                                  u16 *blue, uint32_t size)
409 {
410         printk(KERN_CRIT "glamo_crtc_gamma_set\n");
411 }
412
413
414 static void glamo_crtc_destroy(struct drm_crtc *crtc)
415 {
416         struct glamo_crtc *glamo_crtc = to_glamo_crtc(crtc);
417         printk(KERN_CRIT "glamo_crtc_destroy\n");
418         drm_crtc_cleanup(crtc);
419         kfree(glamo_crtc);
420 }
421
422
423 static enum drm_connector_status
424 glamo_connector_detect(struct drm_connector *connector)
425 {
426         /* One hopes it hasn't been de-soldered... */
427         printk(KERN_CRIT "glamo_connector_detect\n");
428         return connector_status_connected;
429 }
430
431
432 static void glamo_connector_destroy(struct drm_connector *connector)
433 {
434         printk(KERN_CRIT "glamo_connector_destroy\n");
435         drm_sysfs_connector_remove(connector);
436         drm_connector_cleanup(connector);
437         kfree(connector);
438 }
439
440
441 static int glamo_connector_get_modes(struct drm_connector *connector)
442 {
443         struct drm_display_mode *mode;
444         struct glamofb_platform_data *mach_info;
445         struct glamo_output *goutput = to_glamo_output(connector);
446         struct glamodrm_handle *gdrm = goutput->gdrm;
447
448         /* Dig out the record which will tell us about the hardware */
449         mach_info = gdrm->glamo_core->pdev->dev.platform_data;
450
451         printk(KERN_CRIT "glamo_connector_get_modes\n");
452
453         mode = drm_mode_create(connector->dev);
454         if (!mode)
455                 return 0;
456         /* Fill in 'mode' here */
457         mode->type = DRM_MODE_TYPE_DEFAULT | DRM_MODE_TYPE_PREFERRED;
458
459         /* Convert framebuffer timings into KMS timings */
460         mode->clock = 1000000000UL / mach_info->pixclock;       /* ps -> kHz */
461         mode->clock *= 1000;    /* kHz -> Hz */
462         mode->hdisplay = mach_info->xres.defval;
463         mode->hsync_start = mach_info->right_margin + mode->hdisplay;
464         mode->hsync_end = mode->hsync_start + mach_info->hsync_len;
465         mode->htotal = mode->hsync_end + mach_info->left_margin;
466         mode->hskew = 0;
467
468         mode->vdisplay = mach_info->yres.defval;
469         mode->vsync_start = mach_info->lower_margin + mode->vdisplay;
470         mode->vsync_end = mode->vsync_start + mach_info->vsync_len;
471         mode->vtotal = mode->vsync_end + mach_info->upper_margin;
472         mode->vscan = 0;
473
474         mode->width_mm = mach_info->width;
475         mode->height_mm = mach_info->height;
476
477         printk(KERN_CRIT "Modeline \"%ix%i\" %i   %i %i %i %i    %i %i %i %i\n",
478                mode->hdisplay, mode->vdisplay, mode->clock,
479                mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
480                mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal);
481
482         drm_mode_set_name(mode);
483         drm_mode_probed_add(connector, mode);
484
485         return 1;       /* one mode, for now */
486 }
487
488
489 static int glamo_connector_set_property(struct drm_connector *connector,
490                                   struct drm_property *property,
491                                   uint64_t value)
492 {
493         printk(KERN_CRIT "glamo_connector_set_property\n");
494         return 0;
495 }
496
497
498 static int glamo_connector_mode_valid(struct drm_connector *connector,
499                                       struct drm_display_mode *mode)
500 {
501         printk(KERN_CRIT "glamo_connector_mode_valid\n");
502         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
503                 return MODE_NO_DBLESCAN;
504
505         return MODE_OK;
506 }
507
508
509 struct drm_encoder *
510 glamo_connector_best_encoder(struct drm_connector *connector)
511 {
512         struct glamo_output *glamo_output = to_glamo_output(connector);
513         printk(KERN_CRIT "glamo_connector_best_encoder\n");
514         return &glamo_output->enc;
515 }
516
517
518 static void glamo_encoder_dpms(struct drm_encoder *encoder, int mode)
519 {
520         printk(KERN_CRIT "glamo_encoder_dpms\n");
521 }
522
523
524 static bool glamo_encoder_mode_fixup(struct drm_encoder *encoder,
525                                  struct drm_display_mode *mode,
526                                  struct drm_display_mode *adjusted_mode)
527 {
528         printk(KERN_CRIT "glamo_encoder_mode_fixup\n");
529         return true;
530 }
531
532
533 void glamo_encoder_prepare(struct drm_encoder *encoder)
534 {
535         printk(KERN_CRIT "glamo_encoder_prepare\n");
536 }
537
538
539 void glamo_encoder_commit(struct drm_encoder *encoder)
540 {
541         printk(KERN_CRIT "glamo_encoder_commit\n");
542 }
543
544
545 static void glamo_encoder_mode_set(struct drm_encoder *encoder,
546                                struct drm_display_mode *mode,
547                                struct drm_display_mode *adjusted_mode)
548 {
549         printk(KERN_CRIT "glamo_encoder_mode_set\n");
550 }
551
552
553 static void glamo_encoder_destroy(struct drm_encoder *encoder)
554 {
555         printk(KERN_CRIT "glamo_encoder_destroy\n");
556         drm_encoder_cleanup(encoder);
557 }
558
559
560 static void glamo_framebuffer_destroy(struct drm_framebuffer *fb)
561 {
562         struct glamo_framebuffer *glamo_fb = to_glamo_framebuffer(fb);
563         struct drm_device *dev = fb->dev;
564         printk(KERN_CRIT "glamo_user_framebuffer_destroy\n");
565
566         drm_framebuffer_cleanup(fb);
567         mutex_lock(&dev->struct_mutex);
568         drm_gem_object_unreference(glamo_fb->obj);
569         mutex_unlock(&dev->struct_mutex);
570
571         kfree(glamo_fb);
572 }
573
574 static int glamo_framebuffer_create_handle(struct drm_framebuffer *fb,
575                                                 struct drm_file *file_priv,
576                                                 unsigned int *handle)
577 {
578         struct glamo_framebuffer *glamo_fb = to_glamo_framebuffer(fb);
579         struct drm_gem_object *object = glamo_fb->obj;
580         printk(KERN_CRIT "glamo_user_framebuffer_create_handle\n");
581
582         return drm_gem_handle_create(file_priv, object, handle);
583 }
584
585
586 static const struct drm_framebuffer_funcs glamo_fb_funcs = {
587         .destroy = glamo_framebuffer_destroy,
588         .create_handle = glamo_framebuffer_create_handle,
589 };
590
591
592 int glamo_framebuffer_create(struct drm_device *dev,
593                              struct drm_mode_fb_cmd *mode_cmd,
594                              struct drm_framebuffer **fb,
595                              struct drm_gem_object *obj)
596 {
597         struct glamo_framebuffer *glamo_fb;
598         int ret;
599
600         printk(KERN_CRIT "glamo_framebuffer_create\n");
601         glamo_fb = kzalloc(sizeof(*glamo_fb), GFP_KERNEL);
602         if (!glamo_fb)
603                 return -ENOMEM;
604
605         ret = drm_framebuffer_init(dev, &glamo_fb->base, &glamo_fb_funcs);
606         if (ret) {
607                 DRM_ERROR("framebuffer init failed %d\n", ret);
608                 return ret;
609         }
610
611         drm_helper_mode_fill_fb_struct(&glamo_fb->base, mode_cmd);
612
613         glamo_fb->obj = obj;
614
615         *fb = &glamo_fb->base;
616
617         return 0;
618 }
619
620
621 static struct drm_framebuffer *
622 glamo_user_framebuffer_create(struct drm_device *dev,
623                               struct drm_file *filp,
624                               struct drm_mode_fb_cmd *mode_cmd)
625 {
626         struct drm_gem_object *obj;
627         struct drm_framebuffer *fb;
628         int ret;
629         printk(KERN_CRIT "glamo_user_framebuffer_create\n");
630
631         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
632         if (!obj)
633                 return NULL;
634
635         ret = glamo_framebuffer_create(dev, mode_cmd, &fb, obj);
636         if (ret) {
637                 drm_gem_object_unreference(obj);
638                 return NULL;
639         }
640
641         return fb;
642 }
643
644
645 int glamo_fbchanged(struct drm_device *dev)
646 {
647         printk(KERN_CRIT "glamo_fb_changed\n");
648         return 0;
649 }
650
651
652 /* CRTC functions */
653 static const struct drm_crtc_funcs glamo_crtc_funcs = {
654         .cursor_set = glamo_crtc_cursor_set,
655         .cursor_move = glamo_crtc_cursor_move,
656         .gamma_set = glamo_crtc_gamma_set,
657         .set_config = drm_crtc_helper_set_config,
658         .destroy = glamo_crtc_destroy,
659 };
660
661
662 /* CRTC helper functions */
663 static const struct drm_crtc_helper_funcs glamo_crtc_helper_funcs = {
664         .dpms = glamo_crtc_dpms,
665         .mode_fixup = glamo_crtc_mode_fixup,
666         .mode_set = glamo_crtc_mode_set,
667         .mode_set_base = glamo_crtc_mode_set_base,
668         .prepare = glamo_crtc_prepare,
669         .commit = glamo_crtc_commit,
670 };
671
672
673 /* Connector functions */
674 static const struct drm_connector_funcs glamo_connector_funcs = {
675         .detect = glamo_connector_detect,
676         .fill_modes = drm_helper_probe_single_connector_modes,
677         .destroy = glamo_connector_destroy,
678         .set_property = glamo_connector_set_property,
679 };
680
681
682 /* Connector helper functions */
683 static const struct drm_connector_helper_funcs glamo_connector_helper_funcs = {
684         .mode_valid = glamo_connector_mode_valid,
685         .get_modes = glamo_connector_get_modes,
686         .best_encoder = glamo_connector_best_encoder,
687 };
688
689
690 /* Encoder functions */
691 static const struct drm_encoder_funcs glamo_encoder_funcs = {
692         .destroy = glamo_encoder_destroy,
693 };
694
695
696 /* Encoder helper functions */
697 static const struct drm_encoder_helper_funcs glamo_encoder_helper_funcs = {
698         .dpms = glamo_encoder_dpms,
699         .mode_fixup = glamo_encoder_mode_fixup,
700         .prepare = glamo_encoder_prepare,
701         .commit = glamo_encoder_commit,
702         .mode_set = glamo_encoder_mode_set,
703 };
704
705
706 /* Mode functions */
707 static const struct drm_mode_config_funcs glamo_mode_funcs = {
708         .fb_create = glamo_user_framebuffer_create,
709         .fb_changed = glamo_fbchanged
710 };
711
712
713 static struct drm_mode_set kernelfb_mode;
714
715
716 /* Restore's the kernel's fbcon mode, used for panic path */
717 void glamo_display_restore(void)
718 {
719         drm_crtc_helper_set_config(&kernelfb_mode);
720 }
721
722
723 static int glamo_display_panic(struct notifier_block *n, unsigned long ununsed,
724                                void *panic_str)
725 {
726         DRM_ERROR("panic occurred, switching back to text console\n");
727
728         glamo_display_restore();
729         return 0;
730 }
731
732
733 static struct notifier_block paniced = {
734         .notifier_call = glamo_display_panic,
735 };
736
737
738 int glamo_display_init(struct drm_device *dev)
739 {
740         struct glamodrm_handle *gdrm;
741         struct glamo_crtc *glamo_crtc;
742         struct glamo_output *glamo_output;
743         struct drm_connector *connector;
744         struct glamo_framebuffer *glamo_fb;
745         struct fb_info *info;
746         struct glamofb_par *par;
747         struct drm_mode_set *modeset;
748
749         gdrm = dev->dev_private;
750
751         printk(KERN_CRIT "glamo_display_init\n");
752
753         glamo_engine_enable(gdrm->glamo_core, GLAMO_ENGINE_LCD);
754         glamo_engine_reset(gdrm->glamo_core, GLAMO_ENGINE_LCD);
755
756         drm_mode_config_init(dev);
757
758         dev->mode_config.min_width = 240;
759         dev->mode_config.min_height = 320;
760         dev->mode_config.max_width = 480;
761         dev->mode_config.max_height = 640;
762
763         dev->mode_config.funcs = (void *)&glamo_mode_funcs;
764
765         /* Initialise our CRTC object.
766          * Only one connector per CRTC.  We know this: it's kind of soldered. */
767         glamo_crtc = kzalloc(sizeof(struct glamo_crtc)
768                            + sizeof(struct drm_connector *), GFP_KERNEL);
769         if (glamo_crtc == NULL) return 1;
770         glamo_crtc->gdrm = gdrm;
771         glamo_crtc->blank_mode = DRM_MODE_DPMS_OFF;
772         drm_crtc_init(dev, &glamo_crtc->base, &glamo_crtc_funcs);
773         drm_crtc_helper_add(&glamo_crtc->base, &glamo_crtc_helper_funcs);
774
775         glamo_crtc->mode_set.crtc = &glamo_crtc->base;
776         glamo_crtc->mode_set.connectors =
777                                       (struct drm_connector **)(glamo_crtc + 1);
778         glamo_crtc->mode_set.num_connectors = 0;
779
780         /* Create our "output" object: consists of an output and an encoder */
781         glamo_output = kzalloc(sizeof(struct glamo_output), GFP_KERNEL);
782         if (glamo_output == NULL) return 1;
783         connector = &glamo_output->base;
784         glamo_output->gdrm = gdrm;
785
786         /* Initialise the connector */
787         drm_connector_init(dev, connector, &glamo_connector_funcs,
788                            DRM_MODE_CONNECTOR_Unknown);
789         drm_sysfs_connector_add(connector);
790         connector->interlace_allowed = 0;
791         connector->doublescan_allowed = 0;
792
793         /* Initialise the encoder */
794         drm_encoder_init(dev, &glamo_output->enc, &glamo_encoder_funcs,
795                          DRM_MODE_ENCODER_DAC);
796         glamo_output->enc.possible_crtcs = 1 << 0;
797         drm_mode_connector_attach_encoder(&glamo_output->base,
798                                           &glamo_output->enc);
799
800         drm_encoder_helper_add(&glamo_output->enc, &glamo_encoder_helper_funcs);
801         drm_connector_helper_add(connector, &glamo_connector_helper_funcs);
802
803         drm_helper_initial_config(dev, false);
804
805         /* Initial setup of the LCD controller */
806         glamo_run_lcd_script(gdrm, lcd_init_script,
807                                    ARRAY_SIZE(lcd_init_script));
808
809         if (list_empty(&dev->mode_config.fb_kernel_list)) {
810                 int ret;
811                 ret = glamofb_create(dev, 480, 640, 480, 640, &glamo_fb);
812                 if (ret) return -EINVAL;
813         }
814
815         info = glamo_fb->base.fbdev;
816         par = info->par;
817
818         modeset = &glamo_crtc->mode_set;
819         modeset->fb = &glamo_fb->base;
820         modeset->connectors[0] = connector;
821
822         par->crtc_ids[0] = glamo_crtc->base.base.id;
823
824         modeset->num_connectors = 1;
825         modeset->mode = modeset->crtc->desired_mode;
826
827         par->crtc_count = 1;
828
829         if (register_framebuffer(info) < 0)
830                 return -EINVAL;
831
832         printk(KERN_INFO "[glamo-drm] fb%d: %s frame buffer device\n",
833                info->node, info->fix.id);
834
835         /* Switch back to kernel console on panic */
836         kernelfb_mode = *modeset;
837         atomic_notifier_chain_register(&panic_notifier_list, &paniced);
838         printk(KERN_INFO "[glamo-drm] registered panic notifier\n");
839
840         return 0;
841 }
842
843
844 void glamo_display_suspend(struct glamodrm_handle *gdrm)
845 {
846         jbt6k74_action(0);
847
848         gdrm->saved_width = reg_read_lcd(gdrm, GLAMO_REG_LCD_WIDTH);
849         gdrm->saved_height = reg_read_lcd(gdrm, GLAMO_REG_LCD_HEIGHT);
850         gdrm->saved_pitch = reg_read_lcd(gdrm, GLAMO_REG_LCD_PITCH);
851         gdrm->saved_htotal = reg_read_lcd(gdrm, GLAMO_REG_LCD_HORIZ_TOTAL);
852         gdrm->saved_hrtrst = reg_read_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_START);
853         gdrm->saved_hrtren = reg_read_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_END);
854         gdrm->saved_hdspst = reg_read_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_START);
855         gdrm->saved_hdspen = reg_read_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_END);
856         gdrm->saved_vtotal = reg_read_lcd(gdrm, GLAMO_REG_LCD_VERT_TOTAL);
857         gdrm->saved_vrtrst = reg_read_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_START);
858         gdrm->saved_vrtren = reg_read_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_END);
859         gdrm->saved_vdspst = reg_read_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_START);
860         gdrm->saved_vdspen = reg_read_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_END);
861 }
862
863
864 void glamo_display_resume(struct glamodrm_handle *gdrm)
865 {
866         /* Reinitialise the LCD controller */
867         jbt6k74_action(0);
868         mdelay(5);
869
870         glamo_engine_enable(gdrm->glamo_core, GLAMO_ENGINE_LCD);
871         glamo_engine_reset(gdrm->glamo_core, GLAMO_ENGINE_LCD);
872         glamo_run_lcd_script(gdrm, lcd_init_script,
873                                    ARRAY_SIZE(lcd_init_script));
874
875         /* Enable pixel clock */
876         glamo_engine_clkreg_set(gdrm->glamo_core,
877                                 GLAMO_ENGINE_LCD,
878                                 GLAMO_CLOCK_LCD_EN_DCLK,
879                                 GLAMO_CLOCK_LCD_EN_DCLK);
880
881         /* Restore timings */
882         glamo_lcd_cmd_mode(gdrm, 1);
883         glamo_engine_reclock(gdrm->glamo_core, GLAMO_ENGINE_LCD,
884                              gdrm->saved_clock);
885         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_WIDTH, GLAMO_LCD_WIDTH_MASK,
886                              gdrm->saved_width);
887         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HEIGHT, GLAMO_LCD_HEIGHT_MASK,
888                              gdrm->saved_height);
889         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_PITCH, GLAMO_LCD_PITCH_MASK,
890                              gdrm->saved_pitch);
891         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_TOTAL,
892                              GLAMO_LCD_HV_TOTAL_MASK, gdrm->saved_htotal);
893         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_START,
894                              GLAMO_LCD_HV_RETR_START_MASK, gdrm->saved_hrtrst);
895         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_END,
896                              GLAMO_LCD_HV_RETR_END_MASK, gdrm->saved_hrtren);
897         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_START,
898                              GLAMO_LCD_HV_RETR_DISP_START_MASK,
899                              gdrm->saved_hdspst);
900         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_END,
901                              GLAMO_LCD_HV_RETR_DISP_END_MASK,
902                              gdrm->saved_hdspen);
903         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_TOTAL,
904                              GLAMO_LCD_HV_TOTAL_MASK, gdrm->saved_vtotal);
905         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_START,
906                              GLAMO_LCD_HV_RETR_START_MASK, gdrm->saved_vrtrst);
907         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_END,
908                              GLAMO_LCD_HV_RETR_END_MASK, gdrm->saved_vrtren);
909         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_START,
910                              GLAMO_LCD_HV_RETR_DISP_START_MASK,
911                              gdrm->saved_vdspst);
912         reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_END,
913                              GLAMO_LCD_HV_RETR_DISP_END_MASK,
914                              gdrm->saved_vdspen);
915         glamo_lcd_cmd_mode(gdrm, 0);
916
917         jbt6k74_action(1);
918 }