fix-glamo-idleclock-around-suspend.patch
[kernel.git] / drivers / mfd / glamo / glamo-mci.c
1 /*
2  *  linux/drivers/mmc/host/glamo-mmc.c - Glamo MMC driver
3  *
4  *  Copyright (C) 2007 Openmoko, Inc,  Andy Green <andy@openmoko.com>
5  *  Based on S3C MMC driver that was:
6  *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/clk.h>
16 #include <linux/mmc/mmc.h>
17 #include <linux/mmc/host.h>
18 #include <linux/platform_device.h>
19 #include <linux/irq.h>
20 #include <linux/pcf50633.h>
21 #include <linux/delay.h>
22 #include <linux/interrupt.h>
23 #include <linux/spinlock.h>
24
25 #include <asm/dma.h>
26 #include <asm/dma-mapping.h>
27 #include <asm/io.h>
28
29 #include "glamo-mci.h"
30 #include "glamo-core.h"
31 #include "glamo-regs.h"
32
33 /* from glamo-core.c */
34 extern struct glamo_mci_pdata glamo_mci_def_pdata;
35
36 static spinlock_t clock_lock;
37
38 #define DRIVER_NAME "glamo-mci"
39 #define RESSIZE(ressource) (((ressource)->end - (ressource)->start) + 1)
40
41 static void glamo_mci_send_request(struct mmc_host *mmc);
42
43 /*
44  * Max SD clock rate
45  *
46  * held at /(3 + 1) due to concerns of 100R recommended series resistor
47  * allows 16MHz @ 4-bit --> 8MBytes/sec raw
48  *
49  * you can override this on kernel commandline using
50  *
51  *   glamo_mci.sd_max_clk=10000000
52  *
53  * for example
54  */
55
56 static int sd_max_clk = 50000000 / 3;
57 module_param(sd_max_clk, int, 0644);
58
59 /*
60  * Slow SD clock rate
61  *
62  * you can override this on kernel commandline using
63  *
64  *   glamo_mci.sd_slow_ratio=8
65  *
66  * for example
67  *
68  * platform callback is used to decide effective clock rate, if not
69  * defined then max is used, if defined and returns nonzero, rate is
70  * divided by this factor
71  */
72
73 static int sd_slow_ratio = 8;
74 module_param(sd_slow_ratio, int, 0644);
75
76 /*
77  * SD Signal drive strength
78  *
79  * you can override this on kernel commandline using
80  *
81  *   glamo_mci.sd_drive=0
82  *
83  * for example
84  */
85
86 static int sd_drive;
87 module_param(sd_drive, int, 0644);
88
89 /*
90  * SD allow SD clock to run while idle
91  *
92  * you can override this on kernel commandline using
93  *
94  *   glamo_mci.sd_idleclk=0
95  *
96  * for example
97  */
98
99 static int sd_idleclk = 0; /* disallow idle clock by default */
100 module_param(sd_idleclk, int, 0644);
101
102 /* used to stash real idleclk state in suspend: we force it to run in there */
103 static int suspend_sd_idleclk;
104
105
106 unsigned char CRC7(u8 * pu8, int cnt)
107 {
108         u8 crc = 0;
109
110         while (cnt--) {
111                 int n;
112                 u8 d = *pu8++;
113                 for (n = 0; n < 8; n++) {
114                         crc <<= 1;
115                         if ((d & 0x80) ^ (crc & 0x80))
116                                 crc ^= 0x09;
117                         d <<= 1;
118                 }
119         }
120         return (crc << 1) | 1;
121 }
122
123 /* these _dly versions account for the dead time rules for reg access */
124 static u16 readw_dly(u16 __iomem * pu16)
125 {
126         glamo_reg_access_delay();
127         return readw(pu16);
128 }
129
130 static void writew_dly(u16 val, u16 __iomem * pu16)
131 {
132         glamo_reg_access_delay();
133         writew(val, pu16);
134 }
135
136 static int get_data_buffer(struct glamo_mci_host *host,
137                            volatile u32 *words, volatile u16 **pointer)
138 {
139         struct scatterlist *sg;
140
141         *words = 0;
142         *pointer = NULL;
143
144         if (host->pio_active == XFER_NONE)
145                 return -EINVAL;
146
147         if ((!host->mrq) || (!host->mrq->data))
148                 return -EINVAL;
149
150         if (host->pio_sgptr >= host->mrq->data->sg_len) {
151                 dev_dbg(&host->pdev->dev, "no more buffers (%i/%i)\n",
152                       host->pio_sgptr, host->mrq->data->sg_len);
153                 return -EBUSY;
154         }
155         sg = &host->mrq->data->sg[host->pio_sgptr];
156
157         *words = sg->length >> 1; /* we are working with a 16-bit data bus */
158         *pointer = page_address(sg_page(sg)) + sg->offset;
159
160         BUG_ON(((long)(*pointer)) & 1);
161
162         host->pio_sgptr++;
163
164         /* dev_info(&host->pdev->dev, "new buffer (%i/%i)\n",
165               host->pio_sgptr, host->mrq->data->sg_len); */
166         return 0;
167 }
168
169 static void do_pio_read(struct glamo_mci_host *host)
170 {
171         int res;
172         u16 __iomem *from_ptr = host->base_data + (RESSIZE(host->mem_data) /
173                                                               sizeof(u16) / 2);
174 #ifdef DEBUG
175         u16 * block;
176 #endif
177
178         while (1) {
179                 res = get_data_buffer(host, &host->pio_words, &host->pio_ptr);
180                 if (res) {
181                         host->pio_active = XFER_NONE;
182                         host->complete_what = COMPLETION_FINALIZE;
183
184                         dev_dbg(&host->pdev->dev, "pio_read(): "
185                                 "complete (no more data).\n");
186                         return;
187                 }
188
189                 dev_dbg(&host->pdev->dev, "pio_read(): host->pio_words: %d\n",
190                                 host->pio_words);
191
192                 host->pio_count += host->pio_words << 1;
193
194 #ifdef DEBUG
195                 block = (u16 *)host->pio_ptr;
196                 res = host->pio_words << 1;
197 #endif
198                 while (host->pio_words--)
199                         *host->pio_ptr++ = *from_ptr++;
200 #ifdef DEBUG
201                 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1,
202                                (void *)block, res, 1);
203 #endif
204         }
205 }
206
207 static int do_pio_write(struct glamo_mci_host *host)
208 {
209         int res = 0;
210         volatile u16 __iomem *to_ptr = host->base_data;
211         int err = 0;
212
213         dev_dbg(&host->pdev->dev, "pio_write():\n");
214         while (!res) {
215                 res = get_data_buffer(host, &host->pio_words, &host->pio_ptr);
216                 if (res)
217                         continue;
218
219                 dev_dbg(&host->pdev->dev, "pio_write():new source: [%i]@[%p]\n",
220                         host->pio_words, host->pio_ptr);
221
222                 host->pio_count += host->pio_words << 1;
223                 while (host->pio_words--)
224                         writew(*host->pio_ptr++, to_ptr++);
225         }
226
227         dev_dbg(&host->pdev->dev, "pio_write(): complete\n");
228         host->pio_active = XFER_NONE;
229         return err;
230 }
231
232 static void __glamo_mci_fix_card_div(struct glamo_mci_host *host, int div)
233 {
234         unsigned long flags;
235
236         spin_lock_irqsave(&clock_lock, flags);
237
238         if (div < 0) {
239                 /* stop clock - remove clock from divider input */
240                 writew(readw(glamo_mci_def_pdata.pglamo->base +
241                      GLAMO_REG_CLOCK_GEN5_1) & (~GLAMO_CLOCK_GEN51_EN_DIV_TCLK),
242                      glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN5_1);
243         } else {
244                 /* set the nearest prescaler factor
245                 *
246                 * register shared with SCLK divisor -- no chance of race because
247                 * we don't use sensor interface
248                 */
249                 writew_dly((readw(glamo_mci_def_pdata.pglamo->base +
250                                 GLAMO_REG_CLOCK_GEN8) & 0xff00) | div,
251                        glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN8);
252                 /* enable clock to divider input */
253                 writew_dly(readw(glamo_mci_def_pdata.pglamo->base +
254                         GLAMO_REG_CLOCK_GEN5_1) | GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
255                      glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN5_1);
256         }
257
258         spin_unlock_irqrestore(&clock_lock, flags);
259 }
260
261 static int __glamo_mci_set_card_clock(struct glamo_mci_host *host, int freq,
262                                                                   int *division)
263 {
264         int div = 0;
265         int real_rate = 0;
266
267         if (freq) {
268                 /* Set clock */
269                 for (div = 0; div < 256; div++) {
270                         real_rate = host->clk_rate / (div + 1);
271                         if (real_rate <= freq)
272                                 break;
273                 }
274                 if (div > 255)
275                         div = 255;
276
277                 if (division)
278                         *division = div;
279
280                 __glamo_mci_fix_card_div(host, div);
281
282         } else {
283                 /* stop clock */
284                 if (division)
285                         *division = 0xff;
286
287                 if (!sd_idleclk)
288                         /* clock off */
289                         __glamo_mci_fix_card_div(host, -1);
290         }
291
292         return real_rate;
293 }
294
295 static void glamo_mci_irq(unsigned int irq, struct irq_desc *desc)
296 {
297         struct glamo_mci_host *host = (struct glamo_mci_host *)
298                                       desc->handler_data;
299         u16 status;
300         struct mmc_command *cmd;
301         unsigned long iflags;
302
303         if (!host)
304                 return;
305         if (!host->mrq)
306                 return;
307         cmd = host->mrq->cmd;
308         if (!cmd)
309                 return;
310
311         spin_lock_irqsave(&host->complete_lock, iflags);
312
313         status = readw_dly(host->base + GLAMO_REG_MMC_RB_STAT1);
314
315         /* ack this interrupt source */
316         writew(GLAMO_IRQ_MMC,
317                glamo_mci_def_pdata.pglamo->base + GLAMO_REG_IRQ_CLEAR);
318
319         if (status & (GLAMO_STAT1_MMC_RTOUT |
320                       GLAMO_STAT1_MMC_DTOUT))
321                 cmd->error = -ETIMEDOUT;
322         if (status & (GLAMO_STAT1_MMC_BWERR |
323                       GLAMO_STAT1_MMC_BRERR))
324                 cmd->error = -EILSEQ;
325         if (cmd->error) {
326                 dev_err(&host->pdev->dev, "Error after cmd: 0x%x\n", status);
327                 goto done;
328         }
329
330         if (host->pio_active == XFER_READ)
331                 do_pio_read(host);
332
333         host->mrq->data->bytes_xfered = host->pio_count;
334         dev_dbg(&host->pdev->dev, "status = 0x%04x count=%d\n",
335                  status, host->pio_count);
336
337         /* issue STOP if we have been given one to use */
338         if (host->mrq->stop) {
339                 host->cmd_is_stop = 1;
340                 glamo_mci_send_request(host->mmc);
341                 host->cmd_is_stop = 0;
342         }
343
344         if (!sd_idleclk)
345                 /* clock off */
346                 __glamo_mci_fix_card_div(host, -1);
347
348 done:
349         host->complete_what = COMPLETION_NONE;
350         host->mrq = NULL;
351         mmc_request_done(host->mmc, cmd->mrq);
352         spin_unlock_irqrestore(&host->complete_lock, iflags);
353 }
354
355 static int glamo_mci_send_command(struct glamo_mci_host *host,
356                                   struct mmc_command *cmd)
357 {
358         u8 u8a[6];
359         u16 fire = 0;
360         u16 timeout = 0xfff; /* max glamo MMC timeout, in units of 16 clocks */
361
362         /* if we can't do it, reject as busy */
363         if (!readw_dly(host->base + GLAMO_REG_MMC_RB_STAT1) &
364              GLAMO_STAT1_MMC_IDLE) {
365                 host->mrq = NULL;
366                 cmd->error = -EBUSY;
367                 mmc_request_done(host->mmc, host->mrq);
368                 return -EBUSY;
369         }
370
371         /* create an array in wire order for CRC computation */
372         u8a[0] = 0x40 | (cmd->opcode & 0x3f);
373         u8a[1] = (u8)(cmd->arg >> 24);
374         u8a[2] = (u8)(cmd->arg >> 16);
375         u8a[3] = (u8)(cmd->arg >> 8);
376         u8a[4] = (u8)cmd->arg;
377         u8a[5] = CRC7(&u8a[0], 5); /* CRC7 on first 5 bytes of packet */
378
379         /* issue the wire-order array including CRC in register order */
380         writew_dly((u8a[4] << 8) | u8a[5], host->base + GLAMO_REG_MMC_CMD_REG1);
381         writew_dly((u8a[2] << 8) | u8a[3], host->base + GLAMO_REG_MMC_CMD_REG2);
382         writew_dly((u8a[0] << 8) | u8a[1], host->base + GLAMO_REG_MMC_CMD_REG3);
383
384         /* command index toggle */
385         fire |= (host->ccnt & 1) << 12;
386
387         /* set type of command */
388         switch (mmc_cmd_type(cmd)) {
389         case MMC_CMD_BC:
390                 fire |= GLAMO_FIRE_MMC_CMDT_BNR;
391                 break;
392         case MMC_CMD_BCR:
393                 fire |= GLAMO_FIRE_MMC_CMDT_BR;
394                 break;
395         case MMC_CMD_AC:
396                 fire |= GLAMO_FIRE_MMC_CMDT_AND;
397                 break;
398         case MMC_CMD_ADTC:
399                 fire |= GLAMO_FIRE_MMC_CMDT_AD;
400                 break;
401         }
402         /*
403          * if it expects a response, set the type expected
404          *
405          * R1, Length  : 48bit, Normal response
406          * R1b, Length : 48bit, same R1, but added card busy status
407          * R2, Length  : 136bit (really 128 bits with CRC snipped)
408          * R3, Length  : 48bit (OCR register value)
409          * R4, Length  : 48bit, SDIO_OP_CONDITION, Reverse SDIO Card
410          * R5, Length  : 48bit, IO_RW_DIRECTION, Reverse SDIO Card
411          * R6, Length  : 48bit (RCA register)
412          * R7, Length  : 48bit (interface condition, VHS(voltage supplied),
413          *                     check pattern, CRC7)
414          */
415         switch (mmc_resp_type(cmd)) {
416         case MMC_RSP_R6: /* same index as R7 and R1 */
417                 fire |= GLAMO_FIRE_MMC_RSPT_R1;
418                 break;
419         case MMC_RSP_R1B:
420                 fire |= GLAMO_FIRE_MMC_RSPT_R1b;
421                 break;
422         case MMC_RSP_R2:
423                 fire |= GLAMO_FIRE_MMC_RSPT_R2;
424                 break;
425         case MMC_RSP_R3:
426                 fire |= GLAMO_FIRE_MMC_RSPT_R3;
427                 break;
428         /* R4 and R5 supported by chip not defined in linux/mmc/core.h (sdio) */
429         }
430         /*
431          * From the command index, set up the command class in the host ctrllr
432          *
433          * missing guys present on chip but couldn't figure out how to use yet:
434          *     0x0 "stream read"
435          *     0x9 "cancel running command"
436          */
437         switch (cmd->opcode) {
438         case MMC_READ_SINGLE_BLOCK:
439                 fire |= GLAMO_FIRE_MMC_CC_SBR; /* single block read */
440                 break;
441         case MMC_SWITCH: /* 64 byte payload */
442         case 0x33: /* observed issued by MCI */
443         case MMC_READ_MULTIPLE_BLOCK:
444                 /* we will get an interrupt off this */
445                 if (!cmd->mrq->stop)
446                         /* multiblock no stop */
447                         fire |= GLAMO_FIRE_MMC_CC_MBRNS;
448                 else
449                          /* multiblock with stop */
450                         fire |= GLAMO_FIRE_MMC_CC_MBRS;
451                 break;
452         case MMC_WRITE_BLOCK:
453                 fire |= GLAMO_FIRE_MMC_CC_SBW; /* single block write */
454                 break;
455         case MMC_WRITE_MULTIPLE_BLOCK:
456                 if (cmd->mrq->stop)
457                          /* multiblock with stop */
458                         fire |= GLAMO_FIRE_MMC_CC_MBWS;
459                 else
460                          /* multiblock NO stop-- 'RESERVED'? */
461                         fire |= GLAMO_FIRE_MMC_CC_MBWNS;
462                 break;
463         case MMC_STOP_TRANSMISSION:
464                 fire |= GLAMO_FIRE_MMC_CC_STOP; /* STOP */
465                 break;
466         default:
467                 fire |= GLAMO_FIRE_MMC_CC_BASIC; /* "basic command" */
468                 break;
469         }
470         /* enforce timeout, clipping at default 65520 clocks if larger */
471         if (cmd->data)
472                 /* so long as there is one... */
473                 if (cmd->data->timeout_clks &&
474                     /* ... and it is not longer than we can handle */
475                     (cmd->data->timeout_clks <= 0xffff))
476                         timeout = cmd->data->timeout_clks >> 4; /* / 16 clks */
477
478         writew(timeout, host->base + GLAMO_REG_MMC_TIMEOUT);
479
480         /* Generate interrupt on txfer */
481         writew_dly((readw_dly(host->base + GLAMO_REG_MMC_BASIC) & 0x3e) |
482                    0x0800 | GLAMO_BASIC_MMC_NO_CLK_RD_WAIT |
483                    GLAMO_BASIC_MMC_EN_COMPL_INT | (sd_drive << 6),
484                    host->base + GLAMO_REG_MMC_BASIC);
485
486         /* send the command out on the wire */
487         /* dev_info(&host->pdev->dev, "Using FIRE %04X\n", fire); */
488         writew_dly(fire, host->base + GLAMO_REG_MMC_CMD_FIRE);
489         cmd->error = 0;
490         return 0;
491 }
492
493 static int glamo_mci_prepare_pio(struct glamo_mci_host *host,
494                                  struct mmc_data *data)
495 {
496         /*
497          * the S-Media-internal RAM offset for our MMC buffer
498          * Read is halfway up the buffer and write is at the start
499          */
500         if (data->flags & MMC_DATA_READ) {
501                 writew_dly((u16)(GLAMO_FB_SIZE + (RESSIZE(host->mem_data) / 2)),
502                            host->base + GLAMO_REG_MMC_WDATADS1);
503                 writew_dly((u16)((GLAMO_FB_SIZE +
504                                         (RESSIZE(host->mem_data) / 2)) >> 16),
505                            host->base + GLAMO_REG_MMC_WDATADS2);
506         } else {
507                 writew_dly((u16)GLAMO_FB_SIZE, host->base +
508                                                GLAMO_REG_MMC_RDATADS1);
509                 writew_dly((u16)(GLAMO_FB_SIZE >> 16), host->base +
510                                                        GLAMO_REG_MMC_RDATADS2);
511         }
512
513         /* set up the block info */
514         writew_dly(data->blksz, host->base + GLAMO_REG_MMC_DATBLKLEN);
515         writew_dly(data->blocks, host->base + GLAMO_REG_MMC_DATBLKCNT);
516         dev_dbg(&host->pdev->dev, "(blksz=%d, count=%d)\n",
517                                    data->blksz, data->blocks);
518         host->pio_sgptr = 0;
519         host->pio_words = 0;
520         host->pio_count = 0;
521         host->pio_active = 0;
522         /* if write, prep the write into the shared RAM before the command */
523         if (data->flags & MMC_DATA_WRITE) {
524                 host->pio_active = XFER_WRITE;
525                 return do_pio_write(host);
526         }
527         host->pio_active = XFER_READ;
528         return 0;
529 }
530
531 static void glamo_mci_send_request(struct mmc_host *mmc)
532 {
533         struct glamo_mci_host *host = mmc_priv(mmc);
534         struct mmc_request *mrq = host->mrq;
535         struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
536         u16 * pu16 = (u16 *)&cmd->resp[0];
537         u16 * reg_resp = (u16 *)(host->base + GLAMO_REG_MMC_CMD_RSP1);
538         u16 status;
539         int n;
540         int timeout = 100000000;
541
542         if (host->suspending) {
543                 dev_err(&host->pdev->dev, "faking cmd %d "
544                         "during suspend\n", cmd->opcode);
545                 mmc_request_done(mmc, mrq);
546                 return;
547         }
548
549         host->ccnt++;
550         /*
551          * somehow 2.6.24 MCI manages to issue MMC_WRITE_BLOCK *without* the
552          * MMC_DATA_WRITE flag, WTF?  Work around the madness.
553          */
554         if (cmd->opcode == MMC_WRITE_BLOCK)
555                 if (mrq->data)
556                         mrq->data->flags |= MMC_DATA_WRITE;
557
558          /* this guy has data to read/write? */
559         if ((!host->cmd_is_stop) && cmd->data) {
560                 int res;
561                 host->dcnt++;
562                 res = glamo_mci_prepare_pio(host, cmd->data);
563                 if (res) {
564                         cmd->error = -EIO;
565                         cmd->data->error = -EIO;
566                         mmc_request_done(mmc, mrq);
567                         return;
568                 }
569         }
570
571         dev_dbg(&host->pdev->dev,"cmd 0x%x, "
572                  "arg 0x%x data=%p mrq->stop=%p flags 0x%x\n",
573                  cmd->opcode, cmd->arg, cmd->data, cmd->mrq->stop,
574                  cmd->flags);
575
576         /* resume requested clock rate
577          * scale it down by sd_slow_ratio if platform requests it
578          */
579         if (host->pdata->glamo_mci_use_slow)
580                 if ((host->pdata->glamo_mci_use_slow)())
581                         __glamo_mci_fix_card_div(host, host->clk_div *
582                                                                  sd_slow_ratio);
583                 else
584                         __glamo_mci_fix_card_div(host, host->clk_div);
585         else
586                 __glamo_mci_fix_card_div(host, host->clk_div);
587
588         if (glamo_mci_send_command(host, cmd))
589                 goto bail;
590         /*
591          * we must spin until response is ready or timed out
592          * -- we don't get interrupts unless there is a bulk rx
593          */
594         do
595                 status = readw_dly(host->base + GLAMO_REG_MMC_RB_STAT1);
596         while ((((status >> 15) & 1) != (host->ccnt & 1)) ||
597                 (!(status & (GLAMO_STAT1_MMC_RB_RRDY |
598                              GLAMO_STAT1_MMC_RTOUT |
599                              GLAMO_STAT1_MMC_DTOUT |
600                              GLAMO_STAT1_MMC_BWERR |
601                              GLAMO_STAT1_MMC_BRERR))));
602
603         if (status & (GLAMO_STAT1_MMC_RTOUT |
604                       GLAMO_STAT1_MMC_DTOUT))
605                 cmd->error = -ETIMEDOUT;
606         if (status & (GLAMO_STAT1_MMC_BWERR |
607                       GLAMO_STAT1_MMC_BRERR))
608                 cmd->error = -EILSEQ;
609
610         if (host->cmd_is_stop)
611                 goto bail;
612
613         if (cmd->error) {
614                 dev_err(&host->pdev->dev, "Error after cmd: 0x%x\n", status);
615                 goto done;
616         }
617         /*
618          * mangle the response registers in two different exciting
619          * undocumented ways discovered by trial and error
620          */
621         if (mmc_resp_type(cmd) == MMC_RSP_R2)
622                 /* grab the response */
623                 for (n = 0; n < 8; n++) /* super mangle power 1 */
624                         pu16[n ^ 6] = readw_dly(&reg_resp[n]);
625         else
626                 for (n = 0; n < 3; n++) /* super mangle power 2 */
627                         pu16[n] = (readw_dly(&reg_resp[n]) >> 8) |
628                                   (readw_dly(&reg_resp[n + 1]) << 8);
629         /*
630          * if we don't have bulk data to take care of, we're done
631          */
632         if (!cmd->data)
633                 goto done;
634         if (!(cmd->data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)))
635                 goto done;
636         /*
637          * Otherwise can can use the interrupt as async completion --
638          * if there is read data coming, or we wait for write data to complete,
639          * exit without mmc_request_done() as the payload interrupt
640          * will service it
641          */
642         dev_dbg(&host->pdev->dev, "Waiting for payload data\n");
643         /*
644          * if the glamo INT# line isn't wired (*cough* it can happen)
645          * I'm afraid we have to spin on the IRQ status bit and "be
646          * our own INT# line"
647          */
648         if (!glamo_mci_def_pdata.pglamo->irq_works) {
649                 /*
650                  * we have faith we will get an "interrupt"...
651                  * but something insane like suspend problems can mean
652                  * we spin here forever, so we timeout after a LONG time
653                  */
654                 while ((!(readw_dly(glamo_mci_def_pdata.pglamo->base +
655                          GLAMO_REG_IRQ_STATUS) & GLAMO_IRQ_MMC)) &&
656                        (timeout--))
657                         ;
658
659                 if (timeout < 0) {
660                         if (cmd->data->error)
661                                 cmd->data->error = -ETIMEDOUT;
662                         dev_err(&host->pdev->dev, "Payload timeout\n");
663                         goto bail;
664                 }
665
666                 /* yay we are an interrupt controller! -- call the ISR
667                  * it will stop clock to card
668                  */
669                 glamo_mci_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC),
670                               irq_desc + IRQ_GLAMO(GLAMO_IRQIDX_MMC));
671         }
672         return;
673
674 done:
675         host->complete_what = COMPLETION_NONE;
676         host->mrq = NULL;
677         mmc_request_done(host->mmc, cmd->mrq);
678 bail:
679         if (!sd_idleclk)
680                 /* stop the clock to card */
681                 __glamo_mci_fix_card_div(host, -1);
682 }
683
684 static void glamo_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
685 {
686         struct glamo_mci_host *host = mmc_priv(mmc);
687
688         host->cmd_is_stop = 0;
689         host->mrq = mrq;
690         glamo_mci_send_request(mmc);
691 }
692
693 static void glamo_mci_reset(struct glamo_mci_host *host)
694 {
695         dev_dbg(&host->pdev->dev, "******* glamo_mci_reset\n");
696         /* reset MMC controller */
697         writew_dly(GLAMO_CLOCK_MMC_RESET | GLAMO_CLOCK_MMC_DG_TCLK |
698                    GLAMO_CLOCK_MMC_EN_TCLK | GLAMO_CLOCK_MMC_DG_M9CLK |
699                    GLAMO_CLOCK_MMC_EN_M9CLK,
700                    glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_MMC);
701         msleep(1);
702         /* and disable reset */
703         writew_dly(GLAMO_CLOCK_MMC_DG_TCLK |
704                    GLAMO_CLOCK_MMC_EN_TCLK | GLAMO_CLOCK_MMC_DG_M9CLK |
705                    GLAMO_CLOCK_MMC_EN_M9CLK,
706                    glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_MMC);
707 }
708
709
710 static void glamo_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
711 {
712         struct glamo_mci_host *host = mmc_priv(mmc);
713         int n = 0;
714         int div;
715         int powering = 0;
716
717         /* Set power */
718         switch(ios->power_mode) {
719         case MMC_POWER_ON:
720         case MMC_POWER_UP:
721                 if (host->vdd_current != ios->vdd) {
722                         host->pdata->glamo_set_mci_power(ios->power_mode,
723                                                          ios->vdd);
724                         host->vdd_current = ios->vdd;
725                 }
726                 if (host->power_mode_current == MMC_POWER_OFF) {
727                         glamo_engine_enable(glamo_mci_def_pdata.pglamo,
728                                                               GLAMO_ENGINE_MMC);
729                         powering = 1;
730                 }
731                 break;
732
733         case MMC_POWER_OFF:
734         default:
735                 if (host->power_mode_current == MMC_POWER_OFF)
736                         break;
737                 glamo_engine_disable(glamo_mci_def_pdata.pglamo,
738                                      GLAMO_ENGINE_MMC);
739                 host->pdata->glamo_set_mci_power(MMC_POWER_OFF, 0);
740                 host->vdd_current = -1;
741                 break;
742         }
743         host->power_mode_current = ios->power_mode;
744
745         host->real_rate = __glamo_mci_set_card_clock(host, ios->clock, &div);
746         host->clk_div = div;
747
748         /* after power-up, we are meant to give it >= 74 clocks so it can
749          * initialize itself.  Doubt any modern cards need it but anyway...
750          */
751         if (powering)
752                 msleep(1);
753
754         if (!sd_idleclk)
755                 /* stop the clock to card, because we are idle until transfer */
756                 __glamo_mci_fix_card_div(host, -1);
757
758         if ((ios->power_mode == MMC_POWER_ON) ||
759             (ios->power_mode == MMC_POWER_UP)) {
760                 dev_info(&host->pdev->dev,
761                         "powered (vdd = %d) clk: %lukHz div=%d (req: %ukHz). "
762                         "Bus width=%d\n",(int)ios->vdd,
763                         host->real_rate / 1000, (int)host->clk_div,
764                         ios->clock / 1000, (int)ios->bus_width);
765         } else
766                 dev_info(&host->pdev->dev, "glamo_mci_set_ios: power down.\n");
767
768         /* set bus width */
769         host->bus_width = ios->bus_width;
770         if (host->bus_width == MMC_BUS_WIDTH_4)
771                 n = GLAMO_BASIC_MMC_EN_4BIT_DATA;
772         writew_dly((readw_dly(host->base + GLAMO_REG_MMC_BASIC) &
773                                           (~(GLAMO_BASIC_MMC_EN_4BIT_DATA |
774                                              GLAMO_BASIC_MMC_EN_DR_STR0 |
775                                              GLAMO_BASIC_MMC_EN_DR_STR1))) | n |
776                                sd_drive << 6, host->base + GLAMO_REG_MMC_BASIC);
777 }
778
779
780 /*
781  * no physical write protect supported by us
782  */
783 static int glamo_mci_get_ro(struct mmc_host *mmc)
784 {
785         return 0;
786 }
787
788 static struct mmc_host_ops glamo_mci_ops = {
789         .request        = glamo_mci_request,
790         .set_ios        = glamo_mci_set_ios,
791         .get_ro         = glamo_mci_get_ro,
792 };
793
794 static int glamo_mci_probe(struct platform_device *pdev)
795 {
796         struct mmc_host         *mmc;
797         struct glamo_mci_host   *host;
798         int ret;
799
800         dev_info(&pdev->dev, "glamo_mci driver (C)2007 Openmoko, Inc\n");
801
802         mmc = mmc_alloc_host(sizeof(struct glamo_mci_host), &pdev->dev);
803         if (!mmc) {
804                 ret = -ENOMEM;
805                 goto probe_out;
806         }
807
808         host = mmc_priv(mmc);
809         host->mmc = mmc;
810         host->pdev = pdev;
811         host->pdata = &glamo_mci_def_pdata;
812         host->power_mode_current = MMC_POWER_OFF;
813
814         host->complete_what = COMPLETION_NONE;
815         host->pio_active = XFER_NONE;
816
817         spin_lock_init(&host->complete_lock);
818
819         host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
820         if (!host->mem) {
821                 dev_err(&pdev->dev,
822                         "failed to get io memory region resouce.\n");
823
824                 ret = -ENOENT;
825                 goto probe_free_host;
826         }
827
828         host->mem = request_mem_region(host->mem->start,
829                 RESSIZE(host->mem), pdev->name);
830
831         if (!host->mem) {
832                 dev_err(&pdev->dev, "failed to request io memory region.\n");
833                 ret = -ENOENT;
834                 goto probe_free_host;
835         }
836
837         host->base = ioremap(host->mem->start, RESSIZE(host->mem));
838         if (!host->base) {
839                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
840                 ret = -EINVAL;
841                 goto probe_free_mem_region;
842         }
843
844         /* set the handler for our bit of the shared chip irq register */
845         set_irq_handler(IRQ_GLAMO(GLAMO_IRQIDX_MMC), glamo_mci_irq);
846         /* stash host as our handler's private data */
847         set_irq_data(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
848
849         /* Get ahold of our data buffer we use for data in and out on MMC */
850         host->mem_data = platform_get_resource(pdev, IORESOURCE_MEM, 1);
851         if (!host->mem_data) {
852                 dev_err(&pdev->dev,
853                         "failed to get io memory region resource.\n");
854                 ret = -ENOENT;
855                 goto probe_iounmap;
856         }
857
858         host->mem_data = request_mem_region(host->mem_data->start,
859                 RESSIZE(host->mem_data), pdev->name);
860
861         if (!host->mem_data) {
862                 dev_err(&pdev->dev, "failed to request io memory region.\n");
863                 ret = -ENOENT;
864                 goto probe_iounmap;
865         }
866         host->base_data = ioremap(host->mem_data->start,
867                                           RESSIZE(host->mem_data));
868         host->data_max_size = RESSIZE(host->mem_data);
869
870         if (host->base_data == 0) {
871                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
872                 ret = -EINVAL;
873                 goto probe_free_mem_region_data;
874         }
875
876         host->vdd_current = 0;
877         host->clk_rate = 50000000; /* really it's 49152000 */
878         host->clk_div = 16;
879
880         /* explain our host controller capabilities */
881         mmc->ops        = &glamo_mci_ops;
882         mmc->ocr_avail  = host->pdata->ocr_avail;
883         mmc->caps       = MMC_CAP_4_BIT_DATA |
884                           MMC_CAP_MMC_HIGHSPEED |
885                           MMC_CAP_SD_HIGHSPEED;
886         mmc->f_min      = host->clk_rate / 256;
887         mmc->f_max      = sd_max_clk;
888
889         mmc->max_blk_count      = (1 << 16) - 1; /* GLAMO_REG_MMC_RB_BLKCNT */
890         mmc->max_blk_size       = (1 << 12) - 1; /* GLAMO_REG_MMC_RB_BLKLEN */
891         mmc->max_req_size       = RESSIZE(host->mem_data) / 2;
892         mmc->max_seg_size       = mmc->max_req_size;
893         mmc->max_phys_segs      = 1; /* hw doesn't talk about segs??? */
894         mmc->max_hw_segs        = 1;
895
896         dev_info(&host->pdev->dev, "probe: mapped mci_base:%p irq:%u.\n",
897                 host->base, host->irq);
898
899         if ((ret = mmc_add_host(mmc))) {
900                 dev_err(&pdev->dev, "failed to add mmc host.\n");
901                 goto probe_free_mem_region_data;
902         }
903
904         platform_set_drvdata(pdev, mmc);
905
906         dev_info(&pdev->dev,"initialisation done.\n");
907         return 0;
908
909  probe_free_mem_region_data:
910         release_mem_region(host->mem_data->start, RESSIZE(host->mem_data));
911
912  probe_iounmap:
913         iounmap(host->base);
914
915  probe_free_mem_region:
916         release_mem_region(host->mem->start, RESSIZE(host->mem));
917
918  probe_free_host:
919         mmc_free_host(mmc);
920  probe_out:
921         return ret;
922 }
923
924 static int glamo_mci_remove(struct platform_device *pdev)
925 {
926         struct mmc_host         *mmc  = platform_get_drvdata(pdev);
927         struct glamo_mci_host   *host = mmc_priv(mmc);
928
929         mmc_remove_host(mmc);
930         /* stop using our handler, revert it to default */
931         set_irq_handler(IRQ_GLAMO(GLAMO_IRQIDX_MMC), handle_level_irq);
932         iounmap(host->base);
933         iounmap(host->base_data);
934         release_mem_region(host->mem->start, RESSIZE(host->mem));
935         release_mem_region(host->mem_data->start, RESSIZE(host->mem_data));
936         mmc_free_host(mmc);
937
938         glamo_engine_disable(glamo_mci_def_pdata.pglamo, GLAMO_ENGINE_MMC);
939         return 0;
940 }
941
942
943 #ifdef CONFIG_PM
944
945 static int glamo_mci_suspend(struct platform_device *dev, pm_message_t state)
946 {
947         struct mmc_host *mmc = platform_get_drvdata(dev);
948         struct glamo_mci_host   *host = mmc_priv(mmc);
949         int ret;
950
951         /*
952          * possible workaround for SD corruption during suspend - resume
953          * make sure the clock was running during suspend and consequently
954          * resume
955          */
956         if (host->pdata->glamo_mci_use_slow)
957                 if ((host->pdata->glamo_mci_use_slow)())
958                         __glamo_mci_fix_card_div(host, host->clk_div *
959                                                                  sd_slow_ratio);
960                 else
961                         __glamo_mci_fix_card_div(host, host->clk_div);
962         else
963                 __glamo_mci_fix_card_div(host, host->clk_div);
964
965         /* we are going to do more commands to override this in
966          * mmc_suspend_host(), so we need to change sd_idleclk for the
967          * duration as well
968          */
969         suspend_sd_idleclk = sd_idleclk;
970         sd_idleclk = 1;
971
972         host->suspending++;
973         if (host->pdata->mci_all_dependencies_resumed)
974                 (host->pdata->mci_suspending)(dev);
975
976         ret = mmc_suspend_host(mmc, state);
977
978         /* so that when we resume, we use any modified max rate */
979         mmc->f_max = sd_max_clk;
980
981         return ret;
982 }
983
984 int glamo_mci_resume(struct platform_device *dev)
985 {
986         struct mmc_host *mmc = platform_get_drvdata(dev);
987         struct glamo_mci_host   *host = mmc_priv(mmc);
988         int ret;
989
990         if (host->pdata->mci_all_dependencies_resumed)
991                 if (!(host->pdata->mci_all_dependencies_resumed)(dev))
992                         return 0;
993
994         host->suspending--;
995
996         ret = mmc_resume_host(mmc);
997
998         /* put sd_idleclk back to pre-suspend state */
999         sd_idleclk = suspend_sd_idleclk;
1000
1001         return ret;
1002 }
1003 EXPORT_SYMBOL_GPL(glamo_mci_resume);
1004
1005
1006 #else /* CONFIG_PM */
1007 #define glamo_mci_suspend NULL
1008 #define glamo_mci_resume NULL
1009 #endif /* CONFIG_PM */
1010
1011
1012 static struct platform_driver glamo_mci_driver =
1013 {
1014         .driver.name    = "glamo-mci",
1015         .probe          = glamo_mci_probe,
1016         .remove         = glamo_mci_remove,
1017         .suspend        = glamo_mci_suspend,
1018         .resume         = glamo_mci_resume,
1019 };
1020
1021 static int __init glamo_mci_init(void)
1022 {
1023         spin_lock_init(&clock_lock);
1024         platform_driver_register(&glamo_mci_driver);
1025         return 0;
1026 }
1027
1028 static void __exit glamo_mci_exit(void)
1029 {
1030         platform_driver_unregister(&glamo_mci_driver);
1031 }
1032
1033 module_init(glamo_mci_init);
1034 module_exit(glamo_mci_exit);
1035
1036 MODULE_DESCRIPTION("Glamo MMC/SD Card Interface driver");
1037 MODULE_LICENSE("GPL");
1038 MODULE_AUTHOR("Andy Green <andy@openmoko.com>");