adb0edf2c8b02cb563bfc72fcfddb4922dceb125
[kernel.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2  * Copyright (c) 2008-2009 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19 #include "btcoex.h"
20
21 static char *dev_info = "ath9k";
22
23 MODULE_AUTHOR("Atheros Communications");
24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26 MODULE_LICENSE("Dual BSD/GPL");
27
28 static int modparam_nohwcrypt;
29 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31
32 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
33 module_param_named(debug, ath9k_debug, uint, 0);
34 MODULE_PARM_DESC(debug, "Debugging mask");
35
36 /* We use the hw_value as an index into our private channel structure */
37
38 #define CHAN2G(_freq, _idx)  { \
39         .center_freq = (_freq), \
40         .hw_value = (_idx), \
41         .max_power = 20, \
42 }
43
44 #define CHAN5G(_freq, _idx) { \
45         .band = IEEE80211_BAND_5GHZ, \
46         .center_freq = (_freq), \
47         .hw_value = (_idx), \
48         .max_power = 20, \
49 }
50
51 /* Some 2 GHz radios are actually tunable on 2312-2732
52  * on 5 MHz steps, we support the channels which we know
53  * we have calibration data for all cards though to make
54  * this static */
55 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
56         CHAN2G(2412, 0), /* Channel 1 */
57         CHAN2G(2417, 1), /* Channel 2 */
58         CHAN2G(2422, 2), /* Channel 3 */
59         CHAN2G(2427, 3), /* Channel 4 */
60         CHAN2G(2432, 4), /* Channel 5 */
61         CHAN2G(2437, 5), /* Channel 6 */
62         CHAN2G(2442, 6), /* Channel 7 */
63         CHAN2G(2447, 7), /* Channel 8 */
64         CHAN2G(2452, 8), /* Channel 9 */
65         CHAN2G(2457, 9), /* Channel 10 */
66         CHAN2G(2462, 10), /* Channel 11 */
67         CHAN2G(2467, 11), /* Channel 12 */
68         CHAN2G(2472, 12), /* Channel 13 */
69         CHAN2G(2484, 13), /* Channel 14 */
70 };
71
72 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
73  * on 5 MHz steps, we support the channels which we know
74  * we have calibration data for all cards though to make
75  * this static */
76 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
77         /* _We_ call this UNII 1 */
78         CHAN5G(5180, 14), /* Channel 36 */
79         CHAN5G(5200, 15), /* Channel 40 */
80         CHAN5G(5220, 16), /* Channel 44 */
81         CHAN5G(5240, 17), /* Channel 48 */
82         /* _We_ call this UNII 2 */
83         CHAN5G(5260, 18), /* Channel 52 */
84         CHAN5G(5280, 19), /* Channel 56 */
85         CHAN5G(5300, 20), /* Channel 60 */
86         CHAN5G(5320, 21), /* Channel 64 */
87         /* _We_ call this "Middle band" */
88         CHAN5G(5500, 22), /* Channel 100 */
89         CHAN5G(5520, 23), /* Channel 104 */
90         CHAN5G(5540, 24), /* Channel 108 */
91         CHAN5G(5560, 25), /* Channel 112 */
92         CHAN5G(5580, 26), /* Channel 116 */
93         CHAN5G(5600, 27), /* Channel 120 */
94         CHAN5G(5620, 28), /* Channel 124 */
95         CHAN5G(5640, 29), /* Channel 128 */
96         CHAN5G(5660, 30), /* Channel 132 */
97         CHAN5G(5680, 31), /* Channel 136 */
98         CHAN5G(5700, 32), /* Channel 140 */
99         /* _We_ call this UNII 3 */
100         CHAN5G(5745, 33), /* Channel 149 */
101         CHAN5G(5765, 34), /* Channel 153 */
102         CHAN5G(5785, 35), /* Channel 157 */
103         CHAN5G(5805, 36), /* Channel 161 */
104         CHAN5G(5825, 37), /* Channel 165 */
105 };
106
107 /* Atheros hardware rate code addition for short premble */
108 #define SHPCHECK(__hw_rate, __flags) \
109         ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
110
111 #define RATE(_bitrate, _hw_rate, _flags) {              \
112         .bitrate        = (_bitrate),                   \
113         .flags          = (_flags),                     \
114         .hw_value       = (_hw_rate),                   \
115         .hw_value_short = (SHPCHECK(_hw_rate, _flags))  \
116 }
117
118 static struct ieee80211_rate ath9k_legacy_rates[] = {
119         RATE(10, 0x1b, 0),
120         RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
121         RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
122         RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
123         RATE(60, 0x0b, 0),
124         RATE(90, 0x0f, 0),
125         RATE(120, 0x0a, 0),
126         RATE(180, 0x0e, 0),
127         RATE(240, 0x09, 0),
128         RATE(360, 0x0d, 0),
129         RATE(480, 0x08, 0),
130         RATE(540, 0x0c, 0),
131 };
132
133 static void ath_cache_conf_rate(struct ath_softc *sc,
134                                 struct ieee80211_conf *conf)
135 {
136         switch (conf->channel->band) {
137         case IEEE80211_BAND_2GHZ:
138                 if (conf_is_ht20(conf))
139                         sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
140                 else if (conf_is_ht40_minus(conf))
141                         sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
142                 else if (conf_is_ht40_plus(conf))
143                         sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
144                 else
145                         sc->cur_rate_mode = ATH9K_MODE_11G;
146                 break;
147         case IEEE80211_BAND_5GHZ:
148                 if (conf_is_ht20(conf))
149                         sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
150                 else if (conf_is_ht40_minus(conf))
151                         sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
152                 else if (conf_is_ht40_plus(conf))
153                         sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
154                 else
155                         sc->cur_rate_mode = ATH9K_MODE_11A;
156                 break;
157         default:
158                 BUG_ON(1);
159                 break;
160         }
161 }
162
163 static void ath_update_txpow(struct ath_softc *sc)
164 {
165         struct ath_hw *ah = sc->sc_ah;
166         u32 txpow;
167
168         if (sc->curtxpow != sc->config.txpowlimit) {
169                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
170                 /* read back in case value is clamped */
171                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
172                 sc->curtxpow = txpow;
173         }
174 }
175
176 static u8 parse_mpdudensity(u8 mpdudensity)
177 {
178         /*
179          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
180          *   0 for no restriction
181          *   1 for 1/4 us
182          *   2 for 1/2 us
183          *   3 for 1 us
184          *   4 for 2 us
185          *   5 for 4 us
186          *   6 for 8 us
187          *   7 for 16 us
188          */
189         switch (mpdudensity) {
190         case 0:
191                 return 0;
192         case 1:
193         case 2:
194         case 3:
195                 /* Our lower layer calculations limit our precision to
196                    1 microsecond */
197                 return 1;
198         case 4:
199                 return 2;
200         case 5:
201                 return 4;
202         case 6:
203                 return 8;
204         case 7:
205                 return 16;
206         default:
207                 return 0;
208         }
209 }
210
211 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
212                                                 struct ieee80211_hw *hw)
213 {
214         struct ieee80211_channel *curchan = hw->conf.channel;
215         struct ath9k_channel *channel;
216         u8 chan_idx;
217
218         chan_idx = curchan->hw_value;
219         channel = &sc->sc_ah->channels[chan_idx];
220         ath9k_update_ichannel(sc, hw, channel);
221         return channel;
222 }
223
224 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
225 {
226         unsigned long flags;
227         bool ret;
228
229         spin_lock_irqsave(&sc->sc_pm_lock, flags);
230         ret = ath9k_hw_setpower(sc->sc_ah, mode);
231         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
232
233         return ret;
234 }
235
236 void ath9k_ps_wakeup(struct ath_softc *sc)
237 {
238         unsigned long flags;
239
240         spin_lock_irqsave(&sc->sc_pm_lock, flags);
241         if (++sc->ps_usecount != 1)
242                 goto unlock;
243
244         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
245
246  unlock:
247         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
248 }
249
250 void ath9k_ps_restore(struct ath_softc *sc)
251 {
252         unsigned long flags;
253
254         spin_lock_irqsave(&sc->sc_pm_lock, flags);
255         if (--sc->ps_usecount != 0)
256                 goto unlock;
257
258         if (sc->ps_enabled &&
259             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
260                               SC_OP_WAIT_FOR_CAB |
261                               SC_OP_WAIT_FOR_PSPOLL_DATA |
262                               SC_OP_WAIT_FOR_TX_ACK)))
263                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
264
265  unlock:
266         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
267 }
268
269 /*
270  * Set/change channels.  If the channel is really being changed, it's done
271  * by reseting the chip.  To accomplish this we must first cleanup any pending
272  * DMA, then restart stuff.
273 */
274 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
275                     struct ath9k_channel *hchan)
276 {
277         struct ath_hw *ah = sc->sc_ah;
278         struct ath_common *common = ath9k_hw_common(ah);
279         struct ieee80211_conf *conf = &common->hw->conf;
280         bool fastcc = true, stopped;
281         struct ieee80211_channel *channel = hw->conf.channel;
282         int r;
283
284         if (sc->sc_flags & SC_OP_INVALID)
285                 return -EIO;
286
287         ath9k_ps_wakeup(sc);
288
289         /*
290          * This is only performed if the channel settings have
291          * actually changed.
292          *
293          * To switch channels clear any pending DMA operations;
294          * wait long enough for the RX fifo to drain, reset the
295          * hardware at the new frequency, and then re-enable
296          * the relevant bits of the h/w.
297          */
298         ath9k_hw_set_interrupts(ah, 0);
299         ath_drain_all_txq(sc, false);
300         stopped = ath_stoprecv(sc);
301
302         /* XXX: do not flush receive queue here. We don't want
303          * to flush data frames already in queue because of
304          * changing channel. */
305
306         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
307                 fastcc = false;
308
309         ath_print(common, ATH_DBG_CONFIG,
310                   "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
311                   sc->sc_ah->curchan->channel,
312                   channel->center_freq, conf_is_ht40(conf));
313
314         spin_lock_bh(&sc->sc_resetlock);
315
316         r = ath9k_hw_reset(ah, hchan, fastcc);
317         if (r) {
318                 ath_print(common, ATH_DBG_FATAL,
319                           "Unable to reset channel (%u Mhz) "
320                           "reset status %d\n",
321                           channel->center_freq, r);
322                 spin_unlock_bh(&sc->sc_resetlock);
323                 goto ps_restore;
324         }
325         spin_unlock_bh(&sc->sc_resetlock);
326
327         sc->sc_flags &= ~SC_OP_FULL_RESET;
328
329         if (ath_startrecv(sc) != 0) {
330                 ath_print(common, ATH_DBG_FATAL,
331                           "Unable to restart recv logic\n");
332                 r = -EIO;
333                 goto ps_restore;
334         }
335
336         ath_cache_conf_rate(sc, &hw->conf);
337         ath_update_txpow(sc);
338         ath9k_hw_set_interrupts(ah, sc->imask);
339
340  ps_restore:
341         ath9k_ps_restore(sc);
342         return r;
343 }
344
345 /*
346  *  This routine performs the periodic noise floor calibration function
347  *  that is used to adjust and optimize the chip performance.  This
348  *  takes environmental changes (location, temperature) into account.
349  *  When the task is complete, it reschedules itself depending on the
350  *  appropriate interval that was calculated.
351  */
352 static void ath_ani_calibrate(unsigned long data)
353 {
354         struct ath_softc *sc = (struct ath_softc *)data;
355         struct ath_hw *ah = sc->sc_ah;
356         struct ath_common *common = ath9k_hw_common(ah);
357         bool longcal = false;
358         bool shortcal = false;
359         bool aniflag = false;
360         unsigned int timestamp = jiffies_to_msecs(jiffies);
361         u32 cal_interval, short_cal_interval;
362
363         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
364                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
365
366         /* Only calibrate if awake */
367         if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
368                 goto set_timer;
369
370         ath9k_ps_wakeup(sc);
371
372         /* Long calibration runs independently of short calibration. */
373         if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
374                 longcal = true;
375                 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
376                 common->ani.longcal_timer = timestamp;
377         }
378
379         /* Short calibration applies only while caldone is false */
380         if (!common->ani.caldone) {
381                 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
382                         shortcal = true;
383                         ath_print(common, ATH_DBG_ANI,
384                                   "shortcal @%lu\n", jiffies);
385                         common->ani.shortcal_timer = timestamp;
386                         common->ani.resetcal_timer = timestamp;
387                 }
388         } else {
389                 if ((timestamp - common->ani.resetcal_timer) >=
390                     ATH_RESTART_CALINTERVAL) {
391                         common->ani.caldone = ath9k_hw_reset_calvalid(ah);
392                         if (common->ani.caldone)
393                                 common->ani.resetcal_timer = timestamp;
394                 }
395         }
396
397         /* Verify whether we must check ANI */
398         if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
399                 aniflag = true;
400                 common->ani.checkani_timer = timestamp;
401         }
402
403         /* Skip all processing if there's nothing to do. */
404         if (longcal || shortcal || aniflag) {
405                 /* Call ANI routine if necessary */
406                 if (aniflag)
407                         ath9k_hw_ani_monitor(ah, ah->curchan);
408
409                 /* Perform calibration if necessary */
410                 if (longcal || shortcal) {
411                         common->ani.caldone =
412                                 ath9k_hw_calibrate(ah,
413                                                    ah->curchan,
414                                                    common->rx_chainmask,
415                                                    longcal);
416
417                         if (longcal)
418                                 common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
419                                                                      ah->curchan);
420
421                         ath_print(common, ATH_DBG_ANI,
422                                   " calibrate chan %u/%x nf: %d\n",
423                                   ah->curchan->channel,
424                                   ah->curchan->channelFlags,
425                                   common->ani.noise_floor);
426                 }
427         }
428
429         ath9k_ps_restore(sc);
430
431 set_timer:
432         /*
433         * Set timer interval based on previous results.
434         * The interval must be the shortest necessary to satisfy ANI,
435         * short calibration and long calibration.
436         */
437         cal_interval = ATH_LONG_CALINTERVAL;
438         if (sc->sc_ah->config.enable_ani)
439                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
440         if (!common->ani.caldone)
441                 cal_interval = min(cal_interval, (u32)short_cal_interval);
442
443         mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
444 }
445
446 static void ath_start_ani(struct ath_common *common)
447 {
448         unsigned long timestamp = jiffies_to_msecs(jiffies);
449
450         common->ani.longcal_timer = timestamp;
451         common->ani.shortcal_timer = timestamp;
452         common->ani.checkani_timer = timestamp;
453
454         mod_timer(&common->ani.timer,
455                   jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
456 }
457
458 /*
459  * Update tx/rx chainmask. For legacy association,
460  * hard code chainmask to 1x1, for 11n association, use
461  * the chainmask configuration, for bt coexistence, use
462  * the chainmask configuration even in legacy mode.
463  */
464 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
465 {
466         struct ath_hw *ah = sc->sc_ah;
467         struct ath_common *common = ath9k_hw_common(ah);
468
469         if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
470             (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
471                 common->tx_chainmask = ah->caps.tx_chainmask;
472                 common->rx_chainmask = ah->caps.rx_chainmask;
473         } else {
474                 common->tx_chainmask = 1;
475                 common->rx_chainmask = 1;
476         }
477
478         ath_print(common, ATH_DBG_CONFIG,
479                   "tx chmask: %d, rx chmask: %d\n",
480                   common->tx_chainmask,
481                   common->rx_chainmask);
482 }
483
484 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
485 {
486         struct ath_node *an;
487
488         an = (struct ath_node *)sta->drv_priv;
489
490         if (sc->sc_flags & SC_OP_TXAGGR) {
491                 ath_tx_node_init(sc, an);
492                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
493                                      sta->ht_cap.ampdu_factor);
494                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
495                 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
496         }
497 }
498
499 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
500 {
501         struct ath_node *an = (struct ath_node *)sta->drv_priv;
502
503         if (sc->sc_flags & SC_OP_TXAGGR)
504                 ath_tx_node_cleanup(sc, an);
505 }
506
507 static void ath9k_tasklet(unsigned long data)
508 {
509         struct ath_softc *sc = (struct ath_softc *)data;
510         struct ath_hw *ah = sc->sc_ah;
511         struct ath_common *common = ath9k_hw_common(ah);
512
513         u32 status = sc->intrstatus;
514
515         ath9k_ps_wakeup(sc);
516
517         if (status & ATH9K_INT_FATAL) {
518                 ath_reset(sc, false);
519                 ath9k_ps_restore(sc);
520                 return;
521         }
522
523         if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
524                 spin_lock_bh(&sc->rx.rxflushlock);
525                 ath_rx_tasklet(sc, 0);
526                 spin_unlock_bh(&sc->rx.rxflushlock);
527         }
528
529         if (status & ATH9K_INT_TX)
530                 ath_tx_tasklet(sc);
531
532         if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
533                 /*
534                  * TSF sync does not look correct; remain awake to sync with
535                  * the next Beacon.
536                  */
537                 ath_print(common, ATH_DBG_PS,
538                           "TSFOOR - Sync with next Beacon\n");
539                 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
540         }
541
542         if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
543                 if (status & ATH9K_INT_GENTIMER)
544                         ath_gen_timer_isr(sc->sc_ah);
545
546         /* re-enable hardware interrupt */
547         ath9k_hw_set_interrupts(ah, sc->imask);
548         ath9k_ps_restore(sc);
549 }
550
551 irqreturn_t ath_isr(int irq, void *dev)
552 {
553 #define SCHED_INTR (                            \
554                 ATH9K_INT_FATAL |               \
555                 ATH9K_INT_RXORN |               \
556                 ATH9K_INT_RXEOL |               \
557                 ATH9K_INT_RX |                  \
558                 ATH9K_INT_TX |                  \
559                 ATH9K_INT_BMISS |               \
560                 ATH9K_INT_CST |                 \
561                 ATH9K_INT_TSFOOR |              \
562                 ATH9K_INT_GENTIMER)
563
564         struct ath_softc *sc = dev;
565         struct ath_hw *ah = sc->sc_ah;
566         enum ath9k_int status;
567         bool sched = false;
568
569         /*
570          * The hardware is not ready/present, don't
571          * touch anything. Note this can happen early
572          * on if the IRQ is shared.
573          */
574         if (sc->sc_flags & SC_OP_INVALID)
575                 return IRQ_NONE;
576
577
578         /* shared irq, not for us */
579
580         if (!ath9k_hw_intrpend(ah))
581                 return IRQ_NONE;
582
583         /*
584          * Figure out the reason(s) for the interrupt.  Note
585          * that the hal returns a pseudo-ISR that may include
586          * bits we haven't explicitly enabled so we mask the
587          * value to insure we only process bits we requested.
588          */
589         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
590         status &= sc->imask;    /* discard unasked-for bits */
591
592         /*
593          * If there are no status bits set, then this interrupt was not
594          * for me (should have been caught above).
595          */
596         if (!status)
597                 return IRQ_NONE;
598
599         /* Cache the status */
600         sc->intrstatus = status;
601
602         if (status & SCHED_INTR)
603                 sched = true;
604
605         /*
606          * If a FATAL or RXORN interrupt is received, we have to reset the
607          * chip immediately.
608          */
609         if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
610                 goto chip_reset;
611
612         if (status & ATH9K_INT_SWBA)
613                 tasklet_schedule(&sc->bcon_tasklet);
614
615         if (status & ATH9K_INT_TXURN)
616                 ath9k_hw_updatetxtriglevel(ah, true);
617
618         if (status & ATH9K_INT_MIB) {
619                 /*
620                  * Disable interrupts until we service the MIB
621                  * interrupt; otherwise it will continue to
622                  * fire.
623                  */
624                 ath9k_hw_set_interrupts(ah, 0);
625                 /*
626                  * Let the hal handle the event. We assume
627                  * it will clear whatever condition caused
628                  * the interrupt.
629                  */
630                 ath9k_hw_procmibevent(ah);
631                 ath9k_hw_set_interrupts(ah, sc->imask);
632         }
633
634         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
635                 if (status & ATH9K_INT_TIM_TIMER) {
636                         /* Clear RxAbort bit so that we can
637                          * receive frames */
638                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
639                         ath9k_hw_setrxabort(sc->sc_ah, 0);
640                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
641                 }
642
643 chip_reset:
644
645         ath_debug_stat_interrupt(sc, status);
646
647         if (sched) {
648                 /* turn off every interrupt except SWBA */
649                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
650                 tasklet_schedule(&sc->intr_tq);
651         }
652
653         return IRQ_HANDLED;
654
655 #undef SCHED_INTR
656 }
657
658 static u32 ath_get_extchanmode(struct ath_softc *sc,
659                                struct ieee80211_channel *chan,
660                                enum nl80211_channel_type channel_type)
661 {
662         u32 chanmode = 0;
663
664         switch (chan->band) {
665         case IEEE80211_BAND_2GHZ:
666                 switch(channel_type) {
667                 case NL80211_CHAN_NO_HT:
668                 case NL80211_CHAN_HT20:
669                         chanmode = CHANNEL_G_HT20;
670                         break;
671                 case NL80211_CHAN_HT40PLUS:
672                         chanmode = CHANNEL_G_HT40PLUS;
673                         break;
674                 case NL80211_CHAN_HT40MINUS:
675                         chanmode = CHANNEL_G_HT40MINUS;
676                         break;
677                 }
678                 break;
679         case IEEE80211_BAND_5GHZ:
680                 switch(channel_type) {
681                 case NL80211_CHAN_NO_HT:
682                 case NL80211_CHAN_HT20:
683                         chanmode = CHANNEL_A_HT20;
684                         break;
685                 case NL80211_CHAN_HT40PLUS:
686                         chanmode = CHANNEL_A_HT40PLUS;
687                         break;
688                 case NL80211_CHAN_HT40MINUS:
689                         chanmode = CHANNEL_A_HT40MINUS;
690                         break;
691                 }
692                 break;
693         default:
694                 break;
695         }
696
697         return chanmode;
698 }
699
700 static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
701                            struct ath9k_keyval *hk, const u8 *addr,
702                            bool authenticator)
703 {
704         struct ath_hw *ah = common->ah;
705         const u8 *key_rxmic;
706         const u8 *key_txmic;
707
708         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
709         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
710
711         if (addr == NULL) {
712                 /*
713                  * Group key installation - only two key cache entries are used
714                  * regardless of splitmic capability since group key is only
715                  * used either for TX or RX.
716                  */
717                 if (authenticator) {
718                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
719                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
720                 } else {
721                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
722                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
723                 }
724                 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
725         }
726         if (!common->splitmic) {
727                 /* TX and RX keys share the same key cache entry. */
728                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
729                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
730                 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
731         }
732
733         /* Separate key cache entries for TX and RX */
734
735         /* TX key goes at first index, RX key at +32. */
736         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
737         if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
738                 /* TX MIC entry failed. No need to proceed further */
739                 ath_print(common, ATH_DBG_FATAL,
740                           "Setting TX MIC Key Failed\n");
741                 return 0;
742         }
743
744         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
745         /* XXX delete tx key on failure? */
746         return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
747 }
748
749 static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
750 {
751         int i;
752
753         for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
754                 if (test_bit(i, common->keymap) ||
755                     test_bit(i + 64, common->keymap))
756                         continue; /* At least one part of TKIP key allocated */
757                 if (common->splitmic &&
758                     (test_bit(i + 32, common->keymap) ||
759                      test_bit(i + 64 + 32, common->keymap)))
760                         continue; /* At least one part of TKIP key allocated */
761
762                 /* Found a free slot for a TKIP key */
763                 return i;
764         }
765         return -1;
766 }
767
768 static int ath_reserve_key_cache_slot(struct ath_common *common)
769 {
770         int i;
771
772         /* First, try to find slots that would not be available for TKIP. */
773         if (common->splitmic) {
774                 for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
775                         if (!test_bit(i, common->keymap) &&
776                             (test_bit(i + 32, common->keymap) ||
777                              test_bit(i + 64, common->keymap) ||
778                              test_bit(i + 64 + 32, common->keymap)))
779                                 return i;
780                         if (!test_bit(i + 32, common->keymap) &&
781                             (test_bit(i, common->keymap) ||
782                              test_bit(i + 64, common->keymap) ||
783                              test_bit(i + 64 + 32, common->keymap)))
784                                 return i + 32;
785                         if (!test_bit(i + 64, common->keymap) &&
786                             (test_bit(i , common->keymap) ||
787                              test_bit(i + 32, common->keymap) ||
788                              test_bit(i + 64 + 32, common->keymap)))
789                                 return i + 64;
790                         if (!test_bit(i + 64 + 32, common->keymap) &&
791                             (test_bit(i, common->keymap) ||
792                              test_bit(i + 32, common->keymap) ||
793                              test_bit(i + 64, common->keymap)))
794                                 return i + 64 + 32;
795                 }
796         } else {
797                 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
798                         if (!test_bit(i, common->keymap) &&
799                             test_bit(i + 64, common->keymap))
800                                 return i;
801                         if (test_bit(i, common->keymap) &&
802                             !test_bit(i + 64, common->keymap))
803                                 return i + 64;
804                 }
805         }
806
807         /* No partially used TKIP slots, pick any available slot */
808         for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
809                 /* Do not allow slots that could be needed for TKIP group keys
810                  * to be used. This limitation could be removed if we know that
811                  * TKIP will not be used. */
812                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
813                         continue;
814                 if (common->splitmic) {
815                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
816                                 continue;
817                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
818                                 continue;
819                 }
820
821                 if (!test_bit(i, common->keymap))
822                         return i; /* Found a free slot for a key */
823         }
824
825         /* No free slot found */
826         return -1;
827 }
828
829 static int ath_key_config(struct ath_common *common,
830                           struct ieee80211_vif *vif,
831                           struct ieee80211_sta *sta,
832                           struct ieee80211_key_conf *key)
833 {
834         struct ath_hw *ah = common->ah;
835         struct ath9k_keyval hk;
836         const u8 *mac = NULL;
837         int ret = 0;
838         int idx;
839
840         memset(&hk, 0, sizeof(hk));
841
842         switch (key->alg) {
843         case ALG_WEP:
844                 hk.kv_type = ATH9K_CIPHER_WEP;
845                 break;
846         case ALG_TKIP:
847                 hk.kv_type = ATH9K_CIPHER_TKIP;
848                 break;
849         case ALG_CCMP:
850                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
851                 break;
852         default:
853                 return -EOPNOTSUPP;
854         }
855
856         hk.kv_len = key->keylen;
857         memcpy(hk.kv_val, key->key, key->keylen);
858
859         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
860                 /* For now, use the default keys for broadcast keys. This may
861                  * need to change with virtual interfaces. */
862                 idx = key->keyidx;
863         } else if (key->keyidx) {
864                 if (WARN_ON(!sta))
865                         return -EOPNOTSUPP;
866                 mac = sta->addr;
867
868                 if (vif->type != NL80211_IFTYPE_AP) {
869                         /* Only keyidx 0 should be used with unicast key, but
870                          * allow this for client mode for now. */
871                         idx = key->keyidx;
872                 } else
873                         return -EIO;
874         } else {
875                 if (WARN_ON(!sta))
876                         return -EOPNOTSUPP;
877                 mac = sta->addr;
878
879                 if (key->alg == ALG_TKIP)
880                         idx = ath_reserve_key_cache_slot_tkip(common);
881                 else
882                         idx = ath_reserve_key_cache_slot(common);
883                 if (idx < 0)
884                         return -ENOSPC; /* no free key cache entries */
885         }
886
887         if (key->alg == ALG_TKIP)
888                 ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
889                                       vif->type == NL80211_IFTYPE_AP);
890         else
891                 ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
892
893         if (!ret)
894                 return -EIO;
895
896         set_bit(idx, common->keymap);
897         if (key->alg == ALG_TKIP) {
898                 set_bit(idx + 64, common->keymap);
899                 if (common->splitmic) {
900                         set_bit(idx + 32, common->keymap);
901                         set_bit(idx + 64 + 32, common->keymap);
902                 }
903         }
904
905         return idx;
906 }
907
908 static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
909 {
910         struct ath_hw *ah = common->ah;
911
912         ath9k_hw_keyreset(ah, key->hw_key_idx);
913         if (key->hw_key_idx < IEEE80211_WEP_NKID)
914                 return;
915
916         clear_bit(key->hw_key_idx, common->keymap);
917         if (key->alg != ALG_TKIP)
918                 return;
919
920         clear_bit(key->hw_key_idx + 64, common->keymap);
921         if (common->splitmic) {
922                 clear_bit(key->hw_key_idx + 32, common->keymap);
923                 clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
924         }
925 }
926
927 static void setup_ht_cap(struct ath_softc *sc,
928                          struct ieee80211_sta_ht_cap *ht_info)
929 {
930         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
931         u8 tx_streams, rx_streams;
932
933         ht_info->ht_supported = true;
934         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
935                        IEEE80211_HT_CAP_SM_PS |
936                        IEEE80211_HT_CAP_SGI_40 |
937                        IEEE80211_HT_CAP_DSSSCCK40;
938
939         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
940         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
941
942         /* set up supported mcs set */
943         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
944         tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
945                      1 : 2;
946         rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
947                      1 : 2;
948
949         if (tx_streams != rx_streams) {
950                 ath_print(common, ATH_DBG_CONFIG,
951                           "TX streams %d, RX streams: %d\n",
952                           tx_streams, rx_streams);
953                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
954                 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
955                                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
956         }
957
958         ht_info->mcs.rx_mask[0] = 0xff;
959         if (rx_streams >= 2)
960                 ht_info->mcs.rx_mask[1] = 0xff;
961
962         ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
963 }
964
965 static void ath9k_bss_assoc_info(struct ath_softc *sc,
966                                  struct ieee80211_vif *vif,
967                                  struct ieee80211_bss_conf *bss_conf)
968 {
969         struct ath_hw *ah = sc->sc_ah;
970         struct ath_common *common = ath9k_hw_common(ah);
971
972         if (bss_conf->assoc) {
973                 ath_print(common, ATH_DBG_CONFIG,
974                           "Bss Info ASSOC %d, bssid: %pM\n",
975                            bss_conf->aid, common->curbssid);
976
977                 /* New association, store aid */
978                 common->curaid = bss_conf->aid;
979                 ath9k_hw_write_associd(ah);
980
981                 /*
982                  * Request a re-configuration of Beacon related timers
983                  * on the receipt of the first Beacon frame (i.e.,
984                  * after time sync with the AP).
985                  */
986                 sc->sc_flags |= SC_OP_BEACON_SYNC;
987
988                 /* Configure the beacon */
989                 ath_beacon_config(sc, vif);
990
991                 /* Reset rssi stats */
992                 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
993
994                 ath_start_ani(common);
995         } else {
996                 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
997                 common->curaid = 0;
998                 /* Stop ANI */
999                 del_timer_sync(&common->ani.timer);
1000         }
1001 }
1002
1003 /********************************/
1004 /*       LED functions          */
1005 /********************************/
1006
1007 static void ath_led_blink_work(struct work_struct *work)
1008 {
1009         struct ath_softc *sc = container_of(work, struct ath_softc,
1010                                             ath_led_blink_work.work);
1011
1012         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1013                 return;
1014
1015         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1016             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
1017                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1018         else
1019                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1020                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
1021
1022         ieee80211_queue_delayed_work(sc->hw,
1023                                      &sc->ath_led_blink_work,
1024                                      (sc->sc_flags & SC_OP_LED_ON) ?
1025                                         msecs_to_jiffies(sc->led_off_duration) :
1026                                         msecs_to_jiffies(sc->led_on_duration));
1027
1028         sc->led_on_duration = sc->led_on_cnt ?
1029                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1030                         ATH_LED_ON_DURATION_IDLE;
1031         sc->led_off_duration = sc->led_off_cnt ?
1032                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1033                         ATH_LED_OFF_DURATION_IDLE;
1034         sc->led_on_cnt = sc->led_off_cnt = 0;
1035         if (sc->sc_flags & SC_OP_LED_ON)
1036                 sc->sc_flags &= ~SC_OP_LED_ON;
1037         else
1038                 sc->sc_flags |= SC_OP_LED_ON;
1039 }
1040
1041 static void ath_led_brightness(struct led_classdev *led_cdev,
1042                                enum led_brightness brightness)
1043 {
1044         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1045         struct ath_softc *sc = led->sc;
1046
1047         switch (brightness) {
1048         case LED_OFF:
1049                 if (led->led_type == ATH_LED_ASSOC ||
1050                     led->led_type == ATH_LED_RADIO) {
1051                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1052                                 (led->led_type == ATH_LED_RADIO));
1053                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1054                         if (led->led_type == ATH_LED_RADIO)
1055                                 sc->sc_flags &= ~SC_OP_LED_ON;
1056                 } else {
1057                         sc->led_off_cnt++;
1058                 }
1059                 break;
1060         case LED_FULL:
1061                 if (led->led_type == ATH_LED_ASSOC) {
1062                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1063                         ieee80211_queue_delayed_work(sc->hw,
1064                                                      &sc->ath_led_blink_work, 0);
1065                 } else if (led->led_type == ATH_LED_RADIO) {
1066                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1067                         sc->sc_flags |= SC_OP_LED_ON;
1068                 } else {
1069                         sc->led_on_cnt++;
1070                 }
1071                 break;
1072         default:
1073                 break;
1074         }
1075 }
1076
1077 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1078                             char *trigger)
1079 {
1080         int ret;
1081
1082         led->sc = sc;
1083         led->led_cdev.name = led->name;
1084         led->led_cdev.default_trigger = trigger;
1085         led->led_cdev.brightness_set = ath_led_brightness;
1086
1087         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1088         if (ret)
1089                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1090                           "Failed to register led:%s", led->name);
1091         else
1092                 led->registered = 1;
1093         return ret;
1094 }
1095
1096 static void ath_unregister_led(struct ath_led *led)
1097 {
1098         if (led->registered) {
1099                 led_classdev_unregister(&led->led_cdev);
1100                 led->registered = 0;
1101         }
1102 }
1103
1104 static void ath_deinit_leds(struct ath_softc *sc)
1105 {
1106         ath_unregister_led(&sc->assoc_led);
1107         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1108         ath_unregister_led(&sc->tx_led);
1109         ath_unregister_led(&sc->rx_led);
1110         ath_unregister_led(&sc->radio_led);
1111         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1112 }
1113
1114 static void ath_init_leds(struct ath_softc *sc)
1115 {
1116         char *trigger;
1117         int ret;
1118
1119         if (AR_SREV_9287(sc->sc_ah))
1120                 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1121         else
1122                 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1123
1124         /* Configure gpio 1 for output */
1125         ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1126                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1127         /* LED off, active low */
1128         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1129
1130         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1131
1132         trigger = ieee80211_get_radio_led_name(sc->hw);
1133         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1134                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1135         ret = ath_register_led(sc, &sc->radio_led, trigger);
1136         sc->radio_led.led_type = ATH_LED_RADIO;
1137         if (ret)
1138                 goto fail;
1139
1140         trigger = ieee80211_get_assoc_led_name(sc->hw);
1141         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1142                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1143         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1144         sc->assoc_led.led_type = ATH_LED_ASSOC;
1145         if (ret)
1146                 goto fail;
1147
1148         trigger = ieee80211_get_tx_led_name(sc->hw);
1149         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1150                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1151         ret = ath_register_led(sc, &sc->tx_led, trigger);
1152         sc->tx_led.led_type = ATH_LED_TX;
1153         if (ret)
1154                 goto fail;
1155
1156         trigger = ieee80211_get_rx_led_name(sc->hw);
1157         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1158                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1159         ret = ath_register_led(sc, &sc->rx_led, trigger);
1160         sc->rx_led.led_type = ATH_LED_RX;
1161         if (ret)
1162                 goto fail;
1163
1164         return;
1165
1166 fail:
1167         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1168         ath_deinit_leds(sc);
1169 }
1170
1171 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
1172 {
1173         struct ath_hw *ah = sc->sc_ah;
1174         struct ath_common *common = ath9k_hw_common(ah);
1175         struct ieee80211_channel *channel = hw->conf.channel;
1176         int r;
1177
1178         ath9k_ps_wakeup(sc);
1179         ath9k_hw_configpcipowersave(ah, 0, 0);
1180
1181         if (!ah->curchan)
1182                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1183
1184         spin_lock_bh(&sc->sc_resetlock);
1185         r = ath9k_hw_reset(ah, ah->curchan, false);
1186         if (r) {
1187                 ath_print(common, ATH_DBG_FATAL,
1188                           "Unable to reset channel %u (%uMhz) ",
1189                           "reset status %d\n",
1190                           channel->center_freq, r);
1191         }
1192         spin_unlock_bh(&sc->sc_resetlock);
1193
1194         ath_update_txpow(sc);
1195         if (ath_startrecv(sc) != 0) {
1196                 ath_print(common, ATH_DBG_FATAL,
1197                           "Unable to restart recv logic\n");
1198                 return;
1199         }
1200
1201         if (sc->sc_flags & SC_OP_BEACONS)
1202                 ath_beacon_config(sc, NULL);    /* restart beacons */
1203
1204         /* Re-Enable  interrupts */
1205         ath9k_hw_set_interrupts(ah, sc->imask);
1206
1207         /* Enable LED */
1208         ath9k_hw_cfg_output(ah, ah->led_pin,
1209                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1210         ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1211
1212         ieee80211_wake_queues(hw);
1213         ath9k_ps_restore(sc);
1214 }
1215
1216 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
1217 {
1218         struct ath_hw *ah = sc->sc_ah;
1219         struct ieee80211_channel *channel = hw->conf.channel;
1220         int r;
1221
1222         ath9k_ps_wakeup(sc);
1223         ieee80211_stop_queues(hw);
1224
1225         /* Disable LED */
1226         ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1227         ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1228
1229         /* Disable interrupts */
1230         ath9k_hw_set_interrupts(ah, 0);
1231
1232         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1233         ath_stoprecv(sc);               /* turn off frame recv */
1234         ath_flushrecv(sc);              /* flush recv queue */
1235
1236         if (!ah->curchan)
1237                 ah->curchan = ath_get_curchannel(sc, hw);
1238
1239         spin_lock_bh(&sc->sc_resetlock);
1240         r = ath9k_hw_reset(ah, ah->curchan, false);
1241         if (r) {
1242                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1243                           "Unable to reset channel %u (%uMhz) "
1244                           "reset status %d\n",
1245                           channel->center_freq, r);
1246         }
1247         spin_unlock_bh(&sc->sc_resetlock);
1248
1249         ath9k_hw_phy_disable(ah);
1250         ath9k_hw_configpcipowersave(ah, 1, 1);
1251         ath9k_ps_restore(sc);
1252         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1253 }
1254
1255 /*******************/
1256 /*      Rfkill     */
1257 /*******************/
1258
1259 static bool ath_is_rfkill_set(struct ath_softc *sc)
1260 {
1261         struct ath_hw *ah = sc->sc_ah;
1262
1263         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1264                                   ah->rfkill_polarity;
1265 }
1266
1267 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1268 {
1269         struct ath_wiphy *aphy = hw->priv;
1270         struct ath_softc *sc = aphy->sc;
1271         bool blocked = !!ath_is_rfkill_set(sc);
1272
1273         wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1274 }
1275
1276 static void ath_start_rfkill_poll(struct ath_softc *sc)
1277 {
1278         struct ath_hw *ah = sc->sc_ah;
1279
1280         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1281                 wiphy_rfkill_start_polling(sc->hw->wiphy);
1282 }
1283
1284 static void ath9k_uninit_hw(struct ath_softc *sc)
1285 {
1286         struct ath_hw *ah = sc->sc_ah;
1287
1288         BUG_ON(!ah);
1289
1290         ath9k_exit_debug(ah);
1291         ath9k_hw_detach(ah);
1292         sc->sc_ah = NULL;
1293 }
1294
1295 static void ath_clean_core(struct ath_softc *sc)
1296 {
1297         struct ieee80211_hw *hw = sc->hw;
1298         struct ath_hw *ah = sc->sc_ah;
1299         int i = 0;
1300
1301         ath9k_ps_wakeup(sc);
1302
1303         dev_dbg(sc->dev, "Detach ATH hw\n");
1304
1305         ath_deinit_leds(sc);
1306         wiphy_rfkill_stop_polling(sc->hw->wiphy);
1307
1308         for (i = 0; i < sc->num_sec_wiphy; i++) {
1309                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1310                 if (aphy == NULL)
1311                         continue;
1312                 sc->sec_wiphy[i] = NULL;
1313                 ieee80211_unregister_hw(aphy->hw);
1314                 ieee80211_free_hw(aphy->hw);
1315         }
1316         ieee80211_unregister_hw(hw);
1317         ath_rx_cleanup(sc);
1318         ath_tx_cleanup(sc);
1319
1320         tasklet_kill(&sc->intr_tq);
1321         tasklet_kill(&sc->bcon_tasklet);
1322
1323         if (!(sc->sc_flags & SC_OP_INVALID))
1324                 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1325
1326         /* cleanup tx queues */
1327         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1328                 if (ATH_TXQ_SETUP(sc, i))
1329                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1330
1331         if ((sc->btcoex.no_stomp_timer) &&
1332             ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1333                 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1334 }
1335
1336 void ath_detach(struct ath_softc *sc)
1337 {
1338         ath_clean_core(sc);
1339         ath9k_uninit_hw(sc);
1340 }
1341
1342 void ath_cleanup(struct ath_softc *sc)
1343 {
1344         struct ath_hw *ah = sc->sc_ah;
1345         struct ath_common *common = ath9k_hw_common(ah);
1346
1347         ath_clean_core(sc);
1348         free_irq(sc->irq, sc);
1349         ath_bus_cleanup(common);
1350         kfree(sc->sec_wiphy);
1351         ieee80211_free_hw(sc->hw);
1352
1353         ath9k_uninit_hw(sc);
1354 }
1355
1356 static int ath9k_reg_notifier(struct wiphy *wiphy,
1357                               struct regulatory_request *request)
1358 {
1359         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1360         struct ath_wiphy *aphy = hw->priv;
1361         struct ath_softc *sc = aphy->sc;
1362         struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
1363
1364         return ath_reg_notifier_apply(wiphy, request, reg);
1365 }
1366
1367 /*
1368  * Detects if there is any priority bt traffic
1369  */
1370 static void ath_detect_bt_priority(struct ath_softc *sc)
1371 {
1372         struct ath_btcoex *btcoex = &sc->btcoex;
1373         struct ath_hw *ah = sc->sc_ah;
1374
1375         if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
1376                 btcoex->bt_priority_cnt++;
1377
1378         if (time_after(jiffies, btcoex->bt_priority_time +
1379                         msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1380                 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1381                         ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1382                                   "BT priority traffic detected");
1383                         sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1384                 } else {
1385                         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1386                 }
1387
1388                 btcoex->bt_priority_cnt = 0;
1389                 btcoex->bt_priority_time = jiffies;
1390         }
1391 }
1392
1393 /*
1394  * Configures appropriate weight based on stomp type.
1395  */
1396 static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1397                                   enum ath_stomp_type stomp_type)
1398 {
1399         struct ath_hw *ah = sc->sc_ah;
1400
1401         switch (stomp_type) {
1402         case ATH_BTCOEX_STOMP_ALL:
1403                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1404                                            AR_STOMP_ALL_WLAN_WGHT);
1405                 break;
1406         case ATH_BTCOEX_STOMP_LOW:
1407                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1408                                            AR_STOMP_LOW_WLAN_WGHT);
1409                 break;
1410         case ATH_BTCOEX_STOMP_NONE:
1411                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1412                                            AR_STOMP_NONE_WLAN_WGHT);
1413                 break;
1414         default:
1415                 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1416                           "Invalid Stomptype\n");
1417                 break;
1418         }
1419
1420         ath9k_hw_btcoex_enable(ah);
1421 }
1422
1423 static void ath9k_gen_timer_start(struct ath_hw *ah,
1424                                   struct ath_gen_timer *timer,
1425                                   u32 timer_next,
1426                                   u32 timer_period)
1427 {
1428         struct ath_common *common = ath9k_hw_common(ah);
1429         struct ath_softc *sc = (struct ath_softc *) common->priv;
1430
1431         ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1432
1433         if ((sc->imask & ATH9K_INT_GENTIMER) == 0) {
1434                 ath9k_hw_set_interrupts(ah, 0);
1435                 sc->imask |= ATH9K_INT_GENTIMER;
1436                 ath9k_hw_set_interrupts(ah, sc->imask);
1437         }
1438 }
1439
1440 static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1441 {
1442         struct ath_common *common = ath9k_hw_common(ah);
1443         struct ath_softc *sc = (struct ath_softc *) common->priv;
1444         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1445
1446         ath9k_hw_gen_timer_stop(ah, timer);
1447
1448         /* if no timer is enabled, turn off interrupt mask */
1449         if (timer_table->timer_mask.val == 0) {
1450                 ath9k_hw_set_interrupts(ah, 0);
1451                 sc->imask &= ~ATH9K_INT_GENTIMER;
1452                 ath9k_hw_set_interrupts(ah, sc->imask);
1453         }
1454 }
1455
1456 /*
1457  * This is the master bt coex timer which runs for every
1458  * 45ms, bt traffic will be given priority during 55% of this
1459  * period while wlan gets remaining 45%
1460  */
1461 static void ath_btcoex_period_timer(unsigned long data)
1462 {
1463         struct ath_softc *sc = (struct ath_softc *) data;
1464         struct ath_hw *ah = sc->sc_ah;
1465         struct ath_btcoex *btcoex = &sc->btcoex;
1466
1467         ath_detect_bt_priority(sc);
1468
1469         spin_lock_bh(&btcoex->btcoex_lock);
1470
1471         ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
1472
1473         spin_unlock_bh(&btcoex->btcoex_lock);
1474
1475         if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1476                 if (btcoex->hw_timer_enabled)
1477                         ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
1478
1479                 ath9k_gen_timer_start(ah,
1480                                       btcoex->no_stomp_timer,
1481                                       (ath9k_hw_gettsf32(ah) +
1482                                        btcoex->btcoex_no_stomp),
1483                                        btcoex->btcoex_no_stomp * 10);
1484                 btcoex->hw_timer_enabled = true;
1485         }
1486
1487         mod_timer(&btcoex->period_timer, jiffies +
1488                                   msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1489 }
1490
1491 /*
1492  * Generic tsf based hw timer which configures weight
1493  * registers to time slice between wlan and bt traffic
1494  */
1495 static void ath_btcoex_no_stomp_timer(void *arg)
1496 {
1497         struct ath_softc *sc = (struct ath_softc *)arg;
1498         struct ath_hw *ah = sc->sc_ah;
1499         struct ath_btcoex *btcoex = &sc->btcoex;
1500
1501         ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1502                   "no stomp timer running \n");
1503
1504         spin_lock_bh(&btcoex->btcoex_lock);
1505
1506         if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
1507                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
1508          else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
1509                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
1510
1511         spin_unlock_bh(&btcoex->btcoex_lock);
1512 }
1513
1514 static int ath_init_btcoex_timer(struct ath_softc *sc)
1515 {
1516         struct ath_btcoex *btcoex = &sc->btcoex;
1517
1518         btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1519         btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1520                 btcoex->btcoex_period / 100;
1521
1522         setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1523                         (unsigned long) sc);
1524
1525         spin_lock_init(&btcoex->btcoex_lock);
1526
1527         btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1528                         ath_btcoex_no_stomp_timer,
1529                         ath_btcoex_no_stomp_timer,
1530                         (void *) sc, AR_FIRST_NDP_TIMER);
1531
1532         if (!btcoex->no_stomp_timer)
1533                 return -ENOMEM;
1534
1535         return 0;
1536 }
1537
1538 /*
1539  * Read and write, they both share the same lock. We do this to serialize
1540  * reads and writes on Atheros 802.11n PCI devices only. This is required
1541  * as the FIFO on these devices can only accept sanely 2 requests. After
1542  * that the device goes bananas. Serializing the reads/writes prevents this
1543  * from happening.
1544  */
1545
1546 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1547 {
1548         struct ath_hw *ah = (struct ath_hw *) hw_priv;
1549         struct ath_common *common = ath9k_hw_common(ah);
1550         struct ath_softc *sc = (struct ath_softc *) common->priv;
1551
1552         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1553                 unsigned long flags;
1554                 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1555                 iowrite32(val, sc->mem + reg_offset);
1556                 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1557         } else
1558                 iowrite32(val, sc->mem + reg_offset);
1559 }
1560
1561 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1562 {
1563         struct ath_hw *ah = (struct ath_hw *) hw_priv;
1564         struct ath_common *common = ath9k_hw_common(ah);
1565         struct ath_softc *sc = (struct ath_softc *) common->priv;
1566         u32 val;
1567
1568         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1569                 unsigned long flags;
1570                 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1571                 val = ioread32(sc->mem + reg_offset);
1572                 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1573         } else
1574                 val = ioread32(sc->mem + reg_offset);
1575         return val;
1576 }
1577
1578 static const struct ath_ops ath9k_common_ops = {
1579         .read = ath9k_ioread32,
1580         .write = ath9k_iowrite32,
1581 };
1582
1583 /*
1584  * Initialize and fill ath_softc, ath_sofct is the
1585  * "Software Carrier" struct. Historically it has existed
1586  * to allow the separation between hardware specific
1587  * variables (now in ath_hw) and driver specific variables.
1588  */
1589 static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
1590                           const struct ath_bus_ops *bus_ops)
1591 {
1592         struct ath_hw *ah = NULL;
1593         struct ath_common *common;
1594         int r = 0, i;
1595         int csz = 0;
1596         int qnum;
1597
1598         /* XXX: hardware will not be ready until ath_open() being called */
1599         sc->sc_flags |= SC_OP_INVALID;
1600
1601         spin_lock_init(&sc->wiphy_lock);
1602         spin_lock_init(&sc->sc_resetlock);
1603         spin_lock_init(&sc->sc_serial_rw);
1604         spin_lock_init(&sc->sc_pm_lock);
1605         mutex_init(&sc->mutex);
1606         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1607         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1608                      (unsigned long)sc);
1609
1610         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1611         if (!ah)
1612                 return -ENOMEM;
1613
1614         ah->hw_version.devid = devid;
1615         ah->hw_version.subsysid = subsysid;
1616         sc->sc_ah = ah;
1617
1618         common = ath9k_hw_common(ah);
1619         common->ops = &ath9k_common_ops;
1620         common->bus_ops = bus_ops;
1621         common->ah = ah;
1622         common->hw = sc->hw;
1623         common->priv = sc;
1624         common->debug_mask = ath9k_debug;
1625
1626         /*
1627          * Cache line size is used to size and align various
1628          * structures used to communicate with the hardware.
1629          */
1630         ath_read_cachesize(common, &csz);
1631         /* XXX assert csz is non-zero */
1632         common->cachelsz = csz << 2;    /* convert to bytes */
1633
1634         r = ath9k_hw_init(ah);
1635         if (r) {
1636                 ath_print(common, ATH_DBG_FATAL,
1637                           "Unable to initialize hardware; "
1638                           "initialization status: %d\n", r);
1639                 goto bad_free_hw;
1640         }
1641
1642         if (ath9k_init_debug(ah) < 0) {
1643                 ath_print(common, ATH_DBG_FATAL,
1644                           "Unable to create debugfs files\n");
1645                 goto bad_free_hw;
1646         }
1647
1648         /* Get the hardware key cache size. */
1649         common->keymax = ah->caps.keycache_size;
1650         if (common->keymax > ATH_KEYMAX) {
1651                 ath_print(common, ATH_DBG_ANY,
1652                           "Warning, using only %u entries in %u key cache\n",
1653                           ATH_KEYMAX, common->keymax);
1654                 common->keymax = ATH_KEYMAX;
1655         }
1656
1657         /*
1658          * Reset the key cache since some parts do not
1659          * reset the contents on initial power up.
1660          */
1661         for (i = 0; i < common->keymax; i++)
1662                 ath9k_hw_keyreset(ah, (u16) i);
1663
1664         /* default to MONITOR mode */
1665         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1666
1667         /*
1668          * Allocate hardware transmit queues: one queue for
1669          * beacon frames and one data queue for each QoS
1670          * priority.  Note that the hal handles reseting
1671          * these queues at the needed time.
1672          */
1673         sc->beacon.beaconq = ath9k_hw_beaconq_setup(ah);
1674         if (sc->beacon.beaconq == -1) {
1675                 ath_print(common, ATH_DBG_FATAL,
1676                           "Unable to setup a beacon xmit queue\n");
1677                 r = -EIO;
1678                 goto bad2;
1679         }
1680         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1681         if (sc->beacon.cabq == NULL) {
1682                 ath_print(common, ATH_DBG_FATAL,
1683                           "Unable to setup CAB xmit queue\n");
1684                 r = -EIO;
1685                 goto bad2;
1686         }
1687
1688         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1689         ath_cabq_update(sc);
1690
1691         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1692                 sc->tx.hwq_map[i] = -1;
1693
1694         /* Setup data queues */
1695         /* NB: ensure BK queue is the lowest priority h/w queue */
1696         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1697                 ath_print(common, ATH_DBG_FATAL,
1698                           "Unable to setup xmit queue for BK traffic\n");
1699                 r = -EIO;
1700                 goto bad2;
1701         }
1702
1703         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1704                 ath_print(common, ATH_DBG_FATAL,
1705                           "Unable to setup xmit queue for BE traffic\n");
1706                 r = -EIO;
1707                 goto bad2;
1708         }
1709         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1710                 ath_print(common, ATH_DBG_FATAL,
1711                           "Unable to setup xmit queue for VI traffic\n");
1712                 r = -EIO;
1713                 goto bad2;
1714         }
1715         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1716                 ath_print(common, ATH_DBG_FATAL,
1717                           "Unable to setup xmit queue for VO traffic\n");
1718                 r = -EIO;
1719                 goto bad2;
1720         }
1721
1722         /* Initializes the noise floor to a reasonable default value.
1723          * Later on this will be updated during ANI processing. */
1724
1725         common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1726         setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1727
1728         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1729                                    ATH9K_CIPHER_TKIP, NULL)) {
1730                 /*
1731                  * Whether we should enable h/w TKIP MIC.
1732                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1733                  * report WMM capable, so it's always safe to turn on
1734                  * TKIP MIC in this case.
1735                  */
1736                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1737                                        0, 1, NULL);
1738         }
1739
1740         /*
1741          * Check whether the separate key cache entries
1742          * are required to handle both tx+rx MIC keys.
1743          * With split mic keys the number of stations is limited
1744          * to 27 otherwise 59.
1745          */
1746         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1747                                    ATH9K_CIPHER_TKIP, NULL)
1748             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1749                                       ATH9K_CIPHER_MIC, NULL)
1750             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1751                                       0, NULL))
1752                 common->splitmic = 1;
1753
1754         /* turn on mcast key search if possible */
1755         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1756                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1757                                              1, NULL);
1758
1759         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1760
1761         /* 11n Capabilities */
1762         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1763                 sc->sc_flags |= SC_OP_TXAGGR;
1764                 sc->sc_flags |= SC_OP_RXAGGR;
1765         }
1766
1767         common->tx_chainmask = ah->caps.tx_chainmask;
1768         common->rx_chainmask = ah->caps.rx_chainmask;
1769
1770         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1771         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1772
1773         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1774                 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
1775
1776         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1777
1778         /* initialize beacon slots */
1779         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1780                 sc->beacon.bslot[i] = NULL;
1781                 sc->beacon.bslot_aphy[i] = NULL;
1782         }
1783
1784         /* setup channels and rates */
1785
1786         if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) {
1787                 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1788                 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1789                 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1790                         ARRAY_SIZE(ath9k_2ghz_chantable);
1791                 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
1792                 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
1793                         ARRAY_SIZE(ath9k_legacy_rates);
1794         }
1795
1796         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1797                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1798                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1799                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1800                         ARRAY_SIZE(ath9k_5ghz_chantable);
1801                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1802                         ath9k_legacy_rates + 4;
1803                 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
1804                         ARRAY_SIZE(ath9k_legacy_rates) - 4;
1805         }
1806
1807         switch (ah->btcoex_hw.scheme) {
1808         case ATH_BTCOEX_CFG_NONE:
1809                 break;
1810         case ATH_BTCOEX_CFG_2WIRE:
1811                 ath9k_hw_btcoex_init_2wire(ah);
1812                 break;
1813         case ATH_BTCOEX_CFG_3WIRE:
1814                 ath9k_hw_btcoex_init_3wire(ah);
1815                 r = ath_init_btcoex_timer(sc);
1816                 if (r)
1817                         goto bad2;
1818                 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
1819                 ath9k_hw_init_btcoex_hw(ah, qnum);
1820                 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
1821                 break;
1822         default:
1823                 WARN_ON(1);
1824                 break;
1825         }
1826
1827         return 0;
1828 bad2:
1829         /* cleanup tx queues */
1830         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1831                 if (ATH_TXQ_SETUP(sc, i))
1832                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1833
1834 bad_free_hw:
1835         ath9k_uninit_hw(sc);
1836         return r;
1837 }
1838
1839 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1840 {
1841         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1842                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1843                 IEEE80211_HW_SIGNAL_DBM |
1844                 IEEE80211_HW_AMPDU_AGGREGATION |
1845                 IEEE80211_HW_SUPPORTS_PS |
1846                 IEEE80211_HW_PS_NULLFUNC_STACK |
1847                 IEEE80211_HW_SPECTRUM_MGMT;
1848
1849         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1850                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1851
1852         hw->wiphy->interface_modes =
1853                 BIT(NL80211_IFTYPE_AP) |
1854                 BIT(NL80211_IFTYPE_STATION) |
1855                 BIT(NL80211_IFTYPE_ADHOC) |
1856                 BIT(NL80211_IFTYPE_MESH_POINT);
1857
1858         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
1859
1860         hw->queues = 4;
1861         hw->max_rates = 4;
1862         hw->channel_change_time = 5000;
1863         hw->max_listen_interval = 10;
1864         /* Hardware supports 10 but we use 4 */
1865         hw->max_rate_tries = 4;
1866         hw->sta_data_size = sizeof(struct ath_node);
1867         hw->vif_data_size = sizeof(struct ath_vif);
1868
1869         hw->rate_control_algorithm = "ath9k_rate_control";
1870
1871         if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
1872                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1873                         &sc->sbands[IEEE80211_BAND_2GHZ];
1874         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1875                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1876                         &sc->sbands[IEEE80211_BAND_5GHZ];
1877 }
1878
1879 /* Device driver core initialization */
1880 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
1881                     const struct ath_bus_ops *bus_ops)
1882 {
1883         struct ieee80211_hw *hw = sc->hw;
1884         struct ath_common *common;
1885         struct ath_hw *ah;
1886         int error = 0, i;
1887         struct ath_regulatory *reg;
1888
1889         dev_dbg(sc->dev, "Attach ATH hw\n");
1890
1891         error = ath_init_softc(devid, sc, subsysid, bus_ops);
1892         if (error != 0)
1893                 return error;
1894
1895         ah = sc->sc_ah;
1896         common = ath9k_hw_common(ah);
1897
1898         /* get mac address from hardware and set in mac80211 */
1899
1900         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1901
1902         ath_set_hw_capab(sc, hw);
1903
1904         error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1905                               ath9k_reg_notifier);
1906         if (error)
1907                 return error;
1908
1909         reg = &common->regulatory;
1910
1911         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1912                 if (test_bit(ATH9K_MODE_11G, ah->caps.wireless_modes))
1913                         setup_ht_cap(sc,
1914                                      &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1915                 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1916                         setup_ht_cap(sc,
1917                                      &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1918         }
1919
1920         /* initialize tx/rx engine */
1921         error = ath_tx_init(sc, ATH_TXBUF);
1922         if (error != 0)
1923                 goto error_attach;
1924
1925         error = ath_rx_init(sc, ATH_RXBUF);
1926         if (error != 0)
1927                 goto error_attach;
1928
1929         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1930         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1931         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1932
1933         error = ieee80211_register_hw(hw);
1934
1935         if (!ath_is_world_regd(reg)) {
1936                 error = regulatory_hint(hw->wiphy, reg->alpha2);
1937                 if (error)
1938                         goto error_attach;
1939         }
1940
1941         /* Initialize LED control */
1942         ath_init_leds(sc);
1943
1944         ath_start_rfkill_poll(sc);
1945
1946         return 0;
1947
1948 error_attach:
1949         /* cleanup tx queues */
1950         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1951                 if (ATH_TXQ_SETUP(sc, i))
1952                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1953
1954         ath9k_uninit_hw(sc);
1955
1956         return error;
1957 }
1958
1959 int ath_reset(struct ath_softc *sc, bool retry_tx)
1960 {
1961         struct ath_hw *ah = sc->sc_ah;
1962         struct ath_common *common = ath9k_hw_common(ah);
1963         struct ieee80211_hw *hw = sc->hw;
1964         int r;
1965
1966         ath9k_hw_set_interrupts(ah, 0);
1967         ath_drain_all_txq(sc, retry_tx);
1968         ath_stoprecv(sc);
1969         ath_flushrecv(sc);
1970
1971         spin_lock_bh(&sc->sc_resetlock);
1972         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1973         if (r)
1974                 ath_print(common, ATH_DBG_FATAL,
1975                           "Unable to reset hardware; reset status %d\n", r);
1976         spin_unlock_bh(&sc->sc_resetlock);
1977
1978         if (ath_startrecv(sc) != 0)
1979                 ath_print(common, ATH_DBG_FATAL,
1980                           "Unable to start recv logic\n");
1981
1982         /*
1983          * We may be doing a reset in response to a request
1984          * that changes the channel so update any state that
1985          * might change as a result.
1986          */
1987         ath_cache_conf_rate(sc, &hw->conf);
1988
1989         ath_update_txpow(sc);
1990
1991         if (sc->sc_flags & SC_OP_BEACONS)
1992                 ath_beacon_config(sc, NULL);    /* restart beacons */
1993
1994         ath9k_hw_set_interrupts(ah, sc->imask);
1995
1996         if (retry_tx) {
1997                 int i;
1998                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1999                         if (ATH_TXQ_SETUP(sc, i)) {
2000                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
2001                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
2002                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
2003                         }
2004                 }
2005         }
2006
2007         return r;
2008 }
2009
2010 /*
2011  *  This function will allocate both the DMA descriptor structure, and the
2012  *  buffers it contains.  These are used to contain the descriptors used
2013  *  by the system.
2014 */
2015 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2016                       struct list_head *head, const char *name,
2017                       int nbuf, int ndesc)
2018 {
2019 #define DS2PHYS(_dd, _ds)                                               \
2020         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2021 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
2022 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
2023         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2024         struct ath_desc *ds;
2025         struct ath_buf *bf;
2026         int i, bsize, error;
2027
2028         ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2029                   name, nbuf, ndesc);
2030
2031         INIT_LIST_HEAD(head);
2032         /* ath_desc must be a multiple of DWORDs */
2033         if ((sizeof(struct ath_desc) % 4) != 0) {
2034                 ath_print(common, ATH_DBG_FATAL,
2035                           "ath_desc not DWORD aligned\n");
2036                 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
2037                 error = -ENOMEM;
2038                 goto fail;
2039         }
2040
2041         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2042
2043         /*
2044          * Need additional DMA memory because we can't use
2045          * descriptors that cross the 4K page boundary. Assume
2046          * one skipped descriptor per 4K page.
2047          */
2048         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2049                 u32 ndesc_skipped =
2050                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
2051                 u32 dma_len;
2052
2053                 while (ndesc_skipped) {
2054                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
2055                         dd->dd_desc_len += dma_len;
2056
2057                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2058                 };
2059         }
2060
2061         /* allocate descriptors */
2062         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2063                                          &dd->dd_desc_paddr, GFP_KERNEL);
2064         if (dd->dd_desc == NULL) {
2065                 error = -ENOMEM;
2066                 goto fail;
2067         }
2068         ds = dd->dd_desc;
2069         ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2070                   name, ds, (u32) dd->dd_desc_len,
2071                   ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
2072
2073         /* allocate buffers */
2074         bsize = sizeof(struct ath_buf) * nbuf;
2075         bf = kzalloc(bsize, GFP_KERNEL);
2076         if (bf == NULL) {
2077                 error = -ENOMEM;
2078                 goto fail2;
2079         }
2080         dd->dd_bufptr = bf;
2081
2082         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2083                 bf->bf_desc = ds;
2084                 bf->bf_daddr = DS2PHYS(dd, ds);
2085
2086                 if (!(sc->sc_ah->caps.hw_caps &
2087                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2088                         /*
2089                          * Skip descriptor addresses which can cause 4KB
2090                          * boundary crossing (addr + length) with a 32 dword
2091                          * descriptor fetch.
2092                          */
2093                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
2094                                 BUG_ON((caddr_t) bf->bf_desc >=
2095                                        ((caddr_t) dd->dd_desc +
2096                                         dd->dd_desc_len));
2097
2098                                 ds += ndesc;
2099                                 bf->bf_desc = ds;
2100                                 bf->bf_daddr = DS2PHYS(dd, ds);
2101                         }
2102                 }
2103                 list_add_tail(&bf->list, head);
2104         }
2105         return 0;
2106 fail2:
2107         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2108                           dd->dd_desc_paddr);
2109 fail:
2110         memset(dd, 0, sizeof(*dd));
2111         return error;
2112 #undef ATH_DESC_4KB_BOUND_CHECK
2113 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2114 #undef DS2PHYS
2115 }
2116
2117 void ath_descdma_cleanup(struct ath_softc *sc,
2118                          struct ath_descdma *dd,
2119                          struct list_head *head)
2120 {
2121         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2122                           dd->dd_desc_paddr);
2123
2124         INIT_LIST_HEAD(head);
2125         kfree(dd->dd_bufptr);
2126         memset(dd, 0, sizeof(*dd));
2127 }
2128
2129 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2130 {
2131         int qnum;
2132
2133         switch (queue) {
2134         case 0:
2135                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
2136                 break;
2137         case 1:
2138                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
2139                 break;
2140         case 2:
2141                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2142                 break;
2143         case 3:
2144                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
2145                 break;
2146         default:
2147                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2148                 break;
2149         }
2150
2151         return qnum;
2152 }
2153
2154 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2155 {
2156         int qnum;
2157
2158         switch (queue) {
2159         case ATH9K_WME_AC_VO:
2160                 qnum = 0;
2161                 break;
2162         case ATH9K_WME_AC_VI:
2163                 qnum = 1;
2164                 break;
2165         case ATH9K_WME_AC_BE:
2166                 qnum = 2;
2167                 break;
2168         case ATH9K_WME_AC_BK:
2169                 qnum = 3;
2170                 break;
2171         default:
2172                 qnum = -1;
2173                 break;
2174         }
2175
2176         return qnum;
2177 }
2178
2179 /* XXX: Remove me once we don't depend on ath9k_channel for all
2180  * this redundant data */
2181 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2182                            struct ath9k_channel *ichan)
2183 {
2184         struct ieee80211_channel *chan = hw->conf.channel;
2185         struct ieee80211_conf *conf = &hw->conf;
2186
2187         ichan->channel = chan->center_freq;
2188         ichan->chan = chan;
2189
2190         if (chan->band == IEEE80211_BAND_2GHZ) {
2191                 ichan->chanmode = CHANNEL_G;
2192                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
2193         } else {
2194                 ichan->chanmode = CHANNEL_A;
2195                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2196         }
2197
2198         if (conf_is_ht(conf))
2199                 ichan->chanmode = ath_get_extchanmode(sc, chan,
2200                                             conf->channel_type);
2201 }
2202
2203 /**********************/
2204 /* mac80211 callbacks */
2205 /**********************/
2206
2207 /*
2208  * (Re)start btcoex timers
2209  */
2210 static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2211 {
2212         struct ath_btcoex *btcoex = &sc->btcoex;
2213         struct ath_hw *ah = sc->sc_ah;
2214
2215         ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2216                   "Starting btcoex timers");
2217
2218         /* make sure duty cycle timer is also stopped when resuming */
2219         if (btcoex->hw_timer_enabled)
2220                 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2221
2222         btcoex->bt_priority_cnt = 0;
2223         btcoex->bt_priority_time = jiffies;
2224         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2225
2226         mod_timer(&btcoex->period_timer, jiffies);
2227 }
2228
2229 static int ath9k_start(struct ieee80211_hw *hw)
2230 {
2231         struct ath_wiphy *aphy = hw->priv;
2232         struct ath_softc *sc = aphy->sc;
2233         struct ath_hw *ah = sc->sc_ah;
2234         struct ath_common *common = ath9k_hw_common(ah);
2235         struct ieee80211_channel *curchan = hw->conf.channel;
2236         struct ath9k_channel *init_channel;
2237         int r;
2238
2239         ath_print(common, ATH_DBG_CONFIG,
2240                   "Starting driver with initial channel: %d MHz\n",
2241                   curchan->center_freq);
2242
2243         mutex_lock(&sc->mutex);
2244
2245         if (ath9k_wiphy_started(sc)) {
2246                 if (sc->chan_idx == curchan->hw_value) {
2247                         /*
2248                          * Already on the operational channel, the new wiphy
2249                          * can be marked active.
2250                          */
2251                         aphy->state = ATH_WIPHY_ACTIVE;
2252                         ieee80211_wake_queues(hw);
2253                 } else {
2254                         /*
2255                          * Another wiphy is on another channel, start the new
2256                          * wiphy in paused state.
2257                          */
2258                         aphy->state = ATH_WIPHY_PAUSED;
2259                         ieee80211_stop_queues(hw);
2260                 }
2261                 mutex_unlock(&sc->mutex);
2262                 return 0;
2263         }
2264         aphy->state = ATH_WIPHY_ACTIVE;
2265
2266         /* setup initial channel */
2267
2268         sc->chan_idx = curchan->hw_value;
2269
2270         init_channel = ath_get_curchannel(sc, hw);
2271
2272         /* Reset SERDES registers */
2273         ath9k_hw_configpcipowersave(ah, 0, 0);
2274
2275         /*
2276          * The basic interface to setting the hardware in a good
2277          * state is ``reset''.  On return the hardware is known to
2278          * be powered up and with interrupts disabled.  This must
2279          * be followed by initialization of the appropriate bits
2280          * and then setup of the interrupt mask.
2281          */
2282         spin_lock_bh(&sc->sc_resetlock);
2283         r = ath9k_hw_reset(ah, init_channel, false);
2284         if (r) {
2285                 ath_print(common, ATH_DBG_FATAL,
2286                           "Unable to reset hardware; reset status %d "
2287                           "(freq %u MHz)\n", r,
2288                           curchan->center_freq);
2289                 spin_unlock_bh(&sc->sc_resetlock);
2290                 goto mutex_unlock;
2291         }
2292         spin_unlock_bh(&sc->sc_resetlock);
2293
2294         /*
2295          * This is needed only to setup initial state
2296          * but it's best done after a reset.
2297          */
2298         ath_update_txpow(sc);
2299
2300         /*
2301          * Setup the hardware after reset:
2302          * The receive engine is set going.
2303          * Frame transmit is handled entirely
2304          * in the frame output path; there's nothing to do
2305          * here except setup the interrupt mask.
2306          */
2307         if (ath_startrecv(sc) != 0) {
2308                 ath_print(common, ATH_DBG_FATAL,
2309                           "Unable to start recv logic\n");
2310                 r = -EIO;
2311                 goto mutex_unlock;
2312         }
2313
2314         /* Setup our intr mask. */
2315         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2316                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2317                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2318
2319         if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2320                 sc->imask |= ATH9K_INT_GTT;
2321
2322         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2323                 sc->imask |= ATH9K_INT_CST;
2324
2325         ath_cache_conf_rate(sc, &hw->conf);
2326
2327         sc->sc_flags &= ~SC_OP_INVALID;
2328
2329         /* Disable BMISS interrupt when we're not associated */
2330         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2331         ath9k_hw_set_interrupts(ah, sc->imask);
2332
2333         ieee80211_wake_queues(hw);
2334
2335         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2336
2337         if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2338             !ah->btcoex_hw.enabled) {
2339                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2340                                            AR_STOMP_LOW_WLAN_WGHT);
2341                 ath9k_hw_btcoex_enable(ah);
2342
2343                 if (common->bus_ops->bt_coex_prep)
2344                         common->bus_ops->bt_coex_prep(common);
2345                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2346                         ath9k_btcoex_timer_resume(sc);
2347         }
2348
2349 mutex_unlock:
2350         mutex_unlock(&sc->mutex);
2351
2352         return r;
2353 }
2354
2355 static int ath9k_tx(struct ieee80211_hw *hw,
2356                     struct sk_buff *skb)
2357 {
2358         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2359         struct ath_wiphy *aphy = hw->priv;
2360         struct ath_softc *sc = aphy->sc;
2361         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2362         struct ath_tx_control txctl;
2363         int padpos, padsize;
2364         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2365
2366         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2367                 ath_print(common, ATH_DBG_XMIT,
2368                           "ath9k: %s: TX in unexpected wiphy state "
2369                           "%d\n", wiphy_name(hw->wiphy), aphy->state);
2370                 goto exit;
2371         }
2372
2373         if (sc->ps_enabled) {
2374                 /*
2375                  * mac80211 does not set PM field for normal data frames, so we
2376                  * need to update that based on the current PS mode.
2377                  */
2378                 if (ieee80211_is_data(hdr->frame_control) &&
2379                     !ieee80211_is_nullfunc(hdr->frame_control) &&
2380                     !ieee80211_has_pm(hdr->frame_control)) {
2381                         ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2382                                   "while in PS mode\n");
2383                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2384                 }
2385         }
2386
2387         if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2388                 /*
2389                  * We are using PS-Poll and mac80211 can request TX while in
2390                  * power save mode. Need to wake up hardware for the TX to be
2391                  * completed and if needed, also for RX of buffered frames.
2392                  */
2393                 ath9k_ps_wakeup(sc);
2394                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2395                 if (ieee80211_is_pspoll(hdr->frame_control)) {
2396                         ath_print(common, ATH_DBG_PS,
2397                                   "Sending PS-Poll to pick a buffered frame\n");
2398                         sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2399                 } else {
2400                         ath_print(common, ATH_DBG_PS,
2401                                   "Wake up to complete TX\n");
2402                         sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2403                 }
2404                 /*
2405                  * The actual restore operation will happen only after
2406                  * the sc_flags bit is cleared. We are just dropping
2407                  * the ps_usecount here.
2408                  */
2409                 ath9k_ps_restore(sc);
2410         }
2411
2412         memset(&txctl, 0, sizeof(struct ath_tx_control));
2413
2414         /*
2415          * As a temporary workaround, assign seq# here; this will likely need
2416          * to be cleaned up to work better with Beacon transmission and virtual
2417          * BSSes.
2418          */
2419         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2420                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2421                         sc->tx.seq_no += 0x10;
2422                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2423                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2424         }
2425
2426         /* Add the padding after the header if this is not already done */
2427         padpos = ath9k_cmn_padpos(hdr->frame_control);
2428         padsize = padpos & 3;
2429         if (padsize && skb->len>padpos) {
2430                 if (skb_headroom(skb) < padsize)
2431                         return -1;
2432                 skb_push(skb, padsize);
2433                 memmove(skb->data, skb->data + padsize, padpos);
2434         }
2435
2436         /* Check if a tx queue is available */
2437
2438         txctl.txq = ath_test_get_txq(sc, skb);
2439         if (!txctl.txq)
2440                 goto exit;
2441
2442         ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2443
2444         if (ath_tx_start(hw, skb, &txctl) != 0) {
2445                 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
2446                 goto exit;
2447         }
2448
2449         return 0;
2450 exit:
2451         dev_kfree_skb_any(skb);
2452         return 0;
2453 }
2454
2455 /*
2456  * Pause btcoex timer and bt duty cycle timer
2457  */
2458 static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2459 {
2460         struct ath_btcoex *btcoex = &sc->btcoex;
2461         struct ath_hw *ah = sc->sc_ah;
2462
2463         del_timer_sync(&btcoex->period_timer);
2464
2465         if (btcoex->hw_timer_enabled)
2466                 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
2467
2468         btcoex->hw_timer_enabled = false;
2469 }
2470
2471 static void ath9k_stop(struct ieee80211_hw *hw)
2472 {
2473         struct ath_wiphy *aphy = hw->priv;
2474         struct ath_softc *sc = aphy->sc;
2475         struct ath_hw *ah = sc->sc_ah;
2476         struct ath_common *common = ath9k_hw_common(ah);
2477
2478         mutex_lock(&sc->mutex);
2479
2480         aphy->state = ATH_WIPHY_INACTIVE;
2481
2482         cancel_delayed_work_sync(&sc->ath_led_blink_work);
2483         cancel_delayed_work_sync(&sc->tx_complete_work);
2484
2485         if (!sc->num_sec_wiphy) {
2486                 cancel_delayed_work_sync(&sc->wiphy_work);
2487                 cancel_work_sync(&sc->chan_work);
2488         }
2489
2490         if (sc->sc_flags & SC_OP_INVALID) {
2491                 ath_print(common, ATH_DBG_ANY, "Device not present\n");
2492                 mutex_unlock(&sc->mutex);
2493                 return;
2494         }
2495
2496         if (ath9k_wiphy_started(sc)) {
2497                 mutex_unlock(&sc->mutex);
2498                 return; /* another wiphy still in use */
2499         }
2500
2501         if (ah->btcoex_hw.enabled) {
2502                 ath9k_hw_btcoex_disable(ah);
2503                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2504                         ath9k_btcoex_timer_pause(sc);
2505         }
2506
2507         /* make sure h/w will not generate any interrupt
2508          * before setting the invalid flag. */
2509         ath9k_hw_set_interrupts(ah, 0);
2510
2511         if (!(sc->sc_flags & SC_OP_INVALID)) {
2512                 ath_drain_all_txq(sc, false);
2513                 ath_stoprecv(sc);
2514                 ath9k_hw_phy_disable(ah);
2515         } else
2516                 sc->rx.rxlink = NULL;
2517
2518         /* disable HAL and put h/w to sleep */
2519         ath9k_hw_disable(ah);
2520         ath9k_hw_configpcipowersave(ah, 1, 1);
2521         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
2522
2523         sc->sc_flags |= SC_OP_INVALID;
2524
2525         mutex_unlock(&sc->mutex);
2526
2527         ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
2528 }
2529
2530 static int ath9k_add_interface(struct ieee80211_hw *hw,
2531                                struct ieee80211_if_init_conf *conf)
2532 {
2533         struct ath_wiphy *aphy = hw->priv;
2534         struct ath_softc *sc = aphy->sc;
2535         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2536         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2537         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2538         int ret = 0;
2539
2540         mutex_lock(&sc->mutex);
2541
2542         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2543             sc->nvifs > 0) {
2544                 ret = -ENOBUFS;
2545                 goto out;
2546         }
2547
2548         switch (conf->type) {
2549         case NL80211_IFTYPE_STATION:
2550                 ic_opmode = NL80211_IFTYPE_STATION;
2551                 break;
2552         case NL80211_IFTYPE_ADHOC:
2553         case NL80211_IFTYPE_AP:
2554         case NL80211_IFTYPE_MESH_POINT:
2555                 if (sc->nbcnvifs >= ATH_BCBUF) {
2556                         ret = -ENOBUFS;
2557                         goto out;
2558                 }
2559                 ic_opmode = conf->type;
2560                 break;
2561         default:
2562                 ath_print(common, ATH_DBG_FATAL,
2563                         "Interface type %d not yet supported\n", conf->type);
2564                 ret = -EOPNOTSUPP;
2565                 goto out;
2566         }
2567
2568         ath_print(common, ATH_DBG_CONFIG,
2569                   "Attach a VIF of type: %d\n", ic_opmode);
2570
2571         /* Set the VIF opmode */
2572         avp->av_opmode = ic_opmode;
2573         avp->av_bslot = -1;
2574
2575         sc->nvifs++;
2576
2577         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2578                 ath9k_set_bssid_mask(hw);
2579
2580         if (sc->nvifs > 1)
2581                 goto out; /* skip global settings for secondary vif */
2582
2583         if (ic_opmode == NL80211_IFTYPE_AP) {
2584                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2585                 sc->sc_flags |= SC_OP_TSF_RESET;
2586         }
2587
2588         /* Set the device opmode */
2589         sc->sc_ah->opmode = ic_opmode;
2590
2591         /*
2592          * Enable MIB interrupts when there are hardware phy counters.
2593          * Note we only do this (at the moment) for station mode.
2594          */
2595         if ((conf->type == NL80211_IFTYPE_STATION) ||
2596             (conf->type == NL80211_IFTYPE_ADHOC) ||
2597             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2598                 sc->imask |= ATH9K_INT_MIB;
2599                 sc->imask |= ATH9K_INT_TSFOOR;
2600         }
2601
2602         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2603
2604         if (conf->type == NL80211_IFTYPE_AP    ||
2605             conf->type == NL80211_IFTYPE_ADHOC ||
2606             conf->type == NL80211_IFTYPE_MONITOR)
2607                 ath_start_ani(common);
2608
2609 out:
2610         mutex_unlock(&sc->mutex);
2611         return ret;
2612 }
2613
2614 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2615                                    struct ieee80211_if_init_conf *conf)
2616 {
2617         struct ath_wiphy *aphy = hw->priv;
2618         struct ath_softc *sc = aphy->sc;
2619         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2620         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2621         int i;
2622
2623         ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
2624
2625         mutex_lock(&sc->mutex);
2626
2627         /* Stop ANI */
2628         del_timer_sync(&common->ani.timer);
2629
2630         /* Reclaim beacon resources */
2631         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2632             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2633             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2634                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2635                 ath_beacon_return(sc, avp);
2636         }
2637
2638         sc->sc_flags &= ~SC_OP_BEACONS;
2639
2640         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2641                 if (sc->beacon.bslot[i] == conf->vif) {
2642                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2643                                "slot\n", __func__);
2644                         sc->beacon.bslot[i] = NULL;
2645                         sc->beacon.bslot_aphy[i] = NULL;
2646                 }
2647         }
2648
2649         sc->nvifs--;
2650
2651         mutex_unlock(&sc->mutex);
2652 }
2653
2654 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2655 {
2656         struct ath_wiphy *aphy = hw->priv;
2657         struct ath_softc *sc = aphy->sc;
2658         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2659         struct ieee80211_conf *conf = &hw->conf;
2660         struct ath_hw *ah = sc->sc_ah;
2661         bool disable_radio;
2662
2663         mutex_lock(&sc->mutex);
2664
2665         /*
2666          * Leave this as the first check because we need to turn on the
2667          * radio if it was disabled before prior to processing the rest
2668          * of the changes. Likewise we must only disable the radio towards
2669          * the end.
2670          */
2671         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2672                 bool enable_radio;
2673                 bool all_wiphys_idle;
2674                 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
2675
2676                 spin_lock_bh(&sc->wiphy_lock);
2677                 all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
2678                 ath9k_set_wiphy_idle(aphy, idle);
2679
2680                 if (!idle && all_wiphys_idle)
2681                         enable_radio = true;
2682
2683                 /*
2684                  * After we unlock here its possible another wiphy
2685                  * can be re-renabled so to account for that we will
2686                  * only disable the radio toward the end of this routine
2687                  * if by then all wiphys are still idle.
2688                  */
2689                 spin_unlock_bh(&sc->wiphy_lock);
2690
2691                 if (enable_radio) {
2692                         ath_radio_enable(sc, hw);
2693                         ath_print(common, ATH_DBG_CONFIG,
2694                                   "not-idle: enabling radio\n");
2695                 }
2696         }
2697
2698         /*
2699          * We just prepare to enable PS. We have to wait until our AP has
2700          * ACK'd our null data frame to disable RX otherwise we'll ignore
2701          * those ACKs and end up retransmitting the same null data frames.
2702          * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
2703          */
2704         if (changed & IEEE80211_CONF_CHANGE_PS) {
2705                 if (conf->flags & IEEE80211_CONF_PS) {
2706                         sc->sc_flags |= SC_OP_PS_ENABLED;
2707                         if (!(ah->caps.hw_caps &
2708                               ATH9K_HW_CAP_AUTOSLEEP)) {
2709                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2710                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2711                                         ath9k_hw_set_interrupts(sc->sc_ah,
2712                                                         sc->imask);
2713                                 }
2714                         }
2715                         /*
2716                          * At this point we know hardware has received an ACK
2717                          * of a previously sent null data frame.
2718                          */
2719                         if ((sc->sc_flags & SC_OP_NULLFUNC_COMPLETED)) {
2720                                 sc->sc_flags &= ~SC_OP_NULLFUNC_COMPLETED;
2721                                 sc->ps_enabled = true;
2722                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2723                         }
2724                 } else {
2725                         sc->ps_enabled = false;
2726                         sc->sc_flags &= ~(SC_OP_PS_ENABLED |
2727                                           SC_OP_NULLFUNC_COMPLETED);
2728                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
2729                         if (!(ah->caps.hw_caps &
2730                               ATH9K_HW_CAP_AUTOSLEEP)) {
2731                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2732                                 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2733                                                   SC_OP_WAIT_FOR_CAB |
2734                                                   SC_OP_WAIT_FOR_PSPOLL_DATA |
2735                                                   SC_OP_WAIT_FOR_TX_ACK);
2736                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2737                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2738                                         ath9k_hw_set_interrupts(sc->sc_ah,
2739                                                         sc->imask);
2740                                 }
2741                         }
2742                 }
2743         }
2744
2745         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2746                 struct ieee80211_channel *curchan = hw->conf.channel;
2747                 int pos = curchan->hw_value;
2748
2749                 aphy->chan_idx = pos;
2750                 aphy->chan_is_ht = conf_is_ht(conf);
2751
2752                 if (aphy->state == ATH_WIPHY_SCAN ||
2753                     aphy->state == ATH_WIPHY_ACTIVE)
2754                         ath9k_wiphy_pause_all_forced(sc, aphy);
2755                 else {
2756                         /*
2757                          * Do not change operational channel based on a paused
2758                          * wiphy changes.
2759                          */
2760                         goto skip_chan_change;
2761                 }
2762
2763                 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2764                           curchan->center_freq);
2765
2766                 /* XXX: remove me eventualy */
2767                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2768
2769                 ath_update_chainmask(sc, conf_is_ht(conf));
2770
2771                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2772                         ath_print(common, ATH_DBG_FATAL,
2773                                   "Unable to set channel\n");
2774                         mutex_unlock(&sc->mutex);
2775                         return -EINVAL;
2776                 }
2777         }
2778
2779 skip_chan_change:
2780         if (changed & IEEE80211_CONF_CHANGE_POWER)
2781                 sc->config.txpowlimit = 2 * conf->power_level;
2782
2783         spin_lock_bh(&sc->wiphy_lock);
2784         disable_radio = ath9k_all_wiphys_idle(sc);
2785         spin_unlock_bh(&sc->wiphy_lock);
2786
2787         if (disable_radio) {
2788                 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
2789                 ath_radio_disable(sc, hw);
2790         }
2791
2792         mutex_unlock(&sc->mutex);
2793
2794         return 0;
2795 }
2796
2797 #define SUPPORTED_FILTERS                       \
2798         (FIF_PROMISC_IN_BSS |                   \
2799         FIF_ALLMULTI |                          \
2800         FIF_CONTROL |                           \
2801         FIF_PSPOLL |                            \
2802         FIF_OTHER_BSS |                         \
2803         FIF_BCN_PRBRESP_PROMISC |               \
2804         FIF_FCSFAIL)
2805
2806 /* FIXME: sc->sc_full_reset ? */
2807 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2808                                    unsigned int changed_flags,
2809                                    unsigned int *total_flags,
2810                                    u64 multicast)
2811 {
2812         struct ath_wiphy *aphy = hw->priv;
2813         struct ath_softc *sc = aphy->sc;
2814         u32 rfilt;
2815
2816         changed_flags &= SUPPORTED_FILTERS;
2817         *total_flags &= SUPPORTED_FILTERS;
2818
2819         sc->rx.rxfilter = *total_flags;
2820         ath9k_ps_wakeup(sc);
2821         rfilt = ath_calcrxfilter(sc);
2822         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2823         ath9k_ps_restore(sc);
2824
2825         ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2826                   "Set HW RX filter: 0x%x\n", rfilt);
2827 }
2828
2829 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2830                              struct ieee80211_vif *vif,
2831                              enum sta_notify_cmd cmd,
2832                              struct ieee80211_sta *sta)
2833 {
2834         struct ath_wiphy *aphy = hw->priv;
2835         struct ath_softc *sc = aphy->sc;
2836
2837         switch (cmd) {
2838         case STA_NOTIFY_ADD:
2839                 ath_node_attach(sc, sta);
2840                 break;
2841         case STA_NOTIFY_REMOVE:
2842                 ath_node_detach(sc, sta);
2843                 break;
2844         default:
2845                 break;
2846         }
2847 }
2848
2849 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2850                          const struct ieee80211_tx_queue_params *params)
2851 {
2852         struct ath_wiphy *aphy = hw->priv;
2853         struct ath_softc *sc = aphy->sc;
2854         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2855         struct ath9k_tx_queue_info qi;
2856         int ret = 0, qnum;
2857
2858         if (queue >= WME_NUM_AC)
2859                 return 0;
2860
2861         mutex_lock(&sc->mutex);
2862
2863         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2864
2865         qi.tqi_aifs = params->aifs;
2866         qi.tqi_cwmin = params->cw_min;
2867         qi.tqi_cwmax = params->cw_max;
2868         qi.tqi_burstTime = params->txop;
2869         qnum = ath_get_hal_qnum(queue, sc);
2870
2871         ath_print(common, ATH_DBG_CONFIG,
2872                   "Configure tx [queue/halq] [%d/%d],  "
2873                   "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2874                   queue, qnum, params->aifs, params->cw_min,
2875                   params->cw_max, params->txop);
2876
2877         ret = ath_txq_update(sc, qnum, &qi);
2878         if (ret)
2879                 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
2880
2881         if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
2882                 if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret)
2883                         ath_beaconq_config(sc);
2884
2885         mutex_unlock(&sc->mutex);
2886
2887         return ret;
2888 }
2889
2890 static int ath9k_set_key(struct ieee80211_hw *hw,
2891                          enum set_key_cmd cmd,
2892                          struct ieee80211_vif *vif,
2893                          struct ieee80211_sta *sta,
2894                          struct ieee80211_key_conf *key)
2895 {
2896         struct ath_wiphy *aphy = hw->priv;
2897         struct ath_softc *sc = aphy->sc;
2898         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2899         int ret = 0;
2900
2901         if (modparam_nohwcrypt)
2902                 return -ENOSPC;
2903
2904         mutex_lock(&sc->mutex);
2905         ath9k_ps_wakeup(sc);
2906         ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
2907
2908         switch (cmd) {
2909         case SET_KEY:
2910                 ret = ath_key_config(common, vif, sta, key);
2911                 if (ret >= 0) {
2912                         key->hw_key_idx = ret;
2913                         /* push IV and Michael MIC generation to stack */
2914                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2915                         if (key->alg == ALG_TKIP)
2916                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2917                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2918                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2919                         ret = 0;
2920                 }
2921                 break;
2922         case DISABLE_KEY:
2923                 ath_key_delete(common, key);
2924                 break;
2925         default:
2926                 ret = -EINVAL;
2927         }
2928
2929         ath9k_ps_restore(sc);
2930         mutex_unlock(&sc->mutex);
2931
2932         return ret;
2933 }
2934
2935 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2936                                    struct ieee80211_vif *vif,
2937                                    struct ieee80211_bss_conf *bss_conf,
2938                                    u32 changed)
2939 {
2940         struct ath_wiphy *aphy = hw->priv;
2941         struct ath_softc *sc = aphy->sc;
2942         struct ath_hw *ah = sc->sc_ah;
2943         struct ath_common *common = ath9k_hw_common(ah);
2944         struct ath_vif *avp = (void *)vif->drv_priv;
2945         int error;
2946
2947         mutex_lock(&sc->mutex);
2948
2949         if (changed & BSS_CHANGED_BSSID) {
2950                 /* Set BSSID */
2951                 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2952                 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2953                 common->curaid = 0;
2954                 ath9k_hw_write_associd(ah);
2955
2956                 /* Set aggregation protection mode parameters */
2957                 sc->config.ath_aggr_prot = 0;
2958
2959                 /* Only legacy IBSS for now */
2960                 if (vif->type == NL80211_IFTYPE_ADHOC)
2961                         ath_update_chainmask(sc, 0);
2962
2963                 ath_print(common, ATH_DBG_CONFIG,
2964                           "BSSID: %pM aid: 0x%x\n",
2965                           common->curbssid, common->curaid);
2966
2967                 /* need to reconfigure the beacon */
2968                 sc->sc_flags &= ~SC_OP_BEACONS ;
2969         }
2970
2971         /* Enable transmission of beacons (AP, IBSS, MESH) */
2972         if ((changed & BSS_CHANGED_BEACON) ||
2973             ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
2974                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2975                 error = ath_beacon_alloc(aphy, vif);
2976                 if (!error)
2977                         ath_beacon_config(sc, vif);
2978         }
2979
2980         /* Disable transmission of beacons */
2981         if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
2982                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2983
2984         if (changed & BSS_CHANGED_BEACON_INT) {
2985                 sc->beacon_interval = bss_conf->beacon_int;
2986                 /*
2987                  * In case of AP mode, the HW TSF has to be reset
2988                  * when the beacon interval changes.
2989                  */
2990                 if (vif->type == NL80211_IFTYPE_AP) {
2991                         sc->sc_flags |= SC_OP_TSF_RESET;
2992                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2993                         error = ath_beacon_alloc(aphy, vif);
2994                         if (!error)
2995                                 ath_beacon_config(sc, vif);
2996                 } else {
2997                         ath_beacon_config(sc, vif);
2998                 }
2999         }
3000
3001         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3002                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
3003                           bss_conf->use_short_preamble);
3004                 if (bss_conf->use_short_preamble)
3005                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
3006                 else
3007                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
3008         }
3009
3010         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
3011                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
3012                           bss_conf->use_cts_prot);
3013                 if (bss_conf->use_cts_prot &&
3014                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
3015                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
3016                 else
3017                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
3018         }
3019
3020         if (changed & BSS_CHANGED_ASSOC) {
3021                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
3022                         bss_conf->assoc);
3023                 ath9k_bss_assoc_info(sc, vif, bss_conf);
3024         }
3025
3026         mutex_unlock(&sc->mutex);
3027 }
3028
3029 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
3030 {
3031         u64 tsf;
3032         struct ath_wiphy *aphy = hw->priv;
3033         struct ath_softc *sc = aphy->sc;
3034
3035         mutex_lock(&sc->mutex);
3036         tsf = ath9k_hw_gettsf64(sc->sc_ah);
3037         mutex_unlock(&sc->mutex);
3038
3039         return tsf;
3040 }
3041
3042 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3043 {
3044         struct ath_wiphy *aphy = hw->priv;
3045         struct ath_softc *sc = aphy->sc;
3046
3047         mutex_lock(&sc->mutex);
3048         ath9k_hw_settsf64(sc->sc_ah, tsf);
3049         mutex_unlock(&sc->mutex);
3050 }
3051
3052 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
3053 {
3054         struct ath_wiphy *aphy = hw->priv;
3055         struct ath_softc *sc = aphy->sc;
3056
3057         mutex_lock(&sc->mutex);
3058
3059         ath9k_ps_wakeup(sc);
3060         ath9k_hw_reset_tsf(sc->sc_ah);
3061         ath9k_ps_restore(sc);
3062
3063         mutex_unlock(&sc->mutex);
3064 }
3065
3066 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
3067                               struct ieee80211_vif *vif,
3068                               enum ieee80211_ampdu_mlme_action action,
3069                               struct ieee80211_sta *sta,
3070                               u16 tid, u16 *ssn)
3071 {
3072         struct ath_wiphy *aphy = hw->priv;
3073         struct ath_softc *sc = aphy->sc;
3074         int ret = 0;
3075
3076         switch (action) {
3077         case IEEE80211_AMPDU_RX_START:
3078                 if (!(sc->sc_flags & SC_OP_RXAGGR))
3079                         ret = -ENOTSUPP;
3080                 break;
3081         case IEEE80211_AMPDU_RX_STOP:
3082                 break;
3083         case IEEE80211_AMPDU_TX_START:
3084                 ath_tx_aggr_start(sc, sta, tid, ssn);
3085                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3086                 break;
3087         case IEEE80211_AMPDU_TX_STOP:
3088                 ath_tx_aggr_stop(sc, sta, tid);
3089                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3090                 break;
3091         case IEEE80211_AMPDU_TX_OPERATIONAL:
3092                 ath_tx_aggr_resume(sc, sta, tid);
3093                 break;
3094         default:
3095                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3096                           "Unknown AMPDU action\n");
3097         }
3098
3099         return ret;
3100 }
3101
3102 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3103 {
3104         struct ath_wiphy *aphy = hw->priv;
3105         struct ath_softc *sc = aphy->sc;
3106         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
3107
3108         mutex_lock(&sc->mutex);
3109         if (ath9k_wiphy_scanning(sc)) {
3110                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3111                        "same time\n");
3112                 /*
3113                  * Do not allow the concurrent scanning state for now. This
3114                  * could be improved with scanning control moved into ath9k.
3115                  */
3116                 mutex_unlock(&sc->mutex);
3117                 return;
3118         }
3119
3120         aphy->state = ATH_WIPHY_SCAN;
3121         ath9k_wiphy_pause_all_forced(sc, aphy);
3122         sc->sc_flags |= SC_OP_SCANNING;
3123         del_timer_sync(&common->ani.timer);
3124         mutex_unlock(&sc->mutex);
3125 }
3126
3127 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3128 {
3129         struct ath_wiphy *aphy = hw->priv;
3130         struct ath_softc *sc = aphy->sc;
3131         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
3132
3133         mutex_lock(&sc->mutex);
3134         aphy->state = ATH_WIPHY_ACTIVE;
3135         sc->sc_flags &= ~SC_OP_SCANNING;
3136         sc->sc_flags |= SC_OP_FULL_RESET;
3137         ath_start_ani(common);
3138         ath_beacon_config(sc, NULL);
3139         mutex_unlock(&sc->mutex);
3140 }
3141
3142 struct ieee80211_ops ath9k_ops = {
3143         .tx                 = ath9k_tx,
3144         .start              = ath9k_start,
3145         .stop               = ath9k_stop,
3146         .add_interface      = ath9k_add_interface,
3147         .remove_interface   = ath9k_remove_interface,
3148         .config             = ath9k_config,
3149         .configure_filter   = ath9k_configure_filter,
3150         .sta_notify         = ath9k_sta_notify,
3151         .conf_tx            = ath9k_conf_tx,
3152         .bss_info_changed   = ath9k_bss_info_changed,
3153         .set_key            = ath9k_set_key,
3154         .get_tsf            = ath9k_get_tsf,
3155         .set_tsf            = ath9k_set_tsf,
3156         .reset_tsf          = ath9k_reset_tsf,
3157         .ampdu_action       = ath9k_ampdu_action,
3158         .sw_scan_start      = ath9k_sw_scan_start,
3159         .sw_scan_complete   = ath9k_sw_scan_complete,
3160         .rfkill_poll        = ath9k_rfkill_poll_state,
3161 };
3162
3163 static int __init ath9k_init(void)
3164 {
3165         int error;
3166
3167         /* Register rate control algorithm */
3168         error = ath_rate_control_register();
3169         if (error != 0) {
3170                 printk(KERN_ERR
3171                         "ath9k: Unable to register rate control "
3172                         "algorithm: %d\n",
3173                         error);
3174                 goto err_out;
3175         }
3176
3177         error = ath9k_debug_create_root();
3178         if (error) {
3179                 printk(KERN_ERR
3180                         "ath9k: Unable to create debugfs root: %d\n",
3181                         error);
3182                 goto err_rate_unregister;
3183         }
3184
3185         error = ath_pci_init();
3186         if (error < 0) {
3187                 printk(KERN_ERR
3188                         "ath9k: No PCI devices found, driver not installed.\n");
3189                 error = -ENODEV;
3190                 goto err_remove_root;
3191         }
3192
3193         error = ath_ahb_init();
3194         if (error < 0) {
3195                 error = -ENODEV;
3196                 goto err_pci_exit;
3197         }
3198
3199         return 0;
3200
3201  err_pci_exit:
3202         ath_pci_exit();
3203
3204  err_remove_root:
3205         ath9k_debug_remove_root();
3206  err_rate_unregister:
3207         ath_rate_control_unregister();
3208  err_out:
3209         return error;
3210 }
3211 module_init(ath9k_init);
3212
3213 static void __exit ath9k_exit(void)
3214 {
3215         ath_ahb_exit();
3216         ath_pci_exit();
3217         ath9k_debug_remove_root();
3218         ath_rate_control_unregister();
3219         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
3220 }
3221 module_exit(ath9k_exit);