aa33d741e5e60211c5c8c15c70a7f14647d420e1
[kernel.git] / drivers / net / wireless / b43 / main.c
1 /*
2
3   Broadcom B43 wireless driver
4
5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6   Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7   Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11   SDIO support
12   Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
13
14   Some parts of the code in this file are derived from the ipw2200
15   driver  Copyright(c) 2003 - 2004 Intel Corporation.
16
17   This program is free software; you can redistribute it and/or modify
18   it under the terms of the GNU General Public License as published by
19   the Free Software Foundation; either version 2 of the License, or
20   (at your option) any later version.
21
22   This program is distributed in the hope that it will be useful,
23   but WITHOUT ANY WARRANTY; without even the implied warranty of
24   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
25   GNU General Public License for more details.
26
27   You should have received a copy of the GNU General Public License
28   along with this program; see the file COPYING.  If not, write to
29   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
30   Boston, MA 02110-1301, USA.
31
32 */
33
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/moduleparam.h>
37 #include <linux/if_arp.h>
38 #include <linux/etherdevice.h>
39 #include <linux/firmware.h>
40 #include <linux/wireless.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
43 #include <linux/io.h>
44 #include <linux/dma-mapping.h>
45 #include <asm/unaligned.h>
46
47 #include "b43.h"
48 #include "main.h"
49 #include "debugfs.h"
50 #include "phy_common.h"
51 #include "phy_g.h"
52 #include "phy_n.h"
53 #include "dma.h"
54 #include "pio.h"
55 #include "sysfs.h"
56 #include "xmit.h"
57 #include "lo.h"
58 #include "pcmcia.h"
59 #include "sdio.h"
60 #include <linux/mmc/sdio_func.h>
61
62 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
63 MODULE_AUTHOR("Martin Langer");
64 MODULE_AUTHOR("Stefano Brivio");
65 MODULE_AUTHOR("Michael Buesch");
66 MODULE_AUTHOR("Gábor Stefanik");
67 MODULE_LICENSE("GPL");
68
69 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
70 MODULE_FIRMWARE("b43/ucode11.fw");
71 MODULE_FIRMWARE("b43/ucode13.fw");
72 MODULE_FIRMWARE("b43/ucode14.fw");
73 MODULE_FIRMWARE("b43/ucode15.fw");
74 MODULE_FIRMWARE("b43/ucode5.fw");
75 MODULE_FIRMWARE("b43/ucode9.fw");
76
77 static int modparam_bad_frames_preempt;
78 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
79 MODULE_PARM_DESC(bad_frames_preempt,
80                  "enable(1) / disable(0) Bad Frames Preemption");
81
82 static char modparam_fwpostfix[16];
83 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
84 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
85
86 static int modparam_hwpctl;
87 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
88 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
89
90 static int modparam_nohwcrypt;
91 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
92 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
93
94 static int modparam_hwtkip;
95 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
96 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
97
98 static int modparam_qos = 1;
99 module_param_named(qos, modparam_qos, int, 0444);
100 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
101
102 static int modparam_btcoex = 1;
103 module_param_named(btcoex, modparam_btcoex, int, 0444);
104 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
105
106 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
107 module_param_named(verbose, b43_modparam_verbose, int, 0644);
108 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
109
110 static int modparam_pio;
111 module_param_named(pio, modparam_pio, int, 0444);
112 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
113
114 static const struct ssb_device_id b43_ssb_tbl[] = {
115         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
116         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
117         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
118         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
119         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
120         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
121         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
122         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
123         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
124         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
125         SSB_DEVTABLE_END
126 };
127
128 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
129
130 /* Channel and ratetables are shared for all devices.
131  * They can't be const, because ieee80211 puts some precalculated
132  * data in there. This data is the same for all devices, so we don't
133  * get concurrency issues */
134 #define RATETAB_ENT(_rateid, _flags) \
135         {                                                               \
136                 .bitrate        = B43_RATE_TO_BASE100KBPS(_rateid),     \
137                 .hw_value       = (_rateid),                            \
138                 .flags          = (_flags),                             \
139         }
140
141 /*
142  * NOTE: When changing this, sync with xmit.c's
143  *       b43_plcp_get_bitrate_idx_* functions!
144  */
145 static struct ieee80211_rate __b43_ratetable[] = {
146         RATETAB_ENT(B43_CCK_RATE_1MB, 0),
147         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
148         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
149         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
150         RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
151         RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
152         RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
153         RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
154         RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
155         RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
156         RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
157         RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
158 };
159
160 #define b43_a_ratetable         (__b43_ratetable + 4)
161 #define b43_a_ratetable_size    8
162 #define b43_b_ratetable         (__b43_ratetable + 0)
163 #define b43_b_ratetable_size    4
164 #define b43_g_ratetable         (__b43_ratetable + 0)
165 #define b43_g_ratetable_size    12
166
167 #define CHAN4G(_channel, _freq, _flags) {                       \
168         .band                   = IEEE80211_BAND_2GHZ,          \
169         .center_freq            = (_freq),                      \
170         .hw_value               = (_channel),                   \
171         .flags                  = (_flags),                     \
172         .max_antenna_gain       = 0,                            \
173         .max_power              = 30,                           \
174 }
175 static struct ieee80211_channel b43_2ghz_chantable[] = {
176         CHAN4G(1, 2412, 0),
177         CHAN4G(2, 2417, 0),
178         CHAN4G(3, 2422, 0),
179         CHAN4G(4, 2427, 0),
180         CHAN4G(5, 2432, 0),
181         CHAN4G(6, 2437, 0),
182         CHAN4G(7, 2442, 0),
183         CHAN4G(8, 2447, 0),
184         CHAN4G(9, 2452, 0),
185         CHAN4G(10, 2457, 0),
186         CHAN4G(11, 2462, 0),
187         CHAN4G(12, 2467, 0),
188         CHAN4G(13, 2472, 0),
189         CHAN4G(14, 2484, 0),
190 };
191 #undef CHAN4G
192
193 #define CHAN5G(_channel, _flags) {                              \
194         .band                   = IEEE80211_BAND_5GHZ,          \
195         .center_freq            = 5000 + (5 * (_channel)),      \
196         .hw_value               = (_channel),                   \
197         .flags                  = (_flags),                     \
198         .max_antenna_gain       = 0,                            \
199         .max_power              = 30,                           \
200 }
201 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
202         CHAN5G(32, 0),          CHAN5G(34, 0),
203         CHAN5G(36, 0),          CHAN5G(38, 0),
204         CHAN5G(40, 0),          CHAN5G(42, 0),
205         CHAN5G(44, 0),          CHAN5G(46, 0),
206         CHAN5G(48, 0),          CHAN5G(50, 0),
207         CHAN5G(52, 0),          CHAN5G(54, 0),
208         CHAN5G(56, 0),          CHAN5G(58, 0),
209         CHAN5G(60, 0),          CHAN5G(62, 0),
210         CHAN5G(64, 0),          CHAN5G(66, 0),
211         CHAN5G(68, 0),          CHAN5G(70, 0),
212         CHAN5G(72, 0),          CHAN5G(74, 0),
213         CHAN5G(76, 0),          CHAN5G(78, 0),
214         CHAN5G(80, 0),          CHAN5G(82, 0),
215         CHAN5G(84, 0),          CHAN5G(86, 0),
216         CHAN5G(88, 0),          CHAN5G(90, 0),
217         CHAN5G(92, 0),          CHAN5G(94, 0),
218         CHAN5G(96, 0),          CHAN5G(98, 0),
219         CHAN5G(100, 0),         CHAN5G(102, 0),
220         CHAN5G(104, 0),         CHAN5G(106, 0),
221         CHAN5G(108, 0),         CHAN5G(110, 0),
222         CHAN5G(112, 0),         CHAN5G(114, 0),
223         CHAN5G(116, 0),         CHAN5G(118, 0),
224         CHAN5G(120, 0),         CHAN5G(122, 0),
225         CHAN5G(124, 0),         CHAN5G(126, 0),
226         CHAN5G(128, 0),         CHAN5G(130, 0),
227         CHAN5G(132, 0),         CHAN5G(134, 0),
228         CHAN5G(136, 0),         CHAN5G(138, 0),
229         CHAN5G(140, 0),         CHAN5G(142, 0),
230         CHAN5G(144, 0),         CHAN5G(145, 0),
231         CHAN5G(146, 0),         CHAN5G(147, 0),
232         CHAN5G(148, 0),         CHAN5G(149, 0),
233         CHAN5G(150, 0),         CHAN5G(151, 0),
234         CHAN5G(152, 0),         CHAN5G(153, 0),
235         CHAN5G(154, 0),         CHAN5G(155, 0),
236         CHAN5G(156, 0),         CHAN5G(157, 0),
237         CHAN5G(158, 0),         CHAN5G(159, 0),
238         CHAN5G(160, 0),         CHAN5G(161, 0),
239         CHAN5G(162, 0),         CHAN5G(163, 0),
240         CHAN5G(164, 0),         CHAN5G(165, 0),
241         CHAN5G(166, 0),         CHAN5G(168, 0),
242         CHAN5G(170, 0),         CHAN5G(172, 0),
243         CHAN5G(174, 0),         CHAN5G(176, 0),
244         CHAN5G(178, 0),         CHAN5G(180, 0),
245         CHAN5G(182, 0),         CHAN5G(184, 0),
246         CHAN5G(186, 0),         CHAN5G(188, 0),
247         CHAN5G(190, 0),         CHAN5G(192, 0),
248         CHAN5G(194, 0),         CHAN5G(196, 0),
249         CHAN5G(198, 0),         CHAN5G(200, 0),
250         CHAN5G(202, 0),         CHAN5G(204, 0),
251         CHAN5G(206, 0),         CHAN5G(208, 0),
252         CHAN5G(210, 0),         CHAN5G(212, 0),
253         CHAN5G(214, 0),         CHAN5G(216, 0),
254         CHAN5G(218, 0),         CHAN5G(220, 0),
255         CHAN5G(222, 0),         CHAN5G(224, 0),
256         CHAN5G(226, 0),         CHAN5G(228, 0),
257 };
258
259 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
260         CHAN5G(34, 0),          CHAN5G(36, 0),
261         CHAN5G(38, 0),          CHAN5G(40, 0),
262         CHAN5G(42, 0),          CHAN5G(44, 0),
263         CHAN5G(46, 0),          CHAN5G(48, 0),
264         CHAN5G(52, 0),          CHAN5G(56, 0),
265         CHAN5G(60, 0),          CHAN5G(64, 0),
266         CHAN5G(100, 0),         CHAN5G(104, 0),
267         CHAN5G(108, 0),         CHAN5G(112, 0),
268         CHAN5G(116, 0),         CHAN5G(120, 0),
269         CHAN5G(124, 0),         CHAN5G(128, 0),
270         CHAN5G(132, 0),         CHAN5G(136, 0),
271         CHAN5G(140, 0),         CHAN5G(149, 0),
272         CHAN5G(153, 0),         CHAN5G(157, 0),
273         CHAN5G(161, 0),         CHAN5G(165, 0),
274         CHAN5G(184, 0),         CHAN5G(188, 0),
275         CHAN5G(192, 0),         CHAN5G(196, 0),
276         CHAN5G(200, 0),         CHAN5G(204, 0),
277         CHAN5G(208, 0),         CHAN5G(212, 0),
278         CHAN5G(216, 0),
279 };
280 #undef CHAN5G
281
282 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
283         .band           = IEEE80211_BAND_5GHZ,
284         .channels       = b43_5ghz_nphy_chantable,
285         .n_channels     = ARRAY_SIZE(b43_5ghz_nphy_chantable),
286         .bitrates       = b43_a_ratetable,
287         .n_bitrates     = b43_a_ratetable_size,
288 };
289
290 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
291         .band           = IEEE80211_BAND_5GHZ,
292         .channels       = b43_5ghz_aphy_chantable,
293         .n_channels     = ARRAY_SIZE(b43_5ghz_aphy_chantable),
294         .bitrates       = b43_a_ratetable,
295         .n_bitrates     = b43_a_ratetable_size,
296 };
297
298 static struct ieee80211_supported_band b43_band_2GHz = {
299         .band           = IEEE80211_BAND_2GHZ,
300         .channels       = b43_2ghz_chantable,
301         .n_channels     = ARRAY_SIZE(b43_2ghz_chantable),
302         .bitrates       = b43_g_ratetable,
303         .n_bitrates     = b43_g_ratetable_size,
304 };
305
306 static void b43_wireless_core_exit(struct b43_wldev *dev);
307 static int b43_wireless_core_init(struct b43_wldev *dev);
308 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
309 static int b43_wireless_core_start(struct b43_wldev *dev);
310
311 static int b43_ratelimit(struct b43_wl *wl)
312 {
313         if (!wl || !wl->current_dev)
314                 return 1;
315         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
316                 return 1;
317         /* We are up and running.
318          * Ratelimit the messages to avoid DoS over the net. */
319         return net_ratelimit();
320 }
321
322 void b43info(struct b43_wl *wl, const char *fmt, ...)
323 {
324         va_list args;
325
326         if (b43_modparam_verbose < B43_VERBOSITY_INFO)
327                 return;
328         if (!b43_ratelimit(wl))
329                 return;
330         va_start(args, fmt);
331         printk(KERN_INFO "b43-%s: ",
332                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
333         vprintk(fmt, args);
334         va_end(args);
335 }
336
337 void b43err(struct b43_wl *wl, const char *fmt, ...)
338 {
339         va_list args;
340
341         if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
342                 return;
343         if (!b43_ratelimit(wl))
344                 return;
345         va_start(args, fmt);
346         printk(KERN_ERR "b43-%s ERROR: ",
347                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
348         vprintk(fmt, args);
349         va_end(args);
350 }
351
352 void b43warn(struct b43_wl *wl, const char *fmt, ...)
353 {
354         va_list args;
355
356         if (b43_modparam_verbose < B43_VERBOSITY_WARN)
357                 return;
358         if (!b43_ratelimit(wl))
359                 return;
360         va_start(args, fmt);
361         printk(KERN_WARNING "b43-%s warning: ",
362                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
363         vprintk(fmt, args);
364         va_end(args);
365 }
366
367 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
368 {
369         va_list args;
370
371         if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
372                 return;
373         va_start(args, fmt);
374         printk(KERN_DEBUG "b43-%s debug: ",
375                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
376         vprintk(fmt, args);
377         va_end(args);
378 }
379
380 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
381 {
382         u32 macctl;
383
384         B43_WARN_ON(offset % 4 != 0);
385
386         macctl = b43_read32(dev, B43_MMIO_MACCTL);
387         if (macctl & B43_MACCTL_BE)
388                 val = swab32(val);
389
390         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
391         mmiowb();
392         b43_write32(dev, B43_MMIO_RAM_DATA, val);
393 }
394
395 static inline void b43_shm_control_word(struct b43_wldev *dev,
396                                         u16 routing, u16 offset)
397 {
398         u32 control;
399
400         /* "offset" is the WORD offset. */
401         control = routing;
402         control <<= 16;
403         control |= offset;
404         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
405 }
406
407 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
408 {
409         u32 ret;
410
411         if (routing == B43_SHM_SHARED) {
412                 B43_WARN_ON(offset & 0x0001);
413                 if (offset & 0x0003) {
414                         /* Unaligned access */
415                         b43_shm_control_word(dev, routing, offset >> 2);
416                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
417                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
418                         ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
419
420                         goto out;
421                 }
422                 offset >>= 2;
423         }
424         b43_shm_control_word(dev, routing, offset);
425         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
426 out:
427         return ret;
428 }
429
430 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
431 {
432         u16 ret;
433
434         if (routing == B43_SHM_SHARED) {
435                 B43_WARN_ON(offset & 0x0001);
436                 if (offset & 0x0003) {
437                         /* Unaligned access */
438                         b43_shm_control_word(dev, routing, offset >> 2);
439                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
440
441                         goto out;
442                 }
443                 offset >>= 2;
444         }
445         b43_shm_control_word(dev, routing, offset);
446         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
447 out:
448         return ret;
449 }
450
451 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
452 {
453         if (routing == B43_SHM_SHARED) {
454                 B43_WARN_ON(offset & 0x0001);
455                 if (offset & 0x0003) {
456                         /* Unaligned access */
457                         b43_shm_control_word(dev, routing, offset >> 2);
458                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
459                                     value & 0xFFFF);
460                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
461                         b43_write16(dev, B43_MMIO_SHM_DATA,
462                                     (value >> 16) & 0xFFFF);
463                         return;
464                 }
465                 offset >>= 2;
466         }
467         b43_shm_control_word(dev, routing, offset);
468         b43_write32(dev, B43_MMIO_SHM_DATA, value);
469 }
470
471 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
472 {
473         if (routing == B43_SHM_SHARED) {
474                 B43_WARN_ON(offset & 0x0001);
475                 if (offset & 0x0003) {
476                         /* Unaligned access */
477                         b43_shm_control_word(dev, routing, offset >> 2);
478                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
479                         return;
480                 }
481                 offset >>= 2;
482         }
483         b43_shm_control_word(dev, routing, offset);
484         b43_write16(dev, B43_MMIO_SHM_DATA, value);
485 }
486
487 /* Read HostFlags */
488 u64 b43_hf_read(struct b43_wldev *dev)
489 {
490         u64 ret;
491
492         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
493         ret <<= 16;
494         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
495         ret <<= 16;
496         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
497
498         return ret;
499 }
500
501 /* Write HostFlags */
502 void b43_hf_write(struct b43_wldev *dev, u64 value)
503 {
504         u16 lo, mi, hi;
505
506         lo = (value & 0x00000000FFFFULL);
507         mi = (value & 0x0000FFFF0000ULL) >> 16;
508         hi = (value & 0xFFFF00000000ULL) >> 32;
509         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
510         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
511         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
512 }
513
514 /* Read the firmware capabilities bitmask (Opensource firmware only) */
515 static u16 b43_fwcapa_read(struct b43_wldev *dev)
516 {
517         B43_WARN_ON(!dev->fw.opensource);
518         return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
519 }
520
521 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
522 {
523         u32 low, high;
524
525         B43_WARN_ON(dev->dev->id.revision < 3);
526
527         /* The hardware guarantees us an atomic read, if we
528          * read the low register first. */
529         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
530         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
531
532         *tsf = high;
533         *tsf <<= 32;
534         *tsf |= low;
535 }
536
537 static void b43_time_lock(struct b43_wldev *dev)
538 {
539         u32 macctl;
540
541         macctl = b43_read32(dev, B43_MMIO_MACCTL);
542         macctl |= B43_MACCTL_TBTTHOLD;
543         b43_write32(dev, B43_MMIO_MACCTL, macctl);
544         /* Commit the write */
545         b43_read32(dev, B43_MMIO_MACCTL);
546 }
547
548 static void b43_time_unlock(struct b43_wldev *dev)
549 {
550         u32 macctl;
551
552         macctl = b43_read32(dev, B43_MMIO_MACCTL);
553         macctl &= ~B43_MACCTL_TBTTHOLD;
554         b43_write32(dev, B43_MMIO_MACCTL, macctl);
555         /* Commit the write */
556         b43_read32(dev, B43_MMIO_MACCTL);
557 }
558
559 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
560 {
561         u32 low, high;
562
563         B43_WARN_ON(dev->dev->id.revision < 3);
564
565         low = tsf;
566         high = (tsf >> 32);
567         /* The hardware guarantees us an atomic write, if we
568          * write the low register first. */
569         b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
570         mmiowb();
571         b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
572         mmiowb();
573 }
574
575 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
576 {
577         b43_time_lock(dev);
578         b43_tsf_write_locked(dev, tsf);
579         b43_time_unlock(dev);
580 }
581
582 static
583 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
584 {
585         static const u8 zero_addr[ETH_ALEN] = { 0 };
586         u16 data;
587
588         if (!mac)
589                 mac = zero_addr;
590
591         offset |= 0x0020;
592         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
593
594         data = mac[0];
595         data |= mac[1] << 8;
596         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
597         data = mac[2];
598         data |= mac[3] << 8;
599         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
600         data = mac[4];
601         data |= mac[5] << 8;
602         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
603 }
604
605 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
606 {
607         const u8 *mac;
608         const u8 *bssid;
609         u8 mac_bssid[ETH_ALEN * 2];
610         int i;
611         u32 tmp;
612
613         bssid = dev->wl->bssid;
614         mac = dev->wl->mac_addr;
615
616         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
617
618         memcpy(mac_bssid, mac, ETH_ALEN);
619         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
620
621         /* Write our MAC address and BSSID to template ram */
622         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
623                 tmp = (u32) (mac_bssid[i + 0]);
624                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
625                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
626                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
627                 b43_ram_write(dev, 0x20 + i, tmp);
628         }
629 }
630
631 static void b43_upload_card_macaddress(struct b43_wldev *dev)
632 {
633         b43_write_mac_bssid_templates(dev);
634         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
635 }
636
637 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
638 {
639         /* slot_time is in usec. */
640         /* This test used to exit for all but a G PHY. */
641         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
642                 return;
643         b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
644         /* Shared memory location 0x0010 is the slot time and should be
645          * set to slot_time; however, this register is initially 0 and changing
646          * the value adversely affects the transmit rate for BCM4311
647          * devices. Until this behavior is unterstood, delete this step
648          *
649          * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
650          */
651 }
652
653 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
654 {
655         b43_set_slot_time(dev, 9);
656 }
657
658 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
659 {
660         b43_set_slot_time(dev, 20);
661 }
662
663 /* DummyTransmission function, as documented on
664  * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
665  */
666 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
667 {
668         struct b43_phy *phy = &dev->phy;
669         unsigned int i, max_loop;
670         u16 value;
671         u32 buffer[5] = {
672                 0x00000000,
673                 0x00D40000,
674                 0x00000000,
675                 0x01000000,
676                 0x00000000,
677         };
678
679         if (ofdm) {
680                 max_loop = 0x1E;
681                 buffer[0] = 0x000201CC;
682         } else {
683                 max_loop = 0xFA;
684                 buffer[0] = 0x000B846E;
685         }
686
687         for (i = 0; i < 5; i++)
688                 b43_ram_write(dev, i * 4, buffer[i]);
689
690         b43_write16(dev, 0x0568, 0x0000);
691         if (dev->dev->id.revision < 11)
692                 b43_write16(dev, 0x07C0, 0x0000);
693         else
694                 b43_write16(dev, 0x07C0, 0x0100);
695         value = (ofdm ? 0x41 : 0x40);
696         b43_write16(dev, 0x050C, value);
697         if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
698                 b43_write16(dev, 0x0514, 0x1A02);
699         b43_write16(dev, 0x0508, 0x0000);
700         b43_write16(dev, 0x050A, 0x0000);
701         b43_write16(dev, 0x054C, 0x0000);
702         b43_write16(dev, 0x056A, 0x0014);
703         b43_write16(dev, 0x0568, 0x0826);
704         b43_write16(dev, 0x0500, 0x0000);
705         if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
706                 //SPEC TODO
707         }
708
709         switch (phy->type) {
710         case B43_PHYTYPE_N:
711                 b43_write16(dev, 0x0502, 0x00D0);
712                 break;
713         case B43_PHYTYPE_LP:
714                 b43_write16(dev, 0x0502, 0x0050);
715                 break;
716         default:
717                 b43_write16(dev, 0x0502, 0x0030);
718         }
719
720         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
721                 b43_radio_write16(dev, 0x0051, 0x0017);
722         for (i = 0x00; i < max_loop; i++) {
723                 value = b43_read16(dev, 0x050E);
724                 if (value & 0x0080)
725                         break;
726                 udelay(10);
727         }
728         for (i = 0x00; i < 0x0A; i++) {
729                 value = b43_read16(dev, 0x050E);
730                 if (value & 0x0400)
731                         break;
732                 udelay(10);
733         }
734         for (i = 0x00; i < 0x19; i++) {
735                 value = b43_read16(dev, 0x0690);
736                 if (!(value & 0x0100))
737                         break;
738                 udelay(10);
739         }
740         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
741                 b43_radio_write16(dev, 0x0051, 0x0037);
742 }
743
744 static void key_write(struct b43_wldev *dev,
745                       u8 index, u8 algorithm, const u8 *key)
746 {
747         unsigned int i;
748         u32 offset;
749         u16 value;
750         u16 kidx;
751
752         /* Key index/algo block */
753         kidx = b43_kidx_to_fw(dev, index);
754         value = ((kidx << 4) | algorithm);
755         b43_shm_write16(dev, B43_SHM_SHARED,
756                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
757
758         /* Write the key to the Key Table Pointer offset */
759         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
760         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
761                 value = key[i];
762                 value |= (u16) (key[i + 1]) << 8;
763                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
764         }
765 }
766
767 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
768 {
769         u32 addrtmp[2] = { 0, 0, };
770         u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
771
772         if (b43_new_kidx_api(dev))
773                 pairwise_keys_start = B43_NR_GROUP_KEYS;
774
775         B43_WARN_ON(index < pairwise_keys_start);
776         /* We have four default TX keys and possibly four default RX keys.
777          * Physical mac 0 is mapped to physical key 4 or 8, depending
778          * on the firmware version.
779          * So we must adjust the index here.
780          */
781         index -= pairwise_keys_start;
782         B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
783
784         if (addr) {
785                 addrtmp[0] = addr[0];
786                 addrtmp[0] |= ((u32) (addr[1]) << 8);
787                 addrtmp[0] |= ((u32) (addr[2]) << 16);
788                 addrtmp[0] |= ((u32) (addr[3]) << 24);
789                 addrtmp[1] = addr[4];
790                 addrtmp[1] |= ((u32) (addr[5]) << 8);
791         }
792
793         /* Receive match transmitter address (RCMTA) mechanism */
794         b43_shm_write32(dev, B43_SHM_RCMTA,
795                         (index * 2) + 0, addrtmp[0]);
796         b43_shm_write16(dev, B43_SHM_RCMTA,
797                         (index * 2) + 1, addrtmp[1]);
798 }
799
800 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
801  * When a packet is received, the iv32 is checked.
802  * - if it doesn't the packet is returned without modification (and software
803  *   decryption can be done). That's what happen when iv16 wrap.
804  * - if it does, the rc4 key is computed, and decryption is tried.
805  *   Either it will success and B43_RX_MAC_DEC is returned,
806  *   either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
807  *   and the packet is not usable (it got modified by the ucode).
808  * So in order to never have B43_RX_MAC_DECERR, we should provide
809  * a iv32 and phase1key that match. Because we drop packets in case of
810  * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
811  * packets will be lost without higher layer knowing (ie no resync possible
812  * until next wrap).
813  *
814  * NOTE : this should support 50 key like RCMTA because
815  * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
816  */
817 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
818                 u16 *phase1key)
819 {
820         unsigned int i;
821         u32 offset;
822         u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
823
824         if (!modparam_hwtkip)
825                 return;
826
827         if (b43_new_kidx_api(dev))
828                 pairwise_keys_start = B43_NR_GROUP_KEYS;
829
830         B43_WARN_ON(index < pairwise_keys_start);
831         /* We have four default TX keys and possibly four default RX keys.
832          * Physical mac 0 is mapped to physical key 4 or 8, depending
833          * on the firmware version.
834          * So we must adjust the index here.
835          */
836         index -= pairwise_keys_start;
837         B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
838
839         if (b43_debug(dev, B43_DBG_KEYS)) {
840                 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
841                                 index, iv32);
842         }
843         /* Write the key to the  RX tkip shared mem */
844         offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
845         for (i = 0; i < 10; i += 2) {
846                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
847                                 phase1key ? phase1key[i / 2] : 0);
848         }
849         b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
850         b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
851 }
852
853 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
854                                    struct ieee80211_vif *vif,
855                                    struct ieee80211_key_conf *keyconf,
856                                    struct ieee80211_sta *sta,
857                                    u32 iv32, u16 *phase1key)
858 {
859         struct b43_wl *wl = hw_to_b43_wl(hw);
860         struct b43_wldev *dev;
861         int index = keyconf->hw_key_idx;
862
863         if (B43_WARN_ON(!modparam_hwtkip))
864                 return;
865
866         /* This is only called from the RX path through mac80211, where
867          * our mutex is already locked. */
868         B43_WARN_ON(!mutex_is_locked(&wl->mutex));
869         dev = wl->current_dev;
870         B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
871
872         keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
873
874         rx_tkip_phase1_write(dev, index, iv32, phase1key);
875         /* only pairwise TKIP keys are supported right now */
876         if (WARN_ON(!sta))
877                 return;
878         keymac_write(dev, index, sta->addr);
879 }
880
881 static void do_key_write(struct b43_wldev *dev,
882                          u8 index, u8 algorithm,
883                          const u8 *key, size_t key_len, const u8 *mac_addr)
884 {
885         u8 buf[B43_SEC_KEYSIZE] = { 0, };
886         u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
887
888         if (b43_new_kidx_api(dev))
889                 pairwise_keys_start = B43_NR_GROUP_KEYS;
890
891         B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
892         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
893
894         if (index >= pairwise_keys_start)
895                 keymac_write(dev, index, NULL); /* First zero out mac. */
896         if (algorithm == B43_SEC_ALGO_TKIP) {
897                 /*
898                  * We should provide an initial iv32, phase1key pair.
899                  * We could start with iv32=0 and compute the corresponding
900                  * phase1key, but this means calling ieee80211_get_tkip_key
901                  * with a fake skb (or export other tkip function).
902                  * Because we are lazy we hope iv32 won't start with
903                  * 0xffffffff and let's b43_op_update_tkip_key provide a
904                  * correct pair.
905                  */
906                 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
907         } else if (index >= pairwise_keys_start) /* clear it */
908                 rx_tkip_phase1_write(dev, index, 0, NULL);
909         if (key)
910                 memcpy(buf, key, key_len);
911         key_write(dev, index, algorithm, buf);
912         if (index >= pairwise_keys_start)
913                 keymac_write(dev, index, mac_addr);
914
915         dev->key[index].algorithm = algorithm;
916 }
917
918 static int b43_key_write(struct b43_wldev *dev,
919                          int index, u8 algorithm,
920                          const u8 *key, size_t key_len,
921                          const u8 *mac_addr,
922                          struct ieee80211_key_conf *keyconf)
923 {
924         int i;
925         int pairwise_keys_start;
926
927         /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
928          *      - Temporal Encryption Key (128 bits)
929          *      - Temporal Authenticator Tx MIC Key (64 bits)
930          *      - Temporal Authenticator Rx MIC Key (64 bits)
931          *
932          *      Hardware only store TEK
933          */
934         if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
935                 key_len = 16;
936         if (key_len > B43_SEC_KEYSIZE)
937                 return -EINVAL;
938         for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
939                 /* Check that we don't already have this key. */
940                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
941         }
942         if (index < 0) {
943                 /* Pairwise key. Get an empty slot for the key. */
944                 if (b43_new_kidx_api(dev))
945                         pairwise_keys_start = B43_NR_GROUP_KEYS;
946                 else
947                         pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
948                 for (i = pairwise_keys_start;
949                      i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
950                      i++) {
951                         B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
952                         if (!dev->key[i].keyconf) {
953                                 /* found empty */
954                                 index = i;
955                                 break;
956                         }
957                 }
958                 if (index < 0) {
959                         b43warn(dev->wl, "Out of hardware key memory\n");
960                         return -ENOSPC;
961                 }
962         } else
963                 B43_WARN_ON(index > 3);
964
965         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
966         if ((index <= 3) && !b43_new_kidx_api(dev)) {
967                 /* Default RX key */
968                 B43_WARN_ON(mac_addr);
969                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
970         }
971         keyconf->hw_key_idx = index;
972         dev->key[index].keyconf = keyconf;
973
974         return 0;
975 }
976
977 static int b43_key_clear(struct b43_wldev *dev, int index)
978 {
979         if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
980                 return -EINVAL;
981         do_key_write(dev, index, B43_SEC_ALGO_NONE,
982                      NULL, B43_SEC_KEYSIZE, NULL);
983         if ((index <= 3) && !b43_new_kidx_api(dev)) {
984                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
985                              NULL, B43_SEC_KEYSIZE, NULL);
986         }
987         dev->key[index].keyconf = NULL;
988
989         return 0;
990 }
991
992 static void b43_clear_keys(struct b43_wldev *dev)
993 {
994         int i, count;
995
996         if (b43_new_kidx_api(dev))
997                 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
998         else
999                 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1000         for (i = 0; i < count; i++)
1001                 b43_key_clear(dev, i);
1002 }
1003
1004 static void b43_dump_keymemory(struct b43_wldev *dev)
1005 {
1006         unsigned int i, index, count, offset, pairwise_keys_start;
1007         u8 mac[ETH_ALEN];
1008         u16 algo;
1009         u32 rcmta0;
1010         u16 rcmta1;
1011         u64 hf;
1012         struct b43_key *key;
1013
1014         if (!b43_debug(dev, B43_DBG_KEYS))
1015                 return;
1016
1017         hf = b43_hf_read(dev);
1018         b43dbg(dev->wl, "Hardware key memory dump:  USEDEFKEYS=%u\n",
1019                !!(hf & B43_HF_USEDEFKEYS));
1020         if (b43_new_kidx_api(dev)) {
1021                 pairwise_keys_start = B43_NR_GROUP_KEYS;
1022                 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1023         } else {
1024                 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1025                 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1026         }
1027         for (index = 0; index < count; index++) {
1028                 key = &(dev->key[index]);
1029                 printk(KERN_DEBUG "Key slot %02u: %s",
1030                        index, (key->keyconf == NULL) ? " " : "*");
1031                 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1032                 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1033                         u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1034                         printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1035                 }
1036
1037                 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1038                                       B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1039                 printk("   Algo: %04X/%02X", algo, key->algorithm);
1040
1041                 if (index >= pairwise_keys_start) {
1042                         if (key->algorithm == B43_SEC_ALGO_TKIP) {
1043                                 printk("   TKIP: ");
1044                                 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1045                                 for (i = 0; i < 14; i += 2) {
1046                                         u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1047                                         printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1048                                 }
1049                         }
1050                         rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1051                                                 ((index - pairwise_keys_start) * 2) + 0);
1052                         rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1053                                                 ((index - pairwise_keys_start) * 2) + 1);
1054                         *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1055                         *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1056                         printk("   MAC: %pM", mac);
1057                 } else
1058                         printk("   DEFAULT KEY");
1059                 printk("\n");
1060         }
1061 }
1062
1063 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1064 {
1065         u32 macctl;
1066         u16 ucstat;
1067         bool hwps;
1068         bool awake;
1069         int i;
1070
1071         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1072                     (ps_flags & B43_PS_DISABLED));
1073         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1074
1075         if (ps_flags & B43_PS_ENABLED) {
1076                 hwps = 1;
1077         } else if (ps_flags & B43_PS_DISABLED) {
1078                 hwps = 0;
1079         } else {
1080                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1081                 //      and thus is not an AP and we are associated, set bit 25
1082         }
1083         if (ps_flags & B43_PS_AWAKE) {
1084                 awake = 1;
1085         } else if (ps_flags & B43_PS_ASLEEP) {
1086                 awake = 0;
1087         } else {
1088                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1089                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
1090                 //      successful, set bit26
1091         }
1092
1093 /* FIXME: For now we force awake-on and hwps-off */
1094         hwps = 0;
1095         awake = 1;
1096
1097         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1098         if (hwps)
1099                 macctl |= B43_MACCTL_HWPS;
1100         else
1101                 macctl &= ~B43_MACCTL_HWPS;
1102         if (awake)
1103                 macctl |= B43_MACCTL_AWAKE;
1104         else
1105                 macctl &= ~B43_MACCTL_AWAKE;
1106         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1107         /* Commit write */
1108         b43_read32(dev, B43_MMIO_MACCTL);
1109         if (awake && dev->dev->id.revision >= 5) {
1110                 /* Wait for the microcode to wake up. */
1111                 for (i = 0; i < 100; i++) {
1112                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1113                                                 B43_SHM_SH_UCODESTAT);
1114                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1115                                 break;
1116                         udelay(10);
1117                 }
1118         }
1119 }
1120
1121 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1122 {
1123         u32 tmslow;
1124         u32 macctl;
1125
1126         flags |= B43_TMSLOW_PHYCLKEN;
1127         flags |= B43_TMSLOW_PHYRESET;
1128         ssb_device_enable(dev->dev, flags);
1129         msleep(2);              /* Wait for the PLL to turn on. */
1130
1131         /* Now take the PHY out of Reset again */
1132         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1133         tmslow |= SSB_TMSLOW_FGC;
1134         tmslow &= ~B43_TMSLOW_PHYRESET;
1135         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1136         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
1137         msleep(1);
1138         tmslow &= ~SSB_TMSLOW_FGC;
1139         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1140         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
1141         msleep(1);
1142
1143         /* Turn Analog ON, but only if we already know the PHY-type.
1144          * This protects against very early setup where we don't know the
1145          * PHY-type, yet. wireless_core_reset will be called once again later,
1146          * when we know the PHY-type. */
1147         if (dev->phy.ops)
1148                 dev->phy.ops->switch_analog(dev, 1);
1149
1150         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1151         macctl &= ~B43_MACCTL_GMODE;
1152         if (flags & B43_TMSLOW_GMODE)
1153                 macctl |= B43_MACCTL_GMODE;
1154         macctl |= B43_MACCTL_IHR_ENABLED;
1155         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1156 }
1157
1158 static void handle_irq_transmit_status(struct b43_wldev *dev)
1159 {
1160         u32 v0, v1;
1161         u16 tmp;
1162         struct b43_txstatus stat;
1163
1164         while (1) {
1165                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1166                 if (!(v0 & 0x00000001))
1167                         break;
1168                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1169
1170                 stat.cookie = (v0 >> 16);
1171                 stat.seq = (v1 & 0x0000FFFF);
1172                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1173                 tmp = (v0 & 0x0000FFFF);
1174                 stat.frame_count = ((tmp & 0xF000) >> 12);
1175                 stat.rts_count = ((tmp & 0x0F00) >> 8);
1176                 stat.supp_reason = ((tmp & 0x001C) >> 2);
1177                 stat.pm_indicated = !!(tmp & 0x0080);
1178                 stat.intermediate = !!(tmp & 0x0040);
1179                 stat.for_ampdu = !!(tmp & 0x0020);
1180                 stat.acked = !!(tmp & 0x0002);
1181
1182                 b43_handle_txstatus(dev, &stat);
1183         }
1184 }
1185
1186 static void drain_txstatus_queue(struct b43_wldev *dev)
1187 {
1188         u32 dummy;
1189
1190         if (dev->dev->id.revision < 5)
1191                 return;
1192         /* Read all entries from the microcode TXstatus FIFO
1193          * and throw them away.
1194          */
1195         while (1) {
1196                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1197                 if (!(dummy & 0x00000001))
1198                         break;
1199                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1200         }
1201 }
1202
1203 static u32 b43_jssi_read(struct b43_wldev *dev)
1204 {
1205         u32 val = 0;
1206
1207         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1208         val <<= 16;
1209         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1210
1211         return val;
1212 }
1213
1214 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1215 {
1216         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1217         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1218 }
1219
1220 static void b43_generate_noise_sample(struct b43_wldev *dev)
1221 {
1222         b43_jssi_write(dev, 0x7F7F7F7F);
1223         b43_write32(dev, B43_MMIO_MACCMD,
1224                     b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1225 }
1226
1227 static void b43_calculate_link_quality(struct b43_wldev *dev)
1228 {
1229         /* Top half of Link Quality calculation. */
1230
1231         if (dev->phy.type != B43_PHYTYPE_G)
1232                 return;
1233         if (dev->noisecalc.calculation_running)
1234                 return;
1235         dev->noisecalc.calculation_running = 1;
1236         dev->noisecalc.nr_samples = 0;
1237
1238         b43_generate_noise_sample(dev);
1239 }
1240
1241 static void handle_irq_noise(struct b43_wldev *dev)
1242 {
1243         struct b43_phy_g *phy = dev->phy.g;
1244         u16 tmp;
1245         u8 noise[4];
1246         u8 i, j;
1247         s32 average;
1248
1249         /* Bottom half of Link Quality calculation. */
1250
1251         if (dev->phy.type != B43_PHYTYPE_G)
1252                 return;
1253
1254         /* Possible race condition: It might be possible that the user
1255          * changed to a different channel in the meantime since we
1256          * started the calculation. We ignore that fact, since it's
1257          * not really that much of a problem. The background noise is
1258          * an estimation only anyway. Slightly wrong results will get damped
1259          * by the averaging of the 8 sample rounds. Additionally the
1260          * value is shortlived. So it will be replaced by the next noise
1261          * calculation round soon. */
1262
1263         B43_WARN_ON(!dev->noisecalc.calculation_running);
1264         *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1265         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1266             noise[2] == 0x7F || noise[3] == 0x7F)
1267                 goto generate_new;
1268
1269         /* Get the noise samples. */
1270         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1271         i = dev->noisecalc.nr_samples;
1272         noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1273         noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1274         noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1275         noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1276         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1277         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1278         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1279         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1280         dev->noisecalc.nr_samples++;
1281         if (dev->noisecalc.nr_samples == 8) {
1282                 /* Calculate the Link Quality by the noise samples. */
1283                 average = 0;
1284                 for (i = 0; i < 8; i++) {
1285                         for (j = 0; j < 4; j++)
1286                                 average += dev->noisecalc.samples[i][j];
1287                 }
1288                 average /= (8 * 4);
1289                 average *= 125;
1290                 average += 64;
1291                 average /= 128;
1292                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1293                 tmp = (tmp / 128) & 0x1F;
1294                 if (tmp >= 8)
1295                         average += 2;
1296                 else
1297                         average -= 25;
1298                 if (tmp == 8)
1299                         average -= 72;
1300                 else
1301                         average -= 48;
1302
1303                 dev->stats.link_noise = average;
1304                 dev->noisecalc.calculation_running = 0;
1305                 return;
1306         }
1307 generate_new:
1308         b43_generate_noise_sample(dev);
1309 }
1310
1311 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1312 {
1313         if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1314                 ///TODO: PS TBTT
1315         } else {
1316                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1317                         b43_power_saving_ctl_bits(dev, 0);
1318         }
1319         if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1320                 dev->dfq_valid = 1;
1321 }
1322
1323 static void handle_irq_atim_end(struct b43_wldev *dev)
1324 {
1325         if (dev->dfq_valid) {
1326                 b43_write32(dev, B43_MMIO_MACCMD,
1327                             b43_read32(dev, B43_MMIO_MACCMD)
1328                             | B43_MACCMD_DFQ_VALID);
1329                 dev->dfq_valid = 0;
1330         }
1331 }
1332
1333 static void handle_irq_pmq(struct b43_wldev *dev)
1334 {
1335         u32 tmp;
1336
1337         //TODO: AP mode.
1338
1339         while (1) {
1340                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1341                 if (!(tmp & 0x00000008))
1342                         break;
1343         }
1344         /* 16bit write is odd, but correct. */
1345         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1346 }
1347
1348 static void b43_write_template_common(struct b43_wldev *dev,
1349                                       const u8 *data, u16 size,
1350                                       u16 ram_offset,
1351                                       u16 shm_size_offset, u8 rate)
1352 {
1353         u32 i, tmp;
1354         struct b43_plcp_hdr4 plcp;
1355
1356         plcp.data = 0;
1357         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1358         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1359         ram_offset += sizeof(u32);
1360         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1361          * So leave the first two bytes of the next write blank.
1362          */
1363         tmp = (u32) (data[0]) << 16;
1364         tmp |= (u32) (data[1]) << 24;
1365         b43_ram_write(dev, ram_offset, tmp);
1366         ram_offset += sizeof(u32);
1367         for (i = 2; i < size; i += sizeof(u32)) {
1368                 tmp = (u32) (data[i + 0]);
1369                 if (i + 1 < size)
1370                         tmp |= (u32) (data[i + 1]) << 8;
1371                 if (i + 2 < size)
1372                         tmp |= (u32) (data[i + 2]) << 16;
1373                 if (i + 3 < size)
1374                         tmp |= (u32) (data[i + 3]) << 24;
1375                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1376         }
1377         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1378                         size + sizeof(struct b43_plcp_hdr6));
1379 }
1380
1381 /* Check if the use of the antenna that ieee80211 told us to
1382  * use is possible. This will fall back to DEFAULT.
1383  * "antenna_nr" is the antenna identifier we got from ieee80211. */
1384 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1385                                   u8 antenna_nr)
1386 {
1387         u8 antenna_mask;
1388
1389         if (antenna_nr == 0) {
1390                 /* Zero means "use default antenna". That's always OK. */
1391                 return 0;
1392         }
1393
1394         /* Get the mask of available antennas. */
1395         if (dev->phy.gmode)
1396                 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1397         else
1398                 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1399
1400         if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1401                 /* This antenna is not available. Fall back to default. */
1402                 return 0;
1403         }
1404
1405         return antenna_nr;
1406 }
1407
1408 /* Convert a b43 antenna number value to the PHY TX control value. */
1409 static u16 b43_antenna_to_phyctl(int antenna)
1410 {
1411         switch (antenna) {
1412         case B43_ANTENNA0:
1413                 return B43_TXH_PHY_ANT0;
1414         case B43_ANTENNA1:
1415                 return B43_TXH_PHY_ANT1;
1416         case B43_ANTENNA2:
1417                 return B43_TXH_PHY_ANT2;
1418         case B43_ANTENNA3:
1419                 return B43_TXH_PHY_ANT3;
1420         case B43_ANTENNA_AUTO0:
1421         case B43_ANTENNA_AUTO1:
1422                 return B43_TXH_PHY_ANT01AUTO;
1423         }
1424         B43_WARN_ON(1);
1425         return 0;
1426 }
1427
1428 static void b43_write_beacon_template(struct b43_wldev *dev,
1429                                       u16 ram_offset,
1430                                       u16 shm_size_offset)
1431 {
1432         unsigned int i, len, variable_len;
1433         const struct ieee80211_mgmt *bcn;
1434         const u8 *ie;
1435         bool tim_found = 0;
1436         unsigned int rate;
1437         u16 ctl;
1438         int antenna;
1439         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1440
1441         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1442         len = min((size_t) dev->wl->current_beacon->len,
1443                   0x200 - sizeof(struct b43_plcp_hdr6));
1444         rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1445
1446         b43_write_template_common(dev, (const u8 *)bcn,
1447                                   len, ram_offset, shm_size_offset, rate);
1448
1449         /* Write the PHY TX control parameters. */
1450         antenna = B43_ANTENNA_DEFAULT;
1451         antenna = b43_antenna_to_phyctl(antenna);
1452         ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1453         /* We can't send beacons with short preamble. Would get PHY errors. */
1454         ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1455         ctl &= ~B43_TXH_PHY_ANT;
1456         ctl &= ~B43_TXH_PHY_ENC;
1457         ctl |= antenna;
1458         if (b43_is_cck_rate(rate))
1459                 ctl |= B43_TXH_PHY_ENC_CCK;
1460         else
1461                 ctl |= B43_TXH_PHY_ENC_OFDM;
1462         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1463
1464         /* Find the position of the TIM and the DTIM_period value
1465          * and write them to SHM. */
1466         ie = bcn->u.beacon.variable;
1467         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1468         for (i = 0; i < variable_len - 2; ) {
1469                 uint8_t ie_id, ie_len;
1470
1471                 ie_id = ie[i];
1472                 ie_len = ie[i + 1];
1473                 if (ie_id == 5) {
1474                         u16 tim_position;
1475                         u16 dtim_period;
1476                         /* This is the TIM Information Element */
1477
1478                         /* Check whether the ie_len is in the beacon data range. */
1479                         if (variable_len < ie_len + 2 + i)
1480                                 break;
1481                         /* A valid TIM is at least 4 bytes long. */
1482                         if (ie_len < 4)
1483                                 break;
1484                         tim_found = 1;
1485
1486                         tim_position = sizeof(struct b43_plcp_hdr6);
1487                         tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1488                         tim_position += i;
1489
1490                         dtim_period = ie[i + 3];
1491
1492                         b43_shm_write16(dev, B43_SHM_SHARED,
1493                                         B43_SHM_SH_TIMBPOS, tim_position);
1494                         b43_shm_write16(dev, B43_SHM_SHARED,
1495                                         B43_SHM_SH_DTIMPER, dtim_period);
1496                         break;
1497                 }
1498                 i += ie_len + 2;
1499         }
1500         if (!tim_found) {
1501                 /*
1502                  * If ucode wants to modify TIM do it behind the beacon, this
1503                  * will happen, for example, when doing mesh networking.
1504                  */
1505                 b43_shm_write16(dev, B43_SHM_SHARED,
1506                                 B43_SHM_SH_TIMBPOS,
1507                                 len + sizeof(struct b43_plcp_hdr6));
1508                 b43_shm_write16(dev, B43_SHM_SHARED,
1509                                 B43_SHM_SH_DTIMPER, 0);
1510         }
1511         b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1512 }
1513
1514 static void b43_upload_beacon0(struct b43_wldev *dev)
1515 {
1516         struct b43_wl *wl = dev->wl;
1517
1518         if (wl->beacon0_uploaded)
1519                 return;
1520         b43_write_beacon_template(dev, 0x68, 0x18);
1521         wl->beacon0_uploaded = 1;
1522 }
1523
1524 static void b43_upload_beacon1(struct b43_wldev *dev)
1525 {
1526         struct b43_wl *wl = dev->wl;
1527
1528         if (wl->beacon1_uploaded)
1529                 return;
1530         b43_write_beacon_template(dev, 0x468, 0x1A);
1531         wl->beacon1_uploaded = 1;
1532 }
1533
1534 static void handle_irq_beacon(struct b43_wldev *dev)
1535 {
1536         struct b43_wl *wl = dev->wl;
1537         u32 cmd, beacon0_valid, beacon1_valid;
1538
1539         if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1540             !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1541                 return;
1542
1543         /* This is the bottom half of the asynchronous beacon update. */
1544
1545         /* Ignore interrupt in the future. */
1546         dev->irq_mask &= ~B43_IRQ_BEACON;
1547
1548         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1549         beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1550         beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1551
1552         /* Schedule interrupt manually, if busy. */
1553         if (beacon0_valid && beacon1_valid) {
1554                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1555                 dev->irq_mask |= B43_IRQ_BEACON;
1556                 return;
1557         }
1558
1559         if (unlikely(wl->beacon_templates_virgin)) {
1560                 /* We never uploaded a beacon before.
1561                  * Upload both templates now, but only mark one valid. */
1562                 wl->beacon_templates_virgin = 0;
1563                 b43_upload_beacon0(dev);
1564                 b43_upload_beacon1(dev);
1565                 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1566                 cmd |= B43_MACCMD_BEACON0_VALID;
1567                 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1568         } else {
1569                 if (!beacon0_valid) {
1570                         b43_upload_beacon0(dev);
1571                         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1572                         cmd |= B43_MACCMD_BEACON0_VALID;
1573                         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1574                 } else if (!beacon1_valid) {
1575                         b43_upload_beacon1(dev);
1576                         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1577                         cmd |= B43_MACCMD_BEACON1_VALID;
1578                         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1579                 }
1580         }
1581 }
1582
1583 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1584 {
1585         u32 old_irq_mask = dev->irq_mask;
1586
1587         /* update beacon right away or defer to irq */
1588         handle_irq_beacon(dev);
1589         if (old_irq_mask != dev->irq_mask) {
1590                 /* The handler updated the IRQ mask. */
1591                 B43_WARN_ON(!dev->irq_mask);
1592                 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1593                         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1594                 } else {
1595                         /* Device interrupts are currently disabled. That means
1596                          * we just ran the hardirq handler and scheduled the
1597                          * IRQ thread. The thread will write the IRQ mask when
1598                          * it finished, so there's nothing to do here. Writing
1599                          * the mask _here_ would incorrectly re-enable IRQs. */
1600                 }
1601         }
1602 }
1603
1604 static void b43_beacon_update_trigger_work(struct work_struct *work)
1605 {
1606         struct b43_wl *wl = container_of(work, struct b43_wl,
1607                                          beacon_update_trigger);
1608         struct b43_wldev *dev;
1609
1610         mutex_lock(&wl->mutex);
1611         dev = wl->current_dev;
1612         if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1613                 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
1614                         /* wl->mutex is enough. */
1615                         b43_do_beacon_update_trigger_work(dev);
1616                         mmiowb();
1617                 } else {
1618                         spin_lock_irq(&wl->hardirq_lock);
1619                         b43_do_beacon_update_trigger_work(dev);
1620                         mmiowb();
1621                         spin_unlock_irq(&wl->hardirq_lock);
1622                 }
1623         }
1624         mutex_unlock(&wl->mutex);
1625 }
1626
1627 /* Asynchronously update the packet templates in template RAM.
1628  * Locking: Requires wl->mutex to be locked. */
1629 static void b43_update_templates(struct b43_wl *wl)
1630 {
1631         struct sk_buff *beacon;
1632
1633         /* This is the top half of the ansynchronous beacon update.
1634          * The bottom half is the beacon IRQ.
1635          * Beacon update must be asynchronous to avoid sending an
1636          * invalid beacon. This can happen for example, if the firmware
1637          * transmits a beacon while we are updating it. */
1638
1639         /* We could modify the existing beacon and set the aid bit in
1640          * the TIM field, but that would probably require resizing and
1641          * moving of data within the beacon template.
1642          * Simply request a new beacon and let mac80211 do the hard work. */
1643         beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1644         if (unlikely(!beacon))
1645                 return;
1646
1647         if (wl->current_beacon)
1648                 dev_kfree_skb_any(wl->current_beacon);
1649         wl->current_beacon = beacon;
1650         wl->beacon0_uploaded = 0;
1651         wl->beacon1_uploaded = 0;
1652         ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1653 }
1654
1655 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1656 {
1657         b43_time_lock(dev);
1658         if (dev->dev->id.revision >= 3) {
1659                 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1660                 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1661         } else {
1662                 b43_write16(dev, 0x606, (beacon_int >> 6));
1663                 b43_write16(dev, 0x610, beacon_int);
1664         }
1665         b43_time_unlock(dev);
1666         b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1667 }
1668
1669 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1670 {
1671         u16 reason;
1672
1673         /* Read the register that contains the reason code for the panic. */
1674         reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1675         b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1676
1677         switch (reason) {
1678         default:
1679                 b43dbg(dev->wl, "The panic reason is unknown.\n");
1680                 /* fallthrough */
1681         case B43_FWPANIC_DIE:
1682                 /* Do not restart the controller or firmware.
1683                  * The device is nonfunctional from now on.
1684                  * Restarting would result in this panic to trigger again,
1685                  * so we avoid that recursion. */
1686                 break;
1687         case B43_FWPANIC_RESTART:
1688                 b43_controller_restart(dev, "Microcode panic");
1689                 break;
1690         }
1691 }
1692
1693 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1694 {
1695         unsigned int i, cnt;
1696         u16 reason, marker_id, marker_line;
1697         __le16 *buf;
1698
1699         /* The proprietary firmware doesn't have this IRQ. */
1700         if (!dev->fw.opensource)
1701                 return;
1702
1703         /* Read the register that contains the reason code for this IRQ. */
1704         reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1705
1706         switch (reason) {
1707         case B43_DEBUGIRQ_PANIC:
1708                 b43_handle_firmware_panic(dev);
1709                 break;
1710         case B43_DEBUGIRQ_DUMP_SHM:
1711                 if (!B43_DEBUG)
1712                         break; /* Only with driver debugging enabled. */
1713                 buf = kmalloc(4096, GFP_ATOMIC);
1714                 if (!buf) {
1715                         b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1716                         goto out;
1717                 }
1718                 for (i = 0; i < 4096; i += 2) {
1719                         u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1720                         buf[i / 2] = cpu_to_le16(tmp);
1721                 }
1722                 b43info(dev->wl, "Shared memory dump:\n");
1723                 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1724                                16, 2, buf, 4096, 1);
1725                 kfree(buf);
1726                 break;
1727         case B43_DEBUGIRQ_DUMP_REGS:
1728                 if (!B43_DEBUG)
1729                         break; /* Only with driver debugging enabled. */
1730                 b43info(dev->wl, "Microcode register dump:\n");
1731                 for (i = 0, cnt = 0; i < 64; i++) {
1732                         u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1733                         if (cnt == 0)
1734                                 printk(KERN_INFO);
1735                         printk("r%02u: 0x%04X  ", i, tmp);
1736                         cnt++;
1737                         if (cnt == 6) {
1738                                 printk("\n");
1739                                 cnt = 0;
1740                         }
1741                 }
1742                 printk("\n");
1743                 break;
1744         case B43_DEBUGIRQ_MARKER:
1745                 if (!B43_DEBUG)
1746                         break; /* Only with driver debugging enabled. */
1747                 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1748                                            B43_MARKER_ID_REG);
1749                 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1750                                              B43_MARKER_LINE_REG);
1751                 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1752                         "at line number %u\n",
1753                         marker_id, marker_line);
1754                 break;
1755         default:
1756                 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1757                        reason);
1758         }
1759 out:
1760         /* Acknowledge the debug-IRQ, so the firmware can continue. */
1761         b43_shm_write16(dev, B43_SHM_SCRATCH,
1762                         B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1763 }
1764
1765 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1766 {
1767         u32 reason;
1768         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1769         u32 merged_dma_reason = 0;
1770         int i;
1771
1772         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1773                 return;
1774
1775         reason = dev->irq_reason;
1776         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1777                 dma_reason[i] = dev->dma_reason[i];
1778                 merged_dma_reason |= dma_reason[i];
1779         }
1780
1781         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1782                 b43err(dev->wl, "MAC transmission error\n");
1783
1784         if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1785                 b43err(dev->wl, "PHY transmission error\n");
1786                 rmb();
1787                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1788                         atomic_set(&dev->phy.txerr_cnt,
1789                                    B43_PHY_TX_BADNESS_LIMIT);
1790                         b43err(dev->wl, "Too many PHY TX errors, "
1791                                         "restarting the controller\n");
1792                         b43_controller_restart(dev, "PHY TX errors");
1793                 }
1794         }
1795
1796         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1797                                           B43_DMAIRQ_NONFATALMASK))) {
1798                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1799                         b43err(dev->wl, "Fatal DMA error: "
1800                                "0x%08X, 0x%08X, 0x%08X, "
1801                                "0x%08X, 0x%08X, 0x%08X\n",
1802                                dma_reason[0], dma_reason[1],
1803                                dma_reason[2], dma_reason[3],
1804                                dma_reason[4], dma_reason[5]);
1805                         b43err(dev->wl, "This device does not support DMA "
1806                                "on your system. Please use PIO instead.\n");
1807                         b43err(dev->wl, "Unload the b43 module and reload "
1808                                "with 'pio=1'\n");
1809                         return;
1810                 }
1811                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1812                         b43err(dev->wl, "DMA error: "
1813                                "0x%08X, 0x%08X, 0x%08X, "
1814                                "0x%08X, 0x%08X, 0x%08X\n",
1815                                dma_reason[0], dma_reason[1],
1816                                dma_reason[2], dma_reason[3],
1817                                dma_reason[4], dma_reason[5]);
1818                 }
1819         }
1820
1821         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1822                 handle_irq_ucode_debug(dev);
1823         if (reason & B43_IRQ_TBTT_INDI)
1824                 handle_irq_tbtt_indication(dev);
1825         if (reason & B43_IRQ_ATIM_END)
1826                 handle_irq_atim_end(dev);
1827         if (reason & B43_IRQ_BEACON)
1828                 handle_irq_beacon(dev);
1829         if (reason & B43_IRQ_PMQ)
1830                 handle_irq_pmq(dev);
1831         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1832                 ;/* TODO */
1833         if (reason & B43_IRQ_NOISESAMPLE_OK)
1834                 handle_irq_noise(dev);
1835
1836         /* Check the DMA reason registers for received data. */
1837         if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1838                 if (b43_using_pio_transfers(dev))
1839                         b43_pio_rx(dev->pio.rx_queue);
1840                 else
1841                         b43_dma_rx(dev->dma.rx_ring);
1842         }
1843         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1844         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1845         B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1846         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1847         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1848
1849         if (reason & B43_IRQ_TX_OK)
1850                 handle_irq_transmit_status(dev);
1851
1852         /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1853         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1854
1855 #if B43_DEBUG
1856         if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1857                 dev->irq_count++;
1858                 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1859                         if (reason & (1 << i))
1860                                 dev->irq_bit_count[i]++;
1861                 }
1862         }
1863 #endif
1864 }
1865
1866 /* Interrupt thread handler. Handles device interrupts in thread context. */
1867 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1868 {
1869         struct b43_wldev *dev = dev_id;
1870
1871         mutex_lock(&dev->wl->mutex);
1872         b43_do_interrupt_thread(dev);
1873         mmiowb();
1874         mutex_unlock(&dev->wl->mutex);
1875
1876         return IRQ_HANDLED;
1877 }
1878
1879 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1880 {
1881         u32 reason;
1882
1883         /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1884          * On SDIO, this runs under wl->mutex. */
1885
1886         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1887         if (reason == 0xffffffff)       /* shared IRQ */
1888                 return IRQ_NONE;
1889         reason &= dev->irq_mask;
1890         if (!reason)
1891                 return IRQ_HANDLED;
1892
1893         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1894             & 0x0001DC00;
1895         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1896             & 0x0000DC00;
1897         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1898             & 0x0000DC00;
1899         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1900             & 0x0001DC00;
1901         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1902             & 0x0000DC00;
1903 /* Unused ring
1904         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1905             & 0x0000DC00;
1906 */
1907
1908         /* ACK the interrupt. */
1909         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1910         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1911         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1912         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1913         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1914         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1915 /* Unused ring
1916         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1917 */
1918
1919         /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
1920         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
1921         /* Save the reason bitmasks for the IRQ thread handler. */
1922         dev->irq_reason = reason;
1923
1924         return IRQ_WAKE_THREAD;
1925 }
1926
1927 /* Interrupt handler top-half. This runs with interrupts disabled. */
1928 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1929 {
1930         struct b43_wldev *dev = dev_id;
1931         irqreturn_t ret;
1932
1933         if (unlikely(b43_status(dev) < B43_STAT_STARTED))
1934                 return IRQ_NONE;
1935
1936         spin_lock(&dev->wl->hardirq_lock);
1937         ret = b43_do_interrupt(dev);
1938         mmiowb();
1939         spin_unlock(&dev->wl->hardirq_lock);
1940
1941         return ret;
1942 }
1943
1944 /* SDIO interrupt handler. This runs in process context. */
1945 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
1946 {
1947         struct b43_wl *wl = dev->wl;
1948         irqreturn_t ret;
1949
1950         mutex_lock(&wl->mutex);
1951
1952         ret = b43_do_interrupt(dev);
1953         if (ret == IRQ_WAKE_THREAD)
1954                 b43_do_interrupt_thread(dev);
1955
1956         mutex_unlock(&wl->mutex);
1957 }
1958
1959 void b43_do_release_fw(struct b43_firmware_file *fw)
1960 {
1961         release_firmware(fw->data);
1962         fw->data = NULL;
1963         fw->filename = NULL;
1964 }
1965
1966 static void b43_release_firmware(struct b43_wldev *dev)
1967 {
1968         b43_do_release_fw(&dev->fw.ucode);
1969         b43_do_release_fw(&dev->fw.pcm);
1970         b43_do_release_fw(&dev->fw.initvals);
1971         b43_do_release_fw(&dev->fw.initvals_band);
1972 }
1973
1974 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1975 {
1976         const char text[] =
1977                 "You must go to " \
1978                 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1979                 "and download the correct firmware for this driver version. " \
1980                 "Please carefully read all instructions on this website.\n";
1981
1982         if (error)
1983                 b43err(wl, text);
1984         else
1985                 b43warn(wl, text);
1986 }
1987
1988 int b43_do_request_fw(struct b43_request_fw_context *ctx,
1989                       const char *name,
1990                       struct b43_firmware_file *fw)
1991 {
1992         const struct firmware *blob;
1993         struct b43_fw_header *hdr;
1994         u32 size;
1995         int err;
1996
1997         if (!name) {
1998                 /* Don't fetch anything. Free possibly cached firmware. */
1999                 /* FIXME: We should probably keep it anyway, to save some headache
2000                  * on suspend/resume with multiband devices. */
2001                 b43_do_release_fw(fw);
2002                 return 0;
2003         }
2004         if (fw->filename) {
2005                 if ((fw->type == ctx->req_type) &&
2006                     (strcmp(fw->filename, name) == 0))
2007                         return 0; /* Already have this fw. */
2008                 /* Free the cached firmware first. */
2009                 /* FIXME: We should probably do this later after we successfully
2010                  * got the new fw. This could reduce headache with multiband devices.
2011                  * We could also redesign this to cache the firmware for all possible
2012                  * bands all the time. */
2013                 b43_do_release_fw(fw);
2014         }
2015
2016         switch (ctx->req_type) {
2017         case B43_FWTYPE_PROPRIETARY:
2018                 snprintf(ctx->fwname, sizeof(ctx->fwname),
2019                          "b43%s/%s.fw",
2020                          modparam_fwpostfix, name);
2021                 break;
2022         case B43_FWTYPE_OPENSOURCE:
2023                 snprintf(ctx->fwname, sizeof(ctx->fwname),
2024                          "b43-open%s/%s.fw",
2025                          modparam_fwpostfix, name);
2026                 break;
2027         default:
2028                 B43_WARN_ON(1);
2029                 return -ENOSYS;
2030         }
2031         err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2032         if (err == -ENOENT) {
2033                 snprintf(ctx->errors[ctx->req_type],
2034                          sizeof(ctx->errors[ctx->req_type]),
2035                          "Firmware file \"%s\" not found\n", ctx->fwname);
2036                 return err;
2037         } else if (err) {
2038                 snprintf(ctx->errors[ctx->req_type],
2039                          sizeof(ctx->errors[ctx->req_type]),
2040                          "Firmware file \"%s\" request failed (err=%d)\n",
2041                          ctx->fwname, err);
2042                 return err;
2043         }
2044         if (blob->size < sizeof(struct b43_fw_header))
2045                 goto err_format;
2046         hdr = (struct b43_fw_header *)(blob->data);
2047         switch (hdr->type) {
2048         case B43_FW_TYPE_UCODE:
2049         case B43_FW_TYPE_PCM:
2050                 size = be32_to_cpu(hdr->size);
2051                 if (size != blob->size - sizeof(struct b43_fw_header))
2052                         goto err_format;
2053                 /* fallthrough */
2054         case B43_FW_TYPE_IV:
2055                 if (hdr->ver != 1)
2056                         goto err_format;
2057                 break;
2058         default:
2059                 goto err_format;
2060         }
2061
2062         fw->data = blob;
2063         fw->filename = name;
2064         fw->type = ctx->req_type;
2065
2066         return 0;
2067
2068 err_format:
2069         snprintf(ctx->errors[ctx->req_type],
2070                  sizeof(ctx->errors[ctx->req_type]),
2071                  "Firmware file \"%s\" format error.\n", ctx->fwname);
2072         release_firmware(blob);
2073
2074         return -EPROTO;
2075 }
2076
2077 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2078 {
2079         struct b43_wldev *dev = ctx->dev;
2080         struct b43_firmware *fw = &ctx->dev->fw;
2081         const u8 rev = ctx->dev->dev->id.revision;
2082         const char *filename;
2083         u32 tmshigh;
2084         int err;
2085
2086         /* Get microcode */
2087         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2088         if ((rev >= 5) && (rev <= 10))
2089                 filename = "ucode5";
2090         else if ((rev >= 11) && (rev <= 12))
2091                 filename = "ucode11";
2092         else if (rev == 13)
2093                 filename = "ucode13";
2094         else if (rev == 14)
2095                 filename = "ucode14";
2096         else if (rev >= 15)
2097                 filename = "ucode15";
2098         else
2099                 goto err_no_ucode;
2100         err = b43_do_request_fw(ctx, filename, &fw->ucode);
2101         if (err)
2102                 goto err_load;
2103
2104         /* Get PCM code */
2105         if ((rev >= 5) && (rev <= 10))
2106                 filename = "pcm5";
2107         else if (rev >= 11)
2108                 filename = NULL;
2109         else
2110                 goto err_no_pcm;
2111         fw->pcm_request_failed = 0;
2112         err = b43_do_request_fw(ctx, filename, &fw->pcm);
2113         if (err == -ENOENT) {
2114                 /* We did not find a PCM file? Not fatal, but
2115                  * core rev <= 10 must do without hwcrypto then. */
2116                 fw->pcm_request_failed = 1;
2117         } else if (err)
2118                 goto err_load;
2119
2120         /* Get initvals */
2121         switch (dev->phy.type) {
2122         case B43_PHYTYPE_A:
2123                 if ((rev >= 5) && (rev <= 10)) {
2124                         if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2125                                 filename = "a0g1initvals5";
2126                         else
2127                                 filename = "a0g0initvals5";
2128                 } else
2129                         goto err_no_initvals;
2130                 break;
2131         case B43_PHYTYPE_G:
2132                 if ((rev >= 5) && (rev <= 10))
2133                         filename = "b0g0initvals5";
2134                 else if (rev >= 13)
2135                         filename = "b0g0initvals13";
2136                 else
2137                         goto err_no_initvals;
2138                 break;
2139         case B43_PHYTYPE_N:
2140                 if ((rev >= 11) && (rev <= 12))
2141                         filename = "n0initvals11";
2142                 else
2143                         goto err_no_initvals;
2144                 break;
2145         case B43_PHYTYPE_LP:
2146                 if (rev == 13)
2147                         filename = "lp0initvals13";
2148                 else if (rev == 14)
2149                         filename = "lp0initvals14";
2150                 else if (rev >= 15)
2151                         filename = "lp0initvals15";
2152                 else
2153                         goto err_no_initvals;
2154                 break;
2155         default:
2156                 goto err_no_initvals;
2157         }
2158         err = b43_do_request_fw(ctx, filename, &fw->initvals);
2159         if (err)
2160                 goto err_load;
2161
2162         /* Get bandswitch initvals */
2163         switch (dev->phy.type) {
2164         case B43_PHYTYPE_A:
2165                 if ((rev >= 5) && (rev <= 10)) {
2166                         if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2167                                 filename = "a0g1bsinitvals5";
2168                         else
2169                                 filename = "a0g0bsinitvals5";
2170                 } else if (rev >= 11)
2171                         filename = NULL;
2172                 else
2173                         goto err_no_initvals;
2174                 break;
2175         case B43_PHYTYPE_G:
2176                 if ((rev >= 5) && (rev <= 10))
2177                         filename = "b0g0bsinitvals5";
2178                 else if (rev >= 11)
2179                         filename = NULL;
2180                 else
2181                         goto err_no_initvals;
2182                 break;
2183         case B43_PHYTYPE_N:
2184                 if ((rev >= 11) && (rev <= 12))
2185                         filename = "n0bsinitvals11";
2186                 else
2187                         goto err_no_initvals;
2188                 break;
2189         case B43_PHYTYPE_LP:
2190                 if (rev == 13)
2191                         filename = "lp0bsinitvals13";
2192                 else if (rev == 14)
2193                         filename = "lp0bsinitvals14";
2194                 else if (rev >= 15)
2195                         filename = "lp0bsinitvals15";
2196                 else
2197                         goto err_no_initvals;
2198                 break;
2199         default:
2200                 goto err_no_initvals;
2201         }
2202         err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2203         if (err)
2204                 goto err_load;
2205
2206         return 0;
2207
2208 err_no_ucode:
2209         err = ctx->fatal_failure = -EOPNOTSUPP;
2210         b43err(dev->wl, "The driver does not know which firmware (ucode) "
2211                "is required for your device (wl-core rev %u)\n", rev);
2212         goto error;
2213
2214 err_no_pcm:
2215         err = ctx->fatal_failure = -EOPNOTSUPP;
2216         b43err(dev->wl, "The driver does not know which firmware (PCM) "
2217                "is required for your device (wl-core rev %u)\n", rev);
2218         goto error;
2219
2220 err_no_initvals:
2221         err = ctx->fatal_failure = -EOPNOTSUPP;
2222         b43err(dev->wl, "The driver does not know which firmware (initvals) "
2223                "is required for your device (wl-core rev %u)\n", rev);
2224         goto error;
2225
2226 err_load:
2227         /* We failed to load this firmware image. The error message
2228          * already is in ctx->errors. Return and let our caller decide
2229          * what to do. */
2230         goto error;
2231
2232 error:
2233         b43_release_firmware(dev);
2234         return err;
2235 }
2236
2237 static int b43_request_firmware(struct b43_wldev *dev)
2238 {
2239         struct b43_request_fw_context *ctx;
2240         unsigned int i;
2241         int err;
2242         const char *errmsg;
2243
2244         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2245         if (!ctx)
2246                 return -ENOMEM;
2247         ctx->dev = dev;
2248
2249         ctx->req_type = B43_FWTYPE_PROPRIETARY;
2250         err = b43_try_request_fw(ctx);
2251         if (!err)
2252                 goto out; /* Successfully loaded it. */
2253         err = ctx->fatal_failure;
2254         if (err)
2255                 goto out;
2256
2257         ctx->req_type = B43_FWTYPE_OPENSOURCE;
2258         err = b43_try_request_fw(ctx);
2259         if (!err)
2260                 goto out; /* Successfully loaded it. */
2261         err = ctx->fatal_failure;
2262         if (err)
2263                 goto out;
2264
2265         /* Could not find a usable firmware. Print the errors. */
2266         for (i = 0; i < B43_NR_FWTYPES; i++) {
2267                 errmsg = ctx->errors[i];
2268                 if (strlen(errmsg))
2269                         b43err(dev->wl, errmsg);
2270         }
2271         b43_print_fw_helptext(dev->wl, 1);
2272         err = -ENOENT;
2273
2274 out:
2275         kfree(ctx);
2276         return err;
2277 }
2278
2279 static int b43_upload_microcode(struct b43_wldev *dev)
2280 {
2281         const size_t hdr_len = sizeof(struct b43_fw_header);
2282         const __be32 *data;
2283         unsigned int i, len;
2284         u16 fwrev, fwpatch, fwdate, fwtime;
2285         u32 tmp, macctl;
2286         int err = 0;
2287
2288         /* Jump the microcode PSM to offset 0 */
2289         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2290         B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2291         macctl |= B43_MACCTL_PSM_JMP0;
2292         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2293         /* Zero out all microcode PSM registers and shared memory. */
2294         for (i = 0; i < 64; i++)
2295                 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2296         for (i = 0; i < 4096; i += 2)
2297                 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2298
2299         /* Upload Microcode. */
2300         data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2301         len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2302         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2303         for (i = 0; i < len; i++) {
2304                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2305                 udelay(10);
2306         }
2307
2308         if (dev->fw.pcm.data) {
2309                 /* Upload PCM data. */
2310                 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2311                 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2312                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2313                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2314                 /* No need for autoinc bit in SHM_HW */
2315                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2316                 for (i = 0; i < len; i++) {
2317                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2318                         udelay(10);
2319                 }
2320         }
2321
2322         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2323
2324         /* Start the microcode PSM */
2325         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2326         macctl &= ~B43_MACCTL_PSM_JMP0;
2327         macctl |= B43_MACCTL_PSM_RUN;
2328         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2329
2330         /* Wait for the microcode to load and respond */
2331         i = 0;
2332         while (1) {
2333                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2334                 if (tmp == B43_IRQ_MAC_SUSPENDED)
2335                         break;
2336                 i++;
2337                 if (i >= 20) {
2338                         b43err(dev->wl, "Microcode not responding\n");
2339                         b43_print_fw_helptext(dev->wl, 1);
2340                         err = -ENODEV;
2341                         goto error;
2342                 }
2343                 msleep(50);
2344         }
2345         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
2346
2347         /* Get and check the revisions. */
2348         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2349         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2350         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2351         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2352
2353         if (fwrev <= 0x128) {
2354                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2355                        "binary drivers older than version 4.x is unsupported. "
2356                        "You must upgrade your firmware files.\n");
2357                 b43_print_fw_helptext(dev->wl, 1);
2358                 err = -EOPNOTSUPP;
2359                 goto error;
2360         }
2361         dev->fw.rev = fwrev;
2362         dev->fw.patch = fwpatch;
2363         dev->fw.opensource = (fwdate == 0xFFFF);
2364
2365         /* Default to use-all-queues. */
2366         dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2367         dev->qos_enabled = !!modparam_qos;
2368         /* Default to firmware/hardware crypto acceleration. */
2369         dev->hwcrypto_enabled = 1;
2370
2371         if (dev->fw.opensource) {
2372                 u16 fwcapa;
2373
2374                 /* Patchlevel info is encoded in the "time" field. */
2375                 dev->fw.patch = fwtime;
2376                 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2377                         dev->fw.rev, dev->fw.patch);
2378
2379                 fwcapa = b43_fwcapa_read(dev);
2380                 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2381                         b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2382                         /* Disable hardware crypto and fall back to software crypto. */
2383                         dev->hwcrypto_enabled = 0;
2384                 }
2385                 if (!(fwcapa & B43_FWCAPA_QOS)) {
2386                         b43info(dev->wl, "QoS not supported by firmware\n");
2387                         /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2388                          * ieee80211_unregister to make sure the networking core can
2389                          * properly free possible resources. */
2390                         dev->wl->hw->queues = 1;
2391                         dev->qos_enabled = 0;
2392                 }
2393         } else {
2394                 b43info(dev->wl, "Loading firmware version %u.%u "
2395                         "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2396                         fwrev, fwpatch,
2397                         (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2398                         (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2399                 if (dev->fw.pcm_request_failed) {
2400                         b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2401                                 "Hardware accelerated cryptography is disabled.\n");
2402                         b43_print_fw_helptext(dev->wl, 0);
2403                 }
2404         }
2405
2406         if (b43_is_old_txhdr_format(dev)) {
2407                 /* We're over the deadline, but we keep support for old fw
2408                  * until it turns out to be in major conflict with something new. */
2409                 b43warn(dev->wl, "You are using an old firmware image. "
2410                         "Support for old firmware will be removed soon "
2411                         "(official deadline was July 2008).\n");
2412                 b43_print_fw_helptext(dev->wl, 0);
2413         }
2414
2415         return 0;
2416
2417 error:
2418         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2419         macctl &= ~B43_MACCTL_PSM_RUN;
2420         macctl |= B43_MACCTL_PSM_JMP0;
2421         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2422
2423         return err;
2424 }
2425
2426 static int b43_write_initvals(struct b43_wldev *dev,
2427                               const struct b43_iv *ivals,
2428                               size_t count,
2429                               size_t array_size)
2430 {
2431         const struct b43_iv *iv;
2432         u16 offset;
2433         size_t i;
2434         bool bit32;
2435
2436         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2437         iv = ivals;
2438         for (i = 0; i < count; i++) {
2439                 if (array_size < sizeof(iv->offset_size))
2440                         goto err_format;
2441                 array_size -= sizeof(iv->offset_size);
2442                 offset = be16_to_cpu(iv->offset_size);
2443                 bit32 = !!(offset & B43_IV_32BIT);
2444                 offset &= B43_IV_OFFSET_MASK;
2445                 if (offset >= 0x1000)
2446                         goto err_format;
2447                 if (bit32) {
2448                         u32 value;
2449
2450                         if (array_size < sizeof(iv->data.d32))
2451                                 goto err_format;
2452                         array_size -= sizeof(iv->data.d32);
2453
2454                         value = get_unaligned_be32(&iv->data.d32);
2455                         b43_write32(dev, offset, value);
2456
2457                         iv = (const struct b43_iv *)((const uint8_t *)iv +
2458                                                         sizeof(__be16) +
2459                                                         sizeof(__be32));
2460                 } else {
2461                         u16 value;
2462
2463                         if (array_size < sizeof(iv->data.d16))
2464                                 goto err_format;
2465                         array_size -= sizeof(iv->data.d16);
2466
2467                         value = be16_to_cpu(iv->data.d16);
2468                         b43_write16(dev, offset, value);
2469
2470                         iv = (const struct b43_iv *)((const uint8_t *)iv +
2471                                                         sizeof(__be16) +
2472                                                         sizeof(__be16));
2473                 }
2474         }
2475         if (array_size)
2476                 goto err_format;
2477
2478         return 0;
2479
2480 err_format:
2481         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2482         b43_print_fw_helptext(dev->wl, 1);
2483
2484         return -EPROTO;
2485 }
2486
2487 static int b43_upload_initvals(struct b43_wldev *dev)
2488 {
2489         const size_t hdr_len = sizeof(struct b43_fw_header);
2490         const struct b43_fw_header *hdr;
2491         struct b43_firmware *fw = &dev->fw;
2492         const struct b43_iv *ivals;
2493         size_t count;
2494         int err;
2495
2496         hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2497         ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2498         count = be32_to_cpu(hdr->size);
2499         err = b43_write_initvals(dev, ivals, count,
2500                                  fw->initvals.data->size - hdr_len);
2501         if (err)
2502                 goto out;
2503         if (fw->initvals_band.data) {
2504                 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2505                 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2506                 count = be32_to_cpu(hdr->size);
2507                 err = b43_write_initvals(dev, ivals, count,
2508                                          fw->initvals_band.data->size - hdr_len);
2509                 if (err)
2510                         goto out;
2511         }
2512 out:
2513
2514         return err;
2515 }
2516
2517 /* Initialize the GPIOs
2518  * http://bcm-specs.sipsolutions.net/GPIO
2519  */
2520 static int b43_gpio_init(struct b43_wldev *dev)
2521 {
2522         struct ssb_bus *bus = dev->dev->bus;
2523         struct ssb_device *gpiodev, *pcidev = NULL;
2524         u32 mask, set;
2525
2526         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2527                     & ~B43_MACCTL_GPOUTSMSK);
2528
2529         b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2530                     | 0x000F);
2531
2532         mask = 0x0000001F;
2533         set = 0x0000000F;
2534         if (dev->dev->bus->chip_id == 0x4301) {
2535                 mask |= 0x0060;
2536                 set |= 0x0060;
2537         }
2538         if (0 /* FIXME: conditional unknown */ ) {
2539                 b43_write16(dev, B43_MMIO_GPIO_MASK,
2540                             b43_read16(dev, B43_MMIO_GPIO_MASK)
2541                             | 0x0100);
2542                 mask |= 0x0180;
2543                 set |= 0x0180;
2544         }
2545         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2546                 b43_write16(dev, B43_MMIO_GPIO_MASK,
2547                             b43_read16(dev, B43_MMIO_GPIO_MASK)
2548                             | 0x0200);
2549                 mask |= 0x0200;
2550                 set |= 0x0200;
2551         }
2552         if (dev->dev->id.revision >= 2)
2553                 mask |= 0x0010; /* FIXME: This is redundant. */
2554
2555 #ifdef CONFIG_SSB_DRIVER_PCICORE
2556         pcidev = bus->pcicore.dev;
2557 #endif
2558         gpiodev = bus->chipco.dev ? : pcidev;
2559         if (!gpiodev)
2560                 return 0;
2561         ssb_write32(gpiodev, B43_GPIO_CONTROL,
2562                     (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2563                      & mask) | set);
2564
2565         return 0;
2566 }
2567
2568 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2569 static void b43_gpio_cleanup(struct b43_wldev *dev)
2570 {
2571         struct ssb_bus *bus = dev->dev->bus;
2572         struct ssb_device *gpiodev, *pcidev = NULL;
2573
2574 #ifdef CONFIG_SSB_DRIVER_PCICORE
2575         pcidev = bus->pcicore.dev;
2576 #endif
2577         gpiodev = bus->chipco.dev ? : pcidev;
2578         if (!gpiodev)
2579                 return;
2580         ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2581 }
2582
2583 /* http://bcm-specs.sipsolutions.net/EnableMac */
2584 void b43_mac_enable(struct b43_wldev *dev)
2585 {
2586         if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2587                 u16 fwstate;
2588
2589                 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2590                                          B43_SHM_SH_UCODESTAT);
2591                 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2592                     (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2593                         b43err(dev->wl, "b43_mac_enable(): The firmware "
2594                                "should be suspended, but current state is %u\n",
2595                                fwstate);
2596                 }
2597         }
2598
2599         dev->mac_suspended--;
2600         B43_WARN_ON(dev->mac_suspended < 0);
2601         if (dev->mac_suspended == 0) {
2602                 b43_write32(dev, B43_MMIO_MACCTL,
2603                             b43_read32(dev, B43_MMIO_MACCTL)
2604                             | B43_MACCTL_ENABLED);
2605                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2606                             B43_IRQ_MAC_SUSPENDED);
2607                 /* Commit writes */
2608                 b43_read32(dev, B43_MMIO_MACCTL);
2609                 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2610                 b43_power_saving_ctl_bits(dev, 0);
2611         }
2612 }
2613
2614 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2615 void b43_mac_suspend(struct b43_wldev *dev)
2616 {
2617         int i;
2618         u32 tmp;
2619
2620         might_sleep();
2621         B43_WARN_ON(dev->mac_suspended < 0);
2622
2623         if (dev->mac_suspended == 0) {
2624                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2625                 b43_write32(dev, B43_MMIO_MACCTL,
2626                             b43_read32(dev, B43_MMIO_MACCTL)
2627                             & ~B43_MACCTL_ENABLED);
2628                 /* force pci to flush the write */
2629                 b43_read32(dev, B43_MMIO_MACCTL);
2630                 for (i = 35; i; i--) {
2631                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2632                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2633                                 goto out;
2634                         udelay(10);
2635                 }
2636                 /* Hm, it seems this will take some time. Use msleep(). */
2637                 for (i = 40; i; i--) {
2638                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2639                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2640                                 goto out;
2641                         msleep(1);
2642                 }
2643                 b43err(dev->wl, "MAC suspend failed\n");
2644         }
2645 out:
2646         dev->mac_suspended++;
2647 }
2648
2649 static void b43_adjust_opmode(struct b43_wldev *dev)
2650 {
2651         struct b43_wl *wl = dev->wl;
2652         u32 ctl;
2653         u16 cfp_pretbtt;
2654
2655         ctl = b43_read32(dev, B43_MMIO_MACCTL);
2656         /* Reset status to STA infrastructure mode. */
2657         ctl &= ~B43_MACCTL_AP;
2658         ctl &= ~B43_MACCTL_KEEP_CTL;
2659         ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2660         ctl &= ~B43_MACCTL_KEEP_BAD;
2661         ctl &= ~B43_MACCTL_PROMISC;
2662         ctl &= ~B43_MACCTL_BEACPROMISC;
2663         ctl |= B43_MACCTL_INFRA;
2664
2665         if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2666             b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2667                 ctl |= B43_MACCTL_AP;
2668         else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2669                 ctl &= ~B43_MACCTL_INFRA;
2670
2671         if (wl->filter_flags & FIF_CONTROL)
2672                 ctl |= B43_MACCTL_KEEP_CTL;
2673         if (wl->filter_flags & FIF_FCSFAIL)
2674                 ctl |= B43_MACCTL_KEEP_BAD;
2675         if (wl->filter_flags & FIF_PLCPFAIL)
2676                 ctl |= B43_MACCTL_KEEP_BADPLCP;
2677         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2678                 ctl |= B43_MACCTL_PROMISC;
2679         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2680                 ctl |= B43_MACCTL_BEACPROMISC;
2681
2682         /* Workaround: On old hardware the HW-MAC-address-filter
2683          * doesn't work properly, so always run promisc in filter
2684          * it in software. */
2685         if (dev->dev->id.revision <= 4)
2686                 ctl |= B43_MACCTL_PROMISC;
2687
2688         b43_write32(dev, B43_MMIO_MACCTL, ctl);
2689
2690         cfp_pretbtt = 2;
2691         if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2692                 if (dev->dev->bus->chip_id == 0x4306 &&
2693                     dev->dev->bus->chip_rev == 3)
2694                         cfp_pretbtt = 100;
2695                 else
2696                         cfp_pretbtt = 50;
2697         }
2698         b43_write16(dev, 0x612, cfp_pretbtt);
2699
2700         /* FIXME: We don't currently implement the PMQ mechanism,
2701          *        so always disable it. If we want to implement PMQ,
2702          *        we need to enable it here (clear DISCPMQ) in AP mode.
2703          */
2704         if (0  /* ctl & B43_MACCTL_AP */) {
2705                 b43_write32(dev, B43_MMIO_MACCTL,
2706                             b43_read32(dev, B43_MMIO_MACCTL)
2707                             & ~B43_MACCTL_DISCPMQ);
2708         } else {
2709                 b43_write32(dev, B43_MMIO_MACCTL,
2710                             b43_read32(dev, B43_MMIO_MACCTL)
2711                             | B43_MACCTL_DISCPMQ);
2712         }
2713 }
2714
2715 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2716 {
2717         u16 offset;
2718
2719         if (is_ofdm) {
2720                 offset = 0x480;
2721                 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2722         } else {
2723                 offset = 0x4C0;
2724                 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2725         }
2726         b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2727                         b43_shm_read16(dev, B43_SHM_SHARED, offset));
2728 }
2729
2730 static void b43_rate_memory_init(struct b43_wldev *dev)
2731 {
2732         switch (dev->phy.type) {
2733         case B43_PHYTYPE_A:
2734         case B43_PHYTYPE_G:
2735         case B43_PHYTYPE_N:
2736         case B43_PHYTYPE_LP:
2737                 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2738                 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2739                 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2740                 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2741                 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2742                 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2743                 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2744                 if (dev->phy.type == B43_PHYTYPE_A)
2745                         break;
2746                 /* fallthrough */
2747         case B43_PHYTYPE_B:
2748                 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2749                 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2750                 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2751                 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2752                 break;
2753         default:
2754                 B43_WARN_ON(1);
2755         }
2756 }
2757
2758 /* Set the default values for the PHY TX Control Words. */
2759 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2760 {
2761         u16 ctl = 0;
2762
2763         ctl |= B43_TXH_PHY_ENC_CCK;
2764         ctl |= B43_TXH_PHY_ANT01AUTO;
2765         ctl |= B43_TXH_PHY_TXPWR;
2766
2767         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2768         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2769         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2770 }
2771
2772 /* Set the TX-Antenna for management frames sent by firmware. */
2773 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2774 {
2775         u16 ant;
2776         u16 tmp;
2777
2778         ant = b43_antenna_to_phyctl(antenna);
2779
2780         /* For ACK/CTS */
2781         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2782         tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2783         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2784         /* For Probe Resposes */
2785         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2786         tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2787         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2788 }
2789
2790 /* This is the opposite of b43_chip_init() */
2791 static void b43_chip_exit(struct b43_wldev *dev)
2792 {
2793         b43_phy_exit(dev);
2794         b43_gpio_cleanup(dev);
2795         /* firmware is released later */
2796 }
2797
2798 /* Initialize the chip
2799  * http://bcm-specs.sipsolutions.net/ChipInit
2800  */
2801 static int b43_chip_init(struct b43_wldev *dev)
2802 {
2803         struct b43_phy *phy = &dev->phy;
2804         int err;
2805         u32 value32, macctl;
2806         u16 value16;
2807
2808         /* Initialize the MAC control */
2809         macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2810         if (dev->phy.gmode)
2811                 macctl |= B43_MACCTL_GMODE;
2812         macctl |= B43_MACCTL_INFRA;
2813         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2814
2815         err = b43_request_firmware(dev);
2816         if (err)
2817                 goto out;
2818         err = b43_upload_microcode(dev);
2819         if (err)
2820                 goto out;       /* firmware is released later */
2821
2822         err = b43_gpio_init(dev);
2823         if (err)
2824                 goto out;       /* firmware is released later */
2825
2826         err = b43_upload_initvals(dev);
2827         if (err)
2828                 goto err_gpio_clean;
2829
2830         /* Turn the Analog on and initialize the PHY. */
2831         phy->ops->switch_analog(dev, 1);
2832         err = b43_phy_init(dev);
2833         if (err)
2834                 goto err_gpio_clean;
2835
2836         /* Disable Interference Mitigation. */
2837         if (phy->ops->interf_mitigation)
2838                 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2839
2840         /* Select the antennae */
2841         if (phy->ops->set_rx_antenna)
2842                 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2843         b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2844
2845         if (phy->type == B43_PHYTYPE_B) {
2846                 value16 = b43_read16(dev, 0x005E);
2847                 value16 |= 0x0004;
2848                 b43_write16(dev, 0x005E, value16);
2849         }
2850         b43_write32(dev, 0x0100, 0x01000000);
2851         if (dev->dev->id.revision < 5)
2852                 b43_write32(dev, 0x010C, 0x01000000);
2853
2854         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2855                     & ~B43_MACCTL_INFRA);
2856         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2857                     | B43_MACCTL_INFRA);
2858
2859         /* Probe Response Timeout value */
2860         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2861         b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2862
2863         /* Initially set the wireless operation mode. */
2864         b43_adjust_opmode(dev);
2865
2866         if (dev->dev->id.revision < 3) {
2867                 b43_write16(dev, 0x060E, 0x0000);
2868                 b43_write16(dev, 0x0610, 0x8000);
2869                 b43_write16(dev, 0x0604, 0x0000);
2870                 b43_write16(dev, 0x0606, 0x0200);
2871         } else {
2872                 b43_write32(dev, 0x0188, 0x80000000);
2873                 b43_write32(dev, 0x018C, 0x02000000);
2874         }
2875         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2876         b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2877         b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2878         b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2879         b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2880         b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2881         b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2882
2883         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2884         value32 |= 0x00100000;
2885         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2886
2887         b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2888                     dev->dev->bus->chipco.fast_pwrup_delay);
2889
2890         err = 0;
2891         b43dbg(dev->wl, "Chip initialized\n");
2892 out:
2893         return err;
2894
2895 err_gpio_clean:
2896         b43_gpio_cleanup(dev);
2897         return err;
2898 }
2899
2900 static void b43_periodic_every60sec(struct b43_wldev *dev)
2901 {
2902         const struct b43_phy_operations *ops = dev->phy.ops;
2903
2904         if (ops->pwork_60sec)
2905                 ops->pwork_60sec(dev);
2906
2907         /* Force check the TX power emission now. */
2908         b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2909 }
2910
2911 static void b43_periodic_every30sec(struct b43_wldev *dev)
2912 {
2913         /* Update device statistics. */
2914         b43_calculate_link_quality(dev);
2915 }
2916
2917 static void b43_periodic_every15sec(struct b43_wldev *dev)
2918 {
2919         struct b43_phy *phy = &dev->phy;
2920         u16 wdr;
2921
2922         if (dev->fw.opensource) {
2923                 /* Check if the firmware is still alive.
2924                  * It will reset the watchdog counter to 0 in its idle loop. */
2925                 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2926                 if (unlikely(wdr)) {
2927                         b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2928                         b43_controller_restart(dev, "Firmware watchdog");
2929                         return;
2930                 } else {
2931                         b43_shm_write16(dev, B43_SHM_SCRATCH,
2932                                         B43_WATCHDOG_REG, 1);
2933                 }
2934         }
2935
2936         if (phy->ops->pwork_15sec)
2937                 phy->ops->pwork_15sec(dev);
2938
2939         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2940         wmb();
2941
2942 #if B43_DEBUG
2943         if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
2944                 unsigned int i;
2945
2946                 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
2947                        dev->irq_count / 15,
2948                        dev->tx_count / 15,
2949                        dev->rx_count / 15);
2950                 dev->irq_count = 0;
2951                 dev->tx_count = 0;
2952                 dev->rx_count = 0;
2953                 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
2954                         if (dev->irq_bit_count[i]) {
2955                                 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
2956                                        dev->irq_bit_count[i] / 15, i, (1 << i));
2957                                 dev->irq_bit_count[i] = 0;
2958                         }
2959                 }
2960         }
2961 #endif
2962 }
2963
2964 static void do_periodic_work(struct b43_wldev *dev)
2965 {
2966         unsigned int state;
2967
2968         state = dev->periodic_state;
2969         if (state % 4 == 0)
2970                 b43_periodic_every60sec(dev);
2971         if (state % 2 == 0)
2972                 b43_periodic_every30sec(dev);
2973         b43_periodic_every15sec(dev);
2974 }
2975
2976 /* Periodic work locking policy:
2977  *      The whole periodic work handler is protected by
2978  *      wl->mutex. If another lock is needed somewhere in the
2979  *      pwork callchain, it's acquired in-place, where it's needed.
2980  */
2981 static void b43_periodic_work_handler(struct work_struct *work)
2982 {
2983         struct b43_wldev *dev = container_of(work, struct b43_wldev,
2984                                              periodic_work.work);
2985         struct b43_wl *wl = dev->wl;
2986         unsigned long delay;
2987
2988         mutex_lock(&wl->mutex);
2989
2990         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2991                 goto out;
2992         if (b43_debug(dev, B43_DBG_PWORK_STOP))
2993                 goto out_requeue;
2994
2995         do_periodic_work(dev);
2996
2997         dev->periodic_state++;
2998 out_requeue:
2999         if (b43_debug(dev, B43_DBG_PWORK_FAST))
3000                 delay = msecs_to_jiffies(50);
3001         else
3002                 delay = round_jiffies_relative(HZ * 15);
3003         ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3004 out:
3005         mutex_unlock(&wl->mutex);
3006 }
3007
3008 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3009 {
3010         struct delayed_work *work = &dev->periodic_work;
3011
3012         dev->periodic_state = 0;
3013         INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3014         ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3015 }
3016
3017 /* Check if communication with the device works correctly. */
3018 static int b43_validate_chipaccess(struct b43_wldev *dev)
3019 {
3020         u32 v, backup0, backup4;
3021
3022         backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3023         backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3024
3025         /* Check for read/write and endianness problems. */
3026         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3027         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3028                 goto error;
3029         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3030         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3031                 goto error;
3032
3033         /* Check if unaligned 32bit SHM_SHARED access works properly.
3034          * However, don't bail out on failure, because it's noncritical. */
3035         b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3036         b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3037         b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3038         b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3039         if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3040                 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3041         b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3042         if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3043             b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3044             b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3045             b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3046                 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3047
3048         b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3049         b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3050
3051         if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
3052                 /* The 32bit register shadows the two 16bit registers
3053                  * with update sideeffects. Validate this. */
3054                 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3055                 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3056                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3057                         goto error;
3058                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3059                         goto error;
3060         }
3061         b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3062
3063         v = b43_read32(dev, B43_MMIO_MACCTL);
3064         v |= B43_MACCTL_GMODE;
3065         if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3066                 goto error;
3067
3068         return 0;
3069 error:
3070         b43err(dev->wl, "Failed to validate the chipaccess\n");
3071         return -ENODEV;
3072 }
3073
3074 static void b43_security_init(struct b43_wldev *dev)
3075 {
3076         dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3077         /* KTP is a word address, but we address SHM bytewise.
3078          * So multiply by two.
3079          */
3080         dev->ktp *= 2;
3081         /* Number of RCMTA address slots */
3082         b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3083         /* Clear the key memory. */
3084         b43_clear_keys(dev);
3085 }
3086
3087 #ifdef CONFIG_B43_HWRNG
3088 static int b43_rng_read(struct hwrng *rng, u32 *data)
3089 {
3090         struct b43_wl *wl = (struct b43_wl *)rng->priv;
3091         struct b43_wldev *dev;
3092         int count = -ENODEV;
3093
3094         mutex_lock(&wl->mutex);
3095         dev = wl->current_dev;
3096         if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3097                 *data = b43_read16(dev, B43_MMIO_RNG);
3098                 count = sizeof(u16);
3099         }
3100         mutex_unlock(&wl->mutex);
3101
3102         return count;
3103 }
3104 #endif /* CONFIG_B43_HWRNG */
3105
3106 static void b43_rng_exit(struct b43_wl *wl)
3107 {
3108 #ifdef CONFIG_B43_HWRNG
3109         if (wl->rng_initialized)
3110                 hwrng_unregister(&wl->rng);
3111 #endif /* CONFIG_B43_HWRNG */
3112 }
3113
3114 static int b43_rng_init(struct b43_wl *wl)
3115 {
3116         int err = 0;
3117
3118 #ifdef CONFIG_B43_HWRNG
3119         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3120                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3121         wl->rng.name = wl->rng_name;
3122         wl->rng.data_read = b43_rng_read;
3123         wl->rng.priv = (unsigned long)wl;
3124         wl->rng_initialized = 1;
3125         err = hwrng_register(&wl->rng);
3126         if (err) {
3127                 wl->rng_initialized = 0;
3128                 b43err(wl, "Failed to register the random "
3129                        "number generator (%d)\n", err);
3130         }
3131 #endif /* CONFIG_B43_HWRNG */
3132
3133         return err;
3134 }
3135
3136 static void b43_tx_work(struct work_struct *work)
3137 {
3138         struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3139         struct b43_wldev *dev;
3140         struct sk_buff *skb;
3141         int err = 0;
3142
3143         mutex_lock(&wl->mutex);
3144         dev = wl->current_dev;
3145         if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3146                 mutex_unlock(&wl->mutex);
3147                 return;
3148         }
3149
3150         while (skb_queue_len(&wl->tx_queue)) {
3151                 skb = skb_dequeue(&wl->tx_queue);
3152
3153                 if (b43_using_pio_transfers(dev))
3154                         err = b43_pio_tx(dev, skb);
3155                 else
3156                         err = b43_dma_tx(dev, skb);
3157                 if (unlikely(err))
3158                         dev_kfree_skb(skb); /* Drop it */
3159         }
3160
3161 #if B43_DEBUG
3162         dev->tx_count++;
3163 #endif
3164         mutex_unlock(&wl->mutex);
3165 }
3166
3167 static int b43_op_tx(struct ieee80211_hw *hw,
3168                      struct sk_buff *skb)
3169 {
3170         struct b43_wl *wl = hw_to_b43_wl(hw);
3171
3172         if (unlikely(skb->len < 2 + 2 + 6)) {
3173                 /* Too short, this can't be a valid frame. */
3174                 dev_kfree_skb_any(skb);
3175                 return NETDEV_TX_OK;
3176         }
3177         B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3178
3179         skb_queue_tail(&wl->tx_queue, skb);
3180         ieee80211_queue_work(wl->hw, &wl->tx_work);
3181
3182         return NETDEV_TX_OK;
3183 }
3184
3185 static void b43_qos_params_upload(struct b43_wldev *dev,
3186                                   const struct ieee80211_tx_queue_params *p,
3187                                   u16 shm_offset)
3188 {
3189         u16 params[B43_NR_QOSPARAMS];
3190         int bslots, tmp;
3191         unsigned int i;
3192
3193         if (!dev->qos_enabled)
3194                 return;
3195
3196         bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3197
3198         memset(&params, 0, sizeof(params));
3199
3200         params[B43_QOSPARAM_TXOP] = p->txop * 32;
3201         params[B43_QOSPARAM_CWMIN] = p->cw_min;
3202         params[B43_QOSPARAM_CWMAX] = p->cw_max;
3203         params[B43_QOSPARAM_CWCUR] = p->cw_min;
3204         params[B43_QOSPARAM_AIFS] = p->aifs;
3205         params[B43_QOSPARAM_BSLOTS] = bslots;
3206         params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3207
3208         for (i = 0; i < ARRAY_SIZE(params); i++) {
3209                 if (i == B43_QOSPARAM_STATUS) {
3210                         tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3211                                              shm_offset + (i * 2));
3212                         /* Mark the parameters as updated. */
3213                         tmp |= 0x100;
3214                         b43_shm_write16(dev, B43_SHM_SHARED,
3215                                         shm_offset + (i * 2),
3216                                         tmp);
3217                 } else {
3218                         b43_shm_write16(dev, B43_SHM_SHARED,
3219                                         shm_offset + (i * 2),
3220                                         params[i]);
3221                 }
3222         }
3223 }
3224
3225 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3226 static const u16 b43_qos_shm_offsets[] = {
3227         /* [mac80211-queue-nr] = SHM_OFFSET, */
3228         [0] = B43_QOS_VOICE,
3229         [1] = B43_QOS_VIDEO,
3230         [2] = B43_QOS_BESTEFFORT,
3231         [3] = B43_QOS_BACKGROUND,
3232 };
3233
3234 /* Update all QOS parameters in hardware. */
3235 static void b43_qos_upload_all(struct b43_wldev *dev)
3236 {
3237         struct b43_wl *wl = dev->wl;
3238         struct b43_qos_params *params;
3239         unsigned int i;
3240
3241         if (!dev->qos_enabled)
3242                 return;
3243
3244         BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3245                      ARRAY_SIZE(wl->qos_params));
3246
3247         b43_mac_suspend(dev);
3248         for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3249                 params = &(wl->qos_params[i]);
3250                 b43_qos_params_upload(dev, &(params->p),
3251                                       b43_qos_shm_offsets[i]);
3252         }
3253         b43_mac_enable(dev);
3254 }
3255
3256 static void b43_qos_clear(struct b43_wl *wl)
3257 {
3258         struct b43_qos_params *params;
3259         unsigned int i;
3260
3261         /* Initialize QoS parameters to sane defaults. */
3262
3263         BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3264                      ARRAY_SIZE(wl->qos_params));
3265
3266         for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3267                 params = &(wl->qos_params[i]);
3268
3269                 switch (b43_qos_shm_offsets[i]) {
3270                 case B43_QOS_VOICE:
3271                         params->p.txop = 0;
3272                         params->p.aifs = 2;
3273                         params->p.cw_min = 0x0001;
3274                         params->p.cw_max = 0x0001;
3275                         break;
3276                 case B43_QOS_VIDEO:
3277                         params->p.txop = 0;
3278                         params->p.aifs = 2;
3279                         params->p.cw_min = 0x0001;
3280                         params->p.cw_max = 0x0001;
3281                         break;
3282                 case B43_QOS_BESTEFFORT:
3283                         params->p.txop = 0;
3284                         params->p.aifs = 3;
3285                         params->p.cw_min = 0x0001;
3286                         params->p.cw_max = 0x03FF;
3287                         break;
3288                 case B43_QOS_BACKGROUND:
3289                         params->p.txop = 0;
3290                         params->p.aifs = 7;
3291                         params->p.cw_min = 0x0001;
3292                         params->p.cw_max = 0x03FF;
3293                         break;
3294                 default:
3295                         B43_WARN_ON(1);
3296                 }
3297         }
3298 }
3299
3300 /* Initialize the core's QOS capabilities */
3301 static void b43_qos_init(struct b43_wldev *dev)
3302 {
3303         if (!dev->qos_enabled) {
3304                 /* Disable QOS support. */
3305                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3306                 b43_write16(dev, B43_MMIO_IFSCTL,
3307                             b43_read16(dev, B43_MMIO_IFSCTL)