1d070be5a678de09584f49adb88fa8da2212b3c9
[kernel.git] / drivers / net / wireless / b43legacy / main.c
1 /*
2  *
3  *  Broadcom B43legacy wireless driver
4  *
5  *  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6  *  Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
7  *  Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8  *  Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9  *  Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10  *  Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
11  *
12  *  Some parts of the code in this file are derived from the ipw2200
13  *  driver  Copyright(c) 2003 - 2004 Intel Corporation.
14
15  *  This program is free software; you can redistribute it and/or modify
16  *  it under the terms of the GNU General Public License as published by
17  *  the Free Software Foundation; either version 2 of the License, or
18  *  (at your option) any later version.
19  *
20  *  This program is distributed in the hope that it will be useful,
21  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
22  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  *  GNU General Public License for more details.
24  *
25  *  You should have received a copy of the GNU General Public License
26  *  along with this program; see the file COPYING.  If not, write to
27  *  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
28  *  Boston, MA 02110-1301, USA.
29  *
30  */
31
32 #include <linux/delay.h>
33 #include <linux/init.h>
34 #include <linux/moduleparam.h>
35 #include <linux/if_arp.h>
36 #include <linux/etherdevice.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/dma-mapping.h>
43 #include <net/dst.h>
44 #include <asm/unaligned.h>
45
46 #include "b43legacy.h"
47 #include "main.h"
48 #include "debugfs.h"
49 #include "phy.h"
50 #include "dma.h"
51 #include "pio.h"
52 #include "sysfs.h"
53 #include "xmit.h"
54 #include "radio.h"
55
56
57 MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
62
63 MODULE_FIRMWARE(B43legacy_SUPPORTED_FIRMWARE_ID);
64 MODULE_FIRMWARE("b43legacy/ucode2.fw");
65 MODULE_FIRMWARE("b43legacy/ucode4.fw");
66
67 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
68 static int modparam_pio;
69 module_param_named(pio, modparam_pio, int, 0444);
70 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
71 #elif defined(CONFIG_B43LEGACY_DMA)
72 # define modparam_pio   0
73 #elif defined(CONFIG_B43LEGACY_PIO)
74 # define modparam_pio   1
75 #endif
76
77 static int modparam_bad_frames_preempt;
78 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
79 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
80                  " Preemption");
81
82 static char modparam_fwpostfix[16];
83 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
84 MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
85
86 /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
87 static const struct ssb_device_id b43legacy_ssb_tbl[] = {
88         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
89         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
90         SSB_DEVTABLE_END
91 };
92 MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
93
94
95 /* Channel and ratetables are shared for all devices.
96  * They can't be const, because ieee80211 puts some precalculated
97  * data in there. This data is the same for all devices, so we don't
98  * get concurrency issues */
99 #define RATETAB_ENT(_rateid, _flags) \
100         {                                                               \
101                 .bitrate        = B43legacy_RATE_TO_100KBPS(_rateid),   \
102                 .hw_value       = (_rateid),                            \
103                 .flags          = (_flags),                             \
104         }
105 /*
106  * NOTE: When changing this, sync with xmit.c's
107  *       b43legacy_plcp_get_bitrate_idx_* functions!
108  */
109 static struct ieee80211_rate __b43legacy_ratetable[] = {
110         RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
111         RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
112         RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
113         RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
114         RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
115         RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
116         RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
117         RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
118         RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
119         RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
120         RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
121         RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
122 };
123 #define b43legacy_b_ratetable           (__b43legacy_ratetable + 0)
124 #define b43legacy_b_ratetable_size      4
125 #define b43legacy_g_ratetable           (__b43legacy_ratetable + 0)
126 #define b43legacy_g_ratetable_size      12
127
128 #define CHANTAB_ENT(_chanid, _freq) \
129         {                                                       \
130                 .center_freq    = (_freq),                      \
131                 .hw_value       = (_chanid),                    \
132         }
133 static struct ieee80211_channel b43legacy_bg_chantable[] = {
134         CHANTAB_ENT(1, 2412),
135         CHANTAB_ENT(2, 2417),
136         CHANTAB_ENT(3, 2422),
137         CHANTAB_ENT(4, 2427),
138         CHANTAB_ENT(5, 2432),
139         CHANTAB_ENT(6, 2437),
140         CHANTAB_ENT(7, 2442),
141         CHANTAB_ENT(8, 2447),
142         CHANTAB_ENT(9, 2452),
143         CHANTAB_ENT(10, 2457),
144         CHANTAB_ENT(11, 2462),
145         CHANTAB_ENT(12, 2467),
146         CHANTAB_ENT(13, 2472),
147         CHANTAB_ENT(14, 2484),
148 };
149
150 static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
151         .channels = b43legacy_bg_chantable,
152         .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
153         .bitrates = b43legacy_b_ratetable,
154         .n_bitrates = b43legacy_b_ratetable_size,
155 };
156
157 static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
158         .channels = b43legacy_bg_chantable,
159         .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
160         .bitrates = b43legacy_g_ratetable,
161         .n_bitrates = b43legacy_g_ratetable_size,
162 };
163
164 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
165 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
166 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
167 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
168
169
170 static int b43legacy_ratelimit(struct b43legacy_wl *wl)
171 {
172         if (!wl || !wl->current_dev)
173                 return 1;
174         if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
175                 return 1;
176         /* We are up and running.
177          * Ratelimit the messages to avoid DoS over the net. */
178         return net_ratelimit();
179 }
180
181 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
182 {
183         va_list args;
184
185         if (!b43legacy_ratelimit(wl))
186                 return;
187         va_start(args, fmt);
188         printk(KERN_INFO "b43legacy-%s: ",
189                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
190         vprintk(fmt, args);
191         va_end(args);
192 }
193
194 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
195 {
196         va_list args;
197
198         if (!b43legacy_ratelimit(wl))
199                 return;
200         va_start(args, fmt);
201         printk(KERN_ERR "b43legacy-%s ERROR: ",
202                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
203         vprintk(fmt, args);
204         va_end(args);
205 }
206
207 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
208 {
209         va_list args;
210
211         if (!b43legacy_ratelimit(wl))
212                 return;
213         va_start(args, fmt);
214         printk(KERN_WARNING "b43legacy-%s warning: ",
215                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
216         vprintk(fmt, args);
217         va_end(args);
218 }
219
220 #if B43legacy_DEBUG
221 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
222 {
223         va_list args;
224
225         va_start(args, fmt);
226         printk(KERN_DEBUG "b43legacy-%s debug: ",
227                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
228         vprintk(fmt, args);
229         va_end(args);
230 }
231 #endif /* DEBUG */
232
233 static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
234                                 u32 val)
235 {
236         u32 status;
237
238         B43legacy_WARN_ON(offset % 4 != 0);
239
240         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
241         if (status & B43legacy_MACCTL_BE)
242                 val = swab32(val);
243
244         b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
245         mmiowb();
246         b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
247 }
248
249 static inline
250 void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
251                                 u16 routing, u16 offset)
252 {
253         u32 control;
254
255         /* "offset" is the WORD offset. */
256
257         control = routing;
258         control <<= 16;
259         control |= offset;
260         b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
261 }
262
263 u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
264                        u16 routing, u16 offset)
265 {
266         u32 ret;
267
268         if (routing == B43legacy_SHM_SHARED) {
269                 B43legacy_WARN_ON((offset & 0x0001) != 0);
270                 if (offset & 0x0003) {
271                         /* Unaligned access */
272                         b43legacy_shm_control_word(dev, routing, offset >> 2);
273                         ret = b43legacy_read16(dev,
274                                 B43legacy_MMIO_SHM_DATA_UNALIGNED);
275                         ret <<= 16;
276                         b43legacy_shm_control_word(dev, routing,
277                                                      (offset >> 2) + 1);
278                         ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
279
280                         return ret;
281                 }
282                 offset >>= 2;
283         }
284         b43legacy_shm_control_word(dev, routing, offset);
285         ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
286
287         return ret;
288 }
289
290 u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
291                            u16 routing, u16 offset)
292 {
293         u16 ret;
294
295         if (routing == B43legacy_SHM_SHARED) {
296                 B43legacy_WARN_ON((offset & 0x0001) != 0);
297                 if (offset & 0x0003) {
298                         /* Unaligned access */
299                         b43legacy_shm_control_word(dev, routing, offset >> 2);
300                         ret = b43legacy_read16(dev,
301                                              B43legacy_MMIO_SHM_DATA_UNALIGNED);
302
303                         return ret;
304                 }
305                 offset >>= 2;
306         }
307         b43legacy_shm_control_word(dev, routing, offset);
308         ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
309
310         return ret;
311 }
312
313 void b43legacy_shm_write32(struct b43legacy_wldev *dev,
314                            u16 routing, u16 offset,
315                            u32 value)
316 {
317         if (routing == B43legacy_SHM_SHARED) {
318                 B43legacy_WARN_ON((offset & 0x0001) != 0);
319                 if (offset & 0x0003) {
320                         /* Unaligned access */
321                         b43legacy_shm_control_word(dev, routing, offset >> 2);
322                         mmiowb();
323                         b43legacy_write16(dev,
324                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
325                                           (value >> 16) & 0xffff);
326                         mmiowb();
327                         b43legacy_shm_control_word(dev, routing,
328                                                    (offset >> 2) + 1);
329                         mmiowb();
330                         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
331                                           value & 0xffff);
332                         return;
333                 }
334                 offset >>= 2;
335         }
336         b43legacy_shm_control_word(dev, routing, offset);
337         mmiowb();
338         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
339 }
340
341 void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
342                            u16 value)
343 {
344         if (routing == B43legacy_SHM_SHARED) {
345                 B43legacy_WARN_ON((offset & 0x0001) != 0);
346                 if (offset & 0x0003) {
347                         /* Unaligned access */
348                         b43legacy_shm_control_word(dev, routing, offset >> 2);
349                         mmiowb();
350                         b43legacy_write16(dev,
351                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
352                                           value);
353                         return;
354                 }
355                 offset >>= 2;
356         }
357         b43legacy_shm_control_word(dev, routing, offset);
358         mmiowb();
359         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
360 }
361
362 /* Read HostFlags */
363 u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
364 {
365         u32 ret;
366
367         ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
368                                    B43legacy_SHM_SH_HOSTFHI);
369         ret <<= 16;
370         ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
371                                     B43legacy_SHM_SH_HOSTFLO);
372
373         return ret;
374 }
375
376 /* Write HostFlags */
377 void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
378 {
379         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
380                               B43legacy_SHM_SH_HOSTFLO,
381                               (value & 0x0000FFFF));
382         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
383                               B43legacy_SHM_SH_HOSTFHI,
384                               ((value & 0xFFFF0000) >> 16));
385 }
386
387 void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
388 {
389         /* We need to be careful. As we read the TSF from multiple
390          * registers, we should take care of register overflows.
391          * In theory, the whole tsf read process should be atomic.
392          * We try to be atomic here, by restaring the read process,
393          * if any of the high registers changed (overflew).
394          */
395         if (dev->dev->id.revision >= 3) {
396                 u32 low;
397                 u32 high;
398                 u32 high2;
399
400                 do {
401                         high = b43legacy_read32(dev,
402                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
403                         low = b43legacy_read32(dev,
404                                         B43legacy_MMIO_REV3PLUS_TSF_LOW);
405                         high2 = b43legacy_read32(dev,
406                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
407                 } while (unlikely(high != high2));
408
409                 *tsf = high;
410                 *tsf <<= 32;
411                 *tsf |= low;
412         } else {
413                 u64 tmp;
414                 u16 v0;
415                 u16 v1;
416                 u16 v2;
417                 u16 v3;
418                 u16 test1;
419                 u16 test2;
420                 u16 test3;
421
422                 do {
423                         v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
424                         v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
425                         v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
426                         v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
427
428                         test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
429                         test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
430                         test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
431                 } while (v3 != test3 || v2 != test2 || v1 != test1);
432
433                 *tsf = v3;
434                 *tsf <<= 48;
435                 tmp = v2;
436                 tmp <<= 32;
437                 *tsf |= tmp;
438                 tmp = v1;
439                 tmp <<= 16;
440                 *tsf |= tmp;
441                 *tsf |= v0;
442         }
443 }
444
445 static void b43legacy_time_lock(struct b43legacy_wldev *dev)
446 {
447         u32 status;
448
449         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
450         status |= B43legacy_MACCTL_TBTTHOLD;
451         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
452         mmiowb();
453 }
454
455 static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
456 {
457         u32 status;
458
459         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
460         status &= ~B43legacy_MACCTL_TBTTHOLD;
461         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
462 }
463
464 static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
465 {
466         /* Be careful with the in-progress timer.
467          * First zero out the low register, so we have a full
468          * register-overflow duration to complete the operation.
469          */
470         if (dev->dev->id.revision >= 3) {
471                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
472                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
473
474                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
475                 mmiowb();
476                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
477                                     hi);
478                 mmiowb();
479                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
480                                     lo);
481         } else {
482                 u16 v0 = (tsf & 0x000000000000FFFFULL);
483                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
484                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
485                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
486
487                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
488                 mmiowb();
489                 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
490                 mmiowb();
491                 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
492                 mmiowb();
493                 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
494                 mmiowb();
495                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
496         }
497 }
498
499 void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
500 {
501         b43legacy_time_lock(dev);
502         b43legacy_tsf_write_locked(dev, tsf);
503         b43legacy_time_unlock(dev);
504 }
505
506 static
507 void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
508                              u16 offset, const u8 *mac)
509 {
510         static const u8 zero_addr[ETH_ALEN] = { 0 };
511         u16 data;
512
513         if (!mac)
514                 mac = zero_addr;
515
516         offset |= 0x0020;
517         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
518
519         data = mac[0];
520         data |= mac[1] << 8;
521         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
522         data = mac[2];
523         data |= mac[3] << 8;
524         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
525         data = mac[4];
526         data |= mac[5] << 8;
527         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
528 }
529
530 static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
531 {
532         static const u8 zero_addr[ETH_ALEN] = { 0 };
533         const u8 *mac = dev->wl->mac_addr;
534         const u8 *bssid = dev->wl->bssid;
535         u8 mac_bssid[ETH_ALEN * 2];
536         int i;
537         u32 tmp;
538
539         if (!bssid)
540                 bssid = zero_addr;
541         if (!mac)
542                 mac = zero_addr;
543
544         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
545
546         memcpy(mac_bssid, mac, ETH_ALEN);
547         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
548
549         /* Write our MAC address and BSSID to template ram */
550         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
551                 tmp =  (u32)(mac_bssid[i + 0]);
552                 tmp |= (u32)(mac_bssid[i + 1]) << 8;
553                 tmp |= (u32)(mac_bssid[i + 2]) << 16;
554                 tmp |= (u32)(mac_bssid[i + 3]) << 24;
555                 b43legacy_ram_write(dev, 0x20 + i, tmp);
556                 b43legacy_ram_write(dev, 0x78 + i, tmp);
557                 b43legacy_ram_write(dev, 0x478 + i, tmp);
558         }
559 }
560
561 static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
562 {
563         b43legacy_write_mac_bssid_templates(dev);
564         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
565                                 dev->wl->mac_addr);
566 }
567
568 static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
569                                     u16 slot_time)
570 {
571         /* slot_time is in usec. */
572         if (dev->phy.type != B43legacy_PHYTYPE_G)
573                 return;
574         b43legacy_write16(dev, 0x684, 510 + slot_time);
575         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
576                               slot_time);
577 }
578
579 static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
580 {
581         b43legacy_set_slot_time(dev, 9);
582 }
583
584 static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
585 {
586         b43legacy_set_slot_time(dev, 20);
587 }
588
589 /* Synchronize IRQ top- and bottom-half.
590  * IRQs must be masked before calling this.
591  * This must not be called with the irq_lock held.
592  */
593 static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
594 {
595         synchronize_irq(dev->dev->irq);
596         tasklet_kill(&dev->isr_tasklet);
597 }
598
599 /* DummyTransmission function, as documented on
600  * http://bcm-specs.sipsolutions.net/DummyTransmission
601  */
602 void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
603 {
604         struct b43legacy_phy *phy = &dev->phy;
605         unsigned int i;
606         unsigned int max_loop;
607         u16 value;
608         u32 buffer[5] = {
609                 0x00000000,
610                 0x00D40000,
611                 0x00000000,
612                 0x01000000,
613                 0x00000000,
614         };
615
616         switch (phy->type) {
617         case B43legacy_PHYTYPE_B:
618         case B43legacy_PHYTYPE_G:
619                 max_loop = 0xFA;
620                 buffer[0] = 0x000B846E;
621                 break;
622         default:
623                 B43legacy_BUG_ON(1);
624                 return;
625         }
626
627         for (i = 0; i < 5; i++)
628                 b43legacy_ram_write(dev, i * 4, buffer[i]);
629
630         /* dummy read follows */
631         b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
632
633         b43legacy_write16(dev, 0x0568, 0x0000);
634         b43legacy_write16(dev, 0x07C0, 0x0000);
635         b43legacy_write16(dev, 0x050C, 0x0000);
636         b43legacy_write16(dev, 0x0508, 0x0000);
637         b43legacy_write16(dev, 0x050A, 0x0000);
638         b43legacy_write16(dev, 0x054C, 0x0000);
639         b43legacy_write16(dev, 0x056A, 0x0014);
640         b43legacy_write16(dev, 0x0568, 0x0826);
641         b43legacy_write16(dev, 0x0500, 0x0000);
642         b43legacy_write16(dev, 0x0502, 0x0030);
643
644         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
645                 b43legacy_radio_write16(dev, 0x0051, 0x0017);
646         for (i = 0x00; i < max_loop; i++) {
647                 value = b43legacy_read16(dev, 0x050E);
648                 if (value & 0x0080)
649                         break;
650                 udelay(10);
651         }
652         for (i = 0x00; i < 0x0A; i++) {
653                 value = b43legacy_read16(dev, 0x050E);
654                 if (value & 0x0400)
655                         break;
656                 udelay(10);
657         }
658         for (i = 0x00; i < 0x0A; i++) {
659                 value = b43legacy_read16(dev, 0x0690);
660                 if (!(value & 0x0100))
661                         break;
662                 udelay(10);
663         }
664         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
665                 b43legacy_radio_write16(dev, 0x0051, 0x0037);
666 }
667
668 /* Turn the Analog ON/OFF */
669 static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
670 {
671         b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
672 }
673
674 void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
675 {
676         u32 tmslow;
677         u32 macctl;
678
679         flags |= B43legacy_TMSLOW_PHYCLKEN;
680         flags |= B43legacy_TMSLOW_PHYRESET;
681         ssb_device_enable(dev->dev, flags);
682         msleep(2); /* Wait for the PLL to turn on. */
683
684         /* Now take the PHY out of Reset again */
685         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
686         tmslow |= SSB_TMSLOW_FGC;
687         tmslow &= ~B43legacy_TMSLOW_PHYRESET;
688         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
689         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
690         msleep(1);
691         tmslow &= ~SSB_TMSLOW_FGC;
692         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
693         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
694         msleep(1);
695
696         /* Turn Analog ON */
697         b43legacy_switch_analog(dev, 1);
698
699         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
700         macctl &= ~B43legacy_MACCTL_GMODE;
701         if (flags & B43legacy_TMSLOW_GMODE) {
702                 macctl |= B43legacy_MACCTL_GMODE;
703                 dev->phy.gmode = 1;
704         } else
705                 dev->phy.gmode = 0;
706         macctl |= B43legacy_MACCTL_IHR_ENABLED;
707         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
708 }
709
710 static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
711 {
712         u32 v0;
713         u32 v1;
714         u16 tmp;
715         struct b43legacy_txstatus stat;
716
717         while (1) {
718                 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
719                 if (!(v0 & 0x00000001))
720                         break;
721                 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
722
723                 stat.cookie = (v0 >> 16);
724                 stat.seq = (v1 & 0x0000FFFF);
725                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
726                 tmp = (v0 & 0x0000FFFF);
727                 stat.frame_count = ((tmp & 0xF000) >> 12);
728                 stat.rts_count = ((tmp & 0x0F00) >> 8);
729                 stat.supp_reason = ((tmp & 0x001C) >> 2);
730                 stat.pm_indicated = !!(tmp & 0x0080);
731                 stat.intermediate = !!(tmp & 0x0040);
732                 stat.for_ampdu = !!(tmp & 0x0020);
733                 stat.acked = !!(tmp & 0x0002);
734
735                 b43legacy_handle_txstatus(dev, &stat);
736         }
737 }
738
739 static void drain_txstatus_queue(struct b43legacy_wldev *dev)
740 {
741         u32 dummy;
742
743         if (dev->dev->id.revision < 5)
744                 return;
745         /* Read all entries from the microcode TXstatus FIFO
746          * and throw them away.
747          */
748         while (1) {
749                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
750                 if (!(dummy & 0x00000001))
751                         break;
752                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
753         }
754 }
755
756 static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
757 {
758         u32 val = 0;
759
760         val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
761         val <<= 16;
762         val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
763
764         return val;
765 }
766
767 static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
768 {
769         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
770                               (jssi & 0x0000FFFF));
771         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
772                               (jssi & 0xFFFF0000) >> 16);
773 }
774
775 static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
776 {
777         b43legacy_jssi_write(dev, 0x7F7F7F7F);
778         b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
779                           b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
780                           | B43legacy_MACCMD_BGNOISE);
781         B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
782                             dev->phy.channel);
783 }
784
785 static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
786 {
787         /* Top half of Link Quality calculation. */
788
789         if (dev->noisecalc.calculation_running)
790                 return;
791         dev->noisecalc.channel_at_start = dev->phy.channel;
792         dev->noisecalc.calculation_running = 1;
793         dev->noisecalc.nr_samples = 0;
794
795         b43legacy_generate_noise_sample(dev);
796 }
797
798 static void handle_irq_noise(struct b43legacy_wldev *dev)
799 {
800         struct b43legacy_phy *phy = &dev->phy;
801         u16 tmp;
802         u8 noise[4];
803         u8 i;
804         u8 j;
805         s32 average;
806
807         /* Bottom half of Link Quality calculation. */
808
809         B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
810         if (dev->noisecalc.channel_at_start != phy->channel)
811                 goto drop_calculation;
812         *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
813         if (noise[0] == 0x7F || noise[1] == 0x7F ||
814             noise[2] == 0x7F || noise[3] == 0x7F)
815                 goto generate_new;
816
817         /* Get the noise samples. */
818         B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
819         i = dev->noisecalc.nr_samples;
820         noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
821         noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
822         noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
823         noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
824         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
825         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
826         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
827         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
828         dev->noisecalc.nr_samples++;
829         if (dev->noisecalc.nr_samples == 8) {
830                 /* Calculate the Link Quality by the noise samples. */
831                 average = 0;
832                 for (i = 0; i < 8; i++) {
833                         for (j = 0; j < 4; j++)
834                                 average += dev->noisecalc.samples[i][j];
835                 }
836                 average /= (8 * 4);
837                 average *= 125;
838                 average += 64;
839                 average /= 128;
840                 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
841                                              0x40C);
842                 tmp = (tmp / 128) & 0x1F;
843                 if (tmp >= 8)
844                         average += 2;
845                 else
846                         average -= 25;
847                 if (tmp == 8)
848                         average -= 72;
849                 else
850                         average -= 48;
851
852                 dev->stats.link_noise = average;
853 drop_calculation:
854                 dev->noisecalc.calculation_running = 0;
855                 return;
856         }
857 generate_new:
858         b43legacy_generate_noise_sample(dev);
859 }
860
861 static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
862 {
863         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
864                 /* TODO: PS TBTT */
865         } else {
866                 if (1/*FIXME: the last PSpoll frame was sent successfully */)
867                         b43legacy_power_saving_ctl_bits(dev, -1, -1);
868         }
869         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
870                 dev->dfq_valid = 1;
871 }
872
873 static void handle_irq_atim_end(struct b43legacy_wldev *dev)
874 {
875         if (dev->dfq_valid) {
876                 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
877                                   b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
878                                   | B43legacy_MACCMD_DFQ_VALID);
879                 dev->dfq_valid = 0;
880         }
881 }
882
883 static void handle_irq_pmq(struct b43legacy_wldev *dev)
884 {
885         u32 tmp;
886
887         /* TODO: AP mode. */
888
889         while (1) {
890                 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
891                 if (!(tmp & 0x00000008))
892                         break;
893         }
894         /* 16bit write is odd, but correct. */
895         b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
896 }
897
898 static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
899                                             const u8 *data, u16 size,
900                                             u16 ram_offset,
901                                             u16 shm_size_offset, u8 rate)
902 {
903         u32 i;
904         u32 tmp;
905         struct b43legacy_plcp_hdr4 plcp;
906
907         plcp.data = 0;
908         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
909         b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
910         ram_offset += sizeof(u32);
911         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
912          * So leave the first two bytes of the next write blank.
913          */
914         tmp = (u32)(data[0]) << 16;
915         tmp |= (u32)(data[1]) << 24;
916         b43legacy_ram_write(dev, ram_offset, tmp);
917         ram_offset += sizeof(u32);
918         for (i = 2; i < size; i += sizeof(u32)) {
919                 tmp = (u32)(data[i + 0]);
920                 if (i + 1 < size)
921                         tmp |= (u32)(data[i + 1]) << 8;
922                 if (i + 2 < size)
923                         tmp |= (u32)(data[i + 2]) << 16;
924                 if (i + 3 < size)
925                         tmp |= (u32)(data[i + 3]) << 24;
926                 b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
927         }
928         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
929                               size + sizeof(struct b43legacy_plcp_hdr6));
930 }
931
932 /* Convert a b43legacy antenna number value to the PHY TX control value. */
933 static u16 b43legacy_antenna_to_phyctl(int antenna)
934 {
935         switch (antenna) {
936         case B43legacy_ANTENNA0:
937                 return B43legacy_TX4_PHY_ANT0;
938         case B43legacy_ANTENNA1:
939                 return B43legacy_TX4_PHY_ANT1;
940         }
941         return B43legacy_TX4_PHY_ANTLAST;
942 }
943
944 static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
945                                             u16 ram_offset,
946                                             u16 shm_size_offset)
947 {
948
949         unsigned int i, len, variable_len;
950         const struct ieee80211_mgmt *bcn;
951         const u8 *ie;
952         bool tim_found = 0;
953         unsigned int rate;
954         u16 ctl;
955         int antenna;
956         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
957
958         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
959         len = min((size_t)dev->wl->current_beacon->len,
960                   0x200 - sizeof(struct b43legacy_plcp_hdr6));
961         rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
962
963         b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset,
964                                         shm_size_offset, rate);
965
966         /* Write the PHY TX control parameters. */
967         antenna = B43legacy_ANTENNA_DEFAULT;
968         antenna = b43legacy_antenna_to_phyctl(antenna);
969         ctl = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
970                                    B43legacy_SHM_SH_BEACPHYCTL);
971         /* We can't send beacons with short preamble. Would get PHY errors. */
972         ctl &= ~B43legacy_TX4_PHY_SHORTPRMBL;
973         ctl &= ~B43legacy_TX4_PHY_ANT;
974         ctl &= ~B43legacy_TX4_PHY_ENC;
975         ctl |= antenna;
976         ctl |= B43legacy_TX4_PHY_ENC_CCK;
977         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
978                               B43legacy_SHM_SH_BEACPHYCTL, ctl);
979
980         /* Find the position of the TIM and the DTIM_period value
981          * and write them to SHM. */
982         ie = bcn->u.beacon.variable;
983         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
984         for (i = 0; i < variable_len - 2; ) {
985                 uint8_t ie_id, ie_len;
986
987                 ie_id = ie[i];
988                 ie_len = ie[i + 1];
989                 if (ie_id == 5) {
990                         u16 tim_position;
991                         u16 dtim_period;
992                         /* This is the TIM Information Element */
993
994                         /* Check whether the ie_len is in the beacon data range. */
995                         if (variable_len < ie_len + 2 + i)
996                                 break;
997                         /* A valid TIM is at least 4 bytes long. */
998                         if (ie_len < 4)
999                                 break;
1000                         tim_found = 1;
1001
1002                         tim_position = sizeof(struct b43legacy_plcp_hdr6);
1003                         tim_position += offsetof(struct ieee80211_mgmt,
1004                                                  u.beacon.variable);
1005                         tim_position += i;
1006
1007                         dtim_period = ie[i + 3];
1008
1009                         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1010                                         B43legacy_SHM_SH_TIMPOS, tim_position);
1011                         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1012                                         B43legacy_SHM_SH_DTIMP, dtim_period);
1013                         break;
1014                 }
1015                 i += ie_len + 2;
1016         }
1017         if (!tim_found) {
1018                 b43legacywarn(dev->wl, "Did not find a valid TIM IE in the "
1019                               "beacon template packet. AP or IBSS operation "
1020                               "may be broken.\n");
1021         } else
1022                 b43legacydbg(dev->wl, "Updated beacon template\n");
1023 }
1024
1025 static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
1026                                             u16 shm_offset, u16 size,
1027                                             struct ieee80211_rate *rate)
1028 {
1029         struct b43legacy_plcp_hdr4 plcp;
1030         u32 tmp;
1031         __le16 dur;
1032
1033         plcp.data = 0;
1034         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1035         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1036                                                dev->wl->vif,
1037                                                size,
1038                                                rate);
1039         /* Write PLCP in two parts and timing for packet transfer */
1040         tmp = le32_to_cpu(plcp.data);
1041         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
1042                               tmp & 0xFFFF);
1043         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
1044                               tmp >> 16);
1045         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
1046                               le16_to_cpu(dur));
1047 }
1048
1049 /* Instead of using custom probe response template, this function
1050  * just patches custom beacon template by:
1051  * 1) Changing packet type
1052  * 2) Patching duration field
1053  * 3) Stripping TIM
1054  */
1055 static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
1056                                                u16 *dest_size,
1057                                                struct ieee80211_rate *rate)
1058 {
1059         const u8 *src_data;
1060         u8 *dest_data;
1061         u16 src_size, elem_size, src_pos, dest_pos;
1062         __le16 dur;
1063         struct ieee80211_hdr *hdr;
1064         size_t ie_start;
1065
1066         src_size = dev->wl->current_beacon->len;
1067         src_data = (const u8 *)dev->wl->current_beacon->data;
1068
1069         /* Get the start offset of the variable IEs in the packet. */
1070         ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1071         B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt,
1072                                                u.beacon.variable));
1073
1074         if (B43legacy_WARN_ON(src_size < ie_start))
1075                 return NULL;
1076
1077         dest_data = kmalloc(src_size, GFP_ATOMIC);
1078         if (unlikely(!dest_data))
1079                 return NULL;
1080
1081         /* Copy the static data and all Information Elements, except the TIM. */
1082         memcpy(dest_data, src_data, ie_start);
1083         src_pos = ie_start;
1084         dest_pos = ie_start;
1085         for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1086                 elem_size = src_data[src_pos + 1] + 2;
1087                 if (src_data[src_pos] == 5) {
1088                         /* This is the TIM. */
1089                         continue;
1090                 }
1091                 memcpy(dest_data + dest_pos, src_data + src_pos, elem_size);
1092                 dest_pos += elem_size;
1093         }
1094         *dest_size = dest_pos;
1095         hdr = (struct ieee80211_hdr *)dest_data;
1096
1097         /* Set the frame control. */
1098         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1099                                          IEEE80211_STYPE_PROBE_RESP);
1100         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1101                                                dev->wl->vif,
1102                                                *dest_size,
1103                                                rate);
1104         hdr->duration_id = dur;
1105
1106         return dest_data;
1107 }
1108
1109 static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1110                                                 u16 ram_offset,
1111                                                 u16 shm_size_offset,
1112                                                 struct ieee80211_rate *rate)
1113 {
1114         const u8 *probe_resp_data;
1115         u16 size;
1116
1117         size = dev->wl->current_beacon->len;
1118         probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1119         if (unlikely(!probe_resp_data))
1120                 return;
1121
1122         /* Looks like PLCP headers plus packet timings are stored for
1123          * all possible basic rates
1124          */
1125         b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
1126                                         &b43legacy_b_ratetable[0]);
1127         b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
1128                                         &b43legacy_b_ratetable[1]);
1129         b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
1130                                         &b43legacy_b_ratetable[2]);
1131         b43legacy_write_probe_resp_plcp(dev, 0x350, size,
1132                                         &b43legacy_b_ratetable[3]);
1133
1134         size = min((size_t)size,
1135                    0x200 - sizeof(struct b43legacy_plcp_hdr6));
1136         b43legacy_write_template_common(dev, probe_resp_data,
1137                                         size, ram_offset,
1138                                         shm_size_offset, rate->hw_value);
1139         kfree(probe_resp_data);
1140 }
1141
1142 static void b43legacy_upload_beacon0(struct b43legacy_wldev *dev)
1143 {
1144         struct b43legacy_wl *wl = dev->wl;
1145
1146         if (wl->beacon0_uploaded)
1147                 return;
1148         b43legacy_write_beacon_template(dev, 0x68, 0x18);
1149         /* FIXME: Probe resp upload doesn't really belong here,
1150          *        but we don't use that feature anyway. */
1151         b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
1152                                       &__b43legacy_ratetable[3]);
1153         wl->beacon0_uploaded = 1;
1154 }
1155
1156 static void b43legacy_upload_beacon1(struct b43legacy_wldev *dev)
1157 {
1158         struct b43legacy_wl *wl = dev->wl;
1159
1160         if (wl->beacon1_uploaded)
1161                 return;
1162         b43legacy_write_beacon_template(dev, 0x468, 0x1A);
1163         wl->beacon1_uploaded = 1;
1164 }
1165
1166 static void handle_irq_beacon(struct b43legacy_wldev *dev)
1167 {
1168         struct b43legacy_wl *wl = dev->wl;
1169         u32 cmd, beacon0_valid, beacon1_valid;
1170
1171         if (!b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1172                 return;
1173
1174         /* This is the bottom half of the asynchronous beacon update. */
1175
1176         /* Ignore interrupt in the future. */
1177         dev->irq_mask &= ~B43legacy_IRQ_BEACON;
1178
1179         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1180         beacon0_valid = (cmd & B43legacy_MACCMD_BEACON0_VALID);
1181         beacon1_valid = (cmd & B43legacy_MACCMD_BEACON1_VALID);
1182
1183         /* Schedule interrupt manually, if busy. */
1184         if (beacon0_valid && beacon1_valid) {
1185                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, B43legacy_IRQ_BEACON);
1186                 dev->irq_mask |= B43legacy_IRQ_BEACON;
1187                 return;
1188         }
1189
1190         if (unlikely(wl->beacon_templates_virgin)) {
1191                 /* We never uploaded a beacon before.
1192                  * Upload both templates now, but only mark one valid. */
1193                 wl->beacon_templates_virgin = 0;
1194                 b43legacy_upload_beacon0(dev);
1195                 b43legacy_upload_beacon1(dev);
1196                 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1197                 cmd |= B43legacy_MACCMD_BEACON0_VALID;
1198                 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1199         } else {
1200                 if (!beacon0_valid) {
1201                         b43legacy_upload_beacon0(dev);
1202                         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1203                         cmd |= B43legacy_MACCMD_BEACON0_VALID;
1204                         b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1205                 } else if (!beacon1_valid) {
1206                         b43legacy_upload_beacon1(dev);
1207                         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1208                         cmd |= B43legacy_MACCMD_BEACON1_VALID;
1209                         b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1210                 }
1211         }
1212 }
1213
1214 static void b43legacy_beacon_update_trigger_work(struct work_struct *work)
1215 {
1216         struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
1217                                          beacon_update_trigger);
1218         struct b43legacy_wldev *dev;
1219
1220         mutex_lock(&wl->mutex);
1221         dev = wl->current_dev;
1222         if (likely(dev && (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED))) {
1223                 spin_lock_irq(&wl->irq_lock);
1224                 /* Update beacon right away or defer to IRQ. */
1225                 handle_irq_beacon(dev);
1226                 /* The handler might have updated the IRQ mask. */
1227                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1228                                   dev->irq_mask);
1229                 mmiowb();
1230                 spin_unlock_irq(&wl->irq_lock);
1231         }
1232         mutex_unlock(&wl->mutex);
1233 }
1234
1235 /* Asynchronously update the packet templates in template RAM.
1236  * Locking: Requires wl->irq_lock to be locked. */
1237 static void b43legacy_update_templates(struct b43legacy_wl *wl)
1238 {
1239         struct sk_buff *beacon;
1240         /* This is the top half of the ansynchronous beacon update. The bottom
1241          * half is the beacon IRQ. Beacon update must be asynchronous to avoid
1242          * sending an invalid beacon. This can happen for example, if the
1243          * firmware transmits a beacon while we are updating it. */
1244
1245         /* We could modify the existing beacon and set the aid bit in the TIM
1246          * field, but that would probably require resizing and moving of data
1247          * within the beacon template. Simply request a new beacon and let
1248          * mac80211 do the hard work. */
1249         beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1250         if (unlikely(!beacon))
1251                 return;
1252
1253         if (wl->current_beacon)
1254                 dev_kfree_skb_any(wl->current_beacon);
1255         wl->current_beacon = beacon;
1256         wl->beacon0_uploaded = 0;
1257         wl->beacon1_uploaded = 0;
1258         ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1259 }
1260
1261 static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1262                                      u16 beacon_int)
1263 {
1264         b43legacy_time_lock(dev);
1265         if (dev->dev->id.revision >= 3) {
1266                 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_REP,
1267                                  (beacon_int << 16));
1268                 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_START,
1269                                  (beacon_int << 10));
1270         } else {
1271                 b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1272                 b43legacy_write16(dev, 0x610, beacon_int);
1273         }
1274         b43legacy_time_unlock(dev);
1275         b43legacydbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1276 }
1277
1278 static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1279 {
1280 }
1281
1282 /* Interrupt handler bottom-half */
1283 static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1284 {
1285         u32 reason;
1286         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1287         u32 merged_dma_reason = 0;
1288         int i;
1289         unsigned long flags;
1290
1291         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1292
1293         B43legacy_WARN_ON(b43legacy_status(dev) <
1294                           B43legacy_STAT_INITIALIZED);
1295
1296         reason = dev->irq_reason;
1297         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1298                 dma_reason[i] = dev->dma_reason[i];
1299                 merged_dma_reason |= dma_reason[i];
1300         }
1301
1302         if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1303                 b43legacyerr(dev->wl, "MAC transmission error\n");
1304
1305         if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
1306                 b43legacyerr(dev->wl, "PHY transmission error\n");
1307                 rmb();
1308                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1309                         b43legacyerr(dev->wl, "Too many PHY TX errors, "
1310                                               "restarting the controller\n");
1311                         b43legacy_controller_restart(dev, "PHY TX errors");
1312                 }
1313         }
1314
1315         if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1316                                           B43legacy_DMAIRQ_NONFATALMASK))) {
1317                 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1318                         b43legacyerr(dev->wl, "Fatal DMA error: "
1319                                "0x%08X, 0x%08X, 0x%08X, "
1320                                "0x%08X, 0x%08X, 0x%08X\n",
1321                                dma_reason[0], dma_reason[1],
1322                                dma_reason[2], dma_reason[3],
1323                                dma_reason[4], dma_reason[5]);
1324                         b43legacy_controller_restart(dev, "DMA error");
1325                         mmiowb();
1326                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1327                         return;
1328                 }
1329                 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1330                         b43legacyerr(dev->wl, "DMA error: "
1331                                "0x%08X, 0x%08X, 0x%08X, "
1332                                "0x%08X, 0x%08X, 0x%08X\n",
1333                                dma_reason[0], dma_reason[1],
1334                                dma_reason[2], dma_reason[3],
1335                                dma_reason[4], dma_reason[5]);
1336         }
1337
1338         if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1339                 handle_irq_ucode_debug(dev);
1340         if (reason & B43legacy_IRQ_TBTT_INDI)
1341                 handle_irq_tbtt_indication(dev);
1342         if (reason & B43legacy_IRQ_ATIM_END)
1343                 handle_irq_atim_end(dev);
1344         if (reason & B43legacy_IRQ_BEACON)
1345                 handle_irq_beacon(dev);
1346         if (reason & B43legacy_IRQ_PMQ)
1347                 handle_irq_pmq(dev);
1348         if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1349                 ;/*TODO*/
1350         if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1351                 handle_irq_noise(dev);
1352
1353         /* Check the DMA reason registers for received data. */
1354         if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1355                 if (b43legacy_using_pio(dev))
1356                         b43legacy_pio_rx(dev->pio.queue0);
1357                 else
1358                         b43legacy_dma_rx(dev->dma.rx_ring0);
1359         }
1360         B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1361         B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1362         if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1363                 if (b43legacy_using_pio(dev))
1364                         b43legacy_pio_rx(dev->pio.queue3);
1365                 else
1366                         b43legacy_dma_rx(dev->dma.rx_ring3);
1367         }
1368         B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1369         B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1370
1371         if (reason & B43legacy_IRQ_TX_OK)
1372                 handle_irq_transmit_status(dev);
1373
1374         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1375         mmiowb();
1376         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1377 }
1378
1379 static void pio_irq_workaround(struct b43legacy_wldev *dev,
1380                                u16 base, int queueidx)
1381 {
1382         u16 rxctl;
1383
1384         rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1385         if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1386                 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1387         else
1388                 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1389 }
1390
1391 static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1392 {
1393         if (b43legacy_using_pio(dev) &&
1394             (dev->dev->id.revision < 3) &&
1395             (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1396                 /* Apply a PIO specific workaround to the dma_reasons */
1397                 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1398                 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1399                 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1400                 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1401         }
1402
1403         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1404
1405         b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1406                           dev->dma_reason[0]);
1407         b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1408                           dev->dma_reason[1]);
1409         b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1410                           dev->dma_reason[2]);
1411         b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1412                           dev->dma_reason[3]);
1413         b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1414                           dev->dma_reason[4]);
1415         b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1416                           dev->dma_reason[5]);
1417 }
1418
1419 /* Interrupt handler top-half */
1420 static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1421 {
1422         irqreturn_t ret = IRQ_NONE;
1423         struct b43legacy_wldev *dev = dev_id;
1424         u32 reason;
1425
1426         B43legacy_WARN_ON(!dev);
1427
1428         spin_lock(&dev->wl->irq_lock);
1429
1430         if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
1431                 /* This can only happen on shared IRQ lines. */
1432                 goto out;
1433         reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1434         if (reason == 0xffffffff) /* shared IRQ */
1435                 goto out;
1436         ret = IRQ_HANDLED;
1437         reason &= dev->irq_mask;
1438         if (!reason)
1439                 goto out;
1440
1441         dev->dma_reason[0] = b43legacy_read32(dev,
1442                                               B43legacy_MMIO_DMA0_REASON)
1443                                               & 0x0001DC00;
1444         dev->dma_reason[1] = b43legacy_read32(dev,
1445                                               B43legacy_MMIO_DMA1_REASON)
1446                                               & 0x0000DC00;
1447         dev->dma_reason[2] = b43legacy_read32(dev,
1448                                               B43legacy_MMIO_DMA2_REASON)
1449                                               & 0x0000DC00;
1450         dev->dma_reason[3] = b43legacy_read32(dev,
1451                                               B43legacy_MMIO_DMA3_REASON)
1452                                               & 0x0001DC00;
1453         dev->dma_reason[4] = b43legacy_read32(dev,
1454                                               B43legacy_MMIO_DMA4_REASON)
1455                                               & 0x0000DC00;
1456         dev->dma_reason[5] = b43legacy_read32(dev,
1457                                               B43legacy_MMIO_DMA5_REASON)
1458                                               & 0x0000DC00;
1459
1460         b43legacy_interrupt_ack(dev, reason);
1461         /* Disable all IRQs. They are enabled again in the bottom half. */
1462         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1463         /* Save the reason code and call our bottom half. */
1464         dev->irq_reason = reason;
1465         tasklet_schedule(&dev->isr_tasklet);
1466 out:
1467         mmiowb();
1468         spin_unlock(&dev->wl->irq_lock);
1469
1470         return ret;
1471 }
1472
1473 static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1474 {
1475         release_firmware(dev->fw.ucode);
1476         dev->fw.ucode = NULL;
1477         release_firmware(dev->fw.pcm);
1478         dev->fw.pcm = NULL;
1479         release_firmware(dev->fw.initvals);
1480         dev->fw.initvals = NULL;
1481         release_firmware(dev->fw.initvals_band);
1482         dev->fw.initvals_band = NULL;
1483 }
1484
1485 static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1486 {
1487         b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
1488                      "Drivers/b43#devicefirmware "
1489                      "and download the correct firmware (version 3).\n");
1490 }
1491
1492 static int do_request_fw(struct b43legacy_wldev *dev,
1493                          const char *name,
1494                          const struct firmware **fw)
1495 {
1496         char path[sizeof(modparam_fwpostfix) + 32];
1497         struct b43legacy_fw_header *hdr;
1498         u32 size;
1499         int err;
1500
1501         if (!name)
1502                 return 0;
1503
1504         snprintf(path, ARRAY_SIZE(path),
1505                  "b43legacy%s/%s.fw",
1506                  modparam_fwpostfix, name);
1507         err = request_firmware(fw, path, dev->dev->dev);
1508         if (err) {
1509                 b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1510                        "or load failed.\n", path);
1511                 return err;
1512         }
1513         if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1514                 goto err_format;
1515         hdr = (struct b43legacy_fw_header *)((*fw)->data);
1516         switch (hdr->type) {
1517         case B43legacy_FW_TYPE_UCODE:
1518         case B43legacy_FW_TYPE_PCM:
1519                 size = be32_to_cpu(hdr->size);
1520                 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1521                         goto err_format;
1522                 /* fallthrough */
1523         case B43legacy_FW_TYPE_IV:
1524                 if (hdr->ver != 1)
1525                         goto err_format;
1526                 break;
1527         default:
1528                 goto err_format;
1529         }
1530
1531         return err;
1532
1533 err_format:
1534         b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1535         return -EPROTO;
1536 }
1537
1538 static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
1539 {
1540         struct b43legacy_firmware *fw = &dev->fw;
1541         const u8 rev = dev->dev->id.revision;
1542         const char *filename;
1543         u32 tmshigh;
1544         int err;
1545
1546         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1547         if (!fw->ucode) {
1548                 if (rev == 2)
1549                         filename = "ucode2";
1550                 else if (rev == 4)
1551                         filename = "ucode4";
1552                 else
1553                         filename = "ucode5";
1554                 err = do_request_fw(dev, filename, &fw->ucode);
1555                 if (err)
1556                         goto err_load;
1557         }
1558         if (!fw->pcm) {
1559                 if (rev < 5)
1560                         filename = "pcm4";
1561                 else
1562                         filename = "pcm5";
1563                 err = do_request_fw(dev, filename, &fw->pcm);
1564                 if (err)
1565                         goto err_load;
1566         }
1567         if (!fw->initvals) {
1568                 switch (dev->phy.type) {
1569                 case B43legacy_PHYTYPE_B:
1570                 case B43legacy_PHYTYPE_G:
1571                         if ((rev >= 5) && (rev <= 10))
1572                                 filename = "b0g0initvals5";
1573                         else if (rev == 2 || rev == 4)
1574                                 filename = "b0g0initvals2";
1575                         else
1576                                 goto err_no_initvals;
1577                         break;
1578                 default:
1579                         goto err_no_initvals;
1580                 }
1581                 err = do_request_fw(dev, filename, &fw->initvals);
1582                 if (err)
1583                         goto err_load;
1584         }
1585         if (!fw->initvals_band) {
1586                 switch (dev->phy.type) {
1587                 case B43legacy_PHYTYPE_B:
1588                 case B43legacy_PHYTYPE_G:
1589                         if ((rev >= 5) && (rev <= 10))
1590                                 filename = "b0g0bsinitvals5";
1591                         else if (rev >= 11)
1592                                 filename = NULL;
1593                         else if (rev == 2 || rev == 4)
1594                                 filename = NULL;
1595                         else
1596                                 goto err_no_initvals;
1597                         break;
1598                 default:
1599                         goto err_no_initvals;
1600                 }
1601                 err = do_request_fw(dev, filename, &fw->initvals_band);
1602                 if (err)
1603                         goto err_load;
1604         }
1605
1606         return 0;
1607
1608 err_load:
1609         b43legacy_print_fw_helptext(dev->wl);
1610         goto error;
1611
1612 err_no_initvals:
1613         err = -ENODEV;
1614         b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1615                "core rev %u\n", dev->phy.type, rev);
1616         goto error;
1617
1618 error:
1619         b43legacy_release_firmware(dev);
1620         return err;
1621 }
1622
1623 static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1624 {
1625         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1626         const __be32 *data;
1627         unsigned int i;
1628         unsigned int len;
1629         u16 fwrev;
1630         u16 fwpatch;
1631         u16 fwdate;
1632         u16 fwtime;
1633         u32 tmp, macctl;
1634         int err = 0;
1635
1636         /* Jump the microcode PSM to offset 0 */
1637         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1638         B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
1639         macctl |= B43legacy_MACCTL_PSM_JMP0;
1640         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1641         /* Zero out all microcode PSM registers and shared memory. */
1642         for (i = 0; i < 64; i++)
1643                 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
1644         for (i = 0; i < 4096; i += 2)
1645                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
1646
1647         /* Upload Microcode. */
1648         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1649         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1650         b43legacy_shm_control_word(dev,
1651                                    B43legacy_SHM_UCODE |
1652                                    B43legacy_SHM_AUTOINC_W,
1653                                    0x0000);
1654         for (i = 0; i < len; i++) {
1655                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1656                                     be32_to_cpu(data[i]));
1657                 udelay(10);
1658         }
1659
1660         if (dev->fw.pcm) {
1661                 /* Upload PCM data. */
1662                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1663                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1664                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1665                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1666                 /* No need for autoinc bit in SHM_HW */
1667                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1668                 for (i = 0; i < len; i++) {
1669                         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1670                                           be32_to_cpu(data[i]));
1671                         udelay(10);
1672                 }
1673         }
1674
1675         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1676                           B43legacy_IRQ_ALL);
1677
1678         /* Start the microcode PSM */
1679         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1680         macctl &= ~B43legacy_MACCTL_PSM_JMP0;
1681         macctl |= B43legacy_MACCTL_PSM_RUN;
1682         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1683
1684         /* Wait for the microcode to load and respond */
1685         i = 0;
1686         while (1) {
1687                 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1688                 if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1689                         break;
1690                 i++;
1691                 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1692                         b43legacyerr(dev->wl, "Microcode not responding\n");
1693                         b43legacy_print_fw_helptext(dev->wl);
1694                         err = -ENODEV;
1695                         goto error;
1696                 }
1697                 msleep_interruptible(50);
1698                 if (signal_pending(current)) {
1699                         err = -EINTR;
1700                         goto error;
1701                 }
1702         }
1703         /* dummy read follows */
1704         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1705
1706         /* Get and check the revisions. */
1707         fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1708                                      B43legacy_SHM_SH_UCODEREV);
1709         fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1710                                        B43legacy_SHM_SH_UCODEPATCH);
1711         fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1712                                       B43legacy_SHM_SH_UCODEDATE);
1713         fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1714                                       B43legacy_SHM_SH_UCODETIME);
1715
1716         if (fwrev > 0x128) {
1717                 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1718                              " Only firmware from binary drivers version 3.x"
1719                              " is supported. You must change your firmware"
1720                              " files.\n");
1721                 b43legacy_print_fw_helptext(dev->wl);
1722                 err = -EOPNOTSUPP;
1723                 goto error;
1724         }
1725         b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
1726                       "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1727                       (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1728                       (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
1729                       fwtime & 0x1F);
1730
1731         dev->fw.rev = fwrev;
1732         dev->fw.patch = fwpatch;
1733
1734         return 0;
1735
1736 error:
1737         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1738         macctl &= ~B43legacy_MACCTL_PSM_RUN;
1739         macctl |= B43legacy_MACCTL_PSM_JMP0;
1740         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1741
1742         return err;
1743 }
1744
1745 static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1746                                     const struct b43legacy_iv *ivals,
1747                                     size_t count,
1748                                     size_t array_size)
1749 {
1750         const struct b43legacy_iv *iv;
1751         u16 offset;
1752         size_t i;
1753         bool bit32;
1754
1755         BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1756         iv = ivals;
1757         for (i = 0; i < count; i++) {
1758                 if (array_size < sizeof(iv->offset_size))
1759                         goto err_format;
1760                 array_size -= sizeof(iv->offset_size);
1761                 offset = be16_to_cpu(iv->offset_size);
1762                 bit32 = !!(offset & B43legacy_IV_32BIT);
1763                 offset &= B43legacy_IV_OFFSET_MASK;
1764                 if (offset >= 0x1000)
1765                         goto err_format;
1766                 if (bit32) {
1767                         u32 value;
1768
1769                         if (array_size < sizeof(iv->data.d32))
1770                                 goto err_format;
1771                         array_size -= sizeof(iv->data.d32);
1772
1773                         value = get_unaligned_be32(&iv->data.d32);
1774                         b43legacy_write32(dev, offset, value);
1775
1776                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1777                                                         sizeof(__be16) +
1778                                                         sizeof(__be32));
1779                 } else {
1780                         u16 value;
1781
1782                         if (array_size < sizeof(iv->data.d16))
1783                                 goto err_format;
1784                         array_size -= sizeof(iv->data.d16);
1785
1786                         value = be16_to_cpu(iv->data.d16);
1787                         b43legacy_write16(dev, offset, value);
1788
1789                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1790                                                         sizeof(__be16) +
1791                                                         sizeof(__be16));
1792                 }
1793         }
1794         if (array_size)
1795                 goto err_format;
1796
1797         return 0;
1798
1799 err_format:
1800         b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1801         b43legacy_print_fw_helptext(dev->wl);
1802
1803         return -EPROTO;
1804 }
1805
1806 static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1807 {
1808         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1809         const struct b43legacy_fw_header *hdr;
1810         struct b43legacy_firmware *fw = &dev->fw;
1811         const struct b43legacy_iv *ivals;
1812         size_t count;
1813         int err;
1814
1815         hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1816         ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1817         count = be32_to_cpu(hdr->size);
1818         err = b43legacy_write_initvals(dev, ivals, count,
1819                                  fw->initvals->size - hdr_len);
1820         if (err)
1821                 goto out;
1822         if (fw->initvals_band) {
1823                 hdr = (const struct b43legacy_fw_header *)
1824                       (fw->initvals_band->data);
1825                 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1826                         + hdr_len);
1827                 count = be32_to_cpu(hdr->size);
1828                 err = b43legacy_write_initvals(dev, ivals, count,
1829                                          fw->initvals_band->size - hdr_len);
1830                 if (err)
1831                         goto out;
1832         }
1833 out:
1834
1835         return err;
1836 }
1837
1838 /* Initialize the GPIOs
1839  * http://bcm-specs.sipsolutions.net/GPIO
1840  */
1841 static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1842 {
1843         struct ssb_bus *bus = dev->dev->bus;
1844         struct ssb_device *gpiodev, *pcidev = NULL;
1845         u32 mask;
1846         u32 set;
1847
1848         b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1849                           b43legacy_read32(dev,
1850                           B43legacy_MMIO_MACCTL)
1851                           & 0xFFFF3FFF);
1852
1853         b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1854                           b43legacy_read16(dev,
1855                           B43legacy_MMIO_GPIO_MASK)
1856                           | 0x000F);
1857
1858         mask = 0x0000001F;
1859         set = 0x0000000F;
1860         if (dev->dev->bus->chip_id == 0x4301) {
1861                 mask |= 0x0060;
1862                 set |= 0x0060;
1863         }
1864         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
1865                 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1866                                   b43legacy_read16(dev,
1867                                   B43legacy_MMIO_GPIO_MASK)
1868                                   | 0x0200);
1869                 mask |= 0x0200;
1870                 set |= 0x0200;
1871         }
1872         if (dev->dev->id.revision >= 2)
1873                 mask  |= 0x0010; /* FIXME: This is redundant. */
1874
1875 #ifdef CONFIG_SSB_DRIVER_PCICORE
1876         pcidev = bus->pcicore.dev;
1877 #endif
1878         gpiodev = bus->chipco.dev ? : pcidev;
1879         if (!gpiodev)
1880                 return 0;
1881         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1882                     (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1883                      & mask) | set);
1884
1885         return 0;
1886 }
1887
1888 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1889 static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1890 {
1891         struct ssb_bus *bus = dev->dev->bus;
1892         struct ssb_device *gpiodev, *pcidev = NULL;
1893
1894 #ifdef CONFIG_SSB_DRIVER_PCICORE
1895         pcidev = bus->pcicore.dev;
1896 #endif
1897         gpiodev = bus->chipco.dev ? : pcidev;
1898         if (!gpiodev)
1899                 return;
1900         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1901 }
1902
1903 /* http://bcm-specs.sipsolutions.net/EnableMac */
1904 void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1905 {
1906         dev->mac_suspended--;
1907         B43legacy_WARN_ON(dev->mac_suspended < 0);
1908         B43legacy_WARN_ON(irqs_disabled());
1909         if (dev->mac_suspended == 0) {
1910                 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1911                                   b43legacy_read32(dev,
1912                                   B43legacy_MMIO_MACCTL)
1913                                   | B43legacy_MACCTL_ENABLED);
1914                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1915                                   B43legacy_IRQ_MAC_SUSPENDED);
1916                 /* the next two are dummy reads */
1917                 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1918                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1919                 b43legacy_power_saving_ctl_bits(dev, -1, -1);
1920
1921                 /* Re-enable IRQs. */
1922                 spin_lock_irq(&dev->wl->irq_lock);
1923                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1924                                   dev->irq_mask);
1925                 spin_unlock_irq(&dev->wl->irq_lock);
1926         }
1927 }
1928
1929 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1930 void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1931 {
1932         int i;
1933         u32 tmp;
1934
1935         might_sleep();
1936         B43legacy_WARN_ON(irqs_disabled());
1937         B43legacy_WARN_ON(dev->mac_suspended < 0);
1938
1939         if (dev->mac_suspended == 0) {
1940                 /* Mask IRQs before suspending MAC. Otherwise
1941                  * the MAC stays busy and won't suspend. */
1942                 spin_lock_irq(&dev->wl->irq_lock);
1943                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1944                 spin_unlock_irq(&dev->wl->irq_lock);
1945                 b43legacy_synchronize_irq(dev);
1946
1947                 b43legacy_power_saving_ctl_bits(dev, -1, 1);
1948                 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1949                                   b43legacy_read32(dev,
1950                                   B43legacy_MMIO_MACCTL)
1951                                   & ~B43legacy_MACCTL_ENABLED);
1952                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1953                 for (i = 40; i; i--) {
1954                         tmp = b43legacy_read32(dev,
1955                                                B43legacy_MMIO_GEN_IRQ_REASON);
1956                         if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1957                                 goto out;
1958                         msleep(1);
1959                 }
1960                 b43legacyerr(dev->wl, "MAC suspend failed\n");
1961         }
1962 out:
1963         dev->mac_suspended++;
1964 }
1965
1966 static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
1967 {
1968         struct b43legacy_wl *wl = dev->wl;
1969         u32 ctl;
1970         u16 cfp_pretbtt;
1971
1972         ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1973         /* Reset status to STA infrastructure mode. */
1974         ctl &= ~B43legacy_MACCTL_AP;
1975         ctl &= ~B43legacy_MACCTL_KEEP_CTL;
1976         ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
1977         ctl &= ~B43legacy_MACCTL_KEEP_BAD;
1978         ctl &= ~B43legacy_MACCTL_PROMISC;
1979         ctl &= ~B43legacy_MACCTL_BEACPROMISC;
1980         ctl |= B43legacy_MACCTL_INFRA;
1981
1982         if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1983                 ctl |= B43legacy_MACCTL_AP;
1984         else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC))
1985                 ctl &= ~B43legacy_MACCTL_INFRA;
1986
1987         if (wl->filter_flags & FIF_CONTROL)
1988                 ctl |= B43legacy_MACCTL_KEEP_CTL;
1989         if (wl->filter_flags & FIF_FCSFAIL)
1990                 ctl |= B43legacy_MACCTL_KEEP_BAD;
1991         if (wl->filter_flags & FIF_PLCPFAIL)
1992                 ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
1993         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
1994                 ctl |= B43legacy_MACCTL_PROMISC;
1995         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
1996                 ctl |= B43legacy_MACCTL_BEACPROMISC;
1997
1998         /* Workaround: On old hardware the HW-MAC-address-filter
1999          * doesn't work properly, so always run promisc in filter
2000          * it in software. */
2001         if (dev->dev->id.revision <= 4)
2002                 ctl |= B43legacy_MACCTL_PROMISC;
2003
2004         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
2005
2006         cfp_pretbtt = 2;
2007         if ((ctl & B43legacy_MACCTL_INFRA) &&
2008             !(ctl & B43legacy_MACCTL_AP)) {
2009                 if (dev->dev->bus->chip_id == 0x4306 &&
2010                     dev->dev->bus->chip_rev == 3)
2011                         cfp_pretbtt = 100;
2012                 else
2013                         cfp_pretbtt = 50;
2014         }
2015         b43legacy_write16(dev, 0x612, cfp_pretbtt);
2016 }
2017
2018 static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
2019                                         u16 rate,
2020                                         int is_ofdm)
2021 {
2022         u16 offset;
2023
2024         if (is_ofdm) {
2025                 offset = 0x480;
2026                 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2027         } else {
2028                 offset = 0x4C0;
2029                 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2030         }
2031         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
2032                               b43legacy_shm_read16(dev,
2033                               B43legacy_SHM_SHARED, offset));
2034 }
2035
2036 static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
2037 {
2038         switch (dev->phy.type) {
2039         case B43legacy_PHYTYPE_G:
2040                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
2041                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
2042                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
2043                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
2044                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
2045                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
2046                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
2047                 /* fallthrough */
2048         case B43legacy_PHYTYPE_B:
2049                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
2050                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
2051                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
2052                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
2053                 break;
2054         default:
2055                 B43legacy_BUG_ON(1);
2056         }
2057 }
2058
2059 /* Set the TX-Antenna for management frames sent by firmware. */
2060 static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
2061                                           int antenna)
2062 {
2063         u16 ant = 0;
2064         u16 tmp;
2065
2066         switch (antenna) {
2067         case B43legacy_ANTENNA0:
2068                 ant |= B43legacy_TX4_PHY_ANT0;
2069                 break;
2070         case B43legacy_ANTENNA1:
2071                 ant |= B43legacy_TX4_PHY_ANT1;
2072                 break;
2073         case B43legacy_ANTENNA_AUTO:
2074                 ant |= B43legacy_TX4_PHY_ANTLAST;
2075                 break;
2076         default:
2077                 B43legacy_BUG_ON(1);
2078         }
2079
2080         /* FIXME We also need to set the other flags of the PHY control
2081          * field somewhere. */
2082
2083         /* For Beacons */
2084         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2085                                    B43legacy_SHM_SH_BEACPHYCTL);
2086         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2087         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2088                               B43legacy_SHM_SH_BEACPHYCTL, tmp);
2089         /* For ACK/CTS */
2090         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2091                                    B43legacy_SHM_SH_ACKCTSPHYCTL);
2092         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2093         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2094                               B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
2095         /* For Probe Resposes */
2096         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2097                                    B43legacy_SHM_SH_PRPHYCTL);
2098         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2099         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2100                               B43legacy_SHM_SH_PRPHYCTL, tmp);
2101 }
2102
2103 /* This is the opposite of b43legacy_chip_init() */
2104 static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
2105 {
2106         b43legacy_radio_turn_off(dev, 1);
2107         b43legacy_gpio_cleanup(dev);
2108         /* firmware is released later */
2109 }
2110
2111 /* Initialize the chip
2112  * http://bcm-specs.sipsolutions.net/ChipInit
2113  */
2114 static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2115 {
2116         struct b43legacy_phy *phy = &dev->phy;
2117         int err;
2118         int tmp;
2119         u32 value32, macctl;
2120         u16 value16;
2121
2122         /* Initialize the MAC control */
2123         macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
2124         if (dev->phy.gmode)
2125                 macctl |= B43legacy_MACCTL_GMODE;
2126         macctl |= B43legacy_MACCTL_INFRA;
2127         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
2128
2129         err = b43legacy_request_firmware(dev);
2130         if (err)
2131                 goto out;
2132         err = b43legacy_upload_microcode(dev);
2133         if (err)
2134                 goto out; /* firmware is released later */
2135
2136         err = b43legacy_gpio_init(dev);
2137         if (err)
2138                 goto out; /* firmware is released later */
2139
2140         err = b43legacy_upload_initvals(dev);
2141         if (err)
2142                 goto err_gpio_clean;
2143         b43legacy_radio_turn_on(dev);
2144
2145         b43legacy_write16(dev, 0x03E6, 0x0000);
2146         err = b43legacy_phy_init(dev);
2147         if (err)
2148                 goto err_radio_off;
2149
2150         /* Select initial Interference Mitigation. */
2151         tmp = phy->interfmode;
2152         phy->interfmode = B43legacy_INTERFMODE_NONE;
2153         b43legacy_radio_set_interference_mitigation(dev, tmp);
2154
2155         b43legacy_phy_set_antenna_diversity(dev);
2156         b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2157
2158         if (phy->type == B43legacy_PHYTYPE_B) {
2159                 value16 = b43legacy_read16(dev, 0x005E);
2160                 value16 |= 0x0004;
2161                 b43legacy_write16(dev, 0x005E, value16);
2162         }
2163         b43legacy_write32(dev, 0x0100, 0x01000000);
2164         if (dev->dev->id.revision < 5)
2165                 b43legacy_write32(dev, 0x010C, 0x01000000);
2166
2167         value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2168         value32 &= ~B43legacy_MACCTL_INFRA;
2169         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2170         value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2171         value32 |= B43legacy_MACCTL_INFRA;
2172         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2173
2174         if (b43legacy_using_pio(dev)) {
2175                 b43legacy_write32(dev, 0x0210, 0x00000100);
2176                 b43legacy_write32(dev, 0x0230, 0x00000100);
2177                 b43legacy_write32(dev, 0x0250, 0x00000100);
2178                 b43legacy_write32(dev, 0x0270, 0x00000100);
2179                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2180                                       0x0000);
2181         }
2182
2183         /* Probe Response Timeout value */
2184         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2185         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2186
2187         /* Initially set the wireless operation mode. */
2188         b43legacy_adjust_opmode(dev);
2189
2190         if (dev->dev->id.revision < 3) {
2191                 b43legacy_write16(dev, 0x060E, 0x0000);
2192                 b43legacy_write16(dev, 0x0610, 0x8000);
2193                 b43legacy_write16(dev, 0x0604, 0x0000);
2194                 b43legacy_write16(dev, 0x0606, 0x0200);
2195         } else {
2196                 b43legacy_write32(dev, 0x0188, 0x80000000);
2197                 b43legacy_write32(dev, 0x018C, 0x02000000);
2198         }
2199         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2200         b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2201         b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2202         b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2203         b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2204         b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2205         b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2206
2207         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2208         value32 |= 0x00100000;
2209         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2210
2211         b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2212                           dev->dev->bus->chipco.fast_pwrup_delay);
2213
2214         /* PHY TX errors counter. */
2215         atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2216
2217         B43legacy_WARN_ON(err != 0);
2218         b43legacydbg(dev->wl, "Chip initialized\n");
2219 out:
2220         return err;
2221
2222 err_radio_off:
2223         b43legacy_radio_turn_off(dev, 1);
2224 err_gpio_clean:
2225         b43legacy_gpio_cleanup(dev);
2226         goto out;
2227 }
2228
2229 static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2230 {
2231         struct b43legacy_phy *phy = &dev->phy;
2232
2233         if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2234                 return;
2235
2236         b43legacy_mac_suspend(dev);
2237         b43legacy_phy_lo_g_measure(dev);
2238         b43legacy_mac_enable(dev);
2239 }
2240
2241 static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2242 {
2243         b43legacy_phy_lo_mark_all_unused(dev);
2244         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
2245                 b43legacy_mac_suspend(dev);
2246                 b43legacy_calc_nrssi_slope(dev);
2247                 b43legacy_mac_enable(dev);
2248         }
2249 }
2250
2251 static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2252 {
2253         /* Update device statistics. */
2254         b43legacy_calculate_link_quality(dev);
2255 }
2256
2257 static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2258 {
2259         b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
2260
2261         atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2262         wmb();
2263 }
2264
2265 static void do_periodic_work(struct b43legacy_wldev *dev)
2266 {
2267         unsigned int state;
2268
2269         state = dev->periodic_state;
2270         if (state % 8 == 0)
2271                 b43legacy_periodic_every120sec(dev);
2272         if (state % 4 == 0)
2273                 b43legacy_periodic_every60sec(dev);
2274         if (state % 2 == 0)
2275                 b43legacy_periodic_every30sec(dev);
2276         b43legacy_periodic_every15sec(dev);
2277 }
2278
2279 /* Periodic work locking policy:
2280  *      The whole periodic work handler is protected by
2281  *      wl->mutex. If another lock is needed somewhere in the
2282  *      pwork callchain, it's acquired in-place, where it's needed.
2283  */
2284 static void b43legacy_periodic_work_handler(struct work_struct *work)
2285 {
2286         struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2287                                              periodic_work.work);
2288         struct b43legacy_wl *wl = dev->wl;
2289         unsigned long delay;
2290
2291         mutex_lock(&wl->mutex);
2292
2293         if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2294                 goto out;
2295         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2296                 goto out_requeue;
2297
2298         do_periodic_work(dev);
2299
2300         dev->periodic_state++;
2301 out_requeue:
2302         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2303                 delay = msecs_to_jiffies(50);
2304         else
2305                 delay = round_jiffies_relative(HZ * 15);
2306         ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
2307 out:
2308         mutex_unlock(&wl->mutex);
2309 }
2310
2311 static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2312 {
2313         struct delayed_work *work = &dev->periodic_work;
2314
2315         dev->periodic_state = 0;
2316         INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
2317         ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
2318 }
2319
2320 /* Validate access to the chip (SHM) */
2321 static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2322 {
2323         u32 value;
2324         u32 shm_backup;
2325
2326         shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2327         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2328         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2329                                  0xAA5555AA)
2330                 goto error;
2331         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2332         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2333                                  0x55AAAA55)
2334                 goto error;
2335         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2336
2337         value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2338         if ((value | B43legacy_MACCTL_GMODE) !=
2339             (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2340                 goto error;
2341
2342         value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2343         if (value)
2344                 goto error;
2345
2346         return 0;
2347 error:
2348         b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2349         return -ENODEV;
2350 }
2351
2352 static void b43legacy_security_init(struct b43legacy_wldev *dev)
2353 {
2354         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2355         B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2356         dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2357                                         0x0056);
2358         /* KTP is a word address, but we address SHM bytewise.
2359          * So multiply by two.
2360          */
2361         dev->ktp *= 2;
2362         if (dev->dev->id.revision >= 5)
2363                 /* Number of RCMTA address slots */
2364                 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2365                                   dev->max_nr_keys - 8);
2366 }
2367
2368 #ifdef CONFIG_B43LEGACY_HWRNG
2369 static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2370 {
2371         struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2372         unsigned long flags;
2373
2374         /* Don't take wl->mutex here, as it could deadlock with
2375          * hwrng internal locking. It's not needed to take
2376          * wl->mutex here, anyway. */
2377
2378         spin_lock_irqsave(&wl->irq_lock, flags);
2379         *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2380         spin_unlock_irqrestore(&wl->irq_lock, flags);
2381
2382         return (sizeof(u16));
2383 }
2384 #endif
2385
2386 static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2387 {
2388 #ifdef CONFIG_B43LEGACY_HWRNG
2389         if (wl->rng_initialized)
2390                 hwrng_unregister(&wl->rng);
2391 #endif
2392 }
2393
2394 static int b43legacy_rng_init(struct b43legacy_wl *wl)
2395 {
2396         int err = 0;
2397
2398 #ifdef CONFIG_B43LEGACY_HWRNG
2399         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2400                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2401         wl->rng.name = wl->rng_name;
2402         wl->rng.data_read = b43legacy_rng_read;
2403         wl->rng.priv = (unsigned long)wl;
2404         wl->rng_initialized = 1;
2405         err = hwrng_register(&wl->rng);
2406         if (err) {
2407                 wl->rng_initialized = 0;
2408                 b43legacyerr(wl, "Failed to register the random "
2409                        "number generator (%d)\n", err);
2410         }
2411
2412 #endif
2413         return err;
2414 }
2415
2416 static int b43legacy_op_tx(struct ieee80211_hw *hw,
2417                            struct sk_buff *skb)
2418 {
2419         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2420         struct b43legacy_wldev *dev = wl->current_dev;
2421         int err = -ENODEV;
2422         unsigned long flags;
2423
2424         if (unlikely(!dev))
2425                 goto out;
2426         if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
2427                 goto out;
2428         /* DMA-TX is done without a global lock. */
2429         if (b43legacy_using_pio(dev)) {
2430                 spin_lock_irqsave(&wl->irq_lock, flags);
2431                 err = b43legacy_pio_tx(dev, skb);
2432                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2433         } else
2434                 err = b43legacy_dma_tx(dev, skb);
2435 out:
2436         if (unlikely(err)) {
2437                 /* Drop the packet. */
2438                 dev_kfree_skb_any(skb);
2439         }
2440         return NETDEV_TX_OK;
2441 }
2442
2443 static int b43legacy_op_conf_tx(struct ieee80211_hw *hw, u16 queue,
2444                                 const struct ieee80211_tx_queue_params *params)
2445 {
2446         return 0;
2447 }
2448
2449 static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2450                                   struct ieee80211_low_level_stats *stats)
2451 {
2452         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2453         unsigned long flags;
2454
2455         spin_lock_irqsave(&wl->irq_lock, flags);
2456         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2457         spin_unlock_irqrestore(&wl->irq_lock, flags);
2458
2459         return 0;
2460 }
2461
2462 static const char *phymode_to_string(unsigned int phymode)
2463 {
2464         switch (phymode) {
2465         case B43legacy_PHYMODE_B:
2466                 return "B";
2467         case B43legacy_PHYMODE_G:
2468                 return "G";
2469         default:
2470                 B43legacy_BUG_ON(1);
2471         }
2472         return "";
2473 }
2474
2475 static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2476                                   unsigned int phymode,
2477                                   struct b43legacy_wldev **dev,
2478                                   bool *gmode)
2479 {
2480         struct b43legacy_wldev *d;
2481
2482         list_for_each_entry(d, &wl->devlist, list) {
2483                 if (d->phy.possible_phymodes & phymode) {
2484                         /* Ok, this device supports the PHY-mode.
2485                          * Set the gmode bit. */
2486                         *gmode = 1;
2487                         *dev = d;
2488
2489                         return 0;
2490                 }
2491         }
2492
2493         return -ESRCH;
2494 }
2495
2496 static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2497 {
2498         struct ssb_device *sdev = dev->dev;
2499         u32 tmslow;
2500
2501         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2502         tmslow &= ~B43legacy_TMSLOW_GMODE;
2503         tmslow |= B43legacy_TMSLOW_PHYRESET;
2504         tmslow |= SSB_TMSLOW_FGC;
2505         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2506         msleep(1);
2507
2508         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2509         tmslow &= ~SSB_TMSLOW_FGC;
2510         tmslow |= B43legacy_TMSLOW_PHYRESET;
2511         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2512         msleep(1);
2513 }
2514
2515 /* Expects wl->mutex locked */
2516 static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2517                                       unsigned int new_mode)
2518 {
2519         struct b43legacy_wldev *uninitialized_var(up_dev);
2520         struct b43legacy_wldev *down_dev;
2521         int err;
2522         bool gmode = 0;
2523         int prev_status;
2524
2525         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2526         if (err) {
2527                 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2528                        phymode_to_string(new_mode));
2529                 return err;
2530         }
2531         if ((up_dev == wl->current_dev) &&
2532             (!!wl->current_dev->phy.gmode == !!gmode))
2533                 /* This device is already running. */
2534                 return 0;
2535         b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2536                phymode_to_string(new_mode));
2537         down_dev = wl->current_dev;
2538
2539         prev_status = b43legacy_status(down_dev);
2540         /* Shutdown the currently running core. */
2541         if (prev_status >= B43legacy_STAT_STARTED)
2542                 b43legacy_wireless_core_stop(down_dev);
2543         if (prev_status >= B43legacy_STAT_INITIALIZED)
2544                 b43legacy_wireless_core_exit(down_dev);
2545
2546         if (down_dev != up_dev)
2547                 /* We switch to a different core, so we put PHY into
2548                  * RESET on the old core. */
2549                 b43legacy_put_phy_into_reset(down_dev);
2550
2551         /* Now start the new core. */
2552         up_dev->phy.gmode = gmode;
2553         if (prev_status >= B43legacy_STAT_INITIALIZED) {
2554                 err = b43legacy_wireless_core_init(up_dev);
2555                 if (err) {
2556                         b43legacyerr(wl, "Fatal: Could not initialize device"
2557                                      " for newly selected %s-PHY mode\n",
2558                                      phymode_to_string(new_mode));
2559                         goto init_failure;
2560                 }
2561         }
2562         if (prev_status >= B43legacy_STAT_STARTED) {
2563                 err = b43legacy_wireless_core_start(up_dev);
2564                 if (err) {
2565                         b43legacyerr(wl, "Fatal: Coult not start device for "
2566                                "newly selected %s-PHY mode\n",
2567                                phymode_to_string(new_mode));
2568                         b43legacy_wireless_core_exit(up_dev);
2569                         goto init_failure;
2570                 }
2571         }
2572         B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2573
2574         b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2575
2576         wl->current_dev = up_dev;
2577
2578         return 0;
2579 init_failure:
2580         /* Whoops, failed to init the new core. No core is operating now. */
2581         wl->current_dev = NULL;
2582         return err;
2583 }
2584
2585 /* Write the short and long frame retry limit values. */
2586 static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2587                                        unsigned int short_retry,
2588                                        unsigned int long_retry)
2589 {
2590         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2591          * the chip-internal counter. */
2592         short_retry = min(short_retry, (unsigned int)0xF);
2593         long_retry = min(long_retry, (unsigned int)0xF);
2594
2595         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2596         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2597 }
2598
2599 static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
2600                                    u32 changed)
2601 {
2602         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2603         struct b43legacy_wldev *dev;
2604         struct b43legacy_phy *phy;
2605         struct ieee80211_conf *conf = &hw->conf;
2606         unsigned long flags;
2607         unsigned int new_phymode = 0xFFFF;
2608         int antenna_tx;
2609         int antenna_rx;
2610         int err = 0;
2611
2612         antenna_tx = B43legacy_ANTENNA_DEFAULT;
2613         antenna_rx = B43legacy_ANTENNA_DEFAULT;
2614
2615         mutex_lock(&wl->mutex);
2616         dev = wl->current_dev;
2617         phy = &dev->phy;
2618
2619         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2620                 b43legacy_set_retry_limits(dev,
2621                                            conf->short_frame_max_tx_count,
2622                                            conf->long_frame_max_tx_count);
2623         changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
2624         if (!changed)
2625                 goto out_unlock_mutex;
2626
2627         /* Switch the PHY mode (if necessary). */
2628         switch (conf->channel->band) {
2629         case IEEE80211_BAND_2GHZ:
2630                 if (phy->type == B43legacy_PHYTYPE_B)
2631                         new_phymode = B43legacy_PHYMODE_B;
2632                 else
2633                         new_phymode = B43legacy_PHYMODE_G;
2634                 break;
2635         default:
2636                 B43legacy_WARN_ON(1);
2637         }
2638         err = b43legacy_switch_phymode(wl, new_phymode);
2639         if (err)
2640                 goto out_unlock_mutex;
2641
2642         /* Disable IRQs while reconfiguring the device.
2643          * This makes it possible to drop the spinlock throughout
2644          * the reconfiguration process. */
2645         spin_lock_irqsave(&wl->irq_lock, flags);
2646         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2647                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2648                 goto out_unlock_mutex;
2649         }
2650         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2651         spin_unlock_irqrestore(&wl->irq_lock, flags);
2652         b43legacy_synchronize_irq(dev);
2653
2654         /* Switch to the requested channel.
2655          * The firmware takes care of races with the TX handler. */
2656         if (conf->channel->hw_value != phy->channel)
2657                 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
2658
2659         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
2660
2661         /* Adjust the desired TX power level. */
2662         if (conf->power_level != 0) {
2663                 if (conf->power_level != phy->power_level) {
2664                         phy->power_level = conf->power_level;
2665                         b43legacy_phy_xmitpower(dev);
2666                 }
2667         }
2668
2669         /* Antennas for RX and management frame TX. */
2670         b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2671
2672         if (wl->radio_enabled != phy->radio_on) {
2673                 if (wl->radio_enabled) {
2674                         b43legacy_radio_turn_on(dev);
2675                         b43legacyinfo(dev->wl, "Radio turned on by software\n");
2676                         if (!dev->radio_hw_enable)
2677                                 b43legacyinfo(dev->wl, "The hardware RF-kill"
2678                                               " button still turns the radio"
2679                                               " physically off. Press the"
2680                                               " button to turn it on.\n");
2681                 } else {
2682                         b43legacy_radio_turn_off(dev, 0);
2683                         b43legacyinfo(dev->wl, "Radio turned off by"
2684                                       " software\n");
2685                 }
2686         }
2687
2688         spin_lock_irqsave(&wl->irq_lock, flags);
2689         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2690         mmiowb();
2691         spin_unlock_irqrestore(&wl->irq_lock, flags);
2692 out_unlock_mutex:
2693         mutex_unlock(&wl->mutex);
2694
2695         return err;
2696 }
2697
2698 static void b43legacy_update_basic_rates(struct b43legacy_wldev *dev, u32 brates)
2699 {
2700         struct ieee80211_supported_band *sband =
2701                 dev->wl->hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2702         struct ieee80211_rate *rate;
2703         int i;
2704         u16 basic, direct, offset, basic_offset, rateptr;
2705
2706         for (i = 0; i < sband->n_bitrates; i++) {
2707                 rate = &sband->bitrates[i];
2708
2709                 if (b43legacy_is_cck_rate(rate->hw_value)) {
2710                         direct = B43legacy_SHM_SH_CCKDIRECT;
2711                         basic = B43legacy_SHM_SH_CCKBASIC;
2712                         offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2713                         offset &= 0xF;
2714                 } else {
2715                         direct = B43legacy_SHM_SH_OFDMDIRECT;
2716                         basic = B43legacy_SHM_SH_OFDMBASIC;
2717                         offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2718                         offset &= 0xF;
2719                 }
2720
2721                 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
2722
2723                 if (b43legacy_is_cck_rate(rate->hw_value)) {
2724                         basic_offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2725                         basic_offset &= 0xF;
2726                 } else {
2727                         basic_offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2728                         basic_offset &= 0xF;
2729                 }
2730
2731                 /*
2732                  * Get the pointer that we need to point to
2733                  * from the direct map
2734                  */
2735                 rateptr = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2736                                                direct + 2 * basic_offset);
2737                 /* and write it to the basic map */
2738                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2739                                       basic + 2 * offset, rateptr);
2740         }
2741 }
2742
2743 static void b43legacy_op_bss_info_changed(struct ieee80211_hw *hw,
2744                                     struct ieee80211_vif *vif,
2745                                     struct ieee80211_bss_conf *conf,
2746                                     u32 changed)
2747 {
2748         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2749         struct b43legacy_wldev *dev;
2750         struct b43legacy_phy *phy;
2751         unsigned long flags;
2752
2753         mutex_lock(&wl->mutex);
2754         B43legacy_WARN_ON(wl->vif != vif);
2755
2756         dev = wl->current_dev;
2757         phy = &dev->phy;
2758
2759         /* Disable IRQs while reconfiguring the device.
2760          * This makes it possible to drop the spinlock throughout
2761          * the reconfiguration process. */
2762         spin_lock_irqsave(&wl->irq_lock, flags);
2763         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2764                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2765                 goto out_unlock_mutex;
2766         }
2767         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2768
2769         if (changed & BSS_CHANGED_BSSID) {
2770                 b43legacy_synchronize_irq(dev);
2771
2772                 if (conf->bssid)
2773                         memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2774                 else
2775                         memset(wl->bssid, 0, ETH_ALEN);
2776         }
2777
2778         if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2779                 if (changed & BSS_CHANGED_BEACON &&
2780                     (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2781                      b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2782                         b43legacy_update_templates(wl);
2783
2784                 if (changed & BSS_CHANGED_BSSID)
2785                         b43legacy_write_mac_bssid_templates(dev);
2786         }
2787         spin_unlock_irqrestore(&wl->irq_lock, flags);
2788
2789         b43legacy_mac_suspend(dev);
2790
2791         if (changed & BSS_CHANGED_BEACON_INT &&
2792             (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2793              b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2794                 b43legacy_set_beacon_int(dev, conf->beacon_int);
2795
2796         if (changed & BSS_CHANGED_BASIC_RATES)
2797                 b43legacy_update_basic_rates(dev, conf->basic_rates);
2798
2799         if (changed & BSS_CHANGED_ERP_SLOT) {
2800                 if (conf->use_short_slot)
2801                         b43legacy_short_slot_timing_enable(dev);
2802                 else
2803                         b43legacy_short_slot_timing_disable(dev);
2804         }
2805
2806         b43legacy_mac_enable(dev);
2807
2808         spin_lock_irqsave(&wl->irq_lock, flags);
2809         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2810         /* XXX: why? */
2811         mmiowb();
2812         spin_unlock_irqrestore(&wl->irq_lock, flags);
2813  out_unlock_mutex:
2814         mutex_unlock(&wl->mutex);
2815 }
2816
2817 static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2818                                           unsigned int changed,
2819                                           unsigned int *fflags,u64 multicast)
2820 {
2821         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2822         struct b43legacy_wldev *dev = wl->current_dev;
2823         unsigned long flags;
2824
2825         if (!dev) {
2826                 *fflags = 0;
2827                 return;
2828         }
2829
2830         spin_lock_irqsave(&wl->irq_lock, flags);
2831         *fflags &= FIF_PROMISC_IN_BSS |
2832                   FIF_ALLMULTI |
2833                   FIF_FCSFAIL |
2834                   FIF_PLCPFAIL |
2835                   FIF_CONTROL |
2836                   FIF_OTHER_BSS |
2837                   FIF_BCN_PRBRESP_PROMISC;
2838
2839         changed &= FIF_PROMISC_IN_BSS |
2840                    FIF_ALLMULTI |
2841                    FIF_FCSFAIL |
2842                    FIF_PLCPFAIL |
2843                    FIF_CONTROL |
2844                    FIF_OTHER_BSS |
2845                    FIF_BCN_PRBRESP_PROMISC;
2846
2847         wl->filter_flags = *fflags;
2848
2849         if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2850                 b43legacy_adjust_opmode(dev);
2851         spin_unlock_irqrestore(&wl->irq_lock, flags);
2852 }
2853
2854 /* Locking: wl->mutex */
2855 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2856 {
2857         struct b43legacy_wl *wl = dev->wl;
2858         unsigned long flags;
2859
2860         if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2861                 return;
2862
2863         /* Disable and sync interrupts. We must do this before than
2864          * setting the status to INITIALIZED, as the interrupt handler
2865          * won't care about IRQs then. */
2866         spin_lock_irqsave(&wl->irq_lock, flags);
2867         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2868         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2869         spin_unlock_irqrestore(&wl->irq_lock, flags);
2870         b43legacy_synchronize_irq(dev);
2871
2872         b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2873
2874         mutex_unlock(&wl->mutex);
2875         /* Must unlock as it would otherwise deadlock. No races here.
2876          * Cancel the possibly running self-rearming periodic work. */
2877         cancel_delayed_work_sync(&dev->periodic_work);
2878         mutex_lock(&wl->mutex);
2879
2880         ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
2881
2882         b43legacy_mac_suspend(dev);
2883         free_irq(dev->dev->irq, dev);
2884         b43legacydbg(wl, "Wireless interface stopped\n");
2885 }
2886
2887 /* Locking: wl->mutex */
2888 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2889 {
2890         int err;
2891
2892         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2893
2894         drain_txstatus_queue(dev);
2895         err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2896                           IRQF_SHARED, KBUILD_MODNAME, dev);
2897         if (err) {
2898                 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2899                        dev->dev->irq);
2900                 goto out;
2901         }
2902         /* We are ready to run. */
2903         ieee80211_wake_queues(dev->wl->hw);
2904         b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2905
2906         /* Start data flow (TX/RX) */
2907         b43legacy_mac_enable(dev);
2908         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2909
2910         /* Start maintenance work */
2911         b43legacy_periodic_tasks_setup(dev);
2912
2913         b43legacydbg(dev->wl, "Wireless interface started\n");
2914 out:
2915         return err;
2916 }
2917
2918 /* Get PHY and RADIO versioning numbers */
2919 static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2920 {
2921         struct b43legacy_phy *phy = &dev->phy;
2922         u32 tmp;
2923         u8 analog_type;
2924         u8 phy_type;
2925         u8 phy_rev;
2926         u16 radio_manuf;
2927         u16 radio_ver;
2928         u16 radio_rev;
2929         int unsupported = 0;
2930
2931         /* Get PHY versioning */
2932         tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
2933         analog_type = (tmp & B43legacy_PHYVER_ANALOG)
2934                       >> B43legacy_PHYVER_ANALOG_SHIFT;
2935         phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
2936         phy_rev = (tmp & B43legacy_PHYVER_VERSION);
2937         switch (phy_type) {
2938         case B43legacy_PHYTYPE_B:
2939                 if (phy_rev != 2 && phy_rev != 4
2940                     && phy_rev != 6 && phy_rev != 7)
2941                         unsupported = 1;
2942                 break;
2943         case B43legacy_PHYTYPE_G:
2944                 if (phy_rev > 8)
2945                         unsupported = 1;
2946                 break;
2947         default:
2948                 unsupported = 1;
2949         };
2950         if (unsupported) {
2951                 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
2952                        "(Analog %u, Type %u, Revision %u)\n",
2953                        analog_type, phy_type, phy_rev);
2954                 return -EOPNOTSUPP;
2955         }
2956         b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
2957                analog_type, phy_type, phy_rev);
2958
2959
2960         /* Get RADIO versioning */
2961         if (dev->dev->bus->chip_id == 0x4317) {
2962                 if (dev->dev->bus->chip_rev == 0)
2963                         tmp = 0x3205017F;
2964                 else if (dev->dev->bus->chip_rev == 1)
2965                         tmp = 0x4205017F;
2966                 else
2967                         tmp = 0x5205017F;
2968         } else {
2969                 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2970                                   B43legacy_RADIOCTL_ID);
2971                 tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
2972                 tmp <<= 16;
2973                 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2974                                   B43legacy_RADIOCTL_ID);
2975                 tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
2976         }
2977         radio_manuf = (tmp & 0x00000FFF);
2978         radio_ver = (tmp & 0x0FFFF000) >> 12;
2979         radio_rev = (tmp & 0xF0000000) >> 28;
2980         switch (phy_type) {
2981         case B43legacy_PHYTYPE_B:
2982                 if ((radio_ver & 0xFFF0) != 0x2050)
2983                         unsupported = 1;
2984                 break;
2985         case B43legacy_PHYTYPE_G:
2986                 if (radio_ver != 0x2050)
2987                         unsupported = 1;
2988                 break;
2989         default:
2990                 B43legacy_BUG_ON(1);
2991         }
2992         if (unsupported) {
2993                 b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
2994                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
2995                        radio_manuf, radio_ver, radio_rev);
2996                 return -EOPNOTSUPP;
2997         }
2998         b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
2999                      " Revision %u\n", radio_manuf, radio_ver, radio_rev);
3000
3001
3002         phy->radio_manuf = radio_manuf;
3003         phy->radio_ver = radio_ver;
3004         phy->radio_rev = radio_rev;
3005
3006         phy->analog = analog_type;
3007         phy->type = phy_type;
3008         phy->rev = phy_rev;
3009
3010         return 0;
3011 }
3012
3013 static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
3014                                       struct b43legacy_phy *phy)
3015 {
3016         struct b43legacy_lopair *lo;
3017         int i;
3018
3019         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3020         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3021
3022         /* Assume the radio is enabled. If it's not enabled, the state will
3023          * immediately get fixed on the first periodic work run. */
3024         dev->radio_hw_enable = 1;
3025
3026         phy->savedpctlreg = 0xFFFF;
3027         phy->aci_enable = 0;
3028         phy->aci_wlan_automatic = 0;
3029         phy->aci_hw_rssi = 0;
3030
3031         lo = phy->_lo_pairs;
3032         if (lo)
3033                 memset(lo, 0, sizeof(struct b43legacy_lopair) *
3034                                      B43legacy_LO_COUNT);
3035         phy->max_lb_gain = 0;
3036         phy->trsw_rx_gain = 0;
3037
3038         /* Set default attenuation values. */
3039         phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3040         phy->rfatt = b43legacy_default_radio_attenuation(dev);
3041         phy->txctl1 = b43legacy_default_txctl1(dev);
3042         phy->txpwr_offset = 0;
3043
3044         /* NRSSI */
3045         phy->nrssislope = 0;
3046         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3047                 phy->nrssi[i] = -1000;
3048         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3049                 phy->nrssi_lt[i] = i;
3050
3051         phy->lofcal = 0xFFFF;
3052         phy->initval = 0xFFFF;
3053
3054         phy->interfmode = B43legacy_INTERFMODE_NONE;
3055         phy->channel = 0xFF;
3056 }
3057
3058 static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
3059 {
3060         /* Flags */
3061         dev->dfq_valid = 0;
3062
3063         /* Stats */
3064         memset(&dev->stats, 0, sizeof(dev->stats));
3065
3066         setup_struct_phy_for_init(dev, &dev->phy);
3067
3068         /* IRQ related flags */
3069         dev->irq_reason = 0;
3070         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3071         dev->irq_mask = B43legacy_IRQ_MASKTEMPLATE;
3072
3073         dev->mac_suspended = 1;
3074
3075         /* Noise calculation context */
3076         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3077 }
3078
3079 static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
3080 {
3081 #ifdef CONFIG_SSB_DRIVER_PCICORE
3082         struct ssb_bus *bus = dev->dev->bus;
3083         u32 tmp;
3084
3085         if (bus->pcicore.dev &&
3086             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3087             bus->pcicore.dev->id.revision <= 5) {
3088                 /* IMCFGLO timeouts workaround. */
3089                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3090                 switch (bus->bustype) {
3091                 case SSB_BUSTYPE_PCI:
3092                 case SSB_BUSTYPE_PCMCIA:
3093                         tmp &= ~SSB_IMCFGLO_REQTO;
3094                         tmp &= ~SSB_IMCFGLO_SERTO;
3095                         tmp |= 0x32;
3096                         break;
3097                 case SSB_BUSTYPE_SSB:
3098                         tmp &= ~SSB_IMCFGLO_REQTO;
3099                         tmp &= ~SSB_IMCFGLO_SERTO;
3100                         tmp |= 0x53;
3101                         break;
3102                 default:
3103                         break;
3104                 }
3105                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3106         }
3107 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3108 }
3109
3110 static void b43legacy_set_synth_pu_delay(struct b43legacy_wldev *dev,
3111                                           bool idle) {
3112         u16 pu_delay = 1050;
3113
3114         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
3115                 pu_delay = 500;
3116         if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3117                 pu_delay = max(pu_delay, (u16)2400);
3118
3119         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3120                               B43legacy_SHM_SH_SPUWKUP, pu_delay);
3121 }
3122
3123 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3124 static void b43legacy_set_pretbtt(struct b43legacy_wldev *dev)
3125 {
3126         u16 pretbtt;
3127
3128         /* The time value is in microseconds. */
3129         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3130                 pretbtt = 2;
3131         else
3132                 pretbtt = 250;
3133         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3134                               B43legacy_SHM_SH_PRETBTT, pretbtt);
3135         b43legacy_write16(dev, B43legacy_MMIO_TSF_CFP_PRETBTT, pretbtt);
3136 }
3137
3138 /* Shutdown a wireless core */
3139 /* Locking: wl->mutex */
3140 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
3141 {
3142         struct b43legacy_phy *phy = &dev->phy;
3143         u32 macctl;
3144
3145         B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
3146         if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
3147                 return;
3148         b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
3149
3150         /* Stop the microcode PSM. */
3151         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
3152         macctl &= ~B43legacy_MACCTL_PSM_RUN;
3153         macctl |= B43legacy_MACCTL_PSM_JMP0;
3154         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
3155
3156         b43legacy_leds_exit(dev);
3157         b43legacy_rng_exit(dev->wl);
3158         b43legacy_pio_free(dev);
3159         b43legacy_dma_free(dev);
3160         b43legacy_chip_exit(dev);
3161         b43legacy_radio_turn_off(dev, 1);
3162         b43legacy_switch_analog(dev, 0);
3163         if (phy->dyn_tssi_tbl)
3164                 kfree(phy->tssi2dbm);
3165         kfree(phy->lo_control);
3166         phy->lo_control = NULL;
3167         if (dev->wl->current_beacon) {
3168                 dev_kfree_skb_any(dev->wl->current_beacon);
3169                 dev->wl->current_beacon = NULL;
3170         }
3171
3172         ssb_device_disable(dev->dev, 0);
3173         ssb_bus_may_powerdown(dev->dev->bus);
3174 }
3175
3176 static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
3177 {
3178         struct b43legacy_phy *phy = &dev->phy;
3179         int i;
3180
3181         /* Set default attenuation values. */
3182         phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3183         phy->rfatt = b43legacy_default_radio_attenuation(dev);
3184         phy->txctl1 = b43legacy_default_txctl1(dev);
3185         phy->txctl2 = 0xFFFF;
3186         phy->txpwr_offset = 0;
3187
3188         /* NRSSI */
3189         phy->nrssislope = 0;
3190         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3191                 phy->nrssi[i] = -1000;
3192         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3193                 phy->nrssi_lt[i] = i;
3194
3195         phy->lofcal = 0xFFFF;
3196         phy->initval = 0xFFFF;
3197
3198         phy->aci_enable = 0;
3199         phy->aci_wlan_automatic = 0;
3200         phy->aci_hw_rssi = 0;
3201
3202         phy->antenna_diversity = 0xFFFF;
3203         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3204         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3205
3206         /* Flags */
3207         phy->calibrated = 0;
3208
3209         if (phy->_lo_pairs)
3210                 memset(phy->_lo_pairs, 0,
3211                        sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
3212         memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3213 }
3214
3215 /* Initialize a wireless core */
3216 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
3217 {
3218         struct b43legacy_wl *wl = dev->wl;
3219         struct ssb_bus *bus = dev->dev->bus;
3220         struct b43legacy_phy *phy = &dev->phy;
3221         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3222         int err;
3223         u32 hf;
3224         u32 tmp;
3225
3226         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3227
3228         err = ssb_bus_powerup(bus, 0);
3229         if (err)
3230                 goto out;
3231         if (!ssb_device_is_enabled(dev->dev)) {
3232                 tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
3233                 b43legacy_wireless_core_reset(dev, tmp);
3234         }
3235
3236         if ((phy->type == B43legacy_PHYTYPE_B) ||
3237             (phy->type == B43legacy_PHYTYPE_G)) {
3238                 phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
3239                                          * B43legacy_LO_COUNT,
3240                                          GFP_KERNEL);
3241                 if (!phy->_lo_pairs)
3242                         return -ENOMEM;
3243         }
3244         setup_struct_wldev_for_init(dev);
3245
3246         err = b43legacy_phy_init_tssi2dbm_table(dev);