Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[kernel.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  *  Intel Linux Wireless <ilw@linux.intel.com>
23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24  *
25  *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/sched.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40 #include <net/mac80211.h>
41
42 #include "iwl-fh.h"
43 #include "iwl-3945-fh.h"
44 #include "iwl-commands.h"
45 #include "iwl-sta.h"
46 #include "iwl-3945.h"
47 #include "iwl-eeprom.h"
48 #include "iwl-helpers.h"
49 #include "iwl-core.h"
50 #include "iwl-led.h"
51 #include "iwl-3945-led.h"
52
53 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
54         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
55                                     IWL_RATE_##r##M_IEEE,   \
56                                     IWL_RATE_##ip##M_INDEX, \
57                                     IWL_RATE_##in##M_INDEX, \
58                                     IWL_RATE_##rp##M_INDEX, \
59                                     IWL_RATE_##rn##M_INDEX, \
60                                     IWL_RATE_##pp##M_INDEX, \
61                                     IWL_RATE_##np##M_INDEX, \
62                                     IWL_RATE_##r##M_INDEX_TABLE, \
63                                     IWL_RATE_##ip##M_INDEX_TABLE }
64
65 /*
66  * Parameter order:
67  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
68  *
69  * If there isn't a valid next or previous rate then INV is used which
70  * maps to IWL_RATE_INVALID
71  *
72  */
73 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
74         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
75         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
76         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
77         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
78         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
79         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
80         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
81         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
82         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
83         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
84         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
85         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
86 };
87
88 /* 1 = enable the iwl3945_disable_events() function */
89 #define IWL_EVT_DISABLE (0)
90 #define IWL_EVT_DISABLE_SIZE (1532/32)
91
92 /**
93  * iwl3945_disable_events - Disable selected events in uCode event log
94  *
95  * Disable an event by writing "1"s into "disable"
96  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
97  *   Default values of 0 enable uCode events to be logged.
98  * Use for only special debugging.  This function is just a placeholder as-is,
99  *   you'll need to provide the special bits! ...
100  *   ... and set IWL_EVT_DISABLE to 1. */
101 void iwl3945_disable_events(struct iwl_priv *priv)
102 {
103         int i;
104         u32 base;               /* SRAM address of event log header */
105         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
106         u32 array_size;         /* # of u32 entries in array */
107         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
108                 0x00000000,     /*   31 -    0  Event id numbers */
109                 0x00000000,     /*   63 -   32 */
110                 0x00000000,     /*   95 -   64 */
111                 0x00000000,     /*  127 -   96 */
112                 0x00000000,     /*  159 -  128 */
113                 0x00000000,     /*  191 -  160 */
114                 0x00000000,     /*  223 -  192 */
115                 0x00000000,     /*  255 -  224 */
116                 0x00000000,     /*  287 -  256 */
117                 0x00000000,     /*  319 -  288 */
118                 0x00000000,     /*  351 -  320 */
119                 0x00000000,     /*  383 -  352 */
120                 0x00000000,     /*  415 -  384 */
121                 0x00000000,     /*  447 -  416 */
122                 0x00000000,     /*  479 -  448 */
123                 0x00000000,     /*  511 -  480 */
124                 0x00000000,     /*  543 -  512 */
125                 0x00000000,     /*  575 -  544 */
126                 0x00000000,     /*  607 -  576 */
127                 0x00000000,     /*  639 -  608 */
128                 0x00000000,     /*  671 -  640 */
129                 0x00000000,     /*  703 -  672 */
130                 0x00000000,     /*  735 -  704 */
131                 0x00000000,     /*  767 -  736 */
132                 0x00000000,     /*  799 -  768 */
133                 0x00000000,     /*  831 -  800 */
134                 0x00000000,     /*  863 -  832 */
135                 0x00000000,     /*  895 -  864 */
136                 0x00000000,     /*  927 -  896 */
137                 0x00000000,     /*  959 -  928 */
138                 0x00000000,     /*  991 -  960 */
139                 0x00000000,     /* 1023 -  992 */
140                 0x00000000,     /* 1055 - 1024 */
141                 0x00000000,     /* 1087 - 1056 */
142                 0x00000000,     /* 1119 - 1088 */
143                 0x00000000,     /* 1151 - 1120 */
144                 0x00000000,     /* 1183 - 1152 */
145                 0x00000000,     /* 1215 - 1184 */
146                 0x00000000,     /* 1247 - 1216 */
147                 0x00000000,     /* 1279 - 1248 */
148                 0x00000000,     /* 1311 - 1280 */
149                 0x00000000,     /* 1343 - 1312 */
150                 0x00000000,     /* 1375 - 1344 */
151                 0x00000000,     /* 1407 - 1376 */
152                 0x00000000,     /* 1439 - 1408 */
153                 0x00000000,     /* 1471 - 1440 */
154                 0x00000000,     /* 1503 - 1472 */
155         };
156
157         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
158         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
159                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
160                 return;
161         }
162
163         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
164         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
165
166         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
167                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
168                                disable_ptr);
169                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
170                         iwl_write_targ_mem(priv,
171                                            disable_ptr + (i * sizeof(u32)),
172                                            evt_disable[i]);
173
174         } else {
175                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
176                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
177                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
178                                disable_ptr, array_size);
179         }
180
181 }
182
183 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
184 {
185         int idx;
186
187         for (idx = 0; idx < IWL_RATE_COUNT; idx++)
188                 if (iwl3945_rates[idx].plcp == plcp)
189                         return idx;
190         return -1;
191 }
192
193 #ifdef CONFIG_IWLWIFI_DEBUG
194 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
195
196 static const char *iwl3945_get_tx_fail_reason(u32 status)
197 {
198         switch (status & TX_STATUS_MSK) {
199         case TX_STATUS_SUCCESS:
200                 return "SUCCESS";
201                 TX_STATUS_ENTRY(SHORT_LIMIT);
202                 TX_STATUS_ENTRY(LONG_LIMIT);
203                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
204                 TX_STATUS_ENTRY(MGMNT_ABORT);
205                 TX_STATUS_ENTRY(NEXT_FRAG);
206                 TX_STATUS_ENTRY(LIFE_EXPIRE);
207                 TX_STATUS_ENTRY(DEST_PS);
208                 TX_STATUS_ENTRY(ABORTED);
209                 TX_STATUS_ENTRY(BT_RETRY);
210                 TX_STATUS_ENTRY(STA_INVALID);
211                 TX_STATUS_ENTRY(FRAG_DROPPED);
212                 TX_STATUS_ENTRY(TID_DISABLE);
213                 TX_STATUS_ENTRY(FRAME_FLUSHED);
214                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
215                 TX_STATUS_ENTRY(TX_LOCKED);
216                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
217         }
218
219         return "UNKNOWN";
220 }
221 #else
222 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
223 {
224         return "";
225 }
226 #endif
227
228 /*
229  * get ieee prev rate from rate scale table.
230  * for A and B mode we need to overright prev
231  * value
232  */
233 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
234 {
235         int next_rate = iwl3945_get_prev_ieee_rate(rate);
236
237         switch (priv->band) {
238         case IEEE80211_BAND_5GHZ:
239                 if (rate == IWL_RATE_12M_INDEX)
240                         next_rate = IWL_RATE_9M_INDEX;
241                 else if (rate == IWL_RATE_6M_INDEX)
242                         next_rate = IWL_RATE_6M_INDEX;
243                 break;
244         case IEEE80211_BAND_2GHZ:
245                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
246                     iwl_is_associated(priv)) {
247                         if (rate == IWL_RATE_11M_INDEX)
248                                 next_rate = IWL_RATE_5M_INDEX;
249                 }
250                 break;
251
252         default:
253                 break;
254         }
255
256         return next_rate;
257 }
258
259
260 /**
261  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
262  *
263  * When FW advances 'R' index, all entries between old and new 'R' index
264  * need to be reclaimed. As result, some free space forms. If there is
265  * enough free space (> low mark), wake the stack that feeds us.
266  */
267 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
268                                      int txq_id, int index)
269 {
270         struct iwl_tx_queue *txq = &priv->txq[txq_id];
271         struct iwl_queue *q = &txq->q;
272         struct iwl_tx_info *tx_info;
273
274         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
275
276         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
277                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
278
279                 tx_info = &txq->txb[txq->q.read_ptr];
280                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
281                 tx_info->skb[0] = NULL;
282                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
283         }
284
285         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
286                         (txq_id != IWL_CMD_QUEUE_NUM) &&
287                         priv->mac80211_registered)
288                 iwl_wake_queue(priv, txq_id);
289 }
290
291 /**
292  * iwl3945_rx_reply_tx - Handle Tx response
293  */
294 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
295                             struct iwl_rx_mem_buffer *rxb)
296 {
297         struct iwl_rx_packet *pkt = rxb_addr(rxb);
298         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
299         int txq_id = SEQ_TO_QUEUE(sequence);
300         int index = SEQ_TO_INDEX(sequence);
301         struct iwl_tx_queue *txq = &priv->txq[txq_id];
302         struct ieee80211_tx_info *info;
303         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
304         u32  status = le32_to_cpu(tx_resp->status);
305         int rate_idx;
306         int fail;
307
308         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
309                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
310                           "is out of range [0-%d] %d %d\n", txq_id,
311                           index, txq->q.n_bd, txq->q.write_ptr,
312                           txq->q.read_ptr);
313                 return;
314         }
315
316         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
317         ieee80211_tx_info_clear_status(info);
318
319         /* Fill the MRR chain with some info about on-chip retransmissions */
320         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
321         if (info->band == IEEE80211_BAND_5GHZ)
322                 rate_idx -= IWL_FIRST_OFDM_RATE;
323
324         fail = tx_resp->failure_frame;
325
326         info->status.rates[0].idx = rate_idx;
327         info->status.rates[0].count = fail + 1; /* add final attempt */
328
329         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
330         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
331                                 IEEE80211_TX_STAT_ACK : 0;
332
333         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
334                         txq_id, iwl3945_get_tx_fail_reason(status), status,
335                         tx_resp->rate, tx_resp->failure_frame);
336
337         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
338         iwl3945_tx_queue_reclaim(priv, txq_id, index);
339
340         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
341                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
342 }
343
344
345
346 /*****************************************************************************
347  *
348  * Intel PRO/Wireless 3945ABG/BG Network Connection
349  *
350  *  RX handler implementations
351  *
352  *****************************************************************************/
353
354 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
355                 struct iwl_rx_mem_buffer *rxb)
356 {
357         struct iwl_rx_packet *pkt = rxb_addr(rxb);
358         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
359                      (int)sizeof(struct iwl3945_notif_statistics),
360                      le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
361
362         memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
363 }
364
365 /******************************************************************************
366  *
367  * Misc. internal state and helper functions
368  *
369  ******************************************************************************/
370 #ifdef CONFIG_IWLWIFI_DEBUG
371
372 /**
373  * iwl3945_report_frame - dump frame to syslog during debug sessions
374  *
375  * You may hack this function to show different aspects of received frames,
376  * including selective frame dumps.
377  * group100 parameter selects whether to show 1 out of 100 good frames.
378  */
379 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
380                       struct iwl_rx_packet *pkt,
381                       struct ieee80211_hdr *header, int group100)
382 {
383         u32 to_us;
384         u32 print_summary = 0;
385         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
386         u32 hundred = 0;
387         u32 dataframe = 0;
388         __le16 fc;
389         u16 seq_ctl;
390         u16 channel;
391         u16 phy_flags;
392         u16 length;
393         u16 status;
394         u16 bcn_tmr;
395         u32 tsf_low;
396         u64 tsf;
397         u8 rssi;
398         u8 agc;
399         u16 sig_avg;
400         u16 noise_diff;
401         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
402         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
403         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
404         u8 *data = IWL_RX_DATA(pkt);
405
406         /* MAC header */
407         fc = header->frame_control;
408         seq_ctl = le16_to_cpu(header->seq_ctrl);
409
410         /* metadata */
411         channel = le16_to_cpu(rx_hdr->channel);
412         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
413         length = le16_to_cpu(rx_hdr->len);
414
415         /* end-of-frame status and timestamp */
416         status = le32_to_cpu(rx_end->status);
417         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
418         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
419         tsf = le64_to_cpu(rx_end->timestamp);
420
421         /* signal statistics */
422         rssi = rx_stats->rssi;
423         agc = rx_stats->agc;
424         sig_avg = le16_to_cpu(rx_stats->sig_avg);
425         noise_diff = le16_to_cpu(rx_stats->noise_diff);
426
427         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
428
429         /* if data frame is to us and all is good,
430          *   (optionally) print summary for only 1 out of every 100 */
431         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
432             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
433                 dataframe = 1;
434                 if (!group100)
435                         print_summary = 1;      /* print each frame */
436                 else if (priv->framecnt_to_us < 100) {
437                         priv->framecnt_to_us++;
438                         print_summary = 0;
439                 } else {
440                         priv->framecnt_to_us = 0;
441                         print_summary = 1;
442                         hundred = 1;
443                 }
444         } else {
445                 /* print summary for all other frames */
446                 print_summary = 1;
447         }
448
449         if (print_summary) {
450                 char *title;
451                 int rate;
452
453                 if (hundred)
454                         title = "100Frames";
455                 else if (ieee80211_has_retry(fc))
456                         title = "Retry";
457                 else if (ieee80211_is_assoc_resp(fc))
458                         title = "AscRsp";
459                 else if (ieee80211_is_reassoc_resp(fc))
460                         title = "RasRsp";
461                 else if (ieee80211_is_probe_resp(fc)) {
462                         title = "PrbRsp";
463                         print_dump = 1; /* dump frame contents */
464                 } else if (ieee80211_is_beacon(fc)) {
465                         title = "Beacon";
466                         print_dump = 1; /* dump frame contents */
467                 } else if (ieee80211_is_atim(fc))
468                         title = "ATIM";
469                 else if (ieee80211_is_auth(fc))
470                         title = "Auth";
471                 else if (ieee80211_is_deauth(fc))
472                         title = "DeAuth";
473                 else if (ieee80211_is_disassoc(fc))
474                         title = "DisAssoc";
475                 else
476                         title = "Frame";
477
478                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
479                 if (rate == -1)
480                         rate = 0;
481                 else
482                         rate = iwl3945_rates[rate].ieee / 2;
483
484                 /* print frame summary.
485                  * MAC addresses show just the last byte (for brevity),
486                  *    but you can hack it to show more, if you'd like to. */
487                 if (dataframe)
488                         IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
489                                      "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
490                                      title, le16_to_cpu(fc), header->addr1[5],
491                                      length, rssi, channel, rate);
492                 else {
493                         /* src/dst addresses assume managed mode */
494                         IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
495                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
496                                      "phy=0x%02x, chnl=%d\n",
497                                      title, le16_to_cpu(fc), header->addr1[5],
498                                      header->addr3[5], rssi,
499                                      tsf_low - priv->scan_start_tsf,
500                                      phy_flags, channel);
501                 }
502         }
503         if (print_dump)
504                 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
505 }
506
507 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
508                       struct iwl_rx_packet *pkt,
509                       struct ieee80211_hdr *header, int group100)
510 {
511         if (iwl_get_debug_level(priv) & IWL_DL_RX)
512                 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
513 }
514
515 #else
516 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
517                       struct iwl_rx_packet *pkt,
518                       struct ieee80211_hdr *header, int group100)
519 {
520 }
521 #endif
522
523 /* This is necessary only for a number of statistics, see the caller. */
524 static int iwl3945_is_network_packet(struct iwl_priv *priv,
525                 struct ieee80211_hdr *header)
526 {
527         /* Filter incoming packets to determine if they are targeted toward
528          * this network, discarding packets coming from ourselves */
529         switch (priv->iw_mode) {
530         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
531                 /* packets to our IBSS update information */
532                 return !compare_ether_addr(header->addr3, priv->bssid);
533         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
534                 /* packets to our IBSS update information */
535                 return !compare_ether_addr(header->addr2, priv->bssid);
536         default:
537                 return 1;
538         }
539 }
540
541 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
542                                    struct iwl_rx_mem_buffer *rxb,
543                                    struct ieee80211_rx_status *stats)
544 {
545         struct iwl_rx_packet *pkt = rxb_addr(rxb);
546         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
547         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
548         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
549         u16 len = le16_to_cpu(rx_hdr->len);
550         struct sk_buff *skb;
551         int ret;
552         __le16 fc = hdr->frame_control;
553
554         /* We received data from the HW, so stop the watchdog */
555         if (unlikely(len + IWL39_RX_FRAME_SIZE >
556                      PAGE_SIZE << priv->hw_params.rx_page_order)) {
557                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
558                 return;
559         }
560
561         /* We only process data packets if the interface is open */
562         if (unlikely(!priv->is_open)) {
563                 IWL_DEBUG_DROP_LIMIT(priv,
564                         "Dropping packet while interface is not open.\n");
565                 return;
566         }
567
568         skb = alloc_skb(IWL_LINK_HDR_MAX * 2, GFP_ATOMIC);
569         if (!skb) {
570                 IWL_ERR(priv, "alloc_skb failed\n");
571                 return;
572         }
573
574         if (!iwl3945_mod_params.sw_crypto)
575                 iwl_set_decrypted_flag(priv,
576                                        (struct ieee80211_hdr *)rxb_addr(rxb),
577                                        le32_to_cpu(rx_end->status), stats);
578
579         skb_reserve(skb, IWL_LINK_HDR_MAX);
580         skb_add_rx_frag(skb, 0, rxb->page,
581                         (void *)rx_hdr->payload - (void *)pkt, len);
582
583         /* mac80211 currently doesn't support paged SKB. Convert it to
584          * linear SKB for management frame and data frame requires
585          * software decryption or software defragementation. */
586         if (ieee80211_is_mgmt(fc) ||
587             ieee80211_has_protected(fc) ||
588             ieee80211_has_morefrags(fc) ||
589             le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)
590                 ret = skb_linearize(skb);
591         else
592                 ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ?
593                         0 : -ENOMEM;
594
595         if (ret) {
596                 kfree_skb(skb);
597                 goto out;
598         }
599
600         /*
601          * XXX: We cannot touch the page and its virtual memory (pkt) after
602          * here. It might have already been freed by the above skb change.
603          */
604
605         iwl_update_stats(priv, false, fc, len);
606         memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
607
608         ieee80211_rx(priv->hw, skb);
609  out:
610         priv->alloc_rxb_page--;
611         rxb->page = NULL;
612 }
613
614 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
615
616 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
617                                 struct iwl_rx_mem_buffer *rxb)
618 {
619         struct ieee80211_hdr *header;
620         struct ieee80211_rx_status rx_status;
621         struct iwl_rx_packet *pkt = rxb_addr(rxb);
622         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
623         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
624         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
625         int snr;
626         u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
627         u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
628         u8 network_packet;
629
630         rx_status.flag = 0;
631         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
632         rx_status.freq =
633                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
634         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
635                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
636
637         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
638         if (rx_status.band == IEEE80211_BAND_5GHZ)
639                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
640
641         rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
642                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
643
644         /* set the preamble flag if appropriate */
645         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
646                 rx_status.flag |= RX_FLAG_SHORTPRE;
647
648         if ((unlikely(rx_stats->phy_count > 20))) {
649                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
650                                 rx_stats->phy_count);
651                 return;
652         }
653
654         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
655             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
656                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
657                 return;
658         }
659
660
661
662         /* Convert 3945's rssi indicator to dBm */
663         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
664
665         /* Set default noise value to -127 */
666         if (priv->last_rx_noise == 0)
667                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
668
669         /* 3945 provides noise info for OFDM frames only.
670          * sig_avg and noise_diff are measured by the 3945's digital signal
671          *   processor (DSP), and indicate linear levels of signal level and
672          *   distortion/noise within the packet preamble after
673          *   automatic gain control (AGC).  sig_avg should stay fairly
674          *   constant if the radio's AGC is working well.
675          * Since these values are linear (not dB or dBm), linear
676          *   signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
677          * Convert linear SNR to dB SNR, then subtract that from rssi dBm
678          *   to obtain noise level in dBm.
679          * Calculate rx_status.signal (quality indicator in %) based on SNR. */
680         if (rx_stats_noise_diff) {
681                 snr = rx_stats_sig_avg / rx_stats_noise_diff;
682                 rx_status.noise = rx_status.signal -
683                                         iwl3945_calc_db_from_ratio(snr);
684                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
685                                                          rx_status.noise);
686
687         /* If noise info not available, calculate signal quality indicator (%)
688          *   using just the dBm signal level. */
689         } else {
690                 rx_status.noise = priv->last_rx_noise;
691                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
692         }
693
694
695         IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
696                         rx_status.signal, rx_status.noise, rx_status.qual,
697                         rx_stats_sig_avg, rx_stats_noise_diff);
698
699         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
700
701         network_packet = iwl3945_is_network_packet(priv, header);
702
703         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
704                               network_packet ? '*' : ' ',
705                               le16_to_cpu(rx_hdr->channel),
706                               rx_status.signal, rx_status.signal,
707                               rx_status.noise, rx_status.rate_idx);
708
709         /* Set "1" to report good data frames in groups of 100 */
710         iwl3945_dbg_report_frame(priv, pkt, header, 1);
711         iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
712
713         if (network_packet) {
714                 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
715                 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
716                 priv->last_rx_rssi = rx_status.signal;
717                 priv->last_rx_noise = rx_status.noise;
718         }
719
720         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
721 }
722
723 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
724                                      struct iwl_tx_queue *txq,
725                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
726 {
727         int count;
728         struct iwl_queue *q;
729         struct iwl3945_tfd *tfd, *tfd_tmp;
730
731         q = &txq->q;
732         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
733         tfd = &tfd_tmp[q->write_ptr];
734
735         if (reset)
736                 memset(tfd, 0, sizeof(*tfd));
737
738         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
739
740         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
741                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
742                           NUM_TFD_CHUNKS);
743                 return -EINVAL;
744         }
745
746         tfd->tbs[count].addr = cpu_to_le32(addr);
747         tfd->tbs[count].len = cpu_to_le32(len);
748
749         count++;
750
751         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
752                                          TFD_CTL_PAD_SET(pad));
753
754         return 0;
755 }
756
757 /**
758  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
759  *
760  * Does NOT advance any indexes
761  */
762 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
763 {
764         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
765         int index = txq->q.read_ptr;
766         struct iwl3945_tfd *tfd = &tfd_tmp[index];
767         struct pci_dev *dev = priv->pci_dev;
768         int i;
769         int counter;
770
771         /* sanity check */
772         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
773         if (counter > NUM_TFD_CHUNKS) {
774                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
775                 /* @todo issue fatal error, it is quite serious situation */
776                 return;
777         }
778
779         /* Unmap tx_cmd */
780         if (counter)
781                 pci_unmap_single(dev,
782                                 pci_unmap_addr(&txq->meta[index], mapping),
783                                 pci_unmap_len(&txq->meta[index], len),
784                                 PCI_DMA_TODEVICE);
785
786         /* unmap chunks if any */
787
788         for (i = 1; i < counter; i++) {
789                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
790                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
791                 if (txq->txb[txq->q.read_ptr].skb[0]) {
792                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
793                         if (txq->txb[txq->q.read_ptr].skb[0]) {
794                                 /* Can be called from interrupt context */
795                                 dev_kfree_skb_any(skb);
796                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
797                         }
798                 }
799         }
800         return ;
801 }
802
803 /**
804  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
805  *
806 */
807 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
808                                   struct iwl_device_cmd *cmd,
809                                   struct ieee80211_tx_info *info,
810                                   struct ieee80211_hdr *hdr,
811                                   int sta_id, int tx_id)
812 {
813         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
814         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
815         u16 rate_mask;
816         int rate;
817         u8 rts_retry_limit;
818         u8 data_retry_limit;
819         __le32 tx_flags;
820         __le16 fc = hdr->frame_control;
821         struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
822
823         rate = iwl3945_rates[rate_index].plcp;
824         tx_flags = tx_cmd->tx_flags;
825
826         /* We need to figure out how to get the sta->supp_rates while
827          * in this running context */
828         rate_mask = IWL_RATES_MASK;
829
830
831         /* Set retry limit on DATA packets and Probe Responses*/
832         if (ieee80211_is_probe_resp(fc))
833                 data_retry_limit = 3;
834         else
835                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
836         tx_cmd->data_retry_limit = data_retry_limit;
837
838         if (tx_id >= IWL_CMD_QUEUE_NUM)
839                 rts_retry_limit = 3;
840         else
841                 rts_retry_limit = 7;
842
843         if (data_retry_limit < rts_retry_limit)
844                 rts_retry_limit = data_retry_limit;
845         tx_cmd->rts_retry_limit = rts_retry_limit;
846
847         if (ieee80211_is_mgmt(fc)) {
848                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
849                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
850                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
851                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
852                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
853                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
854                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
855                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
856                         }
857                         break;
858                 default:
859                         break;
860                 }
861         }
862
863         tx_cmd->rate = rate;
864         tx_cmd->tx_flags = tx_flags;
865
866         /* OFDM */
867         tx_cmd->supp_rates[0] =
868            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
869
870         /* CCK */
871         tx_cmd->supp_rates[1] = (rate_mask & 0xF);
872
873         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
874                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
875                        tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
876                        tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
877 }
878
879 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
880 {
881         unsigned long flags_spin;
882         struct iwl_station_entry *station;
883
884         if (sta_id == IWL_INVALID_STATION)
885                 return IWL_INVALID_STATION;
886
887         spin_lock_irqsave(&priv->sta_lock, flags_spin);
888         station = &priv->stations[sta_id];
889
890         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
891         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
892         station->sta.mode = STA_CONTROL_MODIFY_MSK;
893
894         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
895
896         iwl_send_add_sta(priv, &station->sta, flags);
897         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
898                         sta_id, tx_rate);
899         return sta_id;
900 }
901
902 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
903 {
904         if (src == IWL_PWR_SRC_VAUX) {
905                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
906                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
907                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
908                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
909
910                         iwl_poll_bit(priv, CSR_GPIO_IN,
911                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
912                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
913                 }
914         } else {
915                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
916                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
917                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
918
919                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
920                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
921         }
922
923         return 0;
924 }
925
926 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
927 {
928         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
929         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
930         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
931         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
932                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
933                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
934                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
935                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
936                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
937                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
938                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
939                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
940
941         /* fake read to flush all prev I/O */
942         iwl_read_direct32(priv, FH39_RSSR_CTRL);
943
944         return 0;
945 }
946
947 static int iwl3945_tx_reset(struct iwl_priv *priv)
948 {
949
950         /* bypass mode */
951         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
952
953         /* RA 0 is active */
954         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
955
956         /* all 6 fifo are active */
957         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
958
959         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
960         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
961         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
962         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
963
964         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
965                              priv->shared_phys);
966
967         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
968                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
969                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
970                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
971                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
972                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
973                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
974                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
975
976
977         return 0;
978 }
979
980 /**
981  * iwl3945_txq_ctx_reset - Reset TX queue context
982  *
983  * Destroys all DMA structures and initialize them again
984  */
985 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
986 {
987         int rc;
988         int txq_id, slots_num;
989
990         iwl3945_hw_txq_ctx_free(priv);
991
992         /* allocate tx queue structure */
993         rc = iwl_alloc_txq_mem(priv);
994         if (rc)
995                 return rc;
996
997         /* Tx CMD queue */
998         rc = iwl3945_tx_reset(priv);
999         if (rc)
1000                 goto error;
1001
1002         /* Tx queue(s) */
1003         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1004                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1005                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1006                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1007                                        txq_id);
1008                 if (rc) {
1009                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1010                         goto error;
1011                 }
1012         }
1013
1014         return rc;
1015
1016  error:
1017         iwl3945_hw_txq_ctx_free(priv);
1018         return rc;
1019 }
1020
1021
1022 /*
1023  * Start up 3945's basic functionality after it has been reset
1024  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1025  * NOTE:  This does not load uCode nor start the embedded processor
1026  */
1027 static int iwl3945_apm_init(struct iwl_priv *priv)
1028 {
1029         int ret = iwl_apm_init(priv);
1030
1031         /* Clear APMG (NIC's internal power management) interrupts */
1032         iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1033         iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1034
1035         /* Reset radio chip */
1036         iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1037         udelay(5);
1038         iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1039
1040         return ret;
1041 }
1042
1043 static void iwl3945_nic_config(struct iwl_priv *priv)
1044 {
1045         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1046         unsigned long flags;
1047         u8 rev_id = 0;
1048
1049         spin_lock_irqsave(&priv->lock, flags);
1050
1051         /* Determine HW type */
1052         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1053
1054         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1055
1056         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1057                 IWL_DEBUG_INFO(priv, "RTP type \n");
1058         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1059                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1060                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1061                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1062         } else {
1063                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1064                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1065                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1066         }
1067
1068         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1069                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1070                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1071                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1072         } else
1073                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1074
1075         if ((eeprom->board_revision & 0xF0) == 0xD0) {
1076                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1077                                eeprom->board_revision);
1078                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1079                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1080         } else {
1081                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1082                                eeprom->board_revision);
1083                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1084                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1085         }
1086
1087         if (eeprom->almgor_m_version <= 1) {
1088                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1089                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1090                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1091                                eeprom->almgor_m_version);
1092         } else {
1093                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1094                                eeprom->almgor_m_version);
1095                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1096                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1097         }
1098         spin_unlock_irqrestore(&priv->lock, flags);
1099
1100         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1101                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1102
1103         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1104                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1105 }
1106
1107 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1108 {
1109         int rc;
1110         unsigned long flags;
1111         struct iwl_rx_queue *rxq = &priv->rxq;
1112
1113         spin_lock_irqsave(&priv->lock, flags);
1114         priv->cfg->ops->lib->apm_ops.init(priv);
1115         spin_unlock_irqrestore(&priv->lock, flags);
1116
1117         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1118         if (rc)
1119                 return rc;
1120
1121         priv->cfg->ops->lib->apm_ops.config(priv);
1122
1123         /* Allocate the RX queue, or reset if it is already allocated */
1124         if (!rxq->bd) {
1125                 rc = iwl_rx_queue_alloc(priv);
1126                 if (rc) {
1127                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1128                         return -ENOMEM;
1129                 }
1130         } else
1131                 iwl3945_rx_queue_reset(priv, rxq);
1132
1133         iwl3945_rx_replenish(priv);
1134
1135         iwl3945_rx_init(priv, rxq);
1136
1137
1138         /* Look at using this instead:
1139         rxq->need_update = 1;
1140         iwl_rx_queue_update_write_ptr(priv, rxq);
1141         */
1142
1143         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1144
1145         rc = iwl3945_txq_ctx_reset(priv);
1146         if (rc)
1147                 return rc;
1148
1149         set_bit(STATUS_INIT, &priv->status);
1150
1151         return 0;
1152 }
1153
1154 /**
1155  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1156  *
1157  * Destroy all TX DMA queues and structures
1158  */
1159 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1160 {
1161         int txq_id;
1162
1163         /* Tx queues */
1164         if (priv->txq)
1165                 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1166                      txq_id++)
1167                         if (txq_id == IWL_CMD_QUEUE_NUM)
1168                                 iwl_cmd_queue_free(priv);
1169                         else
1170                                 iwl_tx_queue_free(priv, txq_id);
1171
1172         /* free tx queue structure */
1173         iwl_free_txq_mem(priv);
1174 }
1175
1176 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1177 {
1178         int txq_id;
1179
1180         /* stop SCD */
1181         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1182         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1183
1184         /* reset TFD queues */
1185         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1186                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1187                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1188                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1189                                 1000);
1190         }
1191
1192         iwl3945_hw_txq_ctx_free(priv);
1193 }
1194
1195 /**
1196  * iwl3945_hw_reg_adjust_power_by_temp
1197  * return index delta into power gain settings table
1198 */
1199 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1200 {
1201         return (new_reading - old_reading) * (-11) / 100;
1202 }
1203
1204 /**
1205  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1206  */
1207 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1208 {
1209         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1210 }
1211
1212 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1213 {
1214         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1215 }
1216
1217 /**
1218  * iwl3945_hw_reg_txpower_get_temperature
1219  * get the current temperature by reading from NIC
1220 */
1221 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1222 {
1223         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1224         int temperature;
1225
1226         temperature = iwl3945_hw_get_temperature(priv);
1227
1228         /* driver's okay range is -260 to +25.
1229          *   human readable okay range is 0 to +285 */
1230         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1231
1232         /* handle insane temp reading */
1233         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1234                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1235
1236                 /* if really really hot(?),
1237                  *   substitute the 3rd band/group's temp measured at factory */
1238                 if (priv->last_temperature > 100)
1239                         temperature = eeprom->groups[2].temperature;
1240                 else /* else use most recent "sane" value from driver */
1241                         temperature = priv->last_temperature;
1242         }
1243
1244         return temperature;     /* raw, not "human readable" */
1245 }
1246
1247 /* Adjust Txpower only if temperature variance is greater than threshold.
1248  *
1249  * Both are lower than older versions' 9 degrees */
1250 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1251
1252 /**
1253  * is_temp_calib_needed - determines if new calibration is needed
1254  *
1255  * records new temperature in tx_mgr->temperature.
1256  * replaces tx_mgr->last_temperature *only* if calib needed
1257  *    (assumes caller will actually do the calibration!). */
1258 static int is_temp_calib_needed(struct iwl_priv *priv)
1259 {
1260         int temp_diff;
1261
1262         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1263         temp_diff = priv->temperature - priv->last_temperature;
1264
1265         /* get absolute value */
1266         if (temp_diff < 0) {
1267                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1268                 temp_diff = -temp_diff;
1269         } else if (temp_diff == 0)
1270                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1271         else
1272                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1273
1274         /* if we don't need calibration, *don't* update last_temperature */
1275         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1276                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1277                 return 0;
1278         }
1279
1280         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1281
1282         /* assume that caller will actually do calib ...
1283          *   update the "last temperature" value */
1284         priv->last_temperature = priv->temperature;
1285         return 1;
1286 }
1287
1288 #define IWL_MAX_GAIN_ENTRIES 78
1289 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1290 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1291
1292 /* radio and DSP power table, each step is 1/2 dB.
1293  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1294 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1295         {
1296          {251, 127},            /* 2.4 GHz, highest power */
1297          {251, 127},
1298          {251, 127},
1299          {251, 127},
1300          {251, 125},
1301          {251, 110},
1302          {251, 105},
1303          {251, 98},
1304          {187, 125},
1305          {187, 115},
1306          {187, 108},
1307          {187, 99},
1308          {243, 119},
1309          {243, 111},
1310          {243, 105},
1311          {243, 97},
1312          {243, 92},
1313          {211, 106},
1314          {211, 100},
1315          {179, 120},
1316          {179, 113},
1317          {179, 107},
1318          {147, 125},
1319          {147, 119},
1320          {147, 112},
1321          {147, 106},
1322          {147, 101},
1323          {147, 97},
1324          {147, 91},
1325          {115, 107},
1326          {235, 121},
1327          {235, 115},
1328          {235, 109},
1329          {203, 127},
1330          {203, 121},
1331          {203, 115},
1332          {203, 108},
1333          {203, 102},
1334          {203, 96},
1335          {203, 92},
1336          {171, 110},
1337          {171, 104},
1338          {171, 98},
1339          {139, 116},
1340          {227, 125},
1341          {227, 119},
1342          {227, 113},
1343          {227, 107},
1344          {227, 101},
1345          {227, 96},
1346          {195, 113},
1347          {195, 106},
1348          {195, 102},
1349          {195, 95},
1350          {163, 113},
1351          {163, 106},
1352          {163, 102},
1353          {163, 95},
1354          {131, 113},
1355          {131, 106},
1356          {131, 102},
1357          {131, 95},
1358          {99, 113},
1359          {99, 106},
1360          {99, 102},
1361          {99, 95},
1362          {67, 113},
1363          {67, 106},
1364          {67, 102},
1365          {67, 95},
1366          {35, 113},
1367          {35, 106},
1368          {35, 102},
1369          {35, 95},
1370          {3, 113},
1371          {3, 106},
1372          {3, 102},
1373          {3, 95} },             /* 2.4 GHz, lowest power */
1374         {
1375          {251, 127},            /* 5.x GHz, highest power */
1376          {251, 120},
1377          {251, 114},
1378          {219, 119},
1379          {219, 101},
1380          {187, 113},
1381          {187, 102},
1382          {155, 114},
1383          {155, 103},
1384          {123, 117},
1385          {123, 107},
1386          {123, 99},
1387          {123, 92},
1388          {91, 108},
1389          {59, 125},
1390          {59, 118},
1391          {59, 109},
1392          {59, 102},
1393          {59, 96},
1394          {59, 90},
1395          {27, 104},
1396          {27, 98},
1397          {27, 92},
1398          {115, 118},
1399          {115, 111},
1400          {115, 104},
1401          {83, 126},
1402          {83, 121},
1403          {83, 113},
1404          {83, 105},
1405          {83, 99},
1406          {51, 118},
1407          {51, 111},
1408          {51, 104},
1409          {51, 98},
1410          {19, 116},
1411          {19, 109},
1412          {19, 102},
1413          {19, 98},
1414          {19, 93},
1415          {171, 113},
1416          {171, 107},
1417          {171, 99},
1418          {139, 120},
1419          {139, 113},
1420          {139, 107},
1421          {139, 99},
1422          {107, 120},
1423          {107, 113},
1424          {107, 107},
1425          {107, 99},
1426          {75, 120},
1427          {75, 113},
1428          {75, 107},
1429          {75, 99},
1430          {43, 120},
1431          {43, 113},
1432          {43, 107},
1433          {43, 99},
1434          {11, 120},
1435          {11, 113},
1436          {11, 107},
1437          {11, 99},
1438          {131, 107},
1439          {131, 99},
1440          {99, 120},
1441          {99, 113},
1442          {99, 107},
1443          {99, 99},
1444          {67, 120},
1445          {67, 113},
1446          {67, 107},
1447          {67, 99},
1448          {35, 120},
1449          {35, 113},
1450          {35, 107},
1451          {35, 99},
1452          {3, 120} }             /* 5.x GHz, lowest power */
1453 };
1454
1455 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1456 {
1457         if (index < 0)
1458                 return 0;
1459         if (index >= IWL_MAX_GAIN_ENTRIES)
1460                 return IWL_MAX_GAIN_ENTRIES - 1;
1461         return (u8) index;
1462 }
1463
1464 /* Kick off thermal recalibration check every 60 seconds */
1465 #define REG_RECALIB_PERIOD (60)
1466
1467 /**
1468  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1469  *
1470  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1471  * or 6 Mbit (OFDM) rates.
1472  */
1473 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1474                                s32 rate_index, const s8 *clip_pwrs,
1475                                struct iwl_channel_info *ch_info,
1476                                int band_index)
1477 {
1478         struct iwl3945_scan_power_info *scan_power_info;
1479         s8 power;
1480         u8 power_index;
1481
1482         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1483
1484         /* use this channel group's 6Mbit clipping/saturation pwr,
1485          *   but cap at regulatory scan power restriction (set during init
1486          *   based on eeprom channel data) for this channel.  */
1487         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1488
1489         /* further limit to user's max power preference.
1490          * FIXME:  Other spectrum management power limitations do not
1491          *   seem to apply?? */
1492         power = min(power, priv->tx_power_user_lmt);
1493         scan_power_info->requested_power = power;
1494
1495         /* find difference between new scan *power* and current "normal"
1496          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1497          *   current "normal" temperature-compensated Tx power *index* for
1498          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1499          *   *index*. */
1500         power_index = ch_info->power_info[rate_index].power_table_index
1501             - (power - ch_info->power_info
1502                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1503
1504         /* store reference index that we use when adjusting *all* scan
1505          *   powers.  So we can accommodate user (all channel) or spectrum
1506          *   management (single channel) power changes "between" temperature
1507          *   feedback compensation procedures.
1508          * don't force fit this reference index into gain table; it may be a
1509          *   negative number.  This will help avoid errors when we're at
1510          *   the lower bounds (highest gains, for warmest temperatures)
1511          *   of the table. */
1512
1513         /* don't exceed table bounds for "real" setting */
1514         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1515
1516         scan_power_info->power_table_index = power_index;
1517         scan_power_info->tpc.tx_gain =
1518             power_gain_table[band_index][power_index].tx_gain;
1519         scan_power_info->tpc.dsp_atten =
1520             power_gain_table[band_index][power_index].dsp_atten;
1521 }
1522
1523 /**
1524  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1525  *
1526  * Configures power settings for all rates for the current channel,
1527  * using values from channel info struct, and send to NIC
1528  */
1529 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1530 {
1531         int rate_idx, i;
1532         const struct iwl_channel_info *ch_info = NULL;
1533         struct iwl3945_txpowertable_cmd txpower = {
1534                 .channel = priv->active_rxon.channel,
1535         };
1536
1537         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1538         ch_info = iwl_get_channel_info(priv,
1539                                        priv->band,
1540                                        le16_to_cpu(priv->active_rxon.channel));
1541         if (!ch_info) {
1542                 IWL_ERR(priv,
1543                         "Failed to get channel info for channel %d [%d]\n",
1544                         le16_to_cpu(priv->active_rxon.channel), priv->band);
1545                 return -EINVAL;
1546         }
1547
1548         if (!is_channel_valid(ch_info)) {
1549                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1550                                 "non-Tx channel.\n");
1551                 return 0;
1552         }
1553
1554         /* fill cmd with power settings for all rates for current channel */
1555         /* Fill OFDM rate */
1556         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1557              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1558
1559                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1560                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1561
1562                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1563                                 le16_to_cpu(txpower.channel),
1564                                 txpower.band,
1565                                 txpower.power[i].tpc.tx_gain,
1566                                 txpower.power[i].tpc.dsp_atten,
1567                                 txpower.power[i].rate);
1568         }
1569         /* Fill CCK rates */
1570         for (rate_idx = IWL_FIRST_CCK_RATE;
1571              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1572                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1573                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1574
1575                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1576                                 le16_to_cpu(txpower.channel),
1577                                 txpower.band,
1578                                 txpower.power[i].tpc.tx_gain,
1579                                 txpower.power[i].tpc.dsp_atten,
1580                                 txpower.power[i].rate);
1581         }
1582
1583         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1584                                 sizeof(struct iwl3945_txpowertable_cmd),
1585                                 &txpower);
1586
1587 }
1588
1589 /**
1590  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1591  * @ch_info: Channel to update.  Uses power_info.requested_power.
1592  *
1593  * Replace requested_power and base_power_index ch_info fields for
1594  * one channel.
1595  *
1596  * Called if user or spectrum management changes power preferences.
1597  * Takes into account h/w and modulation limitations (clip power).
1598  *
1599  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1600  *
1601  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1602  *       properly fill out the scan powers, and actual h/w gain settings,
1603  *       and send changes to NIC
1604  */
1605 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1606                              struct iwl_channel_info *ch_info)
1607 {
1608         struct iwl3945_channel_power_info *power_info;
1609         int power_changed = 0;
1610         int i;
1611         const s8 *clip_pwrs;
1612         int power;
1613
1614         /* Get this chnlgrp's rate-to-max/clip-powers table */
1615         clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1616
1617         /* Get this channel's rate-to-current-power settings table */
1618         power_info = ch_info->power_info;
1619
1620         /* update OFDM Txpower settings */
1621         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1622              i++, ++power_info) {
1623                 int delta_idx;
1624
1625                 /* limit new power to be no more than h/w capability */
1626                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1627                 if (power == power_info->requested_power)
1628                         continue;
1629
1630                 /* find difference between old and new requested powers,
1631                  *    update base (non-temp-compensated) power index */
1632                 delta_idx = (power - power_info->requested_power) * 2;
1633                 power_info->base_power_index -= delta_idx;
1634
1635                 /* save new requested power value */
1636                 power_info->requested_power = power;
1637
1638                 power_changed = 1;
1639         }
1640
1641         /* update CCK Txpower settings, based on OFDM 12M setting ...
1642          *    ... all CCK power settings for a given channel are the *same*. */
1643         if (power_changed) {
1644                 power =
1645                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1646                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1647
1648                 /* do all CCK rates' iwl3945_channel_power_info structures */
1649                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1650                         power_info->requested_power = power;
1651                         power_info->base_power_index =
1652                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1653                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1654                         ++power_info;
1655                 }
1656         }
1657
1658         return 0;
1659 }
1660
1661 /**
1662  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1663  *
1664  * NOTE: Returned power limit may be less (but not more) than requested,
1665  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1666  *       (no consideration for h/w clipping limitations).
1667  */
1668 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1669 {
1670         s8 max_power;
1671
1672 #if 0
1673         /* if we're using TGd limits, use lower of TGd or EEPROM */
1674         if (ch_info->tgd_data.max_power != 0)
1675                 max_power = min(ch_info->tgd_data.max_power,
1676                                 ch_info->eeprom.max_power_avg);
1677
1678         /* else just use EEPROM limits */
1679         else
1680 #endif
1681                 max_power = ch_info->eeprom.max_power_avg;
1682
1683         return min(max_power, ch_info->max_power_avg);
1684 }
1685
1686 /**
1687  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1688  *
1689  * Compensate txpower settings of *all* channels for temperature.
1690  * This only accounts for the difference between current temperature
1691  *   and the factory calibration temperatures, and bases the new settings
1692  *   on the channel's base_power_index.
1693  *
1694  * If RxOn is "associated", this sends the new Txpower to NIC!
1695  */
1696 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1697 {
1698         struct iwl_channel_info *ch_info = NULL;
1699         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1700         int delta_index;
1701         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1702         u8 a_band;
1703         u8 rate_index;
1704         u8 scan_tbl_index;
1705         u8 i;
1706         int ref_temp;
1707         int temperature = priv->temperature;
1708
1709         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1710         for (i = 0; i < priv->channel_count; i++) {
1711                 ch_info = &priv->channel_info[i];
1712                 a_band = is_channel_a_band(ch_info);
1713
1714                 /* Get this chnlgrp's factory calibration temperature */
1715                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1716                     temperature;
1717
1718                 /* get power index adjustment based on current and factory
1719                  * temps */
1720                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1721                                                               ref_temp);
1722
1723                 /* set tx power value for all rates, OFDM and CCK */
1724                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1725                      rate_index++) {
1726                         int power_idx =
1727                             ch_info->power_info[rate_index].base_power_index;
1728
1729                         /* temperature compensate */
1730                         power_idx += delta_index;
1731
1732                         /* stay within table range */
1733                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1734                         ch_info->power_info[rate_index].
1735                             power_table_index = (u8) power_idx;
1736                         ch_info->power_info[rate_index].tpc =
1737                             power_gain_table[a_band][power_idx];
1738                 }
1739
1740                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1741                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1742
1743                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1744                 for (scan_tbl_index = 0;
1745                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1746                         s32 actual_index = (scan_tbl_index == 0) ?
1747                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1748                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1749                                            actual_index, clip_pwrs,
1750                                            ch_info, a_band);
1751                 }
1752         }
1753
1754         /* send Txpower command for current channel to ucode */
1755         return priv->cfg->ops->lib->send_tx_power(priv);
1756 }
1757
1758 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1759 {
1760         struct iwl_channel_info *ch_info;
1761         s8 max_power;
1762         u8 a_band;
1763         u8 i;
1764
1765         if (priv->tx_power_user_lmt == power) {
1766                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1767                                 "limit: %ddBm.\n", power);
1768                 return 0;
1769         }
1770
1771         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1772         priv->tx_power_user_lmt = power;
1773
1774         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1775
1776         for (i = 0; i < priv->channel_count; i++) {
1777                 ch_info = &priv->channel_info[i];
1778                 a_band = is_channel_a_band(ch_info);
1779
1780                 /* find minimum power of all user and regulatory constraints
1781                  *    (does not consider h/w clipping limitations) */
1782                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1783                 max_power = min(power, max_power);
1784                 if (max_power != ch_info->curr_txpow) {
1785                         ch_info->curr_txpow = max_power;
1786
1787                         /* this considers the h/w clipping limitations */
1788                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1789                 }
1790         }
1791
1792         /* update txpower settings for all channels,
1793          *   send to NIC if associated. */
1794         is_temp_calib_needed(priv);
1795         iwl3945_hw_reg_comp_txpower_temp(priv);
1796
1797         return 0;
1798 }
1799
1800 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1801 {
1802         int rc = 0;
1803         struct iwl_rx_packet *pkt;
1804         struct iwl3945_rxon_assoc_cmd rxon_assoc;
1805         struct iwl_host_cmd cmd = {
1806                 .id = REPLY_RXON_ASSOC,
1807                 .len = sizeof(rxon_assoc),
1808                 .flags = CMD_WANT_SKB,
1809                 .data = &rxon_assoc,
1810         };
1811         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1812         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1813
1814         if ((rxon1->flags == rxon2->flags) &&
1815             (rxon1->filter_flags == rxon2->filter_flags) &&
1816             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1817             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1818                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1819                 return 0;
1820         }
1821
1822         rxon_assoc.flags = priv->staging_rxon.flags;
1823         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1824         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1825         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1826         rxon_assoc.reserved = 0;
1827
1828         rc = iwl_send_cmd_sync(priv, &cmd);
1829         if (rc)
1830                 return rc;
1831
1832         pkt = (struct iwl_rx_packet *)cmd.reply_page;
1833         if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1834                 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1835                 rc = -EIO;
1836         }
1837
1838         iwl_free_pages(priv, cmd.reply_page);
1839
1840         return rc;
1841 }
1842
1843 /**
1844  * iwl3945_commit_rxon - commit staging_rxon to hardware
1845  *
1846  * The RXON command in staging_rxon is committed to the hardware and
1847  * the active_rxon structure is updated with the new data.  This
1848  * function correctly transitions out of the RXON_ASSOC_MSK state if
1849  * a HW tune is required based on the RXON structure changes.
1850  */
1851 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1852 {
1853         /* cast away the const for active_rxon in this function */
1854         struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1855         struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1856         int rc = 0;
1857         bool new_assoc =
1858                 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1859
1860         if (!iwl_is_alive(priv))
1861                 return -1;
1862
1863         /* always get timestamp with Rx frame */
1864         staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1865
1866         /* select antenna */
1867         staging_rxon->flags &=
1868             ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1869         staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1870
1871         rc = iwl_check_rxon_cmd(priv);
1872         if (rc) {
1873                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
1874                 return -EINVAL;
1875         }
1876
1877         /* If we don't need to send a full RXON, we can use
1878          * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1879          * and other flags for the current radio configuration. */
1880         if (!iwl_full_rxon_required(priv)) {
1881                 rc = iwl_send_rxon_assoc(priv);
1882                 if (rc) {
1883                         IWL_ERR(priv, "Error setting RXON_ASSOC "
1884                                   "configuration (%d).\n", rc);
1885                         return rc;
1886                 }
1887
1888                 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1889
1890                 return 0;
1891         }
1892
1893         /* If we are currently associated and the new config requires
1894          * an RXON_ASSOC and the new config wants the associated mask enabled,
1895          * we must clear the associated from the active configuration
1896          * before we apply the new config */
1897         if (iwl_is_associated(priv) && new_assoc) {
1898                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1899                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1900
1901                 /*
1902                  * reserved4 and 5 could have been filled by the iwlcore code.
1903                  * Let's clear them before pushing to the 3945.
1904                  */
1905                 active_rxon->reserved4 = 0;
1906                 active_rxon->reserved5 = 0;
1907                 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1908                                       sizeof(struct iwl3945_rxon_cmd),
1909                                       &priv->active_rxon);
1910
1911                 /* If the mask clearing failed then we set
1912                  * active_rxon back to what it was previously */
1913                 if (rc) {
1914                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1915                         IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1916                                   "configuration (%d).\n", rc);
1917                         return rc;
1918                 }
1919         }
1920
1921         IWL_DEBUG_INFO(priv, "Sending RXON\n"
1922                        "* with%s RXON_FILTER_ASSOC_MSK\n"
1923                        "* channel = %d\n"
1924                        "* bssid = %pM\n",
1925                        (new_assoc ? "" : "out"),
1926                        le16_to_cpu(staging_rxon->channel),
1927                        staging_rxon->bssid_addr);
1928
1929         /*
1930          * reserved4 and 5 could have been filled by the iwlcore code.
1931          * Let's clear them before pushing to the 3945.
1932          */
1933         staging_rxon->reserved4 = 0;
1934         staging_rxon->reserved5 = 0;
1935
1936         iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1937
1938         /* Apply the new configuration */
1939         rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1940                               sizeof(struct iwl3945_rxon_cmd),
1941                               staging_rxon);
1942         if (rc) {
1943                 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1944                 return rc;
1945         }
1946
1947         memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1948
1949         iwl_clear_stations_table(priv);
1950
1951         /* If we issue a new RXON command which required a tune then we must
1952          * send a new TXPOWER command or we won't be able to Tx any frames */
1953         rc = priv->cfg->ops->lib->send_tx_power(priv);
1954         if (rc) {
1955                 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1956                 return rc;
1957         }
1958
1959         /* Add the broadcast address so we can send broadcast frames */
1960         if (iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL) ==
1961             IWL_INVALID_STATION) {
1962                 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
1963                 return -EIO;
1964         }
1965
1966         /* If we have set the ASSOC_MSK and we are in BSS mode then
1967          * add the IWL_AP_ID to the station rate table */
1968         if (iwl_is_associated(priv) &&
1969             (priv->iw_mode == NL80211_IFTYPE_STATION))
1970                 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
1971                                 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
1972                         IWL_ERR(priv, "Error adding AP address for transmit\n");
1973                         return -EIO;
1974                 }
1975
1976         /* Init the hardware's rate fallback order based on the band */
1977         rc = iwl3945_init_hw_rate_table(priv);
1978         if (rc) {
1979                 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1980                 return -EIO;
1981         }
1982
1983         return 0;
1984 }
1985
1986 /**
1987  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
1988  *
1989  * -- reset periodic timer
1990  * -- see if temp has changed enough to warrant re-calibration ... if so:
1991  *     -- correct coeffs for temp (can reset temp timer)
1992  *     -- save this temp as "last",
1993  *     -- send new set of gain settings to NIC
1994  * NOTE:  This should continue working, even when we're not associated,
1995  *   so we can keep our internal table of scan powers current. */
1996 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1997 {
1998         /* This will kick in the "brute force"
1999          * iwl3945_hw_reg_comp_txpower_temp() below */
2000         if (!is_temp_calib_needed(priv))
2001                 goto reschedule;
2002
2003         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2004          * This is based *only* on current temperature,
2005          * ignoring any previous power measurements */
2006         iwl3945_hw_reg_comp_txpower_temp(priv);
2007
2008  reschedule:
2009         queue_delayed_work(priv->workqueue,
2010                            &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2011 }
2012
2013 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2014 {
2015         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2016                                              thermal_periodic.work);
2017
2018         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2019                 return;
2020
2021         mutex_lock(&priv->mutex);
2022         iwl3945_reg_txpower_periodic(priv);
2023         mutex_unlock(&priv->mutex);
2024 }
2025
2026 /**
2027  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2028  *                                 for the channel.
2029  *
2030  * This function is used when initializing channel-info structs.
2031  *
2032  * NOTE: These channel groups do *NOT* match the bands above!
2033  *       These channel groups are based on factory-tested channels;
2034  *       on A-band, EEPROM's "group frequency" entries represent the top
2035  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
2036  */
2037 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2038                                        const struct iwl_channel_info *ch_info)
2039 {
2040         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2041         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2042         u8 group;
2043         u16 group_index = 0;    /* based on factory calib frequencies */
2044         u8 grp_channel;
2045
2046         /* Find the group index for the channel ... don't use index 1(?) */
2047         if (is_channel_a_band(ch_info)) {
2048                 for (group = 1; group < 5; group++) {
2049                         grp_channel = ch_grp[group].group_channel;
2050                         if (ch_info->channel <= grp_channel) {
2051                                 group_index = group;
2052                                 break;
2053                         }
2054                 }
2055                 /* group 4 has a few channels *above* its factory cal freq */
2056                 if (group == 5)
2057                         group_index = 4;
2058         } else
2059                 group_index = 0;        /* 2.4 GHz, group 0 */
2060
2061         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2062                         group_index);
2063         return group_index;
2064 }
2065
2066 /**
2067  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2068  *
2069  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2070  *   into radio/DSP gain settings table for requested power.
2071  */
2072 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2073                                        s8 requested_power,
2074                                        s32 setting_index, s32 *new_index)
2075 {
2076         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2077         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2078         s32 index0, index1;
2079         s32 power = 2 * requested_power;
2080         s32 i;
2081         const struct iwl3945_eeprom_txpower_sample *samples;
2082         s32 gains0, gains1;
2083         s32 res;
2084         s32 denominator;
2085
2086         chnl_grp = &eeprom->groups[setting_index];
2087         samples = chnl_grp->samples;
2088         for (i = 0; i < 5; i++) {
2089                 if (power == samples[i].power) {
2090                         *new_index = samples[i].gain_index;
2091                         return 0;
2092                 }
2093         }
2094
2095         if (power > samples[1].power) {
2096                 index0 = 0;
2097                 index1 = 1;
2098         } else if (power > samples[2].power) {
2099                 index0 = 1;
2100                 index1 = 2;
2101         } else if (power > samples[3].power) {
2102                 index0 = 2;
2103                 index1 = 3;
2104         } else {
2105                 index0 = 3;
2106                 index1 = 4;
2107         }
2108
2109         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2110         if (denominator == 0)
2111                 return -EINVAL;
2112         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2113         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2114         res = gains0 + (gains1 - gains0) *
2115             ((s32) power - (s32) samples[index0].power) / denominator +
2116             (1 << 18);
2117         *new_index = res >> 19;
2118         return 0;
2119 }
2120
2121 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2122 {
2123         u32 i;
2124         s32 rate_index;
2125         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2126         const struct iwl3945_eeprom_txpower_group *group;
2127
2128         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2129
2130         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2131                 s8 *clip_pwrs;  /* table of power levels for each rate */
2132                 s8 satur_pwr;   /* saturation power for each chnl group */
2133                 group = &eeprom->groups[i];
2134
2135                 /* sanity check on factory saturation power value */
2136                 if (group->saturation_power < 40) {
2137                         IWL_WARN(priv, "Error: saturation power is %d, "
2138                                     "less than minimum expected 40\n",
2139                                     group->saturation_power);
2140                         return;
2141                 }
2142
2143                 /*
2144                  * Derive requested power levels for each rate, based on
2145                  *   hardware capabilities (saturation power for band).
2146                  * Basic value is 3dB down from saturation, with further
2147                  *   power reductions for highest 3 data rates.  These
2148                  *   backoffs provide headroom for high rate modulation
2149                  *   power peaks, without too much distortion (clipping).
2150                  */
2151                 /* we'll fill in this array with h/w max power levels */
2152                 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2153
2154                 /* divide factory saturation power by 2 to find -3dB level */
2155                 satur_pwr = (s8) (group->saturation_power >> 1);
2156
2157                 /* fill in channel group's nominal powers for each rate */
2158                 for (rate_index = 0;
2159                      rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2160                         switch (rate_index) {
2161                         case IWL_RATE_36M_INDEX_TABLE:
2162                                 if (i == 0)     /* B/G */
2163                                         *clip_pwrs = satur_pwr;
2164                                 else    /* A */
2165                                         *clip_pwrs = satur_pwr - 5;
2166                                 break;
2167                         case IWL_RATE_48M_INDEX_TABLE:
2168                                 if (i == 0)
2169                                         *clip_pwrs = satur_pwr - 7;
2170                                 else
2171                                         *clip_pwrs = satur_pwr - 10;
2172                                 break;
2173                         case IWL_RATE_54M_INDEX_TABLE:
2174                                 if (i == 0)
2175                                         *clip_pwrs = satur_pwr - 9;
2176                                 else
2177                                         *clip_pwrs = satur_pwr - 12;
2178                                 break;
2179                         default:
2180                                 *clip_pwrs = satur_pwr;
2181                                 break;
2182                         }
2183                 }
2184         }
2185 }
2186
2187 /**
2188  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2189  *
2190  * Second pass (during init) to set up priv->channel_info
2191  *
2192  * Set up Tx-power settings in our channel info database for each VALID
2193  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2194  * and current temperature.
2195  *
2196  * Since this is based on current temperature (at init time), these values may
2197  * not be valid for very long, but it gives us a starting/default point,
2198  * and allows us to active (i.e. using Tx) scan.
2199  *
2200  * This does *not* write values to NIC, just sets up our internal table.
2201  */
2202 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2203 {
2204         struct iwl_channel_info *ch_info = NULL;
2205         struct iwl3945_channel_power_info *pwr_info;
2206         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2207         int delta_index;
2208         u8 rate_index;
2209         u8 scan_tbl_index;
2210         const s8 *clip_pwrs;    /* array of power levels for each rate */
2211         u8 gain, dsp_atten;
2212         s8 power;
2213         u8 pwr_index, base_pwr_index, a_band;
2214         u8 i;
2215         int temperature;
2216
2217         /* save temperature reference,
2218          *   so we can determine next time to calibrate */
2219         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2220         priv->last_temperature = temperature;
2221
2222         iwl3945_hw_reg_init_channel_groups(priv);
2223
2224         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2225         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2226              i++, ch_info++) {
2227                 a_band = is_channel_a_band(ch_info);
2228                 if (!is_channel_valid(ch_info))
2229                         continue;
2230
2231                 /* find this channel's channel group (*not* "band") index */
2232                 ch_info->group_index =
2233                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2234
2235                 /* Get this chnlgrp's rate->max/clip-powers table */
2236                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2237
2238                 /* calculate power index *adjustment* value according to
2239                  *  diff between current temperature and factory temperature */
2240                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2241                                 eeprom->groups[ch_info->group_index].
2242                                 temperature);
2243
2244                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2245                                 ch_info->channel, delta_index, temperature +
2246                                 IWL_TEMP_CONVERT);
2247
2248                 /* set tx power value for all OFDM rates */
2249                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2250                      rate_index++) {
2251                         s32 uninitialized_var(power_idx);
2252                         int rc;
2253
2254                         /* use channel group's clip-power table,
2255                          *   but don't exceed channel's max power */
2256                         s8 pwr = min(ch_info->max_power_avg,
2257                                      clip_pwrs[rate_index]);
2258
2259                         pwr_info = &ch_info->power_info[rate_index];
2260
2261                         /* get base (i.e. at factory-measured temperature)
2262                          *    power table index for this rate's power */
2263                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2264                                                          ch_info->group_index,
2265                                                          &power_idx);
2266                         if (rc) {
2267                                 IWL_ERR(priv, "Invalid power index\n");
2268                                 return rc;
2269                         }
2270                         pwr_info->base_power_index = (u8) power_idx;
2271
2272                         /* temperature compensate */
2273                         power_idx += delta_index;
2274
2275                         /* stay within range of gain table */
2276                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2277
2278                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2279                         pwr_info->requested_power = pwr;
2280                         pwr_info->power_table_index = (u8) power_idx;
2281                         pwr_info->tpc.tx_gain =
2282                             power_gain_table[a_band][power_idx].tx_gain;
2283                         pwr_info->tpc.dsp_atten =
2284                             power_gain_table[a_band][power_idx].dsp_atten;
2285                 }
2286
2287                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2288                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2289                 power = pwr_info->requested_power +
2290                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2291                 pwr_index = pwr_info->power_table_index +
2292                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2293                 base_pwr_index = pwr_info->base_power_index +
2294                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2295
2296                 /* stay within table range */
2297                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2298                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2299                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2300
2301                 /* fill each CCK rate's iwl3945_channel_power_info structure
2302                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2303                  * NOTE:  CCK rates start at end of OFDM rates! */
2304                 for (rate_index = 0;
2305                      rate_index < IWL_CCK_RATES; rate_index++) {
2306                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2307                         pwr_info->requested_power = power;
2308                         pwr_info->power_table_index = pwr_index;
2309                         pwr_info->base_power_index = base_pwr_index;
2310                         pwr_info->tpc.tx_gain = gain;
2311                         pwr_info->tpc.dsp_atten = dsp_atten;
2312                 }
2313
2314                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2315                 for (scan_tbl_index = 0;
2316                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2317                         s32 actual_index = (scan_tbl_index == 0) ?
2318                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2319                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2320                                 actual_index, clip_pwrs, ch_info, a_band);
2321                 }
2322         }
2323
2324         return 0;
2325 }
2326
2327 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2328 {
2329         int rc;
2330
2331         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2332         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2333                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2334         if (rc < 0)
2335                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2336
2337         return 0;
2338 }
2339
2340 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2341 {
2342         int txq_id = txq->q.id;
2343
2344         struct iwl3945_shared *shared_data = priv->shared_virt;
2345
2346         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2347
2348         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2349         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2350
2351         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2352                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2353                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2354                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2355                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2356                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2357
2358         /* fake read to flush all prev. writes */
2359         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2360
2361         return 0;
2362 }
2363
2364 /*
2365  * HCMD utils
2366  */
2367 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2368 {
2369         switch (cmd_id) {
2370         case REPLY_RXON:
2371                 return sizeof(struct iwl3945_rxon_cmd);
2372         case POWER_TABLE_CMD:
2373                 return sizeof(struct iwl3945_powertable_cmd);
2374         default:
2375                 return len;
2376         }
2377 }
2378
2379
2380 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2381 {
2382         struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2383         addsta->mode = cmd->mode;
2384         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2385         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2386         addsta->station_flags = cmd->station_flags;
2387         addsta->station_flags_msk = cmd->station_flags_msk;
2388         addsta->tid_disable_tx = cpu_to_le16(0);
2389         addsta->rate_n_flags = cmd->rate_n_flags;
2390         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2391         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2392         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2393
2394         return (u16)sizeof(struct iwl3945_addsta_cmd);
2395 }
2396
2397
2398 /**
2399  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2400  */
2401 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2402 {
2403         int rc, i, index, prev_index;
2404         struct iwl3945_rate_scaling_cmd rate_cmd = {
2405                 .reserved = {0, 0, 0},
2406         };
2407         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2408
2409         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2410                 index = iwl3945_rates[i].table_rs_index;
2411
2412                 table[index].rate_n_flags =
2413                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2414                 table[index].try_cnt = priv->retry_rate;
2415                 prev_index = iwl3945_get_prev_ieee_rate(i);
2416                 table[index].next_rate_index =
2417                                 iwl3945_rates[prev_index].table_rs_index;
2418         }
2419
2420         switch (priv->band) {
2421         case IEEE80211_BAND_5GHZ:
2422                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2423                 /* If one of the following CCK rates is used,
2424                  * have it fall back to the 6M OFDM rate */
2425                 for (i = IWL_RATE_1M_INDEX_TABLE;
2426                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2427                         table[i].next_rate_index =
2428                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2429
2430                 /* Don't fall back to CCK rates */
2431                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2432                                                 IWL_RATE_9M_INDEX_TABLE;
2433
2434                 /* Don't drop out of OFDM rates */
2435                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2436                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2437                 break;
2438
2439         case IEEE80211_BAND_2GHZ:
2440                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2441                 /* If an OFDM rate is used, have it fall back to the
2442                  * 1M CCK rates */
2443
2444                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2445                     iwl_is_associated(priv)) {
2446
2447                         index = IWL_FIRST_CCK_RATE;
2448                         for (i = IWL_RATE_6M_INDEX_TABLE;
2449                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2450                                 table[i].next_rate_index =
2451                                         iwl3945_rates[index].table_rs_index;
2452
2453                         index = IWL_RATE_11M_INDEX_TABLE;
2454                         /* CCK shouldn't fall back to OFDM... */
2455                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2456                 }
2457                 break;
2458
2459         default:
2460                 WARN_ON(1);
2461                 break;
2462         }
2463
2464         /* Update the rate scaling for control frame Tx */
2465         rate_cmd.table_id = 0;
2466         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2467                               &rate_cmd);
2468         if (rc)
2469                 return rc;
2470
2471         /* Update the rate scaling for data frame Tx */
2472         rate_cmd.table_id = 1;
2473         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2474                                 &rate_cmd);
2475 }
2476
2477 /* Called when initializing driver */
2478 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2479 {
2480         memset((void *)&priv->hw_params, 0,
2481                sizeof(struct iwl_hw_params));
2482
2483         priv->shared_virt =
2484             pci_alloc_consistent(priv->pci_dev,
2485                                  sizeof(struct iwl3945_shared),
2486                                  &priv->shared_phys);
2487
2488         if (!priv->shared_virt) {
2489                 IWL_ERR(priv, "failed to allocate pci memory\n");
2490                 mutex_unlock(&priv->mutex);
2491                 return -ENOMEM;
2492         }
2493
2494         /* Assign number of Usable TX queues */
2495         priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
2496
2497         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2498         priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2499         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2500         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2501         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2502         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2503
2504         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2505         priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2506
2507         return 0;
2508 }
2509
2510 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2511                           struct iwl3945_frame *frame, u8 rate)
2512 {
2513         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2514         unsigned int frame_size;
2515
2516         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2517         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2518
2519         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2520         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2521
2522         frame_size = iwl3945_fill_beacon_frame(priv,
2523                                 tx_beacon_cmd->frame,
2524                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2525
2526         BUG_ON(frame_size > MAX_MPDU_SIZE);
2527         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2528
2529         tx_beacon_cmd->tx.rate = rate;
2530         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2531                                       TX_CMD_FLG_TSF_MSK);
2532
2533         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2534         tx_beacon_cmd->tx.supp_rates[0] =
2535                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2536
2537         tx_beacon_cmd->tx.supp_rates[1] =
2538                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2539
2540         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2541 }
2542
2543 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2544 {
2545         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2546         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2547 }
2548
2549 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2550 {
2551         INIT_DELAYED_WORK(&priv->thermal_periodic,
2552                           iwl3945_bg_reg_txpower_periodic);
2553 }
2554
2555 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2556 {
2557         cancel_delayed_work(&priv->thermal_periodic);
2558 }
2559
2560 /* check contents of special bootstrap uCode SRAM */
2561 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2562  {
2563         __le32 *image = priv->ucode_boot.v_addr;
2564         u32 len = priv->ucode_boot.len;
2565         u32 reg;
2566         u32 val;
2567
2568         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2569
2570         /* verify BSM SRAM contents */
2571         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2572         for (reg = BSM_SRAM_LOWER_BOUND;
2573              reg < BSM_SRAM_LOWER_BOUND + len;
2574              reg += sizeof(u32), image++) {
2575                 val = iwl_read_prph(priv, reg);
2576                 if (val != le32_to_cpu(*image)) {
2577                         IWL_ERR(priv, "BSM uCode verification failed at "
2578                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2579                                   BSM_SRAM_LOWER_BOUND,
2580                                   reg - BSM_SRAM_LOWER_BOUND, len,
2581                                   val, le32_to_cpu(*image));
2582                         return -EIO;
2583                 }
2584         }
2585
2586         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2587
2588         return 0;
2589 }
2590
2591
2592 /******************************************************************************
2593  *
2594  * EEPROM related functions
2595  *
2596  ******************************************************************************/
2597
2598 /*
2599  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2600  * embedded controller) as EEPROM reader; each read is a series of pulses
2601  * to/from the EEPROM chip, not a single event, so even reads could conflict
2602  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2603  * simply claims ownership, which should be safe when this function is called
2604  * (i.e. before loading uCode!).
2605  */
2606 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2607 {
2608         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2609         return 0;
2610 }
2611
2612
2613 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2614 {
2615         return;
2616 }
2617
2618  /**
2619   * iwl3945_load_bsm - Load bootstrap instructions
2620   *
2621   * BSM operation:
2622   *
2623   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2624   * in special SRAM that does not power down during RFKILL.  When powering back
2625   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2626   * the bootstrap program into the on-board processor, and starts it.
2627   *
2628   * The bootstrap program loads (via DMA) instructions and data for a new
2629   * program from host DRAM locations indicated by the host driver in the
2630   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2631   * automatically.
2632   *
2633   * When initializing the NIC, the host driver points the BSM to the
2634   * "initialize" uCode image.  This uCode sets up some internal data, then
2635   * notifies host via "initialize alive" that it is complete.
2636   *
2637   * The host then replaces the BSM_DRAM_* pointer values to point to the
2638   * normal runtime uCode instructions and a backup uCode data cache buffer
2639   * (filled initially with starting data values for the on-board processor),
2640   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2641   * which begins normal operation.
2642   *
2643   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2644   * the backup data cache in DRAM before SRAM is powered down.
2645   *
2646   * When powering back up, the BSM loads the bootstrap program.  This reloads
2647   * the runtime uCode instructions and the backup data cache into SRAM,
2648   * and re-launches the runtime uCode from where it left off.
2649   */
2650 static int iwl3945_load_bsm(struct iwl_priv *priv)
2651 {
2652         __le32 *image = priv->ucode_boot.v_addr;
2653         u32 len = priv->ucode_boot.len;
2654         dma_addr_t pinst;
2655         dma_addr_t pdata;
2656         u32 inst_len;
2657         u32 data_len;
2658         int rc;
2659         int i;
2660         u32 done;
2661         u32 reg_offset;
2662
2663         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2664
2665         /* make sure bootstrap program is no larger than BSM's SRAM size */
2666         if (len > IWL39_MAX_BSM_SIZE)
2667                 return -EINVAL;
2668
2669         /* Tell bootstrap uCode where to find the "Initialize" uCode
2670         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2671         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2672         *        after the "initialize" uCode has run, to point to
2673         *        runtime/protocol instructions and backup data cache. */
2674         pinst = priv->ucode_init.p_addr;
2675         pdata = priv->ucode_init_data.p_addr;
2676         inst_len = priv->ucode_init.len;
2677         data_len = priv->ucode_init_data.len;
2678
2679         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2680         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2681         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2682         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2683
2684         /* Fill BSM memory with bootstrap instructions */
2685         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2686              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2687              reg_offset += sizeof(u32), image++)
2688                 _iwl_write_prph(priv, reg_offset,
2689                                           le32_to_cpu(*image));
2690
2691         rc = iwl3945_verify_bsm(priv);
2692         if (rc)
2693                 return rc;
2694
2695         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2696         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2697         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2698                                  IWL39_RTC_INST_LOWER_BOUND);
2699         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2700
2701         /* Load bootstrap code into instruction SRAM now,
2702          *   to prepare to load "initialize" uCode */
2703         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2704                 BSM_WR_CTRL_REG_BIT_START);
2705
2706         /* Wait for load of bootstrap uCode to finish */
2707         for (i = 0; i < 100; i++) {
2708                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2709                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2710                         break;
2711                 udelay(10);
2712         }
2713         if (i < 100)
2714                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2715         else {
2716                 IWL_ERR(priv, "BSM write did not complete!\n");
2717                 return -EIO;
2718         }
2719
2720         /* Enable future boot loads whenever power management unit triggers it
2721          *   (e.g. when powering back up after power-save shutdown) */
2722         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2723                 BSM_WR_CTRL_REG_BIT_START_EN);
2724
2725         return 0;
2726 }
2727
2728 #define IWL3945_UCODE_GET(item)                                         \
2729 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2730                                     u32 api_ver)                        \
2731 {                                                                       \
2732         return le32_to_cpu(ucode->u.v1.item);                           \
2733 }
2734
2735 static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2736 {
2737         return UCODE_HEADER_SIZE(1);
2738 }
2739 static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2740                                    u32 api_ver)
2741 {
2742         return 0;
2743 }
2744 static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2745                                   u32 api_ver)
2746 {
2747         return (u8 *) ucode->u.v1.data;
2748 }
2749
2750 IWL3945_UCODE_GET(inst_size);
2751 IWL3945_UCODE_GET(data_size);
2752 IWL3945_UCODE_GET(init_size);
2753 IWL3945_UCODE_GET(init_data_size);
2754 IWL3945_UCODE_GET(boot_size);
2755
2756 static struct iwl_hcmd_ops iwl3945_hcmd = {
2757         .rxon_assoc = iwl3945_send_rxon_assoc,
2758         .commit_rxon = iwl3945_commit_rxon,
2759 };
2760
2761 static struct iwl_ucode_ops iwl3945_ucode = {
2762         .get_header_size = iwl3945_ucode_get_header_size,
2763         .get_build = iwl3945_ucode_get_build,
2764         .get_inst_size = iwl3945_ucode_get_inst_size,
2765         .get_data_size = iwl3945_ucode_get_data_size,
2766         .get_init_size = iwl3945_ucode_get_init_size,
2767         .get_init_data_size = iwl3945_ucode_get_init_data_size,
2768         .get_boot_size = iwl3945_ucode_get_boot_size,
2769         .get_data = iwl3945_ucode_get_data,
2770 };
2771
2772 static struct iwl_lib_ops iwl3945_lib = {
2773         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2774         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2775         .txq_init = iwl3945_hw_tx_queue_init,
2776         .load_ucode = iwl3945_load_bsm,
2777         .dump_nic_event_log = iwl3945_dump_nic_event_log,
2778         .dump_nic_error_log = iwl3945_dump_nic_error_log,
2779         .apm_ops = {
2780                 .init = iwl3945_apm_init,
2781                 .stop = iwl_apm_stop,
2782                 .config = iwl3945_nic_config,
2783                 .set_pwr_src = iwl3945_set_pwr_src,
2784         },
2785         .eeprom_ops = {
2786                 .regulatory_bands = {
2787                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2788                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2789                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2790                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2791                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2792                         EEPROM_REGULATORY_BAND_NO_HT40,
2793                         EEPROM_REGULATORY_BAND_NO_HT40,
2794                 },
2795                 .verify_signature  = iwlcore_eeprom_verify_signature,
2796                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2797                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2798                 .query_addr = iwlcore_eeprom_query_addr,
2799         },
2800         .send_tx_power  = iwl3945_send_tx_power,
2801         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2802         .post_associate = iwl3945_post_associate,
2803         .isr = iwl_isr_legacy,
2804         .config_ap = iwl3945_config_ap,
2805 };
2806
2807 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2808         .get_hcmd_size = iwl3945_get_hcmd_size,
2809         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2810         .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2811 };
2812
2813 static const struct iwl_ops iwl3945_ops = {
2814         .ucode = &iwl3945_ucode,
2815         .lib = &iwl3945_lib,
2816         .hcmd = &iwl3945_hcmd,
2817         .utils = &iwl3945_hcmd_utils,
2818         .led = &iwl3945_led_ops,
2819 };
2820
2821 static struct iwl_cfg iwl3945_bg_cfg = {
2822         .name = "3945BG",
2823         .fw_name_pre = IWL3945_FW_PRE,
2824         .ucode_api_max = IWL3945_UCODE_API_MAX,
2825         .ucode_api_min = IWL3945_UCODE_API_MIN,
2826         .sku = IWL_SKU_G,
2827         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2828         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2829         .ops = &iwl3945_ops,
2830         .num_of_queues = IWL39_NUM_QUEUES,
2831         .mod_params = &iwl3945_mod_params,
2832         .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2833         .set_l0s = false,
2834         .use_bsm = true,
2835         .use_isr_legacy = true,
2836         .ht_greenfield_support = false,
2837         .led_compensation = 64,
2838         .broken_powersave = true,
2839 };
2840
2841 static struct iwl_cfg iwl3945_abg_cfg = {
2842         .name = "3945ABG",
2843         .fw_name_pre = IWL3945_FW_PRE,
2844         .ucode_api_max = IWL3945_UCODE_API_MAX,
2845         .ucode_api_min = IWL3945_UCODE_API_MIN,
2846         .sku = IWL_SKU_A|IWL_SKU_G,
2847         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2848         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2849         .ops = &iwl3945_ops,
2850         .num_of_queues = IWL39_NUM_QUEUES,
2851         .mod_params = &iwl3945_mod_params,
2852         .use_isr_legacy = true,
2853         .ht_greenfield_support = false,
2854         .led_compensation = 64,
2855         .broken_powersave = true,
2856 };
2857
2858 struct pci_device_id iwl3945_hw_card_ids[] = {
2859         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2860         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2861         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2862         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2863         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2864         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2865         {0}
2866 };
2867
2868 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);