89b874ca6107c8a6fcf3a96b99c002ee83f250fa
[kernel.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
1 /*
2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt2400pci
23         Abstract: rt2400pci device specific routines.
24         Supported chipsets: RT2460.
25  */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
38
39 /*
40  * Register access.
41  * All access to the CSR registers will go through the methods
42  * rt2x00pci_register_read and rt2x00pci_register_write.
43  * BBP and RF register require indirect register access,
44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
45  * These indirect registers work with busy bits,
46  * and we will try maximal REGISTER_BUSY_COUNT times to access
47  * the register while taking a REGISTER_BUSY_DELAY us delay
48  * between each attampt. When the busy bit is still set at that time,
49  * the access attempt is considered to have failed,
50  * and we will print an error.
51  */
52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
53 {
54         u32 reg;
55         unsigned int i;
56
57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60                         break;
61                 udelay(REGISTER_BUSY_DELAY);
62         }
63
64         return reg;
65 }
66
67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68                                 const unsigned int word, const u8 value)
69 {
70         u32 reg;
71
72         /*
73          * Wait until the BBP becomes ready.
74          */
75         reg = rt2400pci_bbp_check(rt2x00dev);
76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78                 return;
79         }
80
81         /*
82          * Write the data into the BBP.
83          */
84         reg = 0;
85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91 }
92
93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
94                                const unsigned int word, u8 *value)
95 {
96         u32 reg;
97
98         /*
99          * Wait until the BBP becomes ready.
100          */
101         reg = rt2400pci_bbp_check(rt2x00dev);
102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104                 return;
105         }
106
107         /*
108          * Write the request into the BBP.
109          */
110         reg = 0;
111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117         /*
118          * Wait until the BBP becomes ready.
119          */
120         reg = rt2400pci_bbp_check(rt2x00dev);
121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123                 *value = 0xff;
124                 return;
125         }
126
127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128 }
129
130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
131                                const unsigned int word, const u32 value)
132 {
133         u32 reg;
134         unsigned int i;
135
136         if (!word)
137                 return;
138
139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142                         goto rf_write;
143                 udelay(REGISTER_BUSY_DELAY);
144         }
145
146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147         return;
148
149 rf_write:
150         reg = 0;
151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157         rt2x00_rf_write(rt2x00dev, word, value);
158 }
159
160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161 {
162         struct rt2x00_dev *rt2x00dev = eeprom->data;
163         u32 reg;
164
165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169         eeprom->reg_data_clock =
170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171         eeprom->reg_chip_select =
172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173 }
174
175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176 {
177         struct rt2x00_dev *rt2x00dev = eeprom->data;
178         u32 reg = 0;
179
180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183                            !!eeprom->reg_data_clock);
184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185                            !!eeprom->reg_chip_select);
186
187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188 }
189
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
193 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
194                                const unsigned int word, u32 *data)
195 {
196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197 }
198
199 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
200                                 const unsigned int word, u32 data)
201 {
202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203 }
204
205 static const struct rt2x00debug rt2400pci_rt2x00debug = {
206         .owner  = THIS_MODULE,
207         .csr    = {
208                 .read           = rt2400pci_read_csr,
209                 .write          = rt2400pci_write_csr,
210                 .word_size      = sizeof(u32),
211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
212         },
213         .eeprom = {
214                 .read           = rt2x00_eeprom_read,
215                 .write          = rt2x00_eeprom_write,
216                 .word_size      = sizeof(u16),
217                 .word_count     = EEPROM_SIZE / sizeof(u16),
218         },
219         .bbp    = {
220                 .read           = rt2400pci_bbp_read,
221                 .write          = rt2400pci_bbp_write,
222                 .word_size      = sizeof(u8),
223                 .word_count     = BBP_SIZE / sizeof(u8),
224         },
225         .rf     = {
226                 .read           = rt2x00_rf_read,
227                 .write          = rt2400pci_rf_write,
228                 .word_size      = sizeof(u32),
229                 .word_count     = RF_SIZE / sizeof(u32),
230         },
231 };
232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234 #ifdef CONFIG_RT2400PCI_RFKILL
235 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236 {
237         u32 reg;
238
239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241 }
242 #else
243 #define rt2400pci_rfkill_poll   NULL
244 #endif /* CONFIG_RT2400PCI_RFKILL */
245
246 #ifdef CONFIG_RT2400PCI_LEDS
247 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
248                                      enum led_brightness brightness)
249 {
250         struct rt2x00_led *led =
251             container_of(led_cdev, struct rt2x00_led, led_dev);
252         unsigned int enabled = brightness != LED_OFF;
253         u32 reg;
254
255         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
256
257         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
258                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
259         else if (led->type == LED_TYPE_ACTIVITY)
260                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
261
262         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
263 }
264
265 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
266                                unsigned long *delay_on,
267                                unsigned long *delay_off)
268 {
269         struct rt2x00_led *led =
270             container_of(led_cdev, struct rt2x00_led, led_dev);
271         u32 reg;
272
273         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
274         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
275         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
276         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
277
278         return 0;
279 }
280
281 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
282                                struct rt2x00_led *led,
283                                enum led_type type)
284 {
285         led->rt2x00dev = rt2x00dev;
286         led->type = type;
287         led->led_dev.brightness_set = rt2400pci_brightness_set;
288         led->led_dev.blink_set = rt2400pci_blink_set;
289         led->flags = LED_INITIALIZED;
290 }
291 #endif /* CONFIG_RT2400PCI_LEDS */
292
293 /*
294  * Configuration handlers.
295  */
296 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
297                                     const unsigned int filter_flags)
298 {
299         u32 reg;
300
301         /*
302          * Start configuration steps.
303          * Note that the version error will always be dropped
304          * since there is no filter for it at this time.
305          */
306         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
307         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
308                            !(filter_flags & FIF_FCSFAIL));
309         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
310                            !(filter_flags & FIF_PLCPFAIL));
311         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
312                            !(filter_flags & FIF_CONTROL));
313         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
314                            !(filter_flags & FIF_PROMISC_IN_BSS));
315         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
316                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
317                            !rt2x00dev->intf_ap_count);
318         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
319         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
320 }
321
322 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
323                                   struct rt2x00_intf *intf,
324                                   struct rt2x00intf_conf *conf,
325                                   const unsigned int flags)
326 {
327         unsigned int bcn_preload;
328         u32 reg;
329
330         if (flags & CONFIG_UPDATE_TYPE) {
331                 /*
332                  * Enable beacon config
333                  */
334                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
335                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
336                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
337                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
338
339                 /*
340                  * Enable synchronisation.
341                  */
342                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
343                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
344                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
345                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
346                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
347         }
348
349         if (flags & CONFIG_UPDATE_MAC)
350                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
351                                               conf->mac, sizeof(conf->mac));
352
353         if (flags & CONFIG_UPDATE_BSSID)
354                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
355                                               conf->bssid, sizeof(conf->bssid));
356 }
357
358 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
359                                  struct rt2x00lib_erp *erp)
360 {
361         int preamble_mask;
362         u32 reg;
363
364         /*
365          * When short preamble is enabled, we should set bit 0x08
366          */
367         preamble_mask = erp->short_preamble << 3;
368
369         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
370         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
371                            erp->ack_timeout);
372         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
373                            erp->ack_consume_time);
374         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
375
376         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
377         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
378         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
379         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
380         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
381
382         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
383         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
384         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
385         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
386         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
387
388         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
389         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
390         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
391         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
392         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
393
394         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
395         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
396         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
397         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
398         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
399 }
400
401 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
402                                      const int basic_rate_mask)
403 {
404         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
405 }
406
407 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
408                                      struct rf_channel *rf)
409 {
410         /*
411          * Switch on tuning bits.
412          */
413         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
414         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
415
416         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
417         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
418         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
419
420         /*
421          * RF2420 chipset don't need any additional actions.
422          */
423         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
424                 return;
425
426         /*
427          * For the RT2421 chipsets we need to write an invalid
428          * reference clock rate to activate auto_tune.
429          * After that we set the value back to the correct channel.
430          */
431         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
432         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
433         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
434
435         msleep(1);
436
437         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
438         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
439         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
440
441         msleep(1);
442
443         /*
444          * Switch off tuning bits.
445          */
446         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
447         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
448
449         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
450         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
451
452         /*
453          * Clear false CRC during channel switch.
454          */
455         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
456 }
457
458 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
459 {
460         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
461 }
462
463 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
464                                      struct antenna_setup *ant)
465 {
466         u8 r1;
467         u8 r4;
468
469         /*
470          * We should never come here because rt2x00lib is supposed
471          * to catch this and send us the correct antenna explicitely.
472          */
473         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
474                ant->tx == ANTENNA_SW_DIVERSITY);
475
476         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
477         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
478
479         /*
480          * Configure the TX antenna.
481          */
482         switch (ant->tx) {
483         case ANTENNA_HW_DIVERSITY:
484                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
485                 break;
486         case ANTENNA_A:
487                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
488                 break;
489         case ANTENNA_B:
490         default:
491                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
492                 break;
493         }
494
495         /*
496          * Configure the RX antenna.
497          */
498         switch (ant->rx) {
499         case ANTENNA_HW_DIVERSITY:
500                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
501                 break;
502         case ANTENNA_A:
503                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
504                 break;
505         case ANTENNA_B:
506         default:
507                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
508                 break;
509         }
510
511         rt2400pci_bbp_write(rt2x00dev, 4, r4);
512         rt2400pci_bbp_write(rt2x00dev, 1, r1);
513 }
514
515 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
516                                       struct rt2x00lib_conf *libconf)
517 {
518         u32 reg;
519
520         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
521         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
522         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
523
524         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
525         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
526         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
527         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
528
529         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
530         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
531         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
532         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
533
534         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
535         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
536         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
537         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
538
539         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
540         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
541                            libconf->conf->beacon_int * 16);
542         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
543                            libconf->conf->beacon_int * 16);
544         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
545 }
546
547 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
548                              struct rt2x00lib_conf *libconf,
549                              const unsigned int flags)
550 {
551         if (flags & CONFIG_UPDATE_PHYMODE)
552                 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
553         if (flags & CONFIG_UPDATE_CHANNEL)
554                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
555         if (flags & CONFIG_UPDATE_TXPOWER)
556                 rt2400pci_config_txpower(rt2x00dev,
557                                          libconf->conf->power_level);
558         if (flags & CONFIG_UPDATE_ANTENNA)
559                 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
560         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
561                 rt2400pci_config_duration(rt2x00dev, libconf);
562 }
563
564 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
565                                 const int cw_min, const int cw_max)
566 {
567         u32 reg;
568
569         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
570         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
571         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
572         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
573 }
574
575 /*
576  * Link tuning
577  */
578 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
579                                  struct link_qual *qual)
580 {
581         u32 reg;
582         u8 bbp;
583
584         /*
585          * Update FCS error count from register.
586          */
587         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
588         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
589
590         /*
591          * Update False CCA count from register.
592          */
593         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
594         qual->false_cca = bbp;
595 }
596
597 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
598 {
599         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
600         rt2x00dev->link.vgc_level = 0x08;
601 }
602
603 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
604 {
605         u8 reg;
606
607         /*
608          * The link tuner should not run longer then 60 seconds,
609          * and should run once every 2 seconds.
610          */
611         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
612                 return;
613
614         /*
615          * Base r13 link tuning on the false cca count.
616          */
617         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
618
619         if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
620                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
621                 rt2x00dev->link.vgc_level = reg;
622         } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
623                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
624                 rt2x00dev->link.vgc_level = reg;
625         }
626 }
627
628 /*
629  * Initialization functions.
630  */
631 static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
632                                    struct queue_entry *entry)
633 {
634         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
635         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
636         u32 word;
637
638         rt2x00_desc_read(entry_priv->desc, 2, &word);
639         rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
640         rt2x00_desc_write(entry_priv->desc, 2, word);
641
642         rt2x00_desc_read(entry_priv->desc, 1, &word);
643         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
644         rt2x00_desc_write(entry_priv->desc, 1, word);
645
646         rt2x00_desc_read(entry_priv->desc, 0, &word);
647         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
648         rt2x00_desc_write(entry_priv->desc, 0, word);
649 }
650
651 static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
652                                    struct queue_entry *entry)
653 {
654         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
655         u32 word;
656
657         rt2x00_desc_read(entry_priv->desc, 0, &word);
658         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
659         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
660         rt2x00_desc_write(entry_priv->desc, 0, word);
661 }
662
663 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
664 {
665         struct queue_entry_priv_pci *entry_priv;
666         u32 reg;
667
668         /*
669          * Initialize registers.
670          */
671         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
672         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
673         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
674         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
675         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
676         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
677
678         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
679         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
680         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
681                            entry_priv->desc_dma);
682         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
683
684         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
685         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
686         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
687                            entry_priv->desc_dma);
688         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
689
690         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
691         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
692         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
693                            entry_priv->desc_dma);
694         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
695
696         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
697         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
698         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
699                            entry_priv->desc_dma);
700         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
701
702         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
703         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
704         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
705         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
706
707         entry_priv = rt2x00dev->rx->entries[0].priv_data;
708         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
709         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
710                            entry_priv->desc_dma);
711         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
712
713         return 0;
714 }
715
716 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
717 {
718         u32 reg;
719
720         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
721         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
722         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
723         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
724
725         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
726         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
727         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
728         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
729         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
730
731         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
732         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
733                            (rt2x00dev->rx->data_size / 128));
734         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
735
736         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
737
738         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
739         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
740         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
741         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
742         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
743         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
744
745         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
746         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
747         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
748         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
749         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
750         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
751         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
752         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
753
754         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
755
756         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
757                 return -EBUSY;
758
759         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
760         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
761
762         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
763         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
764         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
765
766         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
767         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
768         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
769         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
770         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
771         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
772
773         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
774         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
775         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
776         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
777         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
778
779         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
780         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
781         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
782         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
783
784         /*
785          * We must clear the FCS and FIFO error count.
786          * These registers are cleared on read,
787          * so we may pass a useless variable to store the value.
788          */
789         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
790         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
791
792         return 0;
793 }
794
795 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
796 {
797         unsigned int i;
798         u8 value;
799
800         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
801                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
802                 if ((value != 0xff) && (value != 0x00))
803                         return 0;
804                 udelay(REGISTER_BUSY_DELAY);
805         }
806
807         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
808         return -EACCES;
809 }
810
811 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
812 {
813         unsigned int i;
814         u16 eeprom;
815         u8 reg_id;
816         u8 value;
817
818         if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
819                 return -EACCES;
820
821         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
822         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
823         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
824         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
825         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
826         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
827         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
828         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
829         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
830         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
831         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
832         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
833         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
834         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
835
836         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
837                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
838
839                 if (eeprom != 0xffff && eeprom != 0x0000) {
840                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
841                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
842                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
843                 }
844         }
845
846         return 0;
847 }
848
849 /*
850  * Device state switch handlers.
851  */
852 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
853                                 enum dev_state state)
854 {
855         u32 reg;
856
857         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
858         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
859                            (state == STATE_RADIO_RX_OFF) ||
860                            (state == STATE_RADIO_RX_OFF_LINK));
861         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
862 }
863
864 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
865                                  enum dev_state state)
866 {
867         int mask = (state == STATE_RADIO_IRQ_OFF);
868         u32 reg;
869
870         /*
871          * When interrupts are being enabled, the interrupt registers
872          * should clear the register to assure a clean state.
873          */
874         if (state == STATE_RADIO_IRQ_ON) {
875                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
876                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
877         }
878
879         /*
880          * Only toggle the interrupts bits we are going to use.
881          * Non-checked interrupt bits are disabled by default.
882          */
883         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
884         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
885         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
886         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
887         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
888         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
889         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
890 }
891
892 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
893 {
894         /*
895          * Initialize all registers.
896          */
897         if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
898                      rt2400pci_init_registers(rt2x00dev) ||
899                      rt2400pci_init_bbp(rt2x00dev)))
900                 return -EIO;
901
902         return 0;
903 }
904
905 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
906 {
907         u32 reg;
908
909         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
910
911         /*
912          * Disable synchronisation.
913          */
914         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
915
916         /*
917          * Cancel RX and TX.
918          */
919         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
920         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
921         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
922 }
923
924 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
925                                enum dev_state state)
926 {
927         u32 reg;
928         unsigned int i;
929         char put_to_sleep;
930         char bbp_state;
931         char rf_state;
932
933         put_to_sleep = (state != STATE_AWAKE);
934
935         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
936         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
937         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
938         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
939         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
940         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
941
942         /*
943          * Device is not guaranteed to be in the requested state yet.
944          * We must wait until the register indicates that the
945          * device has entered the correct state.
946          */
947         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
948                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
949                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
950                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
951                 if (bbp_state == state && rf_state == state)
952                         return 0;
953                 msleep(10);
954         }
955
956         return -EBUSY;
957 }
958
959 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
960                                       enum dev_state state)
961 {
962         int retval = 0;
963
964         switch (state) {
965         case STATE_RADIO_ON:
966                 retval = rt2400pci_enable_radio(rt2x00dev);
967                 break;
968         case STATE_RADIO_OFF:
969                 rt2400pci_disable_radio(rt2x00dev);
970                 break;
971         case STATE_RADIO_RX_ON:
972         case STATE_RADIO_RX_ON_LINK:
973         case STATE_RADIO_RX_OFF:
974         case STATE_RADIO_RX_OFF_LINK:
975                 rt2400pci_toggle_rx(rt2x00dev, state);
976                 break;
977         case STATE_RADIO_IRQ_ON:
978         case STATE_RADIO_IRQ_OFF:
979                 rt2400pci_toggle_irq(rt2x00dev, state);
980                 break;
981         case STATE_DEEP_SLEEP:
982         case STATE_SLEEP:
983         case STATE_STANDBY:
984         case STATE_AWAKE:
985                 retval = rt2400pci_set_state(rt2x00dev, state);
986                 break;
987         default:
988                 retval = -ENOTSUPP;
989                 break;
990         }
991
992         if (unlikely(retval))
993                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
994                       state, retval);
995
996         return retval;
997 }
998
999 /*
1000  * TX descriptor initialization
1001  */
1002 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1003                                     struct sk_buff *skb,
1004                                     struct txentry_desc *txdesc)
1005 {
1006         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1007         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1008         __le32 *txd = skbdesc->desc;
1009         u32 word;
1010
1011         /*
1012          * Start writing the descriptor words.
1013          */
1014         rt2x00_desc_read(entry_priv->desc, 1, &word);
1015         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1016         rt2x00_desc_write(entry_priv->desc, 1, word);
1017
1018         rt2x00_desc_read(txd, 2, &word);
1019         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1020         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
1021         rt2x00_desc_write(txd, 2, word);
1022
1023         rt2x00_desc_read(txd, 3, &word);
1024         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1025         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1026         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1027         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1028         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1029         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1030         rt2x00_desc_write(txd, 3, word);
1031
1032         rt2x00_desc_read(txd, 4, &word);
1033         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1034         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1035         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1036         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1037         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1038         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1039         rt2x00_desc_write(txd, 4, word);
1040
1041         rt2x00_desc_read(txd, 0, &word);
1042         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1043         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1044         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1045                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1046         rt2x00_set_field32(&word, TXD_W0_ACK,
1047                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1048         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1049                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1050         rt2x00_set_field32(&word, TXD_W0_RTS,
1051                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1052         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1053         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1054                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1055         rt2x00_desc_write(txd, 0, word);
1056 }
1057
1058 /*
1059  * TX data initialization
1060  */
1061 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1062                                     const enum data_queue_qid queue)
1063 {
1064         u32 reg;
1065
1066         if (queue == QID_BEACON) {
1067                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1068                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1069                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1070                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1071                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1072                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1073                 }
1074                 return;
1075         }
1076
1077         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1078         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1079         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1080         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1081         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1082 }
1083
1084 /*
1085  * RX control handlers
1086  */
1087 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1088                                   struct rxdone_entry_desc *rxdesc)
1089 {
1090         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1091         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1092         u32 word0;
1093         u32 word2;
1094         u32 word3;
1095         u32 word4;
1096         u64 tsf;
1097         u32 rx_low;
1098         u32 rx_high;
1099
1100         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1101         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1102         rt2x00_desc_read(entry_priv->desc, 3, &word3);
1103         rt2x00_desc_read(entry_priv->desc, 4, &word4);
1104
1105         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1106                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1107         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1108                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1109
1110         /*
1111          * We only get the lower 32bits from the timestamp,
1112          * to get the full 64bits we must complement it with
1113          * the timestamp from get_tsf().
1114          * Note that when a wraparound of the lower 32bits
1115          * has occurred between the frame arrival and the get_tsf()
1116          * call, we must decrease the higher 32bits with 1 to get
1117          * to correct value.
1118          */
1119         tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1120         rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1121         rx_high = upper_32_bits(tsf);
1122
1123         if ((u32)tsf <= rx_low)
1124                 rx_high--;
1125
1126         /*
1127          * Obtain the status about this packet.
1128          * The signal is the PLCP value, and needs to be stripped
1129          * of the preamble bit (0x08).
1130          */
1131         rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1132         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1133         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1134             entry->queue->rt2x00dev->rssi_offset;
1135         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1136
1137         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1138         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1139                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1140 }
1141
1142 /*
1143  * Interrupt functions.
1144  */
1145 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1146                              const enum data_queue_qid queue_idx)
1147 {
1148         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1149         struct queue_entry_priv_pci *entry_priv;
1150         struct queue_entry *entry;
1151         struct txdone_entry_desc txdesc;
1152         u32 word;
1153
1154         while (!rt2x00queue_empty(queue)) {
1155                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1156                 entry_priv = entry->priv_data;
1157                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1158
1159                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1160                     !rt2x00_get_field32(word, TXD_W0_VALID))
1161                         break;
1162
1163                 /*
1164                  * Obtain the status about this packet.
1165                  */
1166                 txdesc.flags = 0;
1167                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1168                 case 0: /* Success */
1169                 case 1: /* Success with retry */
1170                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1171                         break;
1172                 case 2: /* Failure, excessive retries */
1173                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1174                         /* Don't break, this is a failed frame! */
1175                 default: /* Failure */
1176                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1177                 }
1178                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1179
1180                 rt2x00lib_txdone(entry, &txdesc);
1181         }
1182 }
1183
1184 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1185 {
1186         struct rt2x00_dev *rt2x00dev = dev_instance;
1187         u32 reg;
1188
1189         /*
1190          * Get the interrupt sources & saved to local variable.
1191          * Write register value back to clear pending interrupts.
1192          */
1193         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1194         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1195
1196         if (!reg)
1197                 return IRQ_NONE;
1198
1199         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1200                 return IRQ_HANDLED;
1201
1202         /*
1203          * Handle interrupts, walk through all bits
1204          * and run the tasks, the bits are checked in order of
1205          * priority.
1206          */
1207
1208         /*
1209          * 1 - Beacon timer expired interrupt.
1210          */
1211         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1212                 rt2x00lib_beacondone(rt2x00dev);
1213
1214         /*
1215          * 2 - Rx ring done interrupt.
1216          */
1217         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1218                 rt2x00pci_rxdone(rt2x00dev);
1219
1220         /*
1221          * 3 - Atim ring transmit done interrupt.
1222          */
1223         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1224                 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1225
1226         /*
1227          * 4 - Priority ring transmit done interrupt.
1228          */
1229         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1230                 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1231
1232         /*
1233          * 5 - Tx ring transmit done interrupt.
1234          */
1235         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1236                 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1237
1238         return IRQ_HANDLED;
1239 }
1240
1241 /*
1242  * Device probe functions.
1243  */
1244 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1245 {
1246         struct eeprom_93cx6 eeprom;
1247         u32 reg;
1248         u16 word;
1249         u8 *mac;
1250
1251         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1252
1253         eeprom.data = rt2x00dev;
1254         eeprom.register_read = rt2400pci_eepromregister_read;
1255         eeprom.register_write = rt2400pci_eepromregister_write;
1256         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1257             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1258         eeprom.reg_data_in = 0;
1259         eeprom.reg_data_out = 0;
1260         eeprom.reg_data_clock = 0;
1261         eeprom.reg_chip_select = 0;
1262
1263         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1264                                EEPROM_SIZE / sizeof(u16));
1265
1266         /*
1267          * Start validation of the data that has been read.
1268          */
1269         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1270         if (!is_valid_ether_addr(mac)) {
1271                 DECLARE_MAC_BUF(macbuf);
1272
1273                 random_ether_addr(mac);
1274                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1275         }
1276
1277         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1278         if (word == 0xffff) {
1279                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1280                 return -EINVAL;
1281         }
1282
1283         return 0;
1284 }
1285
1286 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1287 {
1288         u32 reg;
1289         u16 value;
1290         u16 eeprom;
1291
1292         /*
1293          * Read EEPROM word for configuration.
1294          */
1295         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1296
1297         /*
1298          * Identify RF chipset.
1299          */
1300         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1301         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1302         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1303
1304         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1305             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1306                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1307                 return -ENODEV;
1308         }
1309
1310         /*
1311          * Identify default antenna configuration.
1312          */
1313         rt2x00dev->default_ant.tx =
1314             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1315         rt2x00dev->default_ant.rx =
1316             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1317
1318         /*
1319          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1320          * I am not 100% sure about this, but the legacy drivers do not
1321          * indicate antenna swapping in software is required when
1322          * diversity is enabled.
1323          */
1324         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1325                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1326         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1327                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1328
1329         /*
1330          * Store led mode, for correct led behaviour.
1331          */
1332 #ifdef CONFIG_RT2400PCI_LEDS
1333         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1334
1335         rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1336         if (value == LED_MODE_TXRX_ACTIVITY)
1337                 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1338                                    LED_TYPE_ACTIVITY);
1339 #endif /* CONFIG_RT2400PCI_LEDS */
1340
1341         /*
1342          * Detect if this device has an hardware controlled radio.
1343          */
1344 #ifdef CONFIG_RT2400PCI_RFKILL
1345         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1346                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1347 #endif /* CONFIG_RT2400PCI_RFKILL */
1348
1349         /*
1350          * Check if the BBP tuning should be enabled.
1351          */
1352         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1353                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1354
1355         return 0;
1356 }
1357
1358 /*
1359  * RF value list for RF2420 & RF2421
1360  * Supports: 2.4 GHz
1361  */
1362 static const struct rf_channel rf_vals_bg[] = {
1363         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1364         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1365         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1366         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1367         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1368         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1369         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1370         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1371         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1372         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1373         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1374         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1375         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1376         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1377 };
1378
1379 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1380 {
1381         struct hw_mode_spec *spec = &rt2x00dev->spec;
1382         u8 *txpower;
1383         unsigned int i;
1384
1385         /*
1386          * Initialize all hw fields.
1387          */
1388         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1389                                IEEE80211_HW_SIGNAL_DBM;
1390         rt2x00dev->hw->extra_tx_headroom = 0;
1391
1392         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1393         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1394                                 rt2x00_eeprom_addr(rt2x00dev,
1395                                                    EEPROM_MAC_ADDR_0));
1396
1397         /*
1398          * Convert tx_power array in eeprom.
1399          */
1400         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1401         for (i = 0; i < 14; i++)
1402                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1403
1404         /*
1405          * Initialize hw_mode information.
1406          */
1407         spec->supported_bands = SUPPORT_BAND_2GHZ;
1408         spec->supported_rates = SUPPORT_RATE_CCK;
1409         spec->tx_power_a = NULL;
1410         spec->tx_power_bg = txpower;
1411         spec->tx_power_default = DEFAULT_TXPOWER;
1412
1413         spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1414         spec->channels = rf_vals_bg;
1415 }
1416
1417 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1418 {
1419         int retval;
1420
1421         /*
1422          * Allocate eeprom data.
1423          */
1424         retval = rt2400pci_validate_eeprom(rt2x00dev);
1425         if (retval)
1426                 return retval;
1427
1428         retval = rt2400pci_init_eeprom(rt2x00dev);
1429         if (retval)
1430                 return retval;
1431
1432         /*
1433          * Initialize hw specifications.
1434          */
1435         rt2400pci_probe_hw_mode(rt2x00dev);
1436
1437         /*
1438          * This device requires the atim queue and DMA-mapped skbs.
1439          */
1440         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1441         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1442
1443         /*
1444          * Set the rssi offset.
1445          */
1446         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1447
1448         return 0;
1449 }
1450
1451 /*
1452  * IEEE80211 stack callback functions.
1453  */
1454 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1455                                      u32 short_retry, u32 long_retry)
1456 {
1457         struct rt2x00_dev *rt2x00dev = hw->priv;
1458         u32 reg;
1459
1460         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1461         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1462         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1463         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1464
1465         return 0;
1466 }
1467
1468 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1469                              const struct ieee80211_tx_queue_params *params)
1470 {
1471         struct rt2x00_dev *rt2x00dev = hw->priv;
1472
1473         /*
1474          * We don't support variating cw_min and cw_max variables
1475          * per queue. So by default we only configure the TX queue,
1476          * and ignore all other configurations.
1477          */
1478         if (queue != 0)
1479                 return -EINVAL;
1480
1481         if (rt2x00mac_conf_tx(hw, queue, params))
1482                 return -EINVAL;
1483
1484         /*
1485          * Write configuration to register.
1486          */
1487         rt2400pci_config_cw(rt2x00dev,
1488                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1489
1490         return 0;
1491 }
1492
1493 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1494 {
1495         struct rt2x00_dev *rt2x00dev = hw->priv;
1496         u64 tsf;
1497         u32 reg;
1498
1499         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1500         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1501         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1502         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1503
1504         return tsf;
1505 }
1506
1507 static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
1508 {
1509         struct rt2x00_dev *rt2x00dev = hw->priv;
1510         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1511         struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
1512         struct queue_entry_priv_pci *entry_priv;
1513         struct skb_frame_desc *skbdesc;
1514         struct txentry_desc txdesc;
1515         u32 reg;
1516
1517         if (unlikely(!intf->beacon))
1518                 return -ENOBUFS;
1519         entry_priv = intf->beacon->priv_data;
1520
1521         /*
1522          * Copy all TX descriptor information into txdesc,
1523          * after that we are free to use the skb->cb array
1524          * for our information.
1525          */
1526         intf->beacon->skb = skb;
1527         rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
1528
1529         /*
1530          * Fill in skb descriptor
1531          */
1532         skbdesc = get_skb_frame_desc(skb);
1533         memset(skbdesc, 0, sizeof(*skbdesc));
1534         skbdesc->desc = entry_priv->desc;
1535         skbdesc->desc_len = intf->beacon->queue->desc_size;
1536         skbdesc->entry = intf->beacon;
1537
1538         /*
1539          * Disable beaconing while we are reloading the beacon data,
1540          * otherwise we might be sending out invalid data.
1541          */
1542         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1543         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1544         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1545         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1546         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1547
1548         /*
1549          * Enable beacon generation.
1550          * Write entire beacon with descriptor to register,
1551          * and kick the beacon generator.
1552          */
1553         rt2x00queue_map_txskb(rt2x00dev, intf->beacon->skb);
1554         rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
1555         rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
1556
1557         return 0;
1558 }
1559
1560 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1561 {
1562         struct rt2x00_dev *rt2x00dev = hw->priv;
1563         u32 reg;
1564
1565         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1566         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1567 }
1568
1569 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1570         .tx                     = rt2x00mac_tx,
1571         .start                  = rt2x00mac_start,
1572         .stop                   = rt2x00mac_stop,
1573         .add_interface          = rt2x00mac_add_interface,
1574         .remove_interface       = rt2x00mac_remove_interface,
1575         .config                 = rt2x00mac_config,
1576         .config_interface       = rt2x00mac_config_interface,
1577         .configure_filter       = rt2x00mac_configure_filter,
1578         .get_stats              = rt2x00mac_get_stats,
1579         .set_retry_limit        = rt2400pci_set_retry_limit,
1580         .bss_info_changed       = rt2x00mac_bss_info_changed,
1581         .conf_tx                = rt2400pci_conf_tx,
1582         .get_tx_stats           = rt2x00mac_get_tx_stats,
1583         .get_tsf                = rt2400pci_get_tsf,
1584         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1585 };
1586
1587 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1588         .irq_handler            = rt2400pci_interrupt,
1589         .probe_hw               = rt2400pci_probe_hw,
1590         .initialize             = rt2x00pci_initialize,
1591         .uninitialize           = rt2x00pci_uninitialize,
1592         .init_rxentry           = rt2400pci_init_rxentry,
1593         .init_txentry           = rt2400pci_init_txentry,
1594         .set_device_state       = rt2400pci_set_device_state,
1595         .rfkill_poll            = rt2400pci_rfkill_poll,
1596         .link_stats             = rt2400pci_link_stats,
1597         .reset_tuner            = rt2400pci_reset_tuner,
1598         .link_tuner             = rt2400pci_link_tuner,
1599         .write_tx_desc          = rt2400pci_write_tx_desc,
1600         .write_tx_data          = rt2x00pci_write_tx_data,
1601         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1602         .fill_rxdone            = rt2400pci_fill_rxdone,
1603         .beacon_update          = rt2400pci_beacon_update,
1604         .config_filter          = rt2400pci_config_filter,
1605         .config_intf            = rt2400pci_config_intf,
1606         .config_erp             = rt2400pci_config_erp,
1607         .config                 = rt2400pci_config,
1608 };
1609
1610 static const struct data_queue_desc rt2400pci_queue_rx = {
1611         .entry_num              = RX_ENTRIES,
1612         .data_size              = DATA_FRAME_SIZE,
1613         .desc_size              = RXD_DESC_SIZE,
1614         .priv_size              = sizeof(struct queue_entry_priv_pci),
1615 };
1616
1617 static const struct data_queue_desc rt2400pci_queue_tx = {
1618         .entry_num              = TX_ENTRIES,
1619         .data_size              = DATA_FRAME_SIZE,
1620         .desc_size              = TXD_DESC_SIZE,
1621         .priv_size              = sizeof(struct queue_entry_priv_pci),
1622 };
1623
1624 static const struct data_queue_desc rt2400pci_queue_bcn = {
1625         .entry_num              = BEACON_ENTRIES,
1626         .data_size              = MGMT_FRAME_SIZE,
1627         .desc_size              = TXD_DESC_SIZE,
1628         .priv_size              = sizeof(struct queue_entry_priv_pci),
1629 };
1630
1631 static const struct data_queue_desc rt2400pci_queue_atim = {
1632         .entry_num              = ATIM_ENTRIES,
1633         .data_size              = DATA_FRAME_SIZE,
1634         .desc_size              = TXD_DESC_SIZE,
1635         .priv_size              = sizeof(struct queue_entry_priv_pci),
1636 };
1637
1638 static const struct rt2x00_ops rt2400pci_ops = {
1639         .name           = KBUILD_MODNAME,
1640         .max_sta_intf   = 1,
1641         .max_ap_intf    = 1,
1642         .eeprom_size    = EEPROM_SIZE,
1643         .rf_size        = RF_SIZE,
1644         .tx_queues      = NUM_TX_QUEUES,
1645         .rx             = &rt2400pci_queue_rx,
1646         .tx             = &rt2400pci_queue_tx,
1647         .bcn            = &rt2400pci_queue_bcn,
1648         .atim           = &rt2400pci_queue_atim,
1649         .lib            = &rt2400pci_rt2x00_ops,
1650         .hw             = &rt2400pci_mac80211_ops,
1651 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1652         .debugfs        = &rt2400pci_rt2x00debug,
1653 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1654 };
1655
1656 /*
1657  * RT2400pci module information.
1658  */
1659 static struct pci_device_id rt2400pci_device_table[] = {
1660         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1661         { 0, }
1662 };
1663
1664 MODULE_AUTHOR(DRV_PROJECT);
1665 MODULE_VERSION(DRV_VERSION);
1666 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1667 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1668 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1669 MODULE_LICENSE("GPL");
1670
1671 static struct pci_driver rt2400pci_driver = {
1672         .name           = KBUILD_MODNAME,
1673         .id_table       = rt2400pci_device_table,
1674         .probe          = rt2x00pci_probe,
1675         .remove         = __devexit_p(rt2x00pci_remove),
1676         .suspend        = rt2x00pci_suspend,
1677         .resume         = rt2x00pci_resume,
1678 };
1679
1680 static int __init rt2400pci_init(void)
1681 {
1682         return pci_register_driver(&rt2400pci_driver);
1683 }
1684
1685 static void __exit rt2400pci_exit(void)
1686 {
1687         pci_unregister_driver(&rt2400pci_driver);
1688 }
1689
1690 module_init(rt2400pci_init);
1691 module_exit(rt2400pci_exit);