852d193a11a94c5672590e7fa1dfc02c9eb58c12
[kernel.git] / drivers / net / wireless / rt2x00 / rt61pci.c
1 /*
2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt61pci
23         Abstract: rt61pci device specific routines.
24         Supported chipsets: RT2561, RT2561s, RT2661.
25  */
26
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/eeprom_93cx6.h>
35
36 #include "rt2x00.h"
37 #include "rt2x00pci.h"
38 #include "rt61pci.h"
39
40 /*
41  * Register access.
42  * BBP and RF register require indirect register access,
43  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
44  * These indirect registers work with busy bits,
45  * and we will try maximal REGISTER_BUSY_COUNT times to access
46  * the register while taking a REGISTER_BUSY_DELAY us delay
47  * between each attampt. When the busy bit is still set at that time,
48  * the access attempt is considered to have failed,
49  * and we will print an error.
50  */
51 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
52 {
53         u32 reg;
54         unsigned int i;
55
56         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
57                 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
58                 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
59                         break;
60                 udelay(REGISTER_BUSY_DELAY);
61         }
62
63         return reg;
64 }
65
66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
67                               const unsigned int word, const u8 value)
68 {
69         u32 reg;
70
71         /*
72          * Wait until the BBP becomes ready.
73          */
74         reg = rt61pci_bbp_check(rt2x00dev);
75         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
76                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
77                 return;
78         }
79
80         /*
81          * Write the data into the BBP.
82          */
83         reg = 0;
84         rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
85         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
86         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
87         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
88
89         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
90 }
91
92 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
93                              const unsigned int word, u8 *value)
94 {
95         u32 reg;
96
97         /*
98          * Wait until the BBP becomes ready.
99          */
100         reg = rt61pci_bbp_check(rt2x00dev);
101         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
102                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
103                 return;
104         }
105
106         /*
107          * Write the request into the BBP.
108          */
109         reg = 0;
110         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
111         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
112         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
113
114         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
115
116         /*
117          * Wait until the BBP becomes ready.
118          */
119         reg = rt61pci_bbp_check(rt2x00dev);
120         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
121                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
122                 *value = 0xff;
123                 return;
124         }
125
126         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
127 }
128
129 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
130                              const unsigned int word, const u32 value)
131 {
132         u32 reg;
133         unsigned int i;
134
135         if (!word)
136                 return;
137
138         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
139                 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
140                 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
141                         goto rf_write;
142                 udelay(REGISTER_BUSY_DELAY);
143         }
144
145         ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
146         return;
147
148 rf_write:
149         reg = 0;
150         rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
151         rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
152         rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
153         rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
154
155         rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
156         rt2x00_rf_write(rt2x00dev, word, value);
157 }
158
159 #ifdef CONFIG_RT61PCI_LEDS
160 /*
161  * This function is only called from rt61pci_led_brightness()
162  * make gcc happy by placing this function inside the
163  * same ifdef statement as the caller.
164  */
165 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
166                                 const u8 command, const u8 token,
167                                 const u8 arg0, const u8 arg1)
168 {
169         u32 reg;
170
171         rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
172
173         if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
174                 ERROR(rt2x00dev, "mcu request error. "
175                       "Request 0x%02x failed for token 0x%02x.\n",
176                       command, token);
177                 return;
178         }
179
180         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
181         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
182         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
183         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
184         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
185
186         rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
187         rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
188         rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
189         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
190 }
191 #endif /* CONFIG_RT61PCI_LEDS */
192
193 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
194 {
195         struct rt2x00_dev *rt2x00dev = eeprom->data;
196         u32 reg;
197
198         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
199
200         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
201         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
202         eeprom->reg_data_clock =
203             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
204         eeprom->reg_chip_select =
205             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
206 }
207
208 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
209 {
210         struct rt2x00_dev *rt2x00dev = eeprom->data;
211         u32 reg = 0;
212
213         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
214         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
215         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
216                            !!eeprom->reg_data_clock);
217         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
218                            !!eeprom->reg_chip_select);
219
220         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
221 }
222
223 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
224 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
225
226 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
227                              const unsigned int word, u32 *data)
228 {
229         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
230 }
231
232 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
233                               const unsigned int word, u32 data)
234 {
235         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
236 }
237
238 static const struct rt2x00debug rt61pci_rt2x00debug = {
239         .owner  = THIS_MODULE,
240         .csr    = {
241                 .read           = rt61pci_read_csr,
242                 .write          = rt61pci_write_csr,
243                 .word_size      = sizeof(u32),
244                 .word_count     = CSR_REG_SIZE / sizeof(u32),
245         },
246         .eeprom = {
247                 .read           = rt2x00_eeprom_read,
248                 .write          = rt2x00_eeprom_write,
249                 .word_size      = sizeof(u16),
250                 .word_count     = EEPROM_SIZE / sizeof(u16),
251         },
252         .bbp    = {
253                 .read           = rt61pci_bbp_read,
254                 .write          = rt61pci_bbp_write,
255                 .word_size      = sizeof(u8),
256                 .word_count     = BBP_SIZE / sizeof(u8),
257         },
258         .rf     = {
259                 .read           = rt2x00_rf_read,
260                 .write          = rt61pci_rf_write,
261                 .word_size      = sizeof(u32),
262                 .word_count     = RF_SIZE / sizeof(u32),
263         },
264 };
265 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
266
267 #ifdef CONFIG_RT61PCI_RFKILL
268 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
269 {
270         u32 reg;
271
272         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
273         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
274 }
275 #else
276 #define rt61pci_rfkill_poll     NULL
277 #endif /* CONFIG_RT61PCI_RFKILL */
278
279 #ifdef CONFIG_RT61PCI_LEDS
280 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
281                                    enum led_brightness brightness)
282 {
283         struct rt2x00_led *led =
284             container_of(led_cdev, struct rt2x00_led, led_dev);
285         unsigned int enabled = brightness != LED_OFF;
286         unsigned int a_mode =
287             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
288         unsigned int bg_mode =
289             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
290
291         if (led->type == LED_TYPE_RADIO) {
292                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
293                                    MCU_LEDCS_RADIO_STATUS, enabled);
294
295                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
296                                     (led->rt2x00dev->led_mcu_reg & 0xff),
297                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
298         } else if (led->type == LED_TYPE_ASSOC) {
299                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
300                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
301                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
302                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
303
304                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
305                                     (led->rt2x00dev->led_mcu_reg & 0xff),
306                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
307         } else if (led->type == LED_TYPE_QUALITY) {
308                 /*
309                  * The brightness is divided into 6 levels (0 - 5),
310                  * this means we need to convert the brightness
311                  * argument into the matching level within that range.
312                  */
313                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
314                                     brightness / (LED_FULL / 6), 0);
315         }
316 }
317
318 static int rt61pci_blink_set(struct led_classdev *led_cdev,
319                              unsigned long *delay_on,
320                              unsigned long *delay_off)
321 {
322         struct rt2x00_led *led =
323             container_of(led_cdev, struct rt2x00_led, led_dev);
324         u32 reg;
325
326         rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
327         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
328         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
329         rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
330
331         return 0;
332 }
333
334 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
335                              struct rt2x00_led *led,
336                              enum led_type type)
337 {
338         led->rt2x00dev = rt2x00dev;
339         led->type = type;
340         led->led_dev.brightness_set = rt61pci_brightness_set;
341         led->led_dev.blink_set = rt61pci_blink_set;
342         led->flags = LED_INITIALIZED;
343 }
344 #endif /* CONFIG_RT61PCI_LEDS */
345
346 /*
347  * Configuration handlers.
348  */
349 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
350                                   const unsigned int filter_flags)
351 {
352         u32 reg;
353
354         /*
355          * Start configuration steps.
356          * Note that the version error will always be dropped
357          * and broadcast frames will always be accepted since
358          * there is no filter for it at this time.
359          */
360         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
361         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
362                            !(filter_flags & FIF_FCSFAIL));
363         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
364                            !(filter_flags & FIF_PLCPFAIL));
365         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
366                            !(filter_flags & FIF_CONTROL));
367         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
368                            !(filter_flags & FIF_PROMISC_IN_BSS));
369         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
370                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
371                            !rt2x00dev->intf_ap_count);
372         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
373         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
374                            !(filter_flags & FIF_ALLMULTI));
375         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
376         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
377                            !(filter_flags & FIF_CONTROL));
378         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
379 }
380
381 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
382                                 struct rt2x00_intf *intf,
383                                 struct rt2x00intf_conf *conf,
384                                 const unsigned int flags)
385 {
386         unsigned int beacon_base;
387         u32 reg;
388
389         if (flags & CONFIG_UPDATE_TYPE) {
390                 /*
391                  * Clear current synchronisation setup.
392                  * For the Beacon base registers we only need to clear
393                  * the first byte since that byte contains the VALID and OWNER
394                  * bits which (when set to 0) will invalidate the entire beacon.
395                  */
396                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
397                 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
398
399                 /*
400                  * Enable synchronisation.
401                  */
402                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
403                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
404                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
405                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
406                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
407         }
408
409         if (flags & CONFIG_UPDATE_MAC) {
410                 reg = le32_to_cpu(conf->mac[1]);
411                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
412                 conf->mac[1] = cpu_to_le32(reg);
413
414                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
415                                               conf->mac, sizeof(conf->mac));
416         }
417
418         if (flags & CONFIG_UPDATE_BSSID) {
419                 reg = le32_to_cpu(conf->bssid[1]);
420                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
421                 conf->bssid[1] = cpu_to_le32(reg);
422
423                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
424                                               conf->bssid, sizeof(conf->bssid));
425         }
426 }
427
428 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
429                                struct rt2x00lib_erp *erp)
430 {
431         u32 reg;
432
433         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
434         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
435         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
436
437         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
438         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
439                            !!erp->short_preamble);
440         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
441 }
442
443 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
444                                    const int basic_rate_mask)
445 {
446         rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
447 }
448
449 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
450                                    struct rf_channel *rf, const int txpower)
451 {
452         u8 r3;
453         u8 r94;
454         u8 smart;
455
456         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
457         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
458
459         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
460                   rt2x00_rf(&rt2x00dev->chip, RF2527));
461
462         rt61pci_bbp_read(rt2x00dev, 3, &r3);
463         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
464         rt61pci_bbp_write(rt2x00dev, 3, r3);
465
466         r94 = 6;
467         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
468                 r94 += txpower - MAX_TXPOWER;
469         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
470                 r94 += txpower;
471         rt61pci_bbp_write(rt2x00dev, 94, r94);
472
473         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
474         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
475         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
476         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
477
478         udelay(200);
479
480         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
481         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
482         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
483         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
484
485         udelay(200);
486
487         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
488         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
489         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
490         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
491
492         msleep(1);
493 }
494
495 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
496                                    const int txpower)
497 {
498         struct rf_channel rf;
499
500         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
501         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
502         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
503         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
504
505         rt61pci_config_channel(rt2x00dev, &rf, txpower);
506 }
507
508 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
509                                       struct antenna_setup *ant)
510 {
511         u8 r3;
512         u8 r4;
513         u8 r77;
514
515         rt61pci_bbp_read(rt2x00dev, 3, &r3);
516         rt61pci_bbp_read(rt2x00dev, 4, &r4);
517         rt61pci_bbp_read(rt2x00dev, 77, &r77);
518
519         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
520                           rt2x00_rf(&rt2x00dev->chip, RF5325));
521
522         /*
523          * Configure the RX antenna.
524          */
525         switch (ant->rx) {
526         case ANTENNA_HW_DIVERSITY:
527                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
528                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
529                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
530                 break;
531         case ANTENNA_A:
532                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
533                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
534                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
535                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
536                 else
537                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
538                 break;
539         case ANTENNA_B:
540         default:
541                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
542                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
543                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
544                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
545                 else
546                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
547                 break;
548         }
549
550         rt61pci_bbp_write(rt2x00dev, 77, r77);
551         rt61pci_bbp_write(rt2x00dev, 3, r3);
552         rt61pci_bbp_write(rt2x00dev, 4, r4);
553 }
554
555 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
556                                       struct antenna_setup *ant)
557 {
558         u8 r3;
559         u8 r4;
560         u8 r77;
561
562         rt61pci_bbp_read(rt2x00dev, 3, &r3);
563         rt61pci_bbp_read(rt2x00dev, 4, &r4);
564         rt61pci_bbp_read(rt2x00dev, 77, &r77);
565
566         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
567                           rt2x00_rf(&rt2x00dev->chip, RF2529));
568         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
569                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
570
571         /*
572          * Configure the RX antenna.
573          */
574         switch (ant->rx) {
575         case ANTENNA_HW_DIVERSITY:
576                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
577                 break;
578         case ANTENNA_A:
579                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
580                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
581                 break;
582         case ANTENNA_B:
583         default:
584                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
585                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
586                 break;
587         }
588
589         rt61pci_bbp_write(rt2x00dev, 77, r77);
590         rt61pci_bbp_write(rt2x00dev, 3, r3);
591         rt61pci_bbp_write(rt2x00dev, 4, r4);
592 }
593
594 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
595                                            const int p1, const int p2)
596 {
597         u32 reg;
598
599         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
600
601         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
602         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
603
604         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
605         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
606
607         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
608 }
609
610 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
611                                         struct antenna_setup *ant)
612 {
613         u8 r3;
614         u8 r4;
615         u8 r77;
616
617         rt61pci_bbp_read(rt2x00dev, 3, &r3);
618         rt61pci_bbp_read(rt2x00dev, 4, &r4);
619         rt61pci_bbp_read(rt2x00dev, 77, &r77);
620
621         /*
622          * Configure the RX antenna.
623          */
624         switch (ant->rx) {
625         case ANTENNA_A:
626                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
627                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
628                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
629                 break;
630         case ANTENNA_HW_DIVERSITY:
631                 /*
632                  * FIXME: Antenna selection for the rf 2529 is very confusing
633                  * in the legacy driver. Just default to antenna B until the
634                  * legacy code can be properly translated into rt2x00 code.
635                  */
636         case ANTENNA_B:
637         default:
638                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
639                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
640                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
641                 break;
642         }
643
644         rt61pci_bbp_write(rt2x00dev, 77, r77);
645         rt61pci_bbp_write(rt2x00dev, 3, r3);
646         rt61pci_bbp_write(rt2x00dev, 4, r4);
647 }
648
649 struct antenna_sel {
650         u8 word;
651         /*
652          * value[0] -> non-LNA
653          * value[1] -> LNA
654          */
655         u8 value[2];
656 };
657
658 static const struct antenna_sel antenna_sel_a[] = {
659         { 96,  { 0x58, 0x78 } },
660         { 104, { 0x38, 0x48 } },
661         { 75,  { 0xfe, 0x80 } },
662         { 86,  { 0xfe, 0x80 } },
663         { 88,  { 0xfe, 0x80 } },
664         { 35,  { 0x60, 0x60 } },
665         { 97,  { 0x58, 0x58 } },
666         { 98,  { 0x58, 0x58 } },
667 };
668
669 static const struct antenna_sel antenna_sel_bg[] = {
670         { 96,  { 0x48, 0x68 } },
671         { 104, { 0x2c, 0x3c } },
672         { 75,  { 0xfe, 0x80 } },
673         { 86,  { 0xfe, 0x80 } },
674         { 88,  { 0xfe, 0x80 } },
675         { 35,  { 0x50, 0x50 } },
676         { 97,  { 0x48, 0x48 } },
677         { 98,  { 0x48, 0x48 } },
678 };
679
680 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
681                                    struct antenna_setup *ant)
682 {
683         const struct antenna_sel *sel;
684         unsigned int lna;
685         unsigned int i;
686         u32 reg;
687
688         /*
689          * We should never come here because rt2x00lib is supposed
690          * to catch this and send us the correct antenna explicitely.
691          */
692         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
693                ant->tx == ANTENNA_SW_DIVERSITY);
694
695         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
696                 sel = antenna_sel_a;
697                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
698         } else {
699                 sel = antenna_sel_bg;
700                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
701         }
702
703         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
704                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
705
706         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
707
708         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
709                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
710         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
711                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
712
713         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
714
715         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
716             rt2x00_rf(&rt2x00dev->chip, RF5325))
717                 rt61pci_config_antenna_5x(rt2x00dev, ant);
718         else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
719                 rt61pci_config_antenna_2x(rt2x00dev, ant);
720         else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
721                 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
722                         rt61pci_config_antenna_2x(rt2x00dev, ant);
723                 else
724                         rt61pci_config_antenna_2529(rt2x00dev, ant);
725         }
726 }
727
728 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
729                                     struct rt2x00lib_conf *libconf)
730 {
731         u32 reg;
732
733         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
734         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
735         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
736
737         rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
738         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
739         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
740         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
741         rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
742
743         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
744         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
745         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
746
747         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
748         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
749         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
750
751         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
752         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
753                            libconf->conf->beacon_int * 16);
754         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
755 }
756
757 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
758                            struct rt2x00lib_conf *libconf,
759                            const unsigned int flags)
760 {
761         if (flags & CONFIG_UPDATE_PHYMODE)
762                 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
763         if (flags & CONFIG_UPDATE_CHANNEL)
764                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
765                                        libconf->conf->power_level);
766         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
767                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
768         if (flags & CONFIG_UPDATE_ANTENNA)
769                 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
770         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
771                 rt61pci_config_duration(rt2x00dev, libconf);
772 }
773
774 /*
775  * Link tuning
776  */
777 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
778                                struct link_qual *qual)
779 {
780         u32 reg;
781
782         /*
783          * Update FCS error count from register.
784          */
785         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
786         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
787
788         /*
789          * Update False CCA count from register.
790          */
791         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
792         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
793 }
794
795 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
796 {
797         rt61pci_bbp_write(rt2x00dev, 17, 0x20);
798         rt2x00dev->link.vgc_level = 0x20;
799 }
800
801 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
802 {
803         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
804         u8 r17;
805         u8 up_bound;
806         u8 low_bound;
807
808         rt61pci_bbp_read(rt2x00dev, 17, &r17);
809
810         /*
811          * Determine r17 bounds.
812          */
813         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
814                 low_bound = 0x28;
815                 up_bound = 0x48;
816                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
817                         low_bound += 0x10;
818                         up_bound += 0x10;
819                 }
820         } else {
821                 low_bound = 0x20;
822                 up_bound = 0x40;
823                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
824                         low_bound += 0x10;
825                         up_bound += 0x10;
826                 }
827         }
828
829         /*
830          * If we are not associated, we should go straight to the
831          * dynamic CCA tuning.
832          */
833         if (!rt2x00dev->intf_associated)
834                 goto dynamic_cca_tune;
835
836         /*
837          * Special big-R17 for very short distance
838          */
839         if (rssi >= -35) {
840                 if (r17 != 0x60)
841                         rt61pci_bbp_write(rt2x00dev, 17, 0x60);
842                 return;
843         }
844
845         /*
846          * Special big-R17 for short distance
847          */
848         if (rssi >= -58) {
849                 if (r17 != up_bound)
850                         rt61pci_bbp_write(rt2x00dev, 17, up_bound);
851                 return;
852         }
853
854         /*
855          * Special big-R17 for middle-short distance
856          */
857         if (rssi >= -66) {
858                 low_bound += 0x10;
859                 if (r17 != low_bound)
860                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
861                 return;
862         }
863
864         /*
865          * Special mid-R17 for middle distance
866          */
867         if (rssi >= -74) {
868                 low_bound += 0x08;
869                 if (r17 != low_bound)
870                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
871                 return;
872         }
873
874         /*
875          * Special case: Change up_bound based on the rssi.
876          * Lower up_bound when rssi is weaker then -74 dBm.
877          */
878         up_bound -= 2 * (-74 - rssi);
879         if (low_bound > up_bound)
880                 up_bound = low_bound;
881
882         if (r17 > up_bound) {
883                 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
884                 return;
885         }
886
887 dynamic_cca_tune:
888
889         /*
890          * r17 does not yet exceed upper limit, continue and base
891          * the r17 tuning on the false CCA count.
892          */
893         if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
894                 if (++r17 > up_bound)
895                         r17 = up_bound;
896                 rt61pci_bbp_write(rt2x00dev, 17, r17);
897         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
898                 if (--r17 < low_bound)
899                         r17 = low_bound;
900                 rt61pci_bbp_write(rt2x00dev, 17, r17);
901         }
902 }
903
904 /*
905  * Firmware functions
906  */
907 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
908 {
909         char *fw_name;
910
911         switch (rt2x00dev->chip.rt) {
912         case RT2561:
913                 fw_name = FIRMWARE_RT2561;
914                 break;
915         case RT2561s:
916                 fw_name = FIRMWARE_RT2561s;
917                 break;
918         case RT2661:
919                 fw_name = FIRMWARE_RT2661;
920                 break;
921         default:
922                 fw_name = NULL;
923                 break;
924         }
925
926         return fw_name;
927 }
928
929 static u16 rt61pci_get_firmware_crc(void *data, const size_t len)
930 {
931         u16 crc;
932
933         /*
934          * Use the crc itu-t algorithm.
935          * The last 2 bytes in the firmware array are the crc checksum itself,
936          * this means that we should never pass those 2 bytes to the crc
937          * algorithm.
938          */
939         crc = crc_itu_t(0, data, len - 2);
940         crc = crc_itu_t_byte(crc, 0);
941         crc = crc_itu_t_byte(crc, 0);
942
943         return crc;
944 }
945
946 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
947                                  const size_t len)
948 {
949         int i;
950         u32 reg;
951
952         /*
953          * Wait for stable hardware.
954          */
955         for (i = 0; i < 100; i++) {
956                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
957                 if (reg)
958                         break;
959                 msleep(1);
960         }
961
962         if (!reg) {
963                 ERROR(rt2x00dev, "Unstable hardware.\n");
964                 return -EBUSY;
965         }
966
967         /*
968          * Prepare MCU and mailbox for firmware loading.
969          */
970         reg = 0;
971         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
972         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
973         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
974         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
975         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
976
977         /*
978          * Write firmware to device.
979          */
980         reg = 0;
981         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
982         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
983         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
984
985         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
986                                       data, len);
987
988         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
989         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
990
991         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
992         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
993
994         for (i = 0; i < 100; i++) {
995                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
996                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
997                         break;
998                 msleep(1);
999         }
1000
1001         if (i == 100) {
1002                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1003                 return -EBUSY;
1004         }
1005
1006         /*
1007          * Reset MAC and BBP registers.
1008          */
1009         reg = 0;
1010         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1011         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1012         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1013
1014         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1015         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1016         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1017         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1018
1019         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1020         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1021         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1022
1023         return 0;
1024 }
1025
1026 /*
1027  * Initialization functions.
1028  */
1029 static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
1030                                  struct queue_entry *entry)
1031 {
1032         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1033         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1034         u32 word;
1035
1036         rt2x00_desc_read(entry_priv->desc, 5, &word);
1037         rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1038                            skbdesc->skb_dma);
1039         rt2x00_desc_write(entry_priv->desc, 5, word);
1040
1041         rt2x00_desc_read(entry_priv->desc, 0, &word);
1042         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1043         rt2x00_desc_write(entry_priv->desc, 0, word);
1044 }
1045
1046 static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1047                                  struct queue_entry *entry)
1048 {
1049         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1050         u32 word;
1051
1052         rt2x00_desc_read(entry_priv->desc, 0, &word);
1053         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1054         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1055         rt2x00_desc_write(entry_priv->desc, 0, word);
1056 }
1057
1058 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1059 {
1060         struct queue_entry_priv_pci *entry_priv;
1061         u32 reg;
1062
1063         /*
1064          * Initialize registers.
1065          */
1066         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1067         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1068                            rt2x00dev->tx[0].limit);
1069         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1070                            rt2x00dev->tx[1].limit);
1071         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1072                            rt2x00dev->tx[2].limit);
1073         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1074                            rt2x00dev->tx[3].limit);
1075         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1076
1077         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1078         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1079                            rt2x00dev->tx[0].desc_size / 4);
1080         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1081
1082         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1083         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1084         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1085                            entry_priv->desc_dma);
1086         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1087
1088         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1089         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1090         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1091                            entry_priv->desc_dma);
1092         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1093
1094         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1095         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1096         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1097                            entry_priv->desc_dma);
1098         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1099
1100         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1101         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1102         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1103                            entry_priv->desc_dma);
1104         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1105
1106         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1107         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1108         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1109                            rt2x00dev->rx->desc_size / 4);
1110         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1111         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1112
1113         entry_priv = rt2x00dev->rx->entries[0].priv_data;
1114         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1115         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1116                            entry_priv->desc_dma);
1117         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1118
1119         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1120         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1121         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1122         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1123         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1124         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1125
1126         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1127         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1128         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1129         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1130         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1131         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1132
1133         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1134         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1135         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1136
1137         return 0;
1138 }
1139
1140 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1141 {
1142         u32 reg;
1143
1144         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1145         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1146         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1147         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1148         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1149
1150         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1151         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1152         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1153         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1154         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1155         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1156         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1157         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1158         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1159         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1160
1161         /*
1162          * CCK TXD BBP registers
1163          */
1164         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1165         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1166         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1167         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1168         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1169         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1170         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1171         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1172         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1173         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1174
1175         /*
1176          * OFDM TXD BBP registers
1177          */
1178         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1179         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1180         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1181         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1182         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1183         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1184         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1185         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1186
1187         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1188         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1189         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1190         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1191         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1192         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1193
1194         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1195         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1196         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1197         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1198         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1199         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1200
1201         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1202
1203         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1204
1205         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1206         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1207         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1208
1209         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1210
1211         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1212                 return -EBUSY;
1213
1214         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1215
1216         /*
1217          * Invalidate all Shared Keys (SEC_CSR0),
1218          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1219          */
1220         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1221         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1222         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1223
1224         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1225         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1226         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1227         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1228
1229         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1230
1231         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1232
1233         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1234
1235         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1236         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1237         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1238         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1239
1240         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1241         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1242         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1243         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1244
1245         /*
1246          * Clear all beacons
1247          * For the Beacon base registers we only need to clear
1248          * the first byte since that byte contains the VALID and OWNER
1249          * bits which (when set to 0) will invalidate the entire beacon.
1250          */
1251         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1252         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1253         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1254         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1255
1256         /*
1257          * We must clear the error counters.
1258          * These registers are cleared on read,
1259          * so we may pass a useless variable to store the value.
1260          */
1261         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1262         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1263         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1264
1265         /*
1266          * Reset MAC and BBP registers.
1267          */
1268         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1269         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1270         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1271         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1272
1273         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1274         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1275         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1276         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1277
1278         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1279         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1280         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1281
1282         return 0;
1283 }
1284
1285 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1286 {
1287         unsigned int i;
1288         u8 value;
1289
1290         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1291                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1292                 if ((value != 0xff) && (value != 0x00))
1293                         return 0;
1294                 udelay(REGISTER_BUSY_DELAY);
1295         }
1296
1297         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1298         return -EACCES;
1299 }
1300
1301 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1302 {
1303         unsigned int i;
1304         u16 eeprom;
1305         u8 reg_id;
1306         u8 value;
1307
1308         if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1309                 return -EACCES;
1310
1311         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1312         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1313         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1314         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1315         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1316         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1317         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1318         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1319         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1320         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1321         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1322         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1323         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1324         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1325         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1326         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1327         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1328         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1329         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1330         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1331         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1332         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1333         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1334         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1335
1336         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1337                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1338
1339                 if (eeprom != 0xffff && eeprom != 0x0000) {
1340                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1341                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1342                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1343                 }
1344         }
1345
1346         return 0;
1347 }
1348
1349 /*
1350  * Device state switch handlers.
1351  */
1352 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1353                               enum dev_state state)
1354 {
1355         u32 reg;
1356
1357         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1358         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1359                            (state == STATE_RADIO_RX_OFF) ||
1360                            (state == STATE_RADIO_RX_OFF_LINK));
1361         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1362 }
1363
1364 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1365                                enum dev_state state)
1366 {
1367         int mask = (state == STATE_RADIO_IRQ_OFF);
1368         u32 reg;
1369
1370         /*
1371          * When interrupts are being enabled, the interrupt registers
1372          * should clear the register to assure a clean state.
1373          */
1374         if (state == STATE_RADIO_IRQ_ON) {
1375                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1376                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1377
1378                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1379                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1380         }
1381
1382         /*
1383          * Only toggle the interrupts bits we are going to use.
1384          * Non-checked interrupt bits are disabled by default.
1385          */
1386         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1387         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1388         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1389         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1390         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1391         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1392
1393         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1394         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1395         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1396         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1397         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1398         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1399         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1400         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1401         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1402         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1403 }
1404
1405 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1406 {
1407         u32 reg;
1408
1409         /*
1410          * Initialize all registers.
1411          */
1412         if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1413                      rt61pci_init_registers(rt2x00dev) ||
1414                      rt61pci_init_bbp(rt2x00dev)))
1415                 return -EIO;
1416
1417         /*
1418          * Enable RX.
1419          */
1420         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1421         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1422         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1423
1424         return 0;
1425 }
1426
1427 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1428 {
1429         u32 reg;
1430
1431         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1432
1433         /*
1434          * Disable synchronisation.
1435          */
1436         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1437
1438         /*
1439          * Cancel RX and TX.
1440          */
1441         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1442         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1443         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1444         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1445         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1446         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1447 }
1448
1449 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1450 {
1451         u32 reg;
1452         unsigned int i;
1453         char put_to_sleep;
1454
1455         put_to_sleep = (state != STATE_AWAKE);
1456
1457         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1458         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1459         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1460         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1461
1462         /*
1463          * Device is not guaranteed to be in the requested state yet.
1464          * We must wait until the register indicates that the
1465          * device has entered the correct state.
1466          */
1467         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1468                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1469                 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1470                 if (state == !put_to_sleep)
1471                         return 0;
1472                 msleep(10);
1473         }
1474
1475         return -EBUSY;
1476 }
1477
1478 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1479                                     enum dev_state state)
1480 {
1481         int retval = 0;
1482
1483         switch (state) {
1484         case STATE_RADIO_ON:
1485                 retval = rt61pci_enable_radio(rt2x00dev);
1486                 break;
1487         case STATE_RADIO_OFF:
1488                 rt61pci_disable_radio(rt2x00dev);
1489                 break;
1490         case STATE_RADIO_RX_ON:
1491         case STATE_RADIO_RX_ON_LINK:
1492         case STATE_RADIO_RX_OFF:
1493         case STATE_RADIO_RX_OFF_LINK:
1494                 rt61pci_toggle_rx(rt2x00dev, state);
1495                 break;
1496         case STATE_RADIO_IRQ_ON:
1497         case STATE_RADIO_IRQ_OFF:
1498                 rt61pci_toggle_irq(rt2x00dev, state);
1499                 break;
1500         case STATE_DEEP_SLEEP:
1501         case STATE_SLEEP:
1502         case STATE_STANDBY:
1503         case STATE_AWAKE:
1504                 retval = rt61pci_set_state(rt2x00dev, state);
1505                 break;
1506         default:
1507                 retval = -ENOTSUPP;
1508                 break;
1509         }
1510
1511         if (unlikely(retval))
1512                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1513                       state, retval);
1514
1515         return retval;
1516 }
1517
1518 /*
1519  * TX descriptor initialization
1520  */
1521 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1522                                     struct sk_buff *skb,
1523                                     struct txentry_desc *txdesc)
1524 {
1525         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1526         __le32 *txd = skbdesc->desc;
1527         u32 word;
1528
1529         /*
1530          * Start writing the descriptor words.
1531          */
1532         rt2x00_desc_read(txd, 1, &word);
1533         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1534         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1535         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1536         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1537         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1538         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1539         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1540         rt2x00_desc_write(txd, 1, word);
1541
1542         rt2x00_desc_read(txd, 2, &word);
1543         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1544         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1545         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1546         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1547         rt2x00_desc_write(txd, 2, word);
1548
1549         rt2x00_desc_read(txd, 5, &word);
1550         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1551         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1552                            skbdesc->entry->entry_idx);
1553         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1554                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1555         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1556         rt2x00_desc_write(txd, 5, word);
1557
1558         rt2x00_desc_read(txd, 6, &word);
1559         rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1560                            skbdesc->skb_dma);
1561         rt2x00_desc_write(txd, 6, word);
1562
1563         if (skbdesc->desc_len > TXINFO_SIZE) {
1564                 rt2x00_desc_read(txd, 11, &word);
1565                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
1566                 rt2x00_desc_write(txd, 11, word);
1567         }
1568
1569         rt2x00_desc_read(txd, 0, &word);
1570         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1571         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1572         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1573                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1574         rt2x00_set_field32(&word, TXD_W0_ACK,
1575                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1576         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1577                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1578         rt2x00_set_field32(&word, TXD_W0_OFDM,
1579                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1580         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1581         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1582                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1583         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1584         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1585         rt2x00_set_field32(&word, TXD_W0_BURST,
1586                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1587         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1588         rt2x00_desc_write(txd, 0, word);
1589 }
1590
1591 /*
1592  * TX data initialization
1593  */
1594 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1595                                   const enum data_queue_qid queue)
1596 {
1597         u32 reg;
1598
1599         if (queue == QID_BEACON) {
1600                 /*
1601                  * For Wi-Fi faily generated beacons between participating
1602                  * stations. Set TBTT phase adaptive adjustment step to 8us.
1603                  */
1604                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1605
1606                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1607                 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1608                         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1609                         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1610                         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1611                         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1612                 }
1613                 return;
1614         }
1615
1616         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1617         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1618         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1619         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1620         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1621         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1622 }
1623
1624 /*
1625  * RX control handlers
1626  */
1627 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1628 {
1629         u16 eeprom;
1630         u8 offset;
1631         u8 lna;
1632
1633         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1634         switch (lna) {
1635         case 3:
1636                 offset = 90;
1637                 break;
1638         case 2:
1639                 offset = 74;
1640                 break;
1641         case 1:
1642                 offset = 64;
1643                 break;
1644         default:
1645                 return 0;
1646         }
1647
1648         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1649                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1650                         offset += 14;
1651
1652                 if (lna == 3 || lna == 2)
1653                         offset += 10;
1654
1655                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1656                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1657         } else {
1658                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1659                         offset += 14;
1660
1661                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1662                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1663         }
1664
1665         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1666 }
1667
1668 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1669                                 struct rxdone_entry_desc *rxdesc)
1670 {
1671         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1672         u32 word0;
1673         u32 word1;
1674
1675         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1676         rt2x00_desc_read(entry_priv->desc, 1, &word1);
1677
1678         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1679                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1680
1681         /*
1682          * Obtain the status about this packet.
1683          * When frame was received with an OFDM bitrate,
1684          * the signal is the PLCP value. If it was received with
1685          * a CCK bitrate the signal is the rate in 100kbit/s.
1686          */
1687         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1688         rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1689         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1690
1691         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1692                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1693         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1694                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1695 }
1696
1697 /*
1698  * Interrupt functions.
1699  */
1700 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1701 {
1702         struct data_queue *queue;
1703         struct queue_entry *entry;
1704         struct queue_entry *entry_done;
1705         struct queue_entry_priv_pci *entry_priv;
1706         struct txdone_entry_desc txdesc;
1707         u32 word;
1708         u32 reg;
1709         u32 old_reg;
1710         int type;
1711         int index;
1712
1713         /*
1714          * During each loop we will compare the freshly read
1715          * STA_CSR4 register value with the value read from
1716          * the previous loop. If the 2 values are equal then
1717          * we should stop processing because the chance it
1718          * quite big that the device has been unplugged and
1719          * we risk going into an endless loop.
1720          */
1721         old_reg = 0;
1722
1723         while (1) {
1724                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1725                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1726                         break;
1727
1728                 if (old_reg == reg)
1729                         break;
1730                 old_reg = reg;
1731
1732                 /*
1733                  * Skip this entry when it contains an invalid
1734                  * queue identication number.
1735                  */
1736                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1737                 queue = rt2x00queue_get_queue(rt2x00dev, type);
1738                 if (unlikely(!queue))
1739                         continue;
1740
1741                 /*
1742                  * Skip this entry when it contains an invalid
1743                  * index number.
1744                  */
1745                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1746                 if (unlikely(index >= queue->limit))
1747                         continue;
1748
1749                 entry = &queue->entries[index];
1750                 entry_priv = entry->priv_data;
1751                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1752
1753                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1754                     !rt2x00_get_field32(word, TXD_W0_VALID))
1755                         return;
1756
1757                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1758                 while (entry != entry_done) {
1759                         /* Catch up.
1760                          * Just report any entries we missed as failed.
1761                          */
1762                         WARNING(rt2x00dev,
1763                                 "TX status report missed for entry %d\n",
1764                                 entry_done->entry_idx);
1765
1766                         txdesc.flags = 0;
1767                         __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
1768                         txdesc.retry = 0;
1769
1770                         rt2x00lib_txdone(entry_done, &txdesc);
1771                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1772                 }
1773
1774                 /*
1775                  * Obtain the status about this packet.
1776                  */
1777                 txdesc.flags = 0;
1778                 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
1779                 case 0: /* Success, maybe with retry */
1780                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1781                         break;
1782                 case 6: /* Failure, excessive retries */
1783                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1784                         /* Don't break, this is a failed frame! */
1785                 default: /* Failure */
1786                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1787                 }
1788                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1789
1790                 rt2x00lib_txdone(entry, &txdesc);
1791         }
1792 }
1793
1794 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1795 {
1796         struct rt2x00_dev *rt2x00dev = dev_instance;
1797         u32 reg_mcu;
1798         u32 reg;
1799
1800         /*
1801          * Get the interrupt sources & saved to local variable.
1802          * Write register value back to clear pending interrupts.
1803          */
1804         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1805         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1806
1807         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1808         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1809
1810         if (!reg && !reg_mcu)
1811                 return IRQ_NONE;
1812
1813         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1814                 return IRQ_HANDLED;
1815
1816         /*
1817          * Handle interrupts, walk through all bits
1818          * and run the tasks, the bits are checked in order of
1819          * priority.
1820          */
1821
1822         /*
1823          * 1 - Rx ring done interrupt.
1824          */
1825         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1826                 rt2x00pci_rxdone(rt2x00dev);
1827
1828         /*
1829          * 2 - Tx ring done interrupt.
1830          */
1831         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1832                 rt61pci_txdone(rt2x00dev);
1833
1834         /*
1835          * 3 - Handle MCU command done.
1836          */
1837         if (reg_mcu)
1838                 rt2x00pci_register_write(rt2x00dev,
1839                                          M2H_CMD_DONE_CSR, 0xffffffff);
1840
1841         return IRQ_HANDLED;
1842 }
1843
1844 /*
1845  * Device probe functions.
1846  */
1847 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1848 {
1849         struct eeprom_93cx6 eeprom;
1850         u32 reg;
1851         u16 word;
1852         u8 *mac;
1853         s8 value;
1854
1855         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1856
1857         eeprom.data = rt2x00dev;
1858         eeprom.register_read = rt61pci_eepromregister_read;
1859         eeprom.register_write = rt61pci_eepromregister_write;
1860         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1861             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1862         eeprom.reg_data_in = 0;
1863         eeprom.reg_data_out = 0;
1864         eeprom.reg_data_clock = 0;
1865         eeprom.reg_chip_select = 0;
1866
1867         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1868                                EEPROM_SIZE / sizeof(u16));
1869
1870         /*
1871          * Start validation of the data that has been read.
1872          */
1873         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1874         if (!is_valid_ether_addr(mac)) {
1875                 DECLARE_MAC_BUF(macbuf);
1876
1877                 random_ether_addr(mac);
1878                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1879         }
1880
1881         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1882         if (word == 0xffff) {
1883                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1884                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1885                                    ANTENNA_B);
1886                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1887                                    ANTENNA_B);
1888                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1889                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1890                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1891                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1892                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1893                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1894         }
1895
1896         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1897         if (word == 0xffff) {
1898                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1899                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1900                 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1901                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1902                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1903                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1904                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1905                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1906         }
1907
1908         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1909         if (word == 0xffff) {
1910                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1911                                    LED_MODE_DEFAULT);
1912                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1913                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1914         }
1915
1916         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1917         if (word == 0xffff) {
1918                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1919                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1920                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1921                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1922         }
1923
1924         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1925         if (word == 0xffff) {
1926                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1927                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1928                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1929                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1930         } else {
1931                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1932                 if (value < -10 || value > 10)
1933                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1934                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1935                 if (value < -10 || value > 10)
1936                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1937                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1938         }
1939
1940         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1941         if (word == 0xffff) {
1942                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1943                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1944                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1945                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1946         } else {
1947                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1948                 if (value < -10 || value > 10)
1949                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1950                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1951                 if (value < -10 || value > 10)
1952                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1953                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1954         }
1955
1956         return 0;
1957 }
1958
1959 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1960 {
1961         u32 reg;
1962         u16 value;
1963         u16 eeprom;
1964         u16 device;
1965
1966         /*
1967          * Read EEPROM word for configuration.
1968          */
1969         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1970
1971         /*
1972          * Identify RF chipset.
1973          * To determine the RT chip we have to read the
1974          * PCI header of the device.
1975          */
1976         pci_read_config_word(to_pci_dev(rt2x00dev->dev),
1977                              PCI_CONFIG_HEADER_DEVICE, &device);
1978         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1979         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1980         rt2x00_set_chip(rt2x00dev, device, value, reg);
1981
1982         if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1983             !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1984             !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1985             !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1986                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1987                 return -ENODEV;
1988         }
1989
1990         /*
1991          * Determine number of antenna's.
1992          */
1993         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1994                 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1995
1996         /*
1997          * Identify default antenna configuration.
1998          */
1999         rt2x00dev->default_ant.tx =
2000             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2001         rt2x00dev->default_ant.rx =
2002             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2003
2004         /*
2005          * Read the Frame type.
2006          */
2007         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2008                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2009
2010         /*
2011          * Detect if this device has an hardware controlled radio.
2012          */
2013 #ifdef CONFIG_RT61PCI_RFKILL
2014         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2015                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2016 #endif /* CONFIG_RT61PCI_RFKILL */
2017
2018         /*
2019          * Read frequency offset and RF programming sequence.
2020          */
2021         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2022         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2023                 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2024
2025         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2026
2027         /*
2028          * Read external LNA informations.
2029          */
2030         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2031
2032         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2033                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2034         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2035                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2036
2037         /*
2038          * When working with a RF2529 chip without double antenna
2039          * the antenna settings should be gathered from the NIC
2040          * eeprom word.
2041          */
2042         if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2043             !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2044                 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2045                 case 0:
2046                         rt2x00dev->default_ant.tx = ANTENNA_B;
2047                         rt2x00dev->default_ant.rx = ANTENNA_A;
2048                         break;
2049                 case 1:
2050                         rt2x00dev->default_ant.tx = ANTENNA_B;
2051                         rt2x00dev->default_ant.rx = ANTENNA_B;
2052                         break;
2053                 case 2:
2054                         rt2x00dev->default_ant.tx = ANTENNA_A;
2055                         rt2x00dev->default_ant.rx = ANTENNA_A;
2056                         break;
2057                 case 3:
2058                         rt2x00dev->default_ant.tx = ANTENNA_A;
2059                         rt2x00dev->default_ant.rx = ANTENNA_B;
2060                         break;
2061                 }
2062
2063                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2064                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2065                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2066                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2067         }
2068
2069         /*
2070          * Store led settings, for correct led behaviour.
2071          * If the eeprom value is invalid,
2072          * switch to default led mode.
2073          */
2074 #ifdef CONFIG_RT61PCI_LEDS
2075         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2076         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2077
2078         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2079         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2080         if (value == LED_MODE_SIGNAL_STRENGTH)
2081                 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2082                                  LED_TYPE_QUALITY);
2083
2084         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2085         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2086                            rt2x00_get_field16(eeprom,
2087                                               EEPROM_LED_POLARITY_GPIO_0));
2088         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2089                            rt2x00_get_field16(eeprom,
2090                                               EEPROM_LED_POLARITY_GPIO_1));
2091         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2092                            rt2x00_get_field16(eeprom,
2093                                               EEPROM_LED_POLARITY_GPIO_2));
2094         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2095                            rt2x00_get_field16(eeprom,
2096                                               EEPROM_LED_POLARITY_GPIO_3));
2097         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2098                            rt2x00_get_field16(eeprom,
2099                                               EEPROM_LED_POLARITY_GPIO_4));
2100         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2101                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2102         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2103                            rt2x00_get_field16(eeprom,
2104                                               EEPROM_LED_POLARITY_RDY_G));
2105         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2106                            rt2x00_get_field16(eeprom,
2107                                               EEPROM_LED_POLARITY_RDY_A));
2108 #endif /* CONFIG_RT61PCI_LEDS */
2109
2110         return 0;
2111 }
2112
2113 /*
2114  * RF value list for RF5225 & RF5325
2115  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2116  */
2117 static const struct rf_channel rf_vals_noseq[] = {
2118         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2119         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2120         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2121         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2122         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2123         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2124         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2125         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2126         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2127         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2128         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2129         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2130         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2131         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2132
2133         /* 802.11 UNI / HyperLan 2 */
2134         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2135         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2136         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2137         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2138         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2139         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2140         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2141         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2142
2143         /* 802.11 HyperLan 2 */
2144         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2145         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2146         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2147         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2148         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2149         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2150         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2151         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2152         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2153         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2154
2155         /* 802.11 UNII */
2156         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2157         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2158         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2159         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2160         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2161         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2162
2163         /* MMAC(Japan)J52 ch 34,38,42,46 */
2164         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2165         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2166         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2167         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2168 };
2169
2170 /*
2171  * RF value list for RF5225 & RF5325
2172  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2173  */
2174 static const struct rf_channel rf_vals_seq[] = {
2175         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2176         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2177         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2178         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2179         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2180         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2181         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2182         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2183         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2184         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2185         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2186         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2187         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2188         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2189
2190         /* 802.11 UNI / HyperLan 2 */
2191         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2192         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2193         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2194         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2195         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2196         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2197         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2198         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2199
2200         /* 802.11 HyperLan 2 */
2201         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2202         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2203         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2204         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2205         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2206         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2207         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2208         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2209         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2210         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2211
2212         /* 802.11 UNII */
2213         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2214         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2215         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2216         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2217         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2218         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2219
2220         /* MMAC(Japan)J52 ch 34,38,42,46 */
2221         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2222         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2223         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2224         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2225 };
2226
2227 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2228 {
2229         struct hw_mode_spec *spec = &rt2x00dev->spec;
2230         u8 *txpower;
2231         unsigned int i;
2232
2233         /*
2234          * Initialize all hw fields.
2235          */
2236         rt2x00dev->hw->flags =
2237             IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2238             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2239             IEEE80211_HW_SIGNAL_DBM;
2240         rt2x00dev->hw->extra_tx_headroom = 0;
2241
2242         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2243         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2244                                 rt2x00_eeprom_addr(rt2x00dev,
2245                                                    EEPROM_MAC_ADDR_0));
2246
2247         /*
2248          * Convert tx_power array in eeprom.
2249          */
2250         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2251         for (i = 0; i < 14; i++)
2252                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2253
2254         /*
2255          * Initialize hw_mode information.
2256          */
2257         spec->supported_bands = SUPPORT_BAND_2GHZ;
2258         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2259         spec->tx_power_a = NULL;
2260         spec->tx_power_bg = txpower;
2261         spec->tx_power_default = DEFAULT_TXPOWER;
2262
2263         if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2264                 spec->num_channels = 14;
2265                 spec->channels = rf_vals_noseq;
2266         } else {
2267                 spec->num_channels = 14;
2268                 spec->channels = rf_vals_seq;
2269         }
2270
2271         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2272             rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2273                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2274                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2275
2276                 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2277                 for (i = 0; i < 14; i++)
2278                         txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2279
2280                 spec->tx_power_a = txpower;
2281         }
2282 }
2283
2284 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2285 {
2286         int retval;
2287
2288         /*
2289          * Allocate eeprom data.
2290          */
2291         retval = rt61pci_validate_eeprom(rt2x00dev);
2292         if (retval)
2293                 return retval;
2294
2295         retval = rt61pci_init_eeprom(rt2x00dev);
2296         if (retval)
2297                 return retval;
2298
2299         /*
2300          * Initialize hw specifications.
2301          */
2302         rt61pci_probe_hw_mode(rt2x00dev);
2303
2304         /*
2305          * This device requires firmware and DMA mapped skbs.
2306          */
2307         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2308         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2309
2310         /*
2311          * Set the rssi offset.
2312          */
2313         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2314
2315         return 0;
2316 }
2317
2318 /*
2319  * IEEE80211 stack callback functions.
2320  */
2321 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2322                                    u32 short_retry, u32 long_retry)
2323 {
2324         struct rt2x00_dev *rt2x00dev = hw->priv;
2325         u32 reg;
2326
2327         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2328         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2329         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2330         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2331
2332         return 0;
2333 }
2334
2335 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2336 {
2337         struct rt2x00_dev *rt2x00dev = hw->priv;
2338         u64 tsf;
2339         u32 reg;
2340
2341         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2342         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2343         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2344         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2345
2346         return tsf;
2347 }
2348
2349 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
2350 {
2351         struct rt2x00_dev *rt2x00dev = hw->priv;
2352         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2353         struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
2354         struct queue_entry_priv_pci *entry_priv;
2355         struct skb_frame_desc *skbdesc;
2356         struct txentry_desc txdesc;
2357         unsigned int beacon_base;
2358         u32 reg;
2359
2360         if (unlikely(!intf->beacon))
2361                 return -ENOBUFS;
2362
2363         /*
2364          * Copy all TX descriptor information into txdesc,
2365          * after that we are free to use the skb->cb array
2366          * for our information.
2367          */
2368         intf->beacon->skb = skb;
2369         rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
2370
2371         entry_priv = intf->beacon->priv_data;
2372         memset(entry_priv->desc, 0, intf->beacon->queue->desc_size);
2373
2374         /*
2375          * Fill in skb descriptor
2376          */
2377         skbdesc = get_skb_frame_desc(skb);
2378         memset(skbdesc, 0, sizeof(*skbdesc));
2379         skbdesc->desc = entry_priv->desc;
2380         skbdesc->desc_len = intf->beacon->queue->desc_size;
2381         skbdesc->entry = intf->beacon;
2382
2383         /*
2384          * Disable beaconing while we are reloading the beacon data,
2385          * otherwise we might be sending out invalid data.
2386          */
2387         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2388         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2389         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2390         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2391         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2392
2393         /*
2394          * Write entire beacon with descriptor to register,
2395          * and kick the beacon generator.
2396          */
2397         rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
2398         beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2399         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
2400                                       skbdesc->desc, skbdesc->desc_len);
2401         rt2x00pci_register_multiwrite(rt2x00dev,
2402                                       beacon_base + skbdesc->desc_len,
2403                                       skb->data, skb->len);
2404         rt61pci_kick_tx_queue(rt2x00dev, QID_BEACON);
2405
2406         /*
2407          * Clean up beacon skb.
2408          */
2409         dev_kfree_skb_any(skb);
2410         intf->beacon->skb = NULL;
2411
2412         return 0;
2413 }
2414
2415 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2416         .tx                     = rt2x00mac_tx,
2417         .start                  = rt2x00mac_start,
2418         .stop                   = rt2x00mac_stop,
2419         .add_interface          = rt2x00mac_add_interface,
2420         .remove_interface       = rt2x00mac_remove_interface,
2421         .config                 = rt2x00mac_config,
2422         .config_interface       = rt2x00mac_config_interface,
2423         .configure_filter       = rt2x00mac_configure_filter,
2424         .get_stats              = rt2x00mac_get_stats,
2425         .set_retry_limit        = rt61pci_set_retry_limit,
2426         .bss_info_changed       = rt2x00mac_bss_info_changed,
2427         .conf_tx                = rt2x00mac_conf_tx,
2428         .get_tx_stats           = rt2x00mac_get_tx_stats,
2429         .get_tsf                = rt61pci_get_tsf,
2430 };
2431
2432 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2433         .irq_handler            = rt61pci_interrupt,
2434         .probe_hw               = rt61pci_probe_hw,
2435         .get_firmware_name      = rt61pci_get_firmware_name,
2436         .get_firmware_crc       = rt61pci_get_firmware_crc,
2437         .load_firmware          = rt61pci_load_firmware,
2438         .initialize             = rt2x00pci_initialize,
2439         .uninitialize           = rt2x00pci_uninitialize,
2440         .init_rxentry           = rt61pci_init_rxentry,
2441         .init_txentry           = rt61pci_init_txentry,
2442         .set_device_state       = rt61pci_set_device_state,
2443         .rfkill_poll            = rt61pci_rfkill_poll,
2444         .link_stats             = rt61pci_link_stats,
2445         .reset_tuner            = rt61pci_reset_tuner,
2446         .link_tuner             = rt61pci_link_tuner,
2447         .write_tx_desc          = rt61pci_write_tx_desc,
2448         .write_tx_data          = rt2x00pci_write_tx_data,
2449         .kick_tx_queue          = rt61pci_kick_tx_queue,
2450         .fill_rxdone            = rt61pci_fill_rxdone,
2451         .beacon_update          = rt61pci_beacon_update,
2452         .config_filter          = rt61pci_config_filter,
2453         .config_intf            = rt61pci_config_intf,
2454         .config_erp             = rt61pci_config_erp,
2455         .config                 = rt61pci_config,
2456 };
2457
2458 static const struct data_queue_desc rt61pci_queue_rx = {
2459         .entry_num              = RX_ENTRIES,
2460         .data_size              = DATA_FRAME_SIZE,
2461         .desc_size              = RXD_DESC_SIZE,
2462         .priv_size              = sizeof(struct queue_entry_priv_pci),
2463 };
2464
2465 static const struct data_queue_desc rt61pci_queue_tx = {
2466         .entry_num              = TX_ENTRIES,
2467         .data_size              = DATA_FRAME_SIZE,
2468         .desc_size              = TXD_DESC_SIZE,
2469         .priv_size              = sizeof(struct queue_entry_priv_pci),
2470 };
2471
2472 static const struct data_queue_desc rt61pci_queue_bcn = {
2473         .entry_num              = 4 * BEACON_ENTRIES,
2474         .data_size              = 0, /* No DMA required for beacons */
2475         .desc_size              = TXINFO_SIZE,
2476         .priv_size              = sizeof(struct queue_entry_priv_pci),
2477 };
2478
2479 static const struct rt2x00_ops rt61pci_ops = {
2480         .name           = KBUILD_MODNAME,
2481         .max_sta_intf   = 1,
2482         .max_ap_intf    = 4,
2483         .eeprom_size    = EEPROM_SIZE,
2484         .rf_size        = RF_SIZE,
2485         .tx_queues      = NUM_TX_QUEUES,
2486         .rx             = &rt61pci_queue_rx,
2487         .tx             = &rt61pci_queue_tx,
2488         .bcn            = &rt61pci_queue_bcn,
2489         .lib            = &rt61pci_rt2x00_ops,
2490         .hw             = &rt61pci_mac80211_ops,
2491 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2492         .debugfs        = &rt61pci_rt2x00debug,
2493 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2494 };
2495
2496 /*
2497  * RT61pci module information.
2498  */
2499 static struct pci_device_id rt61pci_device_table[] = {
2500         /* RT2561s */
2501         { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2502         /* RT2561 v2 */
2503         { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2504         /* RT2661 */
2505         { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2506         { 0, }
2507 };
2508
2509 MODULE_AUTHOR(DRV_PROJECT);
2510 MODULE_VERSION(DRV_VERSION);
2511 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2512 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2513                         "PCI & PCMCIA chipset based cards");
2514 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2515 MODULE_FIRMWARE(FIRMWARE_RT2561);
2516 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2517 MODULE_FIRMWARE(FIRMWARE_RT2661);
2518 MODULE_LICENSE("GPL");
2519
2520 static struct pci_driver rt61pci_driver = {
2521         .name           = KBUILD_MODNAME,
2522         .id_table       = rt61pci_device_table,
2523         .probe          = rt2x00pci_probe,
2524         .remove         = __devexit_p(rt2x00pci_remove),
2525         .suspend        = rt2x00pci_suspend,
2526         .resume         = rt2x00pci_resume,
2527 };
2528
2529 static int __init rt61pci_init(void)
2530 {
2531         return pci_register_driver(&rt61pci_driver);
2532 }
2533
2534 static void __exit rt61pci_exit(void)
2535 {
2536         pci_unregister_driver(&rt61pci_driver);
2537 }
2538
2539 module_init(rt61pci_init);
2540 module_exit(rt61pci_exit);