Merge branch 'master' into export-slabh
[kernel.git] / drivers / video / sunxvr500.c
1 /* sunxvr500.c: Sun 3DLABS XVR-500 Expert3D driver for sparc64 systems
2  *
3  * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4  */
5
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/fb.h>
9 #include <linux/pci.h>
10 #include <linux/init.h>
11 #include <linux/of_device.h>
12
13 #include <asm/io.h>
14
15 /* XXX This device has a 'dev-comm' property which aparently is
16  * XXX a pointer into the openfirmware's address space which is
17  * XXX a shared area the kernel driver can use to keep OBP
18  * XXX informed about the current resolution setting.  The idea
19  * XXX is that the kernel can change resolutions, and as long
20  * XXX as the values in the 'dev-comm' area are accurate then
21  * XXX OBP can still render text properly to the console.
22  * XXX
23  * XXX I'm still working out the layout of this and whether there
24  * XXX are any signatures we need to look for etc.
25  */
26 struct e3d_info {
27         struct fb_info          *info;
28         struct pci_dev          *pdev;
29
30         spinlock_t              lock;
31
32         char __iomem            *fb_base;
33         unsigned long           fb_base_phys;
34
35         unsigned long           fb8_buf_diff;
36         unsigned long           regs_base_phys;
37
38         void __iomem            *ramdac;
39
40         struct device_node      *of_node;
41
42         unsigned int            width;
43         unsigned int            height;
44         unsigned int            depth;
45         unsigned int            fb_size;
46
47         u32                     fb_base_reg;
48         u32                     fb8_0_off;
49         u32                     fb8_1_off;
50
51         u32                     pseudo_palette[16];
52 };
53
54 static int __devinit e3d_get_props(struct e3d_info *ep)
55 {
56         ep->width = of_getintprop_default(ep->of_node, "width", 0);
57         ep->height = of_getintprop_default(ep->of_node, "height", 0);
58         ep->depth = of_getintprop_default(ep->of_node, "depth", 8);
59
60         if (!ep->width || !ep->height) {
61                 printk(KERN_ERR "e3d: Critical properties missing for %s\n",
62                        pci_name(ep->pdev));
63                 return -EINVAL;
64         }
65
66         return 0;
67 }
68
69 /* My XVR-500 comes up, at 1280x768 and a FB base register value of
70  * 0x04000000, the following video layout register values:
71  *
72  * RAMDAC_VID_WH        0x03ff04ff
73  * RAMDAC_VID_CFG       0x1a0b0088
74  * RAMDAC_VID_32FB_0    0x04000000
75  * RAMDAC_VID_32FB_1    0x04800000
76  * RAMDAC_VID_8FB_0     0x05000000
77  * RAMDAC_VID_8FB_1     0x05200000
78  * RAMDAC_VID_XXXFB     0x05400000
79  * RAMDAC_VID_YYYFB     0x05c00000
80  * RAMDAC_VID_ZZZFB     0x05e00000
81  */
82 /* Video layout registers */
83 #define RAMDAC_VID_WH           0x00000070UL /* (height-1)<<16 | (width-1) */
84 #define RAMDAC_VID_CFG          0x00000074UL /* 0x1a000088|(linesz_log2<<16) */
85 #define RAMDAC_VID_32FB_0       0x00000078UL /* PCI base 32bpp FB buffer 0 */
86 #define RAMDAC_VID_32FB_1       0x0000007cUL /* PCI base 32bpp FB buffer 1 */
87 #define RAMDAC_VID_8FB_0        0x00000080UL /* PCI base 8bpp FB buffer 0 */
88 #define RAMDAC_VID_8FB_1        0x00000084UL /* PCI base 8bpp FB buffer 1 */
89 #define RAMDAC_VID_XXXFB        0x00000088UL /* PCI base of XXX FB */
90 #define RAMDAC_VID_YYYFB        0x0000008cUL /* PCI base of YYY FB */
91 #define RAMDAC_VID_ZZZFB        0x00000090UL /* PCI base of ZZZ FB */
92
93 /* CLUT registers */
94 #define RAMDAC_INDEX            0x000000bcUL
95 #define RAMDAC_DATA             0x000000c0UL
96
97 static void e3d_clut_write(struct e3d_info *ep, int index, u32 val)
98 {
99         void __iomem *ramdac = ep->ramdac;
100         unsigned long flags;
101
102         spin_lock_irqsave(&ep->lock, flags);
103
104         writel(index, ramdac + RAMDAC_INDEX);
105         writel(val, ramdac + RAMDAC_DATA);
106
107         spin_unlock_irqrestore(&ep->lock, flags);
108 }
109
110 static int e3d_setcolreg(unsigned regno,
111                          unsigned red, unsigned green, unsigned blue,
112                          unsigned transp, struct fb_info *info)
113 {
114         struct e3d_info *ep = info->par;
115         u32 red_8, green_8, blue_8;
116         u32 red_10, green_10, blue_10;
117         u32 value;
118
119         if (regno >= 256)
120                 return 1;
121
122         red_8 = red >> 8;
123         green_8 = green >> 8;
124         blue_8 = blue >> 8;
125
126         value = (blue_8 << 24) | (green_8 << 16) | (red_8 << 8);
127
128         if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16)
129                 ((u32 *)info->pseudo_palette)[regno] = value;
130
131
132         red_10 = red >> 6;
133         green_10 = green >> 6;
134         blue_10 = blue >> 6;
135
136         value = (blue_10 << 20) | (green_10 << 10) | (red_10 << 0);
137         e3d_clut_write(ep, regno, value);
138
139         return 0;
140 }
141
142 /* XXX This is a bit of a hack.  I can't figure out exactly how the
143  * XXX two 8bpp areas of the framebuffer work.  I imagine there is
144  * XXX a WID attribute somewhere else in the framebuffer which tells
145  * XXX the ramdac which of the two 8bpp framebuffer regions to take
146  * XXX the pixel from.  So, for now, render into both regions to make
147  * XXX sure the pixel shows up.
148  */
149 static void e3d_imageblit(struct fb_info *info, const struct fb_image *image)
150 {
151         struct e3d_info *ep = info->par;
152         unsigned long flags;
153
154         spin_lock_irqsave(&ep->lock, flags);
155         cfb_imageblit(info, image);
156         info->screen_base += ep->fb8_buf_diff;
157         cfb_imageblit(info, image);
158         info->screen_base -= ep->fb8_buf_diff;
159         spin_unlock_irqrestore(&ep->lock, flags);
160 }
161
162 static void e3d_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
163 {
164         struct e3d_info *ep = info->par;
165         unsigned long flags;
166
167         spin_lock_irqsave(&ep->lock, flags);
168         cfb_fillrect(info, rect);
169         info->screen_base += ep->fb8_buf_diff;
170         cfb_fillrect(info, rect);
171         info->screen_base -= ep->fb8_buf_diff;
172         spin_unlock_irqrestore(&ep->lock, flags);
173 }
174
175 static void e3d_copyarea(struct fb_info *info, const struct fb_copyarea *area)
176 {
177         struct e3d_info *ep = info->par;
178         unsigned long flags;
179
180         spin_lock_irqsave(&ep->lock, flags);
181         cfb_copyarea(info, area);
182         info->screen_base += ep->fb8_buf_diff;
183         cfb_copyarea(info, area);
184         info->screen_base -= ep->fb8_buf_diff;
185         spin_unlock_irqrestore(&ep->lock, flags);
186 }
187
188 static struct fb_ops e3d_ops = {
189         .owner                  = THIS_MODULE,
190         .fb_setcolreg           = e3d_setcolreg,
191         .fb_fillrect            = e3d_fillrect,
192         .fb_copyarea            = e3d_copyarea,
193         .fb_imageblit           = e3d_imageblit,
194 };
195
196 static int __devinit e3d_set_fbinfo(struct e3d_info *ep)
197 {
198         struct fb_info *info = ep->info;
199         struct fb_var_screeninfo *var = &info->var;
200
201         info->flags = FBINFO_DEFAULT;
202         info->fbops = &e3d_ops;
203         info->screen_base = ep->fb_base;
204         info->screen_size = ep->fb_size;
205
206         info->pseudo_palette = ep->pseudo_palette;
207
208         /* Fill fix common fields */
209         strlcpy(info->fix.id, "e3d", sizeof(info->fix.id));
210         info->fix.smem_start = ep->fb_base_phys;
211         info->fix.smem_len = ep->fb_size;
212         info->fix.type = FB_TYPE_PACKED_PIXELS;
213         if (ep->depth == 32 || ep->depth == 24)
214                 info->fix.visual = FB_VISUAL_TRUECOLOR;
215         else
216                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
217
218         var->xres = ep->width;
219         var->yres = ep->height;
220         var->xres_virtual = var->xres;
221         var->yres_virtual = var->yres;
222         var->bits_per_pixel = ep->depth;
223
224         var->red.offset = 8;
225         var->red.length = 8;
226         var->green.offset = 16;
227         var->green.length = 8;
228         var->blue.offset = 24;
229         var->blue.length = 8;
230         var->transp.offset = 0;
231         var->transp.length = 0;
232
233         if (fb_alloc_cmap(&info->cmap, 256, 0)) {
234                 printk(KERN_ERR "e3d: Cannot allocate color map.\n");
235                 return -ENOMEM;
236         }
237
238         return 0;
239 }
240
241 static int __devinit e3d_pci_register(struct pci_dev *pdev,
242                                       const struct pci_device_id *ent)
243 {
244         struct device_node *of_node;
245         const char *device_type;
246         struct fb_info *info;
247         struct e3d_info *ep;
248         unsigned int line_length;
249         int err;
250
251         of_node = pci_device_to_OF_node(pdev);
252         if (!of_node) {
253                 printk(KERN_ERR "e3d: Cannot find OF node of %s\n",
254                        pci_name(pdev));
255                 return -ENODEV;
256         }
257
258         device_type = of_get_property(of_node, "device_type", NULL);
259         if (!device_type) {
260                 printk(KERN_INFO "e3d: Ignoring secondary output device "
261                        "at %s\n", pci_name(pdev));
262                 return -ENODEV;
263         }
264
265         err = pci_enable_device(pdev);
266         if (err < 0) {
267                 printk(KERN_ERR "e3d: Cannot enable PCI device %s\n",
268                        pci_name(pdev));
269                 goto err_out;
270         }
271
272         info = framebuffer_alloc(sizeof(struct e3d_info), &pdev->dev);
273         if (!info) {
274                 printk(KERN_ERR "e3d: Cannot allocate fb_info\n");
275                 err = -ENOMEM;
276                 goto err_disable;
277         }
278
279         ep = info->par;
280         ep->info = info;
281         ep->pdev = pdev;
282         spin_lock_init(&ep->lock);
283         ep->of_node = of_node;
284
285         /* Read the PCI base register of the frame buffer, which we
286          * need in order to interpret the RAMDAC_VID_*FB* values in
287          * the ramdac correctly.
288          */
289         pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
290                               &ep->fb_base_reg);
291         ep->fb_base_reg &= PCI_BASE_ADDRESS_MEM_MASK;
292
293         ep->regs_base_phys = pci_resource_start (pdev, 1);
294         err = pci_request_region(pdev, 1, "e3d regs");
295         if (err < 0) {
296                 printk("e3d: Cannot request region 1 for %s\n",
297                        pci_name(pdev));
298                 goto err_release_fb;
299         }
300         ep->ramdac = ioremap(ep->regs_base_phys + 0x8000, 0x1000);
301         if (!ep->ramdac)
302                 goto err_release_pci1;
303
304         ep->fb8_0_off = readl(ep->ramdac + RAMDAC_VID_8FB_0);
305         ep->fb8_0_off -= ep->fb_base_reg;
306
307         ep->fb8_1_off = readl(ep->ramdac + RAMDAC_VID_8FB_1);
308         ep->fb8_1_off -= ep->fb_base_reg;
309
310         ep->fb8_buf_diff = ep->fb8_1_off - ep->fb8_0_off;
311
312         ep->fb_base_phys = pci_resource_start (pdev, 0);
313         ep->fb_base_phys += ep->fb8_0_off;
314
315         err = pci_request_region(pdev, 0, "e3d framebuffer");
316         if (err < 0) {
317                 printk("e3d: Cannot request region 0 for %s\n",
318                        pci_name(pdev));
319                 goto err_unmap_ramdac;
320         }
321
322         err = e3d_get_props(ep);
323         if (err)
324                 goto err_release_pci0;
325
326         line_length = (readl(ep->ramdac + RAMDAC_VID_CFG) >> 16) & 0xff;
327         line_length = 1 << line_length;
328
329         switch (ep->depth) {
330         case 8:
331                 info->fix.line_length = line_length;
332                 break;
333         case 16:
334                 info->fix.line_length = line_length * 2;
335                 break;
336         case 24:
337                 info->fix.line_length = line_length * 3;
338                 break;
339         case 32:
340                 info->fix.line_length = line_length * 4;
341                 break;
342         }
343         ep->fb_size = info->fix.line_length * ep->height;
344
345         ep->fb_base = ioremap(ep->fb_base_phys, ep->fb_size);
346         if (!ep->fb_base)
347                 goto err_release_pci0;
348
349         err = e3d_set_fbinfo(ep);
350         if (err)
351                 goto err_unmap_fb;
352
353         pci_set_drvdata(pdev, info);
354
355         printk("e3d: Found device at %s\n", pci_name(pdev));
356
357         err = register_framebuffer(info);
358         if (err < 0) {
359                 printk(KERN_ERR "e3d: Could not register framebuffer %s\n",
360                        pci_name(pdev));
361                 goto err_free_cmap;
362         }
363
364         return 0;
365
366 err_free_cmap:
367         fb_dealloc_cmap(&info->cmap);
368
369 err_unmap_fb:
370         iounmap(ep->fb_base);
371
372 err_release_pci0:
373         pci_release_region(pdev, 0);
374
375 err_unmap_ramdac:
376         iounmap(ep->ramdac);
377
378 err_release_pci1:
379         pci_release_region(pdev, 1);
380
381 err_release_fb:
382         framebuffer_release(info);
383
384 err_disable:
385         pci_disable_device(pdev);
386
387 err_out:
388         return err;
389 }
390
391 static void __devexit e3d_pci_unregister(struct pci_dev *pdev)
392 {
393         struct fb_info *info = pci_get_drvdata(pdev);
394         struct e3d_info *ep = info->par;
395
396         unregister_framebuffer(info);
397
398         iounmap(ep->ramdac);
399         iounmap(ep->fb_base);
400
401         pci_release_region(pdev, 0);
402         pci_release_region(pdev, 1);
403
404         fb_dealloc_cmap(&info->cmap);
405         framebuffer_release(info);
406
407         pci_disable_device(pdev);
408 }
409
410 static struct pci_device_id e3d_pci_table[] = {
411         {       PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a0),        },
412         {       PCI_DEVICE(0x1091, 0x7a0),                      },
413         {       PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a2),        },
414         {       .vendor = PCI_VENDOR_ID_3DLABS,
415                 .device = PCI_ANY_ID,
416                 .subvendor = PCI_VENDOR_ID_3DLABS,
417                 .subdevice = 0x0108,
418         },
419         {       .vendor = PCI_VENDOR_ID_3DLABS,
420                 .device = PCI_ANY_ID,
421                 .subvendor = PCI_VENDOR_ID_3DLABS,
422                 .subdevice = 0x0140,
423         },
424         {       .vendor = PCI_VENDOR_ID_3DLABS,
425                 .device = PCI_ANY_ID,
426                 .subvendor = PCI_VENDOR_ID_3DLABS,
427                 .subdevice = 0x1024,
428         },
429         { 0, }
430 };
431
432 static struct pci_driver e3d_driver = {
433         .name           = "e3d",
434         .id_table       = e3d_pci_table,
435         .probe          = e3d_pci_register,
436         .remove         = __devexit_p(e3d_pci_unregister),
437 };
438
439 static int __init e3d_init(void)
440 {
441         if (fb_get_options("e3d", NULL))
442                 return -ENODEV;
443
444         return pci_register_driver(&e3d_driver);
445 }
446
447 static void __exit e3d_exit(void)
448 {
449         pci_unregister_driver(&e3d_driver);
450 }
451
452 module_init(e3d_init);
453 module_exit(e3d_exit);
454
455 MODULE_DESCRIPTION("framebuffer driver for Sun XVR-500 graphics");
456 MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
457 MODULE_VERSION("1.0");
458 MODULE_LICENSE("GPL");