3398bd9aab1199a859559bc5acf7d99300cf6e5c
[kernel.git] / include / linux / mfd / pcf50633 / core.h
1 /*
2  * core.h  -- Core driver for NXP PCF50633
3  *
4  * (C) 2006-2008 by Openmoko, Inc.
5  * All rights reserved.
6  *
7  * This program is free software; you can redistribute  it and/or modify it
8  * under  the terms of  the GNU General  Public License as published by the
9  * Free Software Foundation;  either version 2 of the  License, or (at your
10  * option) any later version.
11  */
12
13 #ifndef __LINUX_MFD_PCF50633_CORE_H
14 #define __LINUX_MFD_PCF50633_CORE_H
15
16 #include <linux/i2c.h>
17 #include <linux/workqueue.h>
18 #include <linux/regulator/driver.h>
19 #include <linux/regulator/machine.h>
20 #include <linux/power_supply.h>
21
22 struct pcf50633;
23
24 #define PCF50633_NUM_REGULATORS 11
25
26 struct pcf50633_platform_data {
27         struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS];
28
29         char **batteries;
30         int num_batteries;
31
32         /*
33          * Should be set accordingly to the reference resistor used, see
34          * I_{ch(ref)} charger reference current in the pcf50633 User
35          * Manual.
36          */
37         int charger_reference_current_ma;
38
39         /* Callbacks */
40         void (*probe_done)(struct pcf50633 *);
41         void (*mbc_event_callback)(struct pcf50633 *, int);
42         void (*regulator_registered)(struct pcf50633 *, int);
43         void (*force_shutdown)(struct pcf50633 *);
44
45         u8 resumers[5];
46 };
47
48 struct pcf50633_irq {
49         void (*handler) (int, void *);
50         void *data;
51 };
52
53 int pcf50633_register_irq(struct pcf50633 *pcf, int irq,
54                         void (*handler) (int, void *), void *data);
55 int pcf50633_free_irq(struct pcf50633 *pcf, int irq);
56
57 int pcf50633_irq_mask(struct pcf50633 *pcf, int irq);
58 int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq);
59 int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq);
60
61 int pcf50633_read_block(struct pcf50633 *, u8 reg,
62                                         int nr_regs, u8 *data);
63 int pcf50633_write_block(struct pcf50633 *pcf, u8 reg,
64                                         int nr_regs, u8 *data);
65 u8 pcf50633_reg_read(struct pcf50633 *, u8 reg);
66 int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val);
67
68 int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val);
69 int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits);
70
71 /* Interrupt registers */
72
73 #define PCF50633_REG_INT1       0x02
74 #define PCF50633_REG_INT2       0x03
75 #define PCF50633_REG_INT3       0x04
76 #define PCF50633_REG_INT4       0x05
77 #define PCF50633_REG_INT5       0x06
78
79 #define PCF50633_REG_INT1M      0x07
80 #define PCF50633_REG_INT2M      0x08
81 #define PCF50633_REG_INT3M      0x09
82 #define PCF50633_REG_INT4M      0x0a
83 #define PCF50633_REG_INT5M      0x0b
84
85 enum {
86         /* Chip IRQs */
87         PCF50633_IRQ_ADPINS,
88         PCF50633_IRQ_ADPREM,
89         PCF50633_IRQ_USBINS,
90         PCF50633_IRQ_USBREM,
91         PCF50633_IRQ_RESERVED1,
92         PCF50633_IRQ_RESERVED2,
93         PCF50633_IRQ_ALARM,
94         PCF50633_IRQ_SECOND,
95         PCF50633_IRQ_ONKEYR,
96         PCF50633_IRQ_ONKEYF,
97         PCF50633_IRQ_EXTON1R,
98         PCF50633_IRQ_EXTON1F,
99         PCF50633_IRQ_EXTON2R,
100         PCF50633_IRQ_EXTON2F,
101         PCF50633_IRQ_EXTON3R,
102         PCF50633_IRQ_EXTON3F,
103         PCF50633_IRQ_BATFULL,
104         PCF50633_IRQ_CHGHALT,
105         PCF50633_IRQ_THLIMON,
106         PCF50633_IRQ_THLIMOFF,
107         PCF50633_IRQ_USBLIMON,
108         PCF50633_IRQ_USBLIMOFF,
109         PCF50633_IRQ_ADCRDY,
110         PCF50633_IRQ_ONKEY1S,
111         PCF50633_IRQ_LOWSYS,
112         PCF50633_IRQ_LOWBAT,
113         PCF50633_IRQ_HIGHTMP,
114         PCF50633_IRQ_AUTOPWRFAIL,
115         PCF50633_IRQ_DWN1PWRFAIL,
116         PCF50633_IRQ_DWN2PWRFAIL,
117         PCF50633_IRQ_LEDPWRFAIL,
118         PCF50633_IRQ_LEDOVP,
119         PCF50633_IRQ_LDO1PWRFAIL,
120         PCF50633_IRQ_LDO2PWRFAIL,
121         PCF50633_IRQ_LDO3PWRFAIL,
122         PCF50633_IRQ_LDO4PWRFAIL,
123         PCF50633_IRQ_LDO5PWRFAIL,
124         PCF50633_IRQ_LDO6PWRFAIL,
125         PCF50633_IRQ_HCLDOPWRFAIL,
126         PCF50633_IRQ_HCLDOOVL,
127
128         /* Always last */
129         PCF50633_NUM_IRQ,
130 };
131
132 struct pcf50633 {
133         struct device *dev;
134         struct i2c_client *i2c_client;
135
136         struct pcf50633_platform_data *pdata;
137         int irq;
138         struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ];
139         struct work_struct irq_work;
140         struct workqueue_struct *work_queue;
141         struct mutex lock;
142
143         u8 mask_regs[5];
144
145         u8 suspend_irq_masks[5];
146         u8 resume_reason[5];
147         int is_suspended;
148
149         int onkey1s_held;
150
151         struct platform_device *rtc_pdev;
152         struct platform_device *mbc_pdev;
153         struct platform_device *adc_pdev;
154         struct platform_device *input_pdev;
155         struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS];
156 };
157
158 enum pcf50633_reg_int1 {
159         PCF50633_INT1_ADPINS    = 0x01, /* Adapter inserted */
160         PCF50633_INT1_ADPREM    = 0x02, /* Adapter removed */
161         PCF50633_INT1_USBINS    = 0x04, /* USB inserted */
162         PCF50633_INT1_USBREM    = 0x08, /* USB removed */
163         /* reserved */
164         PCF50633_INT1_ALARM     = 0x40, /* RTC alarm time is reached */
165         PCF50633_INT1_SECOND    = 0x80, /* RTC periodic second interrupt */
166 };
167
168 enum pcf50633_reg_int2 {
169         PCF50633_INT2_ONKEYR    = 0x01, /* ONKEY rising edge */
170         PCF50633_INT2_ONKEYF    = 0x02, /* ONKEY falling edge */
171         PCF50633_INT2_EXTON1R   = 0x04, /* EXTON1 rising edge */
172         PCF50633_INT2_EXTON1F   = 0x08, /* EXTON1 falling edge */
173         PCF50633_INT2_EXTON2R   = 0x10, /* EXTON2 rising edge */
174         PCF50633_INT2_EXTON2F   = 0x20, /* EXTON2 falling edge */
175         PCF50633_INT2_EXTON3R   = 0x40, /* EXTON3 rising edge */
176         PCF50633_INT2_EXTON3F   = 0x80, /* EXTON3 falling edge */
177 };
178
179 enum pcf50633_reg_int3 {
180         PCF50633_INT3_BATFULL   = 0x01, /* Battery full */
181         PCF50633_INT3_CHGHALT   = 0x02, /* Charger halt */
182         PCF50633_INT3_THLIMON   = 0x04,
183         PCF50633_INT3_THLIMOFF  = 0x08,
184         PCF50633_INT3_USBLIMON  = 0x10,
185         PCF50633_INT3_USBLIMOFF = 0x20,
186         PCF50633_INT3_ADCRDY    = 0x40, /* ADC result ready */
187         PCF50633_INT3_ONKEY1S   = 0x80, /* ONKEY pressed 1 second */
188 };
189
190 enum pcf50633_reg_int4 {
191         PCF50633_INT4_LOWSYS            = 0x01,
192         PCF50633_INT4_LOWBAT            = 0x02,
193         PCF50633_INT4_HIGHTMP           = 0x04,
194         PCF50633_INT4_AUTOPWRFAIL       = 0x08,
195         PCF50633_INT4_DWN1PWRFAIL       = 0x10,
196         PCF50633_INT4_DWN2PWRFAIL       = 0x20,
197         PCF50633_INT4_LEDPWRFAIL        = 0x40,
198         PCF50633_INT4_LEDOVP            = 0x80,
199 };
200
201 enum pcf50633_reg_int5 {
202         PCF50633_INT5_LDO1PWRFAIL       = 0x01,
203         PCF50633_INT5_LDO2PWRFAIL       = 0x02,
204         PCF50633_INT5_LDO3PWRFAIL       = 0x04,
205         PCF50633_INT5_LDO4PWRFAIL       = 0x08,
206         PCF50633_INT5_LDO5PWRFAIL       = 0x10,
207         PCF50633_INT5_LDO6PWRFAIL       = 0x20,
208         PCF50633_INT5_HCLDOPWRFAIL      = 0x40,
209         PCF50633_INT5_HCLDOOVL          = 0x80,
210 };
211
212 /* misc. registers */
213 #define PCF50633_REG_OOCSHDWN   0x0c
214
215 /* LED registers */
216 #define PCF50633_REG_LEDOUT 0x28
217 #define PCF50633_REG_LEDENA 0x29
218 #define PCF50633_REG_LEDCTL 0x2a
219 #define PCF50633_REG_LEDDIM 0x2b
220
221 static inline struct pcf50633 *dev_to_pcf50633(struct device *dev)
222 {
223         return dev_get_drvdata(dev);
224 }
225
226 #endif