diff options
| author | Chris Dearman <chris@mips.com> | 2007-05-24 22:46:25 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-06-14 18:25:15 +0100 |
| commit | 7b4f4ec21038ac13c63d130357d1c3015ec3f3e8 (patch) | |
| tree | ce5a28d2a2949a0de36605403a68166be00fb075 | |
| parent | ffe9ee4709cf513fb80e9b7e04d214dd8b76a10d (diff) | |
[MIPS] Fix builds where MSC01E_xxx is undefined.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/mips-boards/generic/time.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index 33432ea188f..8f1000f51b3 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -295,11 +295,14 @@ void __init plat_perf_setup(struct irqaction *irq) void __init plat_timer_setup(struct irqaction *irq) { int hwint = 0; +#ifdef MSC01E_INT_BASE if (cpu_has_veic) { set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; } - else { + else +#endif + { if (cpu_has_mips_r2) /* * Read IntCtl.IPTI to determine the timer interrupt |