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authorSteven Whitehouse <swhiteho@redhat.com>2006-06-06 10:31:26 -0400
committerSteven Whitehouse <swhiteho@redhat.com>2006-06-06 10:31:26 -0400
commit4b01abc977574253f466f65463019de2571c6401 (patch)
treec330615fe9f277ad51a91da3db2d690a3336fb02 /arch/arm/mm/proc-xsc3.S
parent47c96298cd0b04b4478206fde55fd6a6431de980 (diff)
parent1def630a6a49dda5bc89dfbd86656293640456f0 (diff)
Merge branch 'master'
Diffstat (limited to 'arch/arm/mm/proc-xsc3.S')
-rw-r--r--arch/arm/mm/proc-xsc3.S3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 80873b36c3f..8d32e21fe15 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -427,12 +427,13 @@ __xsc3_setup:
#endif
mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
mrc p15, 0, r0, c1, c0, 0 @ get control register
- bic r0, r0, #0x0200 @ .... ..R. .... ....
bic r0, r0, #0x0002 @ .... .... .... ..A.
orr r0, r0, #0x0005 @ .... .... .... .C.M
#if BTB_ENABLE
+ bic r0, r0, #0x0200 @ .... ..R. .... ....
orr r0, r0, #0x3900 @ ..VI Z..S .... ....
#else
+ bic r0, r0, #0x0a00 @ .... Z.R. .... ....
orr r0, r0, #0x3100 @ ..VI ...S .... ....
#endif
#if L2_CACHE_ENABLE