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authorBen Dooks <ben-linux@fluff.org>2010-01-26 11:07:23 +0900
committerBen Dooks <ben-linux@fluff.org>2010-02-20 22:32:00 +0000
commited618aff8a952f712caf1d475e0947a32a8b6606 (patch)
treed106f5b5c24e42c6498c3a8a7340ba74ba62a4a3 /arch/arm/plat-s3c64xx
parent3501c9ae9fc5414d09c9a8d3a5452d2b167db916 (diff)
ARM: S3C64XX: Move IRQ support into mach-s3c64xx
Move IRQ support to mach-s3c64xx as it is unlikely to be re-used outside this machine. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c64xx')
-rw-r--r--arch/arm/plat-s3c64xx/Makefile3
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/irqs.h214
-rw-r--r--arch/arm/plat-s3c64xx/irq-eint.c213
-rw-r--r--arch/arm/plat-s3c64xx/irq-pm.c111
-rw-r--r--arch/arm/plat-s3c64xx/irq.c69
5 files changed, 0 insertions, 610 deletions
diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile
index 80255a5e178..3e52dcdb364 100644
--- a/arch/arm/plat-s3c64xx/Makefile
+++ b/arch/arm/plat-s3c64xx/Makefile
@@ -15,8 +15,6 @@ obj- :=
obj-y += dev-uart.o
obj-y += dev-rtc.o
obj-y += cpu.o
-obj-y += irq.o
-obj-y += irq-eint.o
obj-y += clock.o
obj-y += gpiolib.o
@@ -30,7 +28,6 @@ obj-$(CONFIG_CPU_FREQ_S3C64XX) += cpufreq.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM) += sleep.o
-obj-$(CONFIG_PM) += irq-pm.o
# DMA support
diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h
deleted file mode 100644
index a22758194e6..00000000000
--- a/arch/arm/plat-s3c64xx/include/plat/irqs.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/* linux/arch/arm/plat-s3c64xx/include/mach/irqs.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C64XX - Common IRQ support
- */
-
-#ifndef __ASM_PLAT_S3C64XX_IRQS_H
-#define __ASM_PLAT_S3C64XX_IRQS_H __FILE__
-
-/* we keep the first set of CPU IRQs out of the range of
- * the ISA space, so that the PC104 has them to itself
- * and we don't end up having to do horrible things to the
- * standard ISA drivers....
- *
- * note, since we're using the VICs, our start must be a
- * mulitple of 32 to allow the common code to work
- */
-
-#define S3C_IRQ_OFFSET (32)
-
-#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
-
-#define IRQ_VIC0_BASE S3C_IRQ(0)
-#define IRQ_VIC1_BASE S3C_IRQ(32)
-
-/* UART interrupts, each UART has 4 intterupts per channel so
- * use the space between the ISA and S3C main interrupts. Note, these
- * are not in the same order as the S3C24XX series! */
-
-#define IRQ_S3CUART_BASE0 (16)
-#define IRQ_S3CUART_BASE1 (20)
-#define IRQ_S3CUART_BASE2 (24)
-#define IRQ_S3CUART_BASE3 (28)
-
-#define UART_IRQ_RXD (0)
-#define UART_IRQ_ERR (1)
-#define UART_IRQ_TXD (2)
-#define UART_IRQ_MODEM (3)
-
-#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
-#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
-#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
-
-#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
-#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
-#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
-
-#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
-#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
-#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
-
-#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
-#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
-#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
-
-/* VIC based IRQs */
-
-#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x))
-#define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x))
-
-/* VIC0 */
-
-#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0)
-#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1)
-#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2)
-#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3)
-#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4)
-#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5)
-#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5)
-#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6)
-#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6)
-#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7)
-#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8)
-#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8)
-#define IRQ_POST0 S3C64XX_IRQ_VIC0(9)
-#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10)
-#define IRQ_2D S3C64XX_IRQ_VIC0(11)
-#define IRQ_TVENC S3C64XX_IRQ_VIC0(12)
-#define IRQ_SCALER S3C64XX_IRQ_VIC0(13)
-#define IRQ_BATF S3C64XX_IRQ_VIC0(14)
-#define IRQ_JPEG S3C64XX_IRQ_VIC0(15)
-#define IRQ_MFC S3C64XX_IRQ_VIC0(16)
-#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17)
-#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18)
-#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19)
-#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20)
-#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21)
-#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22)
-#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23)
-#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24)
-#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25)
-#define IRQ_WDT S3C64XX_IRQ_VIC0(26)
-#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27)
-#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28)
-#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29)
-#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30)
-#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31)
-
-/* VIC1 */
-
-#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0)
-#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1)
-#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2)
-#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3)
-#define IRQ_AC97 S3C64XX_IRQ_VIC1(4)
-#define IRQ_UART0 S3C64XX_IRQ_VIC1(5)
-#define IRQ_UART1 S3C64XX_IRQ_VIC1(6)
-#define IRQ_UART2 S3C64XX_IRQ_VIC1(7)
-#define IRQ_UART3 S3C64XX_IRQ_VIC1(8)
-#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9)
-#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10)
-#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11)
-#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12)
-#define IRQ_NFC S3C64XX_IRQ_VIC1(13)
-#define IRQ_CFCON S3C64XX_IRQ_VIC1(14)
-#define IRQ_USBH S3C64XX_IRQ_VIC1(15)
-#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16)
-#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17)
-#define IRQ_IIC S3C64XX_IRQ_VIC1(18)
-#define IRQ_HSItx S3C64XX_IRQ_VIC1(19)
-#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20)
-#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21)
-#define IRQ_MSM S3C64XX_IRQ_VIC1(22)
-#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23)
-#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24)
-#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25)
-#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
-#define IRQ_OTG S3C64XX_IRQ_VIC1(26)
-#define IRQ_IRDA S3C64XX_IRQ_VIC1(27)
-#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28)
-#define IRQ_SEC S3C64XX_IRQ_VIC1(29)
-#define IRQ_PENDN S3C64XX_IRQ_VIC1(30)
-#define IRQ_TC IRQ_PENDN
-#define IRQ_ADC S3C64XX_IRQ_VIC1(31)
-
-#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x))
-
-#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0)
-#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1)
-#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2)
-#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3)
-#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4)
-
-/* compatibility for device defines */
-
-#define IRQ_IIC1 IRQ_S3C6410_IIC1
-
-/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
- * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
- * which we place after the pair of VICs. */
-
-#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5)
-
-#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE)
-#define IRQ_EINT(x) S3C_EINT(x)
-#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0))
-
-/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
- * that they are sourced from the GPIO pins but with a different scheme for
- * priority and source indication.
- *
- * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
- * interrupts, but for historical reasons they are kept apart from these
- * next interrupts.
- *
- * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
- * machine specific support files.
- */
-
-#define IRQ_EINT_GROUP1_NR (15)
-#define IRQ_EINT_GROUP2_NR (8)
-#define IRQ_EINT_GROUP3_NR (5)
-#define IRQ_EINT_GROUP4_NR (14)
-#define IRQ_EINT_GROUP5_NR (7)
-#define IRQ_EINT_GROUP6_NR (10)
-#define IRQ_EINT_GROUP7_NR (16)
-#define IRQ_EINT_GROUP8_NR (15)
-#define IRQ_EINT_GROUP9_NR (9)
-
-#define IRQ_EINT_GROUP_BASE S3C_EINT(28)
-#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00)
-#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
-#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
-#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
-#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
-#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
-#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
-#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
-#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
-
-#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no))
-
-/* Define a group of interrupts for board-specific use (eg, for MFD
- * interrupt controllers). */
-#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
-
-#ifdef CONFIG_SMDK6410_WM1190_EV1
-#define IRQ_BOARD_NR 64
-#else
-#define IRQ_BOARD_NR 16
-#endif
-
-#define IRQ_BOARD_END (IRQ_BOARD_START + IRQ_BOARD_NR)
-
-/* Set the default NR_IRQS */
-
-#define NR_IRQS (IRQ_BOARD_END + 1)
-
-#endif /* __ASM_PLAT_S3C64XX_IRQS_H */
-
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c
deleted file mode 100644
index 5682d6a7f4a..00000000000
--- a/arch/arm/plat-s3c64xx/irq-eint.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/* arch/arm/plat-s3c64xx/irq-eint.c
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C64XX - Interrupt handling for IRQ_EINT(x)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/sysdev.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <asm/hardware/vic.h>
-
-#include <plat/regs-irqtype.h>
-#include <mach/regs-gpio.h>
-#include <plat/gpio-cfg.h>
-
-#include <mach/map.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
-
-#define eint_offset(irq) ((irq) - IRQ_EINT(0))
-#define eint_irq_to_bit(irq) (1 << eint_offset(irq))
-
-static inline void s3c_irq_eint_mask(unsigned int irq)
-{
- u32 mask;
-
- mask = __raw_readl(S3C64XX_EINT0MASK);
- mask |= eint_irq_to_bit(irq);
- __raw_writel(mask, S3C64XX_EINT0MASK);
-}
-
-static void s3c_irq_eint_unmask(unsigned int irq)
-{
- u32 mask;
-
- mask = __raw_readl(S3C64XX_EINT0MASK);
- mask &= ~eint_irq_to_bit(irq);
- __raw_writel(mask, S3C64XX_EINT0MASK);
-}
-
-static inline void s3c_irq_eint_ack(unsigned int irq)
-{
- __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND);
-}
-
-static void s3c_irq_eint_maskack(unsigned int irq)
-{
- /* compiler should in-line these */
- s3c_irq_eint_mask(irq);
- s3c_irq_eint_ack(irq);
-}
-
-static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
-{
- int offs = eint_offset(irq);
- int pin, pin_val;
- int shift;
- u32 ctrl, mask;
- u32 newvalue = 0;
- void __iomem *reg;
-
- if (offs > 27)
- return -EINVAL;
-
- if (offs <= 15)
- reg = S3C64XX_EINT0CON0;
- else
- reg = S3C64XX_EINT0CON1;
-
- switch (type) {
- case IRQ_TYPE_NONE:
- printk(KERN_WARNING "No edge setting!\n");
- break;
-
- case IRQ_TYPE_EDGE_RISING:
- newvalue = S3C2410_EXTINT_RISEEDGE;
- break;
-
- case IRQ_TYPE_EDGE_FALLING:
- newvalue = S3C2410_EXTINT_FALLEDGE;
- break;
-
- case IRQ_TYPE_EDGE_BOTH:
- newvalue = S3C2410_EXTINT_BOTHEDGE;
- break;
-
- case IRQ_TYPE_LEVEL_LOW:
- newvalue = S3C2410_EXTINT_LOWLEV;
- break;
-
- case IRQ_TYPE_LEVEL_HIGH:
- newvalue = S3C2410_EXTINT_HILEV;
- break;
-
- default:
- printk(KERN_ERR "No such irq type %d", type);
- return -1;
- }
-
- if (offs <= 15)
- shift = (offs / 2) * 4;
- else
- shift = ((offs - 16) / 2) * 4;
- mask = 0x7 << shift;
-
- ctrl = __raw_readl(reg);
- ctrl &= ~mask;
- ctrl |= newvalue << shift;
- __raw_writel(ctrl, reg);
-
- /* set the GPIO pin appropriately */
-
- if (offs < 16) {
- pin = S3C64XX_GPN(offs);
- pin_val = S3C_GPIO_SFN(2);
- } else if (offs < 23) {
- pin = S3C64XX_GPL(offs + 8 - 16);
- pin_val = S3C_GPIO_SFN(3);
- } else {
- pin = S3C64XX_GPM(offs - 23);
- pin_val = S3C_GPIO_SFN(3);
- }
-
- s3c_gpio_cfgpin(pin, pin_val);
-
- return 0;
-}
-
-static struct irq_chip s3c_irq_eint = {
- .name = "s3c-eint",
- .mask = s3c_irq_eint_mask,
- .unmask = s3c_irq_eint_unmask,
- .mask_ack = s3c_irq_eint_maskack,
- .ack = s3c_irq_eint_ack,
- .set_type = s3c_irq_eint_set_type,
- .set_wake = s3c_irqext_wake,
-};
-
-/* s3c_irq_demux_eint
- *
- * This function demuxes the IRQ from the group0 external interrupts,
- * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
- * the specific handlers s3c_irq_demux_eintX_Y.
- */
-static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
-{
- u32 status = __raw_readl(S3C64XX_EINT0PEND);
- u32 mask = __raw_readl(S3C64XX_EINT0MASK);
- unsigned int irq;
-
- status &= ~mask;
- status >>= start;
- status &= (1 << (end - start + 1)) - 1;
-
- for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
- if (status & 1)
- generic_handle_irq(irq);
-
- status >>= 1;
- }
-}
-
-static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
-{
- s3c_irq_demux_eint(0, 3);
-}
-
-static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
-{
- s3c_irq_demux_eint(4, 11);
-}
-
-static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
-{
- s3c_irq_demux_eint(12, 19);
-}
-
-static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
-{
- s3c_irq_demux_eint(20, 27);
-}
-
-static int __init s3c64xx_init_irq_eint(void)
-{
- int irq;
-
- for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
- set_irq_chip(irq, &s3c_irq_eint);
- set_irq_handler(irq, handle_level_irq);
- set_irq_flags(irq, IRQF_VALID);
- }
-
- set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
- set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
- set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
- set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
-
- return 0;
-}
-
-arch_initcall(s3c64xx_init_irq_eint);
diff --git a/arch/arm/plat-s3c64xx/irq-pm.c b/arch/arm/plat-s3c64xx/irq-pm.c
deleted file mode 100644
index da1bec64b9d..00000000000
--- a/arch/arm/plat-s3c64xx/irq-pm.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* arch/arm/plat-s3c64xx/irq-pm.c
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C64XX - Interrupt handling Power Management
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/sysdev.h>
-#include <linux/interrupt.h>
-#include <linux/serial_core.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <mach/map.h>
-
-#include <plat/regs-serial.h>
-#include <plat/regs-timer.h>
-#include <mach/regs-gpio.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
-
-/* We handled all the IRQ types in this code, to save having to make several
- * small files to handle each different type separately. Having the EINT_GRP
- * code here shouldn't be as much bloat as the IRQ table space needed when
- * they are enabled. The added benefit is we ensure that these registers are
- * in the same state as we suspended.
- */
-
-static struct sleep_save irq_save[] = {
- SAVE_ITEM(S3C64XX_PRIORITY),
- SAVE_ITEM(S3C64XX_EINT0CON0),
- SAVE_ITEM(S3C64XX_EINT0CON1),
- SAVE_ITEM(S3C64XX_EINT0FLTCON0),
- SAVE_ITEM(S3C64XX_EINT0FLTCON1),
- SAVE_ITEM(S3C64XX_EINT0FLTCON2),
- SAVE_ITEM(S3C64XX_EINT0FLTCON3),
- SAVE_ITEM(S3C64XX_EINT0MASK),
- SAVE_ITEM(S3C64XX_TINT_CSTAT),
-};
-
-static struct irq_grp_save {
- u32 fltcon;
- u32 con;
- u32 mask;
-} eint_grp_save[5];
-
-static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
-
-static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state)
-{
- struct irq_grp_save *grp = eint_grp_save;
- int i;
-
- S3C_PMDBG("%s: suspending IRQs\n", __func__);
-
- s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
-
- for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
- irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
-
- for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
- grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4));
- grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4));
- grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4));
- }
-
- return 0;
-}
-
-static int s3c64xx_irq_pm_resume(struct sys_device *dev)
-{
- struct irq_grp_save *grp = eint_grp_save;
- int i;
-
- S3C_PMDBG("%s: resuming IRQs\n", __func__);
-
- s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
-
- for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
- __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
-
- for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
- __raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4));
- __raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4));
- __raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4));
- }
-
- S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
- return 0;
-}
-
-static struct sysdev_driver s3c64xx_irq_driver = {
- .suspend = s3c64xx_irq_pm_suspend,
- .resume = s3c64xx_irq_pm_resume,
-};
-
-static int __init s3c64xx_irq_pm_init(void)
-{
- return sysdev_driver_register(&s3c64xx_sysclass, &s3c64xx_irq_driver);
-}
-
-arch_initcall(s3c64xx_irq_pm_init);
-
diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c
deleted file mode 100644
index 67a145d440f..00000000000
--- a/arch/arm/plat-s3c64xx/irq.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* arch/arm/plat-s3c64xx/irq.c
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C64XX - Interrupt handling
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/serial_core.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <asm/hardware/vic.h>
-
-#include <mach/map.h>
-#include <plat/irq-vic-timer.h>
-#include <plat/irq-uart.h>
-#include <plat/cpu.h>
-
-static struct s3c_uart_irq uart_irqs[] = {
- [0] = {
- .regs = S3C_VA_UART0,
- .base_irq = IRQ_S3CUART_BASE0,
- .parent_irq = IRQ_UART0,
- },
- [1] = {
- .regs = S3C_VA_UART1,
- .base_irq = IRQ_S3CUART_BASE1,
- .parent_irq = IRQ_UART1,
- },
- [2] = {
- .regs = S3C_VA_UART2,
- .base_irq = IRQ_S3CUART_BASE2,
- .parent_irq = IRQ_UART2,
- },
- [3] = {
- .regs = S3C_VA_UART3,
- .base_irq = IRQ_S3CUART_BASE3,
- .parent_irq = IRQ_UART3,
- },
-};
-
-
-void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
-{
- printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
-
- /* initialise the pair of VICs */
- vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0);
- vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0);
-
- /* add the timer sub-irqs */
-
- s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
- s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
- s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
- s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
- s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
-
- s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
-}