diff options
author | merge <null@invalid> | 2008-12-12 11:56:13 +0000 |
---|---|---|
committer | Andy Green <agreen@pads.home.warmcat.com> | 2008-12-12 11:56:13 +0000 |
commit | a78452203a2a1a852ed9d7b4be5ccf5dd72b5777 (patch) | |
tree | 68cfc4c19627020468dcaef852062598748fcb04 /arch/arm/plat-s3c64xx | |
parent | de473ca893c9285ab2dd3ea82973e6f253eaec1d (diff) |
MERGE-via-pending-tracking-hist-MERGE-via-stable-tracking-MERGE-via-mokopatches-tracking-MERGE-via-master-MERGE-via-master-hist-1229078937-1229079488-1229082516-1229082771
pending-tracking-hist top was MERGE-via-stable-tracking-MERGE-via-mokopatches-tracking-MERGE-via-master-MERGE-via-master-hist-1229078937-1229079488-1229082516-1229082771 / f410ecd0cc4642ae8b0f69c15fe349ea5639f5e2 ... parent commitmessage:
From: merge <null@invalid>
MERGE-via-stable-tracking-hist-MERGE-via-mokopatches-tracking-MERGE-via-master-MERGE-via-master-hist-1229078937-1229079488-1229082516
stable-tracking-hist top was MERGE-via-mokopatches-tracking-MERGE-via-master-MERGE-via-master-hist-1229078937-1229079488-1229082516 / 18f9a76ecc30ba8eee5de0627de3e7eb049775c3 ... parent commitmessage:
From: merge <null@invalid>
MERGE-via-mokopatches-tracking-hist-MERGE-via-master-MERGE-via-master-hist-1229078937-1229079488
mokopatches-tracking-hist top was MERGE-via-master-MERGE-via-master-hist-1229078937-1229079488 / 7eb66508f95eeebbd7ad3487c5183b76524d4765 ... parent commitmessage:
From: merge <null@invalid>
MERGE-via-master-MERGE-via-master-hist-1229078937
master top was MERGE-via-master-hist-1229078937 / ff0b5902f29135a782a3bfb68e3429b86669aea4 ... parent commitmessage:
From: merge <null@invalid>
MERGE-master-patchset-edits
Diffstat (limited to 'arch/arm/plat-s3c64xx')
-rw-r--r-- | arch/arm/plat-s3c64xx/cpu.c | 5 | ||||
-rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/pm-core.h | 40 | ||||
-rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h | 25 | ||||
-rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/regs-gpio.h | 85 | ||||
-rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/regs-modem.h | 31 | ||||
-rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h | 3 | ||||
-rw-r--r-- | arch/arm/plat-s3c64xx/irq-eint.c | 1 | ||||
-rw-r--r-- | arch/arm/plat-s3c64xx/irq-pm.c | 23 | ||||
-rw-r--r-- | arch/arm/plat-s3c64xx/pm.c | 22 | ||||
-rw-r--r-- | arch/arm/plat-s3c64xx/sleep.S | 12 |
10 files changed, 218 insertions, 29 deletions
diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c index 278a04d5c57..58b39fccd15 100644 --- a/arch/arm/plat-s3c64xx/cpu.c +++ b/arch/arm/plat-s3c64xx/cpu.c @@ -98,6 +98,11 @@ static struct map_desc s3c_iodesc[] __initdata = { .pfn = __phys_to_pfn(S3C64XX_PA_GPIO), .length = SZ_4K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C64XX_VA_MODEM, + .pfn = __phys_to_pfn(S3C64XX_PA_MODEM), + .length = SZ_4K, + .type = MT_DEVICE, }, }; diff --git a/arch/arm/plat-s3c64xx/include/plat/pm-core.h b/arch/arm/plat-s3c64xx/include/plat/pm-core.h index 8906c9fd443..10d89baa4a0 100644 --- a/arch/arm/plat-s3c64xx/include/plat/pm-core.h +++ b/arch/arm/plat-s3c64xx/include/plat/pm-core.h @@ -19,7 +19,7 @@ static inline void s3c_pm_debug_init_uart(void) u32 tmp = __raw_readl(S3C_PCLK_GATE); /* As a note, since the S3C64XX UARTs generally have multiple - * clock sources, we simply enable PCLK at the momemnt and hope + * clock sources, we simply enable PCLK at the moment and hope * that the resume settings for the UART are suitable for the * use with PCLK. */ @@ -70,6 +70,7 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK; u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK; u32 new_ucon; + u32 delta; /* S3C64XX UART blocks only support level interrupts, so ensure that * when we restore unused UART blocks we force the level interrupt @@ -83,26 +84,23 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, */ if (ucon_clk != save_clk) { new_ucon = save->ucon; - new_ucon &= ~S3C6400_UCON_CLKMASK; - - /* check for illegal change of UCLK, and fixup */ - - if (ucon_clk == S3C6400_UCON_UCLK0 && - save_clk == S3C6400_UCON_PCLK2) - new_ucon |= S3C6400_UCON_PCLK; - - if (ucon_clk == S3C6400_UCON_UCLK1 && - save_clk == S3C6400_UCON_PCLK) - new_ucon |= S3C6400_UCON_PCLK2; - - if (ucon_clk == S3C6400_UCON_PCLK && - save_clk == S3C6400_UCON_PCLK2) - new_ucon |= S3C6400_UCON_PCLK; - - if (ucon_clk == S3C6400_UCON_PCLK2 && - save_clk == S3C6400_UCON_PCLK) - new_ucon |= S3C6400_UCON_PCLK2; - + delta = ucon_clk ^ save_clk; + + /* change from UCLKx => wrong PCLK, + * either UCLK can be tested for by a bit-test + * with UCLK0 */ + if (ucon_clk & S3C6400_UCON_UCLK0 && + !(save_clk & S3C6400_UCON_UCLK0) && + delta & S3C6400_UCON_PCLK2) { + new_ucon &= ~S3C6400_UCON_UCLK0; + } else if (delta == S3C6400_UCON_PCLK2) { + /* as an precaution, don't change from + * PCLK2 => PCLK or vice-versa */ + new_ucon ^= S3C6400_UCON_PCLK2; + } + + S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n", + ucon, new_ucon, save->ucon); save->ucon = new_ucon; } } diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h b/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h new file mode 100644 index 00000000000..82342f6fd27 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h @@ -0,0 +1,25 @@ +/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - GPIO memory port register definitions + */ + +#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H +#define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__ + +#define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0) +#define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4) + +#define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0) +#define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4) +#define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8) + +#define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0) +#define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4) + +#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */ + diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h index 17944803a32..81f7f6e6832 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h @@ -33,6 +33,91 @@ #define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160) #define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180) +/* SPCON */ + +#define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0) + +#define S3C64XX_SPCON_DRVCON_CAM_MASK (0x3 << 30) +#define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30) +#define S3C64XX_SPCON_DRVCON_CAM_2mA (0x0 << 30) +#define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30) +#define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30) +#define S3C64XX_SPCON_DRVCON_CAM_9mA (0x3 << 30) + +#define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0x3 << 28) +#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28) +#define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0x0 << 28) +#define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28) +#define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28) +#define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0x3 << 28) + +#define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0x3 << 26) +#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26) +#define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0x0 << 26) +#define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26) +#define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26) +#define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0x3 << 26) + +#define S3C64XX_SPCON_DRVCON_LCD_MASK (0x3 << 24) +#define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24) +#define S3C64XX_SPCON_DRVCON_LCD_2mA (0x0 << 24) +#define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24) +#define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24) +#define S3C64XX_SPCON_DRVCON_LCD_9mA (0x3 << 24) + +#define S3C64XX_SPCON_DRVCON_MODEM_MASK (0x3 << 22) +#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22) +#define S3C64XX_SPCON_DRVCON_MODEM_2mA (0x0 << 22) +#define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22) +#define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22) +#define S3C64XX_SPCON_DRVCON_MODEM_9mA (0x3 << 22) + +#define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21) + +#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0x3 << 18) +#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18) +#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0x0 << 18) +#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18) +#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18) +#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0x3 << 18) + +#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0x3 << 16) +#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16) +#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0x0 << 16) +#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16) +#define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16) + +#define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0x3 << 14) +#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14) +#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0x0 << 14) +#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14) +#define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14) + +#define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0x3 << 12) +#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12) +#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0x0 << 12) +#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12) +#define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12) + +#define S3C64XX_SPCON_MEM0_D_PUD_MASK (0x3 << 8) +#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8) +#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0x0 << 8) +#define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 << 8) +#define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8) + +#define S3C64XX_SPCON_USBH_DMPD (1 << 7) +#define S3C64XX_SPCON_USBH_DPPD (1 << 6) +#define S3C64XX_SPCON_USBH_PUSW2 (1 << 5) +#define S3C64XX_SPCON_USBH_PUSW1 (1 << 4) +#define S3C64XX_SPCON_USBH_SUSPND (1 << 3) + +#define S3C64XX_SPCON_LCD_SEL_MASK (0x3 << 0) +#define S3C64XX_SPCON_LCD_SEL_SHIFT (0) +#define S3C64XX_SPCON_LCD_SEL_HOST (0x0 << 0) +#define S3C64XX_SPCON_LCD_SEL_RGB (0x1 << 0) +#define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0) + + /* External interrupt registers */ #define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200) diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-modem.h b/arch/arm/plat-s3c64xx/include/plat/regs-modem.h new file mode 100644 index 00000000000..49f7759dedf --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-modem.h @@ -0,0 +1,31 @@ +/* arch/arm/plat-s3c64xx/include/plat/regs-modem.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C64XX - modem block registers + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_S3C64XX_REGS_MODEM_H +#define __PLAT_S3C64XX_REGS_MODEM_H __FILE__ + +#define S3C64XX_MODEMREG(x) (S3C64XX_VA_MODEM + (x)) + +#define S3C64XX_MODEM_INT2AP S3C64XX_MODEMREG(0x0) +#define S3C64XX_MODEM_INT2MODEM S3C64XX_MODEMREG(0x4) +#define S3C64XX_MODEM_MIFCON S3C64XX_MODEMREG(0x8) +#define S3C64XX_MODEM_MIFPCON S3C64XX_MODEMREG(0xC) +#define S3C64XX_MODEM_INTCLR S3C64XX_MODEMREG(0x10) +#define S3C64XX_MODEM_DMA_TXADDR S3C64XX_MODEMREG(0x14) +#define S3C64XX_MODEM_DMA_RXADDR S3C64XX_MODEMREG(0x18) + +#define MIFPCON_INT2M_LEVEL (1 << 4) +#define MIFPCON_LCD_BYPASS (1 << 3) + +#endif /* __PLAT_S3C64XX_REGS_MODEM_H */ diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h b/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h index 1b155fcb03b..270d96ac970 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h @@ -80,6 +80,9 @@ #define S3C64XX_STOPMEMCFG_IRDA_RETAIN (1 << 1) #define S3C64XX_STOPMEMCFG_NFCON_RETAIN (1 << 0) +#define S3C64XX_OSC_STABLE S3C_SYSREG(0x824) +#define S3C64XX_PWR_STABLE S3C_SYSREG(0x828) + #define S3C64XX_WAKEUP_STAT S3C_SYSREG(0x908) #define S3C64XX_WAKEUPSTAT_MMC2 (1 << 11) diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c index 7f853473df7..f9439fa0be2 100644 --- a/arch/arm/plat-s3c64xx/irq-eint.c +++ b/arch/arm/plat-s3c64xx/irq-eint.c @@ -14,6 +14,7 @@ #include <linux/kernel.h> #include <linux/interrupt.h> +#include <linux/gpio.h> #include <linux/irq.h> #include <linux/io.h> #include <linux/gpio.h> diff --git a/arch/arm/plat-s3c64xx/irq-pm.c b/arch/arm/plat-s3c64xx/irq-pm.c index fd705faf335..72e3b398751 100644 --- a/arch/arm/plat-s3c64xx/irq-pm.c +++ b/arch/arm/plat-s3c64xx/irq-pm.c @@ -5,7 +5,7 @@ * Ben Dooks <ben@simtec.co.uk> * http://armlinux.simtec.co.uk/ * - * S3C64XX - Interrupt handling Power Managment + * S3C64XX - Interrupt handling Power Management * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -30,10 +30,10 @@ #include <plat/pm.h> /* We handled all the IRQ types in this code, to save having to make several - * small files to handle each different type seperately. Having the EINT_GRP + * small files to handle each different type separately. Having the EINT_GRP * code here shouldn't be as much bloat as the IRQ table space needed when * they are enabled. The added benefit is we ensure that these registers are - * in the same state as we suspsended. + * in the same state as we suspended. */ static struct sleep_save irq_save[] = { @@ -57,6 +57,7 @@ static struct irq_grp_save { struct irq_vic_save { u32 int_select; u32 int_enable; + u32 soft_int; u32 protect; u32 vect_addr[32]; u32 vect_cntl[32]; @@ -73,8 +74,12 @@ static void s3c64xx_vic_save(void __iomem *base, struct irq_vic_save *save) save->int_select = readl(base + VIC_INT_SELECT); save->int_enable = readl(base + VIC_INT_ENABLE); + save->soft_int = readl(base + VIC_INT_SOFT); save->protect = readl(base + VIC_PROTECT); + S3C_PMDBG("%s: select=%08x, enable=%08x, protect=%08x\n", __func__, + save->int_select, save->int_enable, save->protect); + for (v = 0; v < ARRAY_SIZE(save->vect_addr); v++) { save->vect_addr[v] = readl(base + VIC_VECT_ADDR0 + (v * 4)); save->vect_cntl[v] = readl(base + VIC_VECT_CNTL0 + (v * 4)); @@ -92,6 +97,13 @@ static void s3c64xx_vic_restore(void __iomem *base, struct irq_vic_save *save) writel(save->int_enable, base + VIC_INT_ENABLE); writel(~save->int_enable, base + VIC_INT_ENABLE_CLEAR); + /* and the same for the soft-int register */ + + writel(save->soft_int, base + VIC_INT_SOFT); + writel(~save->soft_int, base + VIC_INT_SOFT_CLEAR); + + S3C_PMDBG("%s: vic int_enable=%08x\n", __func__, readl(base + VIC_INT_ENABLE)); + for (v = 0; v < ARRAY_SIZE(save->vect_addr); v++) { writel(save->vect_addr[v], base + VIC_VECT_ADDR0 + (v * 4)); writel(save->vect_cntl[v], base + VIC_VECT_CNTL0 + (v * 4)); @@ -103,7 +115,7 @@ static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state) struct irq_grp_save *grp = eint_grp_save; int i; - S3C_PMDBG("%s: suspending IRQs\n"); + S3C_PMDBG("%s: suspending IRQs\n", __func__); s3c64xx_vic_save(S3C_VA_VIC0, &irq_pm_vic0_save); s3c64xx_vic_save(S3C_VA_VIC1, &irq_pm_vic1_save); @@ -127,7 +139,7 @@ static int s3c64xx_irq_pm_resume(struct sys_device *dev) struct irq_grp_save *grp = eint_grp_save; int i; - S3C_PMDBG("%s: resuming IRQs\n"); + S3C_PMDBG("%s: resuming IRQs\n", __func__); s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); @@ -143,6 +155,7 @@ static int s3c64xx_irq_pm_resume(struct sys_device *dev) __raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4)); } + S3C_PMDBG("%s: IRQ configuration restored\n", __func__); return 0; } diff --git a/arch/arm/plat-s3c64xx/pm.c b/arch/arm/plat-s3c64xx/pm.c index 539a93b1b88..8c28e4c93ce 100644 --- a/arch/arm/plat-s3c64xx/pm.c +++ b/arch/arm/plat-s3c64xx/pm.c @@ -23,7 +23,9 @@ #include <plat/regs-sys.h> #include <plat/regs-gpio.h> #include <plat/regs-clock.h> +#include <plat/regs-modem.h> #include <plat/regs-syscon-power.h> +#include <plat/regs-gpio-memport.h> #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK #include <plat/gpio-bank-n.h> @@ -67,6 +69,9 @@ static struct sleep_save core_save[] = { SAVE_ITEM(S3C_EPLL_CON1), SAVE_ITEM(S3C_EPLL_CON0), + SAVE_ITEM(S3C64XX_MEM0DRVCON), + SAVE_ITEM(S3C64XX_MEM1DRVCON), + #ifndef CONFIG_CPU_FREQ SAVE_ITEM(S3C_APLL_CON), SAVE_ITEM(S3C_MPLL_CON), @@ -77,12 +82,20 @@ static struct sleep_save misc_save[] = { SAVE_ITEM(S3C64XX_AHB_CON0), SAVE_ITEM(S3C64XX_AHB_CON1), SAVE_ITEM(S3C64XX_AHB_CON2), + + SAVE_ITEM(S3C64XX_MODEM_MIFPCON), + SAVE_ITEM(S3C64XX_SPCON), + + SAVE_ITEM(S3C64XX_MEM0CONSTOP), + SAVE_ITEM(S3C64XX_MEM1CONSTOP), + SAVE_ITEM(S3C64XX_MEM0CONSLP0), + SAVE_ITEM(S3C64XX_MEM0CONSLP1), + SAVE_ITEM(S3C64XX_MEM1CONSLP), }; void s3c_pm_configure_extint(void) { __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK); - __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK); } void s3c_pm_restore_core(void) @@ -106,6 +119,8 @@ void s3c_pm_save_core(void) * this. */ +#include <plat/regs-gpio.h> + static void s3c64xx_cpu_suspend(void) { unsigned long tmp; @@ -117,6 +132,11 @@ static void s3c64xx_cpu_suspend(void) tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP; __raw_writel(tmp, S3C64XX_PWR_CFG); + /* clear any old wakeup */ + + __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), + S3C64XX_WAKEUP_STAT); + /* set the LED state to 0110 over sleep */ s3c_pm_debug_smdkled(3 << 1, 0xf); diff --git a/arch/arm/plat-s3c64xx/sleep.S b/arch/arm/plat-s3c64xx/sleep.S index 8b96f2f0e06..7b55ced2f22 100644 --- a/arch/arm/plat-s3c64xx/sleep.S +++ b/arch/arm/plat-s3c64xx/sleep.S @@ -47,6 +47,8 @@ ENTRY(s3c_cpu_save) mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control mrc p15, 0, r9, c1, c0, 0 @ Control register + mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register + mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls stmia r0, { r4 - r13 } @ Save CP registers and SP mov r0, #0 @@ -109,14 +111,15 @@ ENTRY(s3c_cpu_resume) #endif /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches - * are thorougly cleaned just in case the bootloader didn't do it + * are thoroughly cleaned just in case the bootloader didn't do it * for us. */ mov r0, #0 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache mcr p15, 0, r0, c7, c10, 4 @ drain write buffer - mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs + @@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs + @@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches ldr r0, s3c_sleep_save_phys ldmia r0, { r4 - r13 } @@ -126,6 +129,11 @@ ENTRY(s3c_cpu_resume) mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control + mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register + + mov r0, #0 @ restore copro access controls + mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls + mcr p15, 0, r0, c7, c5, 4 ldr r2, =resume_with_mmu mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */ |