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authorH. Peter Anvin <hpa@linux.intel.com>2009-03-18 16:54:05 -0700
committerH. Peter Anvin <hpa@linux.intel.com>2009-03-18 16:54:05 -0700
commit5f641356127712fbdce0eee120e5ce115860c17f (patch)
tree25e4fb9f3984bd2cd9621fb599e964975fad2028 /arch/frv
parentbe721696cac9d66566d59b205ee573ecb2f7c35b (diff)
x86, setup: fix the setting of 480-line VGA modes
Impact: fix rarely-used feature The VGA Miscellaneous Output Register is read from address 0x3CC but written to address 0x3C2. This was missed when this code was converted from assembly to C. While we're at it, clean up the code by making the overflow bits and the math used to set the bits explicit. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/frv')
0 files changed, 0 insertions, 0 deletions