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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-01-31 15:52:02 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-01-31 15:52:02 -0800 |
| commit | c5e18af910f4bc2e3d0732ea98b99c0fd884e73c (patch) | |
| tree | f6624e0fb83d482d4fcb265c616ae3f5e5ea53f1 /arch/mips/include/asm/mach-rc32434/irq.h | |
| parent | 878b8619f711280fd05845e21956434b5e588cc4 (diff) | |
| parent | 2d2eca4d11933bd37a4944aae06e6122efffaea8 (diff) | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (27 commits)
MIPS: Alchemy: time.c build fix
MIPS: RB532: Export rb532_gpio_set_func()
MIPS: RB532: Update headers
MIPS: RB532: Simplify dev3 init
MIPS: RB532: Remove {get,set}_434_reg()
MIPS: RB532: Move dev3 init code to devices.c
MIPS: RB532: Fix set_latch_u5()
MIPS: RB532: Fix init of rb532_dev3_ctl_res
MIPS: RB532: Use driver_data instead of platform_data
MIPS: RB532: Detect uart type, add platform device
MIPS: RB532: remove useless CF GPIO initialisation
MIPS: RB532: Auto disable GPIO alternate function
MIPS: RB532: Add set_type() function to IRQ struct.
MIPS: RC32434: Define io_map_base for PCI controller
MIPS: RB532: Fix bit swapping in rb532_set_bit()
MIPS: Use hardware watchpoints on all R1 and R2 CPUs.
MIPS: Read watch registers with interrupts disabled.
MIPS: Fix a typo in watchpoint register structure.
MIPS: TXx9: Add support for TX4939 internal RTC
MIPS: R2: Fix broken installation of cache error handler.
...
Diffstat (limited to 'arch/mips/include/asm/mach-rc32434/irq.h')
| -rw-r--r-- | arch/mips/include/asm/mach-rc32434/irq.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-rc32434/irq.h b/arch/mips/include/asm/mach-rc32434/irq.h index 56738d8ec4e..023a5b100ed 100644 --- a/arch/mips/include/asm/mach-rc32434/irq.h +++ b/arch/mips/include/asm/mach-rc32434/irq.h @@ -30,4 +30,7 @@ #define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9) #define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10) +#define GPIO_MAPPED_IRQ_BASE GROUP4_IRQ_BASE +#define GPIO_MAPPED_IRQ_GROUP 4 + #endif /* __ASM_RC32434_IRQ_H */ |