diff options
| author | Yoshinori Sato <ysato@users.sourceforge.jp> | 2006-11-05 16:15:19 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2006-12-06 10:45:36 +0900 |
| commit | de39840646a223ae13a346048c280b7c871bf56e (patch) | |
| tree | aa2449880c12310ccb92540bfd63e43e8a568745 /arch/sh/kernel/head.S | |
| parent | 0983b31849bbe1fe82520947acc1bec97c457d4b (diff) | |
sh: Exception vector rework and SH-2/SH-2A support.
This splits out common bits from the existing exception handler for
use between SH-2/SH-2A and SH-3/4, and adds support for the SH-2/2A
exceptions.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/head.S')
| -rw-r--r-- | arch/sh/kernel/head.S | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/sh/kernel/head.S b/arch/sh/kernel/head.S index f5f53d14f24..b5ff2326461 100644 --- a/arch/sh/kernel/head.S +++ b/arch/sh/kernel/head.S @@ -53,8 +53,10 @@ ENTRY(_stext) ldc r0, sr ! Initialize global interrupt mask mov #0, r0 +#ifdef CONFIG_CPU_HAS_SR_RB ldc r0, r6_bank - +#endif + /* * Prefetch if possible to reduce cache miss penalty. * @@ -71,8 +73,10 @@ ENTRY(_stext) mov #(THREAD_SIZE >> 8), r1 shll8 r1 ! r1 = THREAD_SIZE sub r1, r0 ! +#ifdef CONFIG_CPU_HAS_SR_RB ldc r0, r7_bank ! ... and initial thread_info - +#endif + ! Clear BSS area mov.l 3f, r1 add #4, r1 @@ -95,7 +99,11 @@ ENTRY(_stext) nop .balign 4 +#if defined(CONFIG_CPU_SH2) +1: .long 0x000000F0 ! IMASK=0xF +#else 1: .long 0x400080F0 ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF +#endif 2: .long init_thread_union+THREAD_SIZE 3: .long __bss_start 4: .long _end |