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authorDavide Rizzo <elpa.rizzo@gmail.com>2009-08-13 11:53:53 +0200
committerBen Dooks <ben-linux@fluff.org>2009-08-14 00:45:49 +0100
commit48ec45e725aa385d72bced73b267dfaf13351876 (patch)
treefe80cfd6e3d22d616124c7b59dba627cfaaac6f2 /arch
parenta219dc4d4463809b1be473038e7d9f3437ca452d (diff)
ARM: S3C24XX: Fix clkout mpx error
Bug correction: CLK Outputs cannot have XTAL as parent Signed-off-by: Davide Rizzo <elpa.rizzo@gmail.com> [ben-linux@fluff.org: updated patch subject] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/plat-s3c24xx/clock-dclk.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
index 5b75a797b5a..0afb217a775 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -129,7 +129,7 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
/* calculate the MISCCR setting for the clock */
- if (parent == &clk_xtal)
+ if (parent == &clk_mpll)
source = S3C2410_MISCCR_CLK0_MPLL;
else if (parent == &clk_upll)
source = S3C2410_MISCCR_CLK0_UPLL;