diff options
| author | Senthil Balasubramanian <senthilkumar@atheros.com> | 2009-02-12 13:57:03 +0530 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2009-02-27 14:51:46 -0500 |
| commit | 8bd1d07f9345750bd4d767e6c1600919672f98ba (patch) | |
| tree | 42b201403637888b4c5cde5e1fd096c373d4ca05 /drivers/net/wireless/ath9k/hw.c | |
| parent | 81cb7623ad3b408f871fa36b774fc20d8dfccac0 (diff) | |
ath9k: Add open loop control support
This patch adds Open Loop Control support for Atheros chipsets that
supports open loop power control.
Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/hw.c')
| -rw-r--r-- | drivers/net/wireless/ath9k/hw.c | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 4af1aac1678..e33c53fb6b7 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -1202,10 +1202,23 @@ static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value); } +static void ath9k_olc_init(struct ath_hw *ah) +{ + u32 i; + + for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) + ah->originalGain[i] = + MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), + AR_PHY_TX_GAIN); + ah->PDADCdelta = 0; +} + static int ath9k_hw_process_ini(struct ath_hw *ah, struct ath9k_channel *chan, enum ath9k_ht_macmode macmode) { +#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ + ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) int i, regWrites = 0; struct ieee80211_channel *channel = chan->chan; u32 modesIndex, freqIndex; @@ -1308,6 +1321,9 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ath9k_hw_set_regs(ah, chan, macmode); ath9k_hw_init_chain_masks(ah); + if (OLC_FOR_AR9280_20_LATER) + ath9k_olc_init(ah); + status = ah->eep_ops->set_txpower(ah, chan, ath9k_regd_get_ctl(ah, chan), channel->max_antenna_gain * 2, @@ -1515,6 +1531,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) AR_RTC_FORCE_WAKE_ON_INT); REG_WRITE(ah, AR_RTC_RESET, 0); + udelay(2); REG_WRITE(ah, AR_RTC_RESET, 1); if (!ath9k_hw_wait(ah, @@ -1582,7 +1599,10 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, static bool ath9k_hw_chip_reset(struct ath_hw *ah, struct ath9k_channel *chan) { - if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) + if (OLC_FOR_AR9280_20_LATER) { + if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) + return false; + } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) return false; if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) @@ -3404,6 +3424,10 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, return 0; } return false; + case ATH9K_CAP_DS: + return (AR_SREV_9280_20_OR_LATER(ah) && + (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1)) + ? false : true; default: return false; } |