diff options
| author | Mark Maule <maule@sgi.com> | 2005-09-06 13:03:51 -0500 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2005-09-07 16:23:41 -0700 |
| commit | 5fbcf9a5c6904bd563f584d12d1f4d3f68a19d7d (patch) | |
| tree | 2da130b000e5c442345e473b4f53104b92a76e4c /include/asm-ia64 | |
| parent | 4706df3d3c42af802597d82c8b1542c3d52eab23 (diff) | |
[IA64-SGI] volatile semantics in places where it seems necessary
Resend using accessors instead of volatile qualifiers per hch comments, and
easier to understand convenience macros per rja comments.
Patch to apply volatile semantics when accessing MMR's in various SN files.
Signed-off-by: Mark Maule <maule@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include/asm-ia64')
| -rw-r--r-- | include/asm-ia64/sn/io.h | 9 | ||||
| -rw-r--r-- | include/asm-ia64/sn/tioca_provider.h | 14 |
2 files changed, 16 insertions, 7 deletions
diff --git a/include/asm-ia64/sn/io.h b/include/asm-ia64/sn/io.h index 42209733f6b..7597a52b426 100644 --- a/include/asm-ia64/sn/io.h +++ b/include/asm-ia64/sn/io.h @@ -36,6 +36,15 @@ extern void sn_dma_flush(unsigned long); #define __sn_readq_relaxed ___sn_readq_relaxed /* + * Convenience macros for setting/clearing bits using the above accessors + */ + +#define __sn_setq_relaxed(addr, val) \ + writeq((__sn_readq_relaxed(addr) | (val)), (addr)) +#define __sn_clrq_relaxed(addr, val) \ + writeq((__sn_readq_relaxed(addr) & ~(val)), (addr)) + +/* * The following routines are SN Platform specific, called when * a reference is made to inX/outX set macros. SN Platform * inX set of macros ensures that Posted DMA writes on the diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h index 5ccec608d32..b532ef6148e 100644 --- a/include/asm-ia64/sn/tioca_provider.h +++ b/include/asm-ia64/sn/tioca_provider.h @@ -182,11 +182,11 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel) * touch every CL aligned GART entry. */ - ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM); - ca_base->ca_control2 |= CA_GART_FLUSH_TLB; - ca_base->ca_control2 |= - (0x2ull << CA_GART_MEM_PARAM_SHFT); - tmp = ca_base->ca_control2; + __sn_clrq_relaxed(&ca_base->ca_control2, CA_GART_MEM_PARAM); + __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB); + __sn_setq_relaxed(&ca_base->ca_control2, + (0x2ull << CA_GART_MEM_PARAM_SHFT)); + tmp = __sn_readq_relaxed(&ca_base->ca_control2); } return; @@ -196,8 +196,8 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel) * Gart in uncached mode ... need an explicit flush. */ - ca_base->ca_control2 |= CA_GART_FLUSH_TLB; - tmp = ca_base->ca_control2; + __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB); + tmp = __sn_readq_relaxed(&ca_base->ca_control2); } extern uint32_t tioca_gart_found; |