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authorBorislav Petkov <borislav.petkov@amd.com>2009-07-28 10:56:15 +0200
committerBorislav Petkov <borislav.petkov@amd.com>2009-09-14 19:01:20 +0200
commitd93cc222adf3532ddb442648f8db00c15d1dc4c1 (patch)
tree57e0ac9280bff2b824a066621a3009ea7f9835ea /lib/prio_heap.c
parentb69b29de65fe4078b125acc9dea34be82f7c362c (diff)
EDAC, AMD: carve out decoding of MCi_STATUS ErrorCode
This is the MCE error code from the MCi_STATUS banks, bits [15:0] which describe what type of error was encountered: GART TLB, Memory or Bus error. The semantics of those bits are identical across all MCE banks so decode those separately, irrespectively of MCE type. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'lib/prio_heap.c')
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