diff options
-rw-r--r-- | arch/arm/mach-s3c6400/include/mach/uncompress.h | 2 | ||||
-rw-r--r-- | arch/arm/plat-s3c/Kconfig | 8 | ||||
-rw-r--r-- | arch/arm/plat-s3c/include/plat/uncompress.h | 28 | ||||
-rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/pll.h | 6 | ||||
-rw-r--r-- | arch/arm/plat-s3c64xx/irq-eint.c | 12 |
5 files changed, 52 insertions, 4 deletions
diff --git a/arch/arm/mach-s3c6400/include/mach/uncompress.h b/arch/arm/mach-s3c6400/include/mach/uncompress.h index cc822c57cc1..c6a82a20bf2 100644 --- a/arch/arm/mach-s3c6400/include/mach/uncompress.h +++ b/arch/arm/mach-s3c6400/include/mach/uncompress.h @@ -21,6 +21,8 @@ static void arch_detect_cpu(void) { /* we do not need to do any cpu detection here at the moment. */ + fifo_mask = S3C2440_UFSTAT_TXMASK; + fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; } #endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig index e80a32822d8..def0bb457ca 100644 --- a/arch/arm/plat-s3c/Kconfig +++ b/arch/arm/plat-s3c/Kconfig @@ -57,6 +57,14 @@ config S3C_BOOT_ERROR_RESET Say y here to use the watchdog to reset the system if the kernel decompressor detects an error during decompression. +config S3C_BOOT_UART_FORCE_FIFO + bool "Force UART FIFO on during boot process" + depends on PLAT_S3C + default y + help + Say Y here to force the UART FIFOs on during the kernel + uncompressor + comment "Power management" config S3C2410_PM_DEBUG diff --git a/arch/arm/plat-s3c/include/plat/uncompress.h b/arch/arm/plat-s3c/include/plat/uncompress.h index eeef32c4312..6061de87f22 100644 --- a/arch/arm/plat-s3c/include/plat/uncompress.h +++ b/arch/arm/plat-s3c/include/plat/uncompress.h @@ -139,6 +139,28 @@ static void arch_decomp_error(const char *x) static void error(char *err); +#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO +static inline void arch_enable_uart_fifo(void) +{ + u32 fifocon = uart_rd(S3C2410_UFCON); + + if (!(fifocon & S3C2410_UFCON_FIFOMODE)) { + fifocon |= S3C2410_UFCON_RESETBOTH; + uart_wr(S3C2410_UFCON, fifocon); + + /* wait for fifo reset to complete */ + while (1) { + fifocon = uart_rd(S3C2410_UFCON); + if (!(fifocon & S3C2410_UFCON_RESETBOTH)) + break; + } + } +} +#else +#define arch_enable_uart_fifo() do { } while(0) +#endif + + static void arch_decomp_setup(void) { @@ -149,6 +171,12 @@ arch_decomp_setup(void) arch_detect_cpu(); arch_decomp_wdog_start(); + + /* Enable the UART FIFOs if they where not enabled and our + * configuration says we should turn them on. + */ + + arch_enable_uart_fifo(); } diff --git a/arch/arm/plat-s3c64xx/include/plat/pll.h b/arch/arm/plat-s3c64xx/include/plat/pll.h index 1a8576422f1..90bbd72fdc4 100644 --- a/arch/arm/plat-s3c64xx/include/plat/pll.h +++ b/arch/arm/plat-s3c64xx/include/plat/pll.h @@ -12,9 +12,9 @@ * published by the Free Software Foundation. */ -#define S3C6400_PLL_MDIV_MASK ((1 << (25-16)) - 1) -#define S3C6400_PLL_PDIV_MASK ((1 << (13-8)) - 1) -#define S3C6400_PLL_SDIV_MASK ((1 << (2-0)) - 1) +#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1) +#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1) +#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1) #define S3C6400_PLL_MDIV_SHIFT (16) #define S3C6400_PLL_PDIV_SHIFT (8) #define S3C6400_PLL_SDIV_SHIFT (0) diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c index 87a43a0e542..a57636137a6 100644 --- a/arch/arm/plat-s3c64xx/irq-eint.c +++ b/arch/arm/plat-s3c64xx/irq-eint.c @@ -74,6 +74,7 @@ static void s3c_irq_eint_maskack(unsigned int irq) static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) { int offs = eint_offset(irq); + int pin; int shift; u32 ctrl, mask; u32 newvalue = 0; @@ -82,7 +83,7 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) if (offs > 27) return -EINVAL; - if (offs < 15) + if (offs <= 15) reg = S3C64XX_EINT0CON0; else reg = S3C64XX_EINT0CON1; @@ -125,6 +126,15 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) ctrl |= newvalue << shift; __raw_writel(ctrl, reg); + /* set the GPIO pin appropriately */ + + if (offs < 23) + pin = S3C64XX_GPN(offs); + else + pin = S3C64XX_GPM(offs - 23); + + s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2)); + return 0; } |