diff options
Diffstat (limited to 'include')
427 files changed, 31689 insertions, 2511 deletions
diff --git a/include/asm-alpha/a.out-core.h b/include/asm-alpha/a.out-core.h new file mode 100644 index 00000000000..9e33e92e524 --- /dev/null +++ b/include/asm-alpha/a.out-core.h @@ -0,0 +1,80 @@ +/* a.out coredump register dumper + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_A_OUT_CORE_H +#define _ASM_A_OUT_CORE_H + +#ifdef __KERNEL__ + +#include <linux/user.h> + +/* + * Fill in the user structure for an ECOFF core dump. + */ +static inline void aout_dump_thread(struct pt_regs *pt, struct user *dump) +{ + /* switch stack follows right below pt_regs: */ + struct switch_stack * sw = ((struct switch_stack *) pt) - 1; + + dump->magic = CMAGIC; + dump->start_code = current->mm->start_code; + dump->start_data = current->mm->start_data; + dump->start_stack = rdusp() & ~(PAGE_SIZE - 1); + dump->u_tsize = ((current->mm->end_code - dump->start_code) + >> PAGE_SHIFT); + dump->u_dsize = ((current->mm->brk + PAGE_SIZE-1 - dump->start_data) + >> PAGE_SHIFT); + dump->u_ssize = (current->mm->start_stack - dump->start_stack + + PAGE_SIZE-1) >> PAGE_SHIFT; + + /* + * We store the registers in an order/format that is + * compatible with DEC Unix/OSF/1 as this makes life easier + * for gdb. + */ + dump->regs[EF_V0] = pt->r0; + dump->regs[EF_T0] = pt->r1; + dump->regs[EF_T1] = pt->r2; + dump->regs[EF_T2] = pt->r3; + dump->regs[EF_T3] = pt->r4; + dump->regs[EF_T4] = pt->r5; + dump->regs[EF_T5] = pt->r6; + dump->regs[EF_T6] = pt->r7; + dump->regs[EF_T7] = pt->r8; + dump->regs[EF_S0] = sw->r9; + dump->regs[EF_S1] = sw->r10; + dump->regs[EF_S2] = sw->r11; + dump->regs[EF_S3] = sw->r12; + dump->regs[EF_S4] = sw->r13; + dump->regs[EF_S5] = sw->r14; + dump->regs[EF_S6] = sw->r15; + dump->regs[EF_A3] = pt->r19; + dump->regs[EF_A4] = pt->r20; + dump->regs[EF_A5] = pt->r21; + dump->regs[EF_T8] = pt->r22; + dump->regs[EF_T9] = pt->r23; + dump->regs[EF_T10] = pt->r24; + dump->regs[EF_T11] = pt->r25; + dump->regs[EF_RA] = pt->r26; + dump->regs[EF_T12] = pt->r27; + dump->regs[EF_AT] = pt->r28; + dump->regs[EF_SP] = rdusp(); + dump->regs[EF_PS] = pt->ps; + dump->regs[EF_PC] = pt->pc; + dump->regs[EF_GP] = pt->gp; + dump->regs[EF_A0] = pt->r16; + dump->regs[EF_A1] = pt->r17; + dump->regs[EF_A2] = pt->r18; + memcpy((char *)dump->regs + EF_SIZE, sw->fp, 32 * 8); +} + +#endif /* __KERNEL__ */ +#endif /* _ASM_A_OUT_CORE_H */ diff --git a/include/asm-alpha/a.out.h b/include/asm-alpha/a.out.h index e43cf61649a..02ce8473870 100644 --- a/include/asm-alpha/a.out.h +++ b/include/asm-alpha/a.out.h @@ -98,11 +98,5 @@ struct exec set_personality (((BFPM->sh_bang || EX.ah.entry < 0x100000000L \ ? ADDR_LIMIT_32BIT : 0) | PER_OSF4)) -#define STACK_TOP \ - (current->personality & ADDR_LIMIT_32BIT ? 0x80000000 : 0x00120000000UL) - -#define STACK_TOP_MAX 0x00120000000UL - -#endif - +#endif /* __KERNEL__ */ #endif /* __A_OUT_GNU_H__ */ diff --git a/include/asm-alpha/page.h b/include/asm-alpha/page.h index 05f09f997d8..22ff9762d17 100644 --- a/include/asm-alpha/page.h +++ b/include/asm-alpha/page.h @@ -62,6 +62,8 @@ typedef unsigned long pgprot_t; #endif /* STRICT_MM_TYPECHECKS */ +typedef struct page *pgtable_t; + #ifdef USE_48_BIT_KSEG #define PAGE_OFFSET 0xffff800000000000UL #else diff --git a/include/asm-alpha/param.h b/include/asm-alpha/param.h index 214e7996346..0982f1d3949 100644 --- a/include/asm-alpha/param.h +++ b/include/asm-alpha/param.h @@ -5,15 +5,7 @@ hardware ignores reprogramming. We also need userland buy-in to the change in HZ, since this is visible in the wait4 resources etc. */ - -#ifndef HZ -# ifndef CONFIG_ALPHA_RAWHIDE -# define HZ 1024 -# else -# define HZ 1200 -# endif -#endif - +#define HZ CONFIG_HZ #define USER_HZ HZ #define EXEC_PAGESIZE 8192 diff --git a/include/asm-alpha/pgalloc.h b/include/asm-alpha/pgalloc.h index fdbedacc737..fd090155dcc 100644 --- a/include/asm-alpha/pgalloc.h +++ b/include/asm-alpha/pgalloc.h @@ -11,10 +11,11 @@ */ static inline void -pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *pte) +pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t pte) { pmd_set(pmd, (pte_t *)(page_to_pa(pte) + PAGE_OFFSET)); } +#define pmd_pgtable(pmd) pmd_page(pmd) static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) @@ -57,18 +58,23 @@ pte_free_kernel(struct mm_struct *mm, pte_t *pte) free_page((unsigned long)pte); } -static inline struct page * -pte_alloc_one(struct mm_struct *mm, unsigned long addr) +static inline pgtable_t +pte_alloc_one(struct mm_struct *mm, unsigned long address) { - pte_t *pte = pte_alloc_one_kernel(mm, addr); - if (pte) - return virt_to_page(pte); - return NULL; + pte_t *pte = pte_alloc_one_kernel(mm, address); + struct page *page; + + if (!pte) + return NULL; + page = virt_to_page(pte); + pgtable_page_ctor(page); + return page; } static inline void -pte_free(struct mm_struct *mm, struct page *page) +pte_free(struct mm_struct *mm, pgtable_t page) { + pgtable_page_dtor(page); __free_page(page); } diff --git a/include/asm-alpha/processor.h b/include/asm-alpha/processor.h index 425b7b6d28c..94afe585930 100644 --- a/include/asm-alpha/processor.h +++ b/include/asm-alpha/processor.h @@ -20,6 +20,11 @@ */ #define TASK_SIZE (0x40000000000UL) +#define STACK_TOP \ + (current->personality & ADDR_LIMIT_32BIT ? 0x80000000 : 0x00120000000UL) + +#define STACK_TOP_MAX 0x00120000000UL + /* This decides where the kernel will search for a free chunk of vm * space during mmap's. */ diff --git a/include/asm-arm/a.out-core.h b/include/asm-arm/a.out-core.h new file mode 100644 index 00000000000..93d04acaa31 --- /dev/null +++ b/include/asm-arm/a.out-core.h @@ -0,0 +1,49 @@ +/* a.out coredump register dumper + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_A_OUT_CORE_H +#define _ASM_A_OUT_CORE_H + +#ifdef __KERNEL__ + +#include <linux/user.h> +#include <linux/elfcore.h> + +/* + * fill in the user structure for an a.out core dump + */ +static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) +{ + struct task_struct *tsk = current; + + dump->magic = CMAGIC; + dump->start_code = tsk->mm->start_code; + dump->start_stack = regs->ARM_sp & ~(PAGE_SIZE - 1); + + dump->u_tsize = (tsk->mm->end_code - tsk->mm->start_code) >> PAGE_SHIFT; + dump->u_dsize = (tsk->mm->brk - tsk->mm->start_data + PAGE_SIZE - 1) >> PAGE_SHIFT; + dump->u_ssize = 0; + + dump->u_debugreg[0] = tsk->thread.debug.bp[0].address; + dump->u_debugreg[1] = tsk->thread.debug.bp[1].address; + dump->u_debugreg[2] = tsk->thread.debug.bp[0].insn.arm; + dump->u_debugreg[3] = tsk->thread.debug.bp[1].insn.arm; + dump->u_debugreg[4] = tsk->thread.debug.nsaved; + + if (dump->start_stack < 0x04000000) + dump->u_ssize = (0x04000000 - dump->start_stack) >> PAGE_SHIFT; + + dump->regs = *regs; + dump->u_fpvalid = dump_fpu (regs, &dump->u_fp); +} + +#endif /* __KERNEL__ */ +#endif /* _ASM_A_OUT_CORE_H */ diff --git a/include/asm-arm/a.out.h b/include/asm-arm/a.out.h index d7165e86df2..79489fdcc8b 100644 --- a/include/asm-arm/a.out.h +++ b/include/asm-arm/a.out.h @@ -27,12 +27,6 @@ struct exec #define M_ARM 103 -#ifdef __KERNEL__ -#define STACK_TOP ((current->personality == PER_LINUX_32BIT) ? \ - TASK_SIZE : TASK_SIZE_26) -#define STACK_TOP_MAX TASK_SIZE -#endif - #ifndef LIBRARY_START_TEXT #define LIBRARY_START_TEXT (0x00c00000) #endif diff --git a/include/asm-arm/mutex.h b/include/asm-arm/mutex.h index cb29d84e690..020bd98710a 100644 --- a/include/asm-arm/mutex.h +++ b/include/asm-arm/mutex.h @@ -24,7 +24,7 @@ * reattempted until it succeeds. */ static inline void -__mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) +__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *)) { int __ex_flag, __res; @@ -44,7 +44,7 @@ __mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) } static inline int -__mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t *)) +__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *)) { int __ex_flag, __res; @@ -70,7 +70,7 @@ __mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t * * better generated assembly. */ static inline void -__mutex_fastpath_unlock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) +__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *)) { int __ex_flag, __res, __orig; diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h index 31ff12f4ffb..c86f68ee651 100644 --- a/include/asm-arm/page.h +++ b/include/asm-arm/page.h @@ -171,6 +171,8 @@ typedef unsigned long pgprot_t; #endif /* STRICT_MM_TYPECHECKS */ +typedef struct page *pgtable_t; + #endif /* CONFIG_MMU */ #include <asm/memory.h> diff --git a/include/asm-arm/pgalloc.h b/include/asm-arm/pgalloc.h index fb6c6e3222b..163b0305dd7 100644 --- a/include/asm-arm/pgalloc.h +++ b/include/asm-arm/pgalloc.h @@ -66,7 +66,7 @@ pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr) return pte; } -static inline struct page * +static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr) { struct page *pte; @@ -75,6 +75,7 @@ pte_alloc_one(struct mm_struct *mm, unsigned long addr) if (pte) { void *page = page_address(pte); clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE); + pgtable_page_ctor(pte); } return pte; @@ -91,8 +92,9 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) } } -static inline void pte_free(struct mm_struct *mm, struct page *pte) +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) { + pgtable_page_dtor(pte); __free_page(pte); } @@ -123,10 +125,11 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) } static inline void -pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep) +pmd_populate(struct mm_struct *mm, pmd_t *pmdp, pgtable_t ptep) { __pmd_populate(pmdp, page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE); } +#define pmd_pgtable(pmd) pmd_page(pmd) #endif /* CONFIG_MMU */ diff --git a/include/asm-arm/posix_types.h b/include/asm-arm/posix_types.h index e142a2a016c..c37379dadcb 100644 --- a/include/asm-arm/posix_types.h +++ b/include/asm-arm/posix_types.h @@ -51,14 +51,10 @@ typedef long long __kernel_loff_t; #endif typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) +#if defined(__KERNEL__) #undef __FD_SET #define __FD_SET(fd, fdsetp) \ diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h index 1bbf16182d6..bd8029e8dc6 100644 --- a/include/asm-arm/processor.h +++ b/include/asm-arm/processor.h @@ -22,6 +22,12 @@ #include <asm/ptrace.h> #include <asm/types.h> +#ifdef __KERNEL__ +#define STACK_TOP ((current->personality == PER_LINUX_32BIT) ? \ + TASK_SIZE : TASK_SIZE_26) +#define STACK_TOP_MAX TASK_SIZE +#endif + union debug_insn { u32 arm; u16 thumb; diff --git a/include/asm-avr32/a.out.h b/include/asm-avr32/a.out.h index 9f398ab28ed..e46375a34a7 100644 --- a/include/asm-avr32/a.out.h +++ b/include/asm-avr32/a.out.h @@ -17,11 +17,4 @@ struct exec #define N_DRSIZE(a) ((a).a_drsize) #define N_SYMSIZE(a) ((a).a_syms) -#ifdef __KERNEL__ - -#define STACK_TOP TASK_SIZE -#define STACK_TOP_MAX STACK_TOP - -#endif - #endif /* __ASM_AVR32_A_OUT_H */ diff --git a/include/asm-avr32/arch-at32ap/board.h b/include/asm-avr32/arch-at32ap/board.h index d6993a6b647..7597b0bd2f0 100644 --- a/include/asm-avr32/arch-at32ap/board.h +++ b/include/asm-avr32/arch-at32ap/board.h @@ -51,6 +51,9 @@ struct platform_device * at32_add_device_ide(unsigned int id, unsigned int extint, struct ide_platform_data *data); +/* mask says which PWM channels to mux */ +struct platform_device *at32_add_device_pwm(u32 mask); + /* depending on what's hooked up, not all SSC pins will be used */ #define ATMEL_SSC_TK 0x01 #define ATMEL_SSC_TF 0x02 diff --git a/include/asm-avr32/page.h b/include/asm-avr32/page.h index ee23499cec3..5582968feee 100644 --- a/include/asm-avr32/page.h +++ b/include/asm-avr32/page.h @@ -34,6 +34,7 @@ extern void copy_page(void *to, void *from); typedef struct { unsigned long pte; } pte_t; typedef struct { unsigned long pgd; } pgd_t; typedef struct { unsigned long pgprot; } pgprot_t; +typedef struct page *pgtable_t; #define pte_val(x) ((x).pte) #define pgd_val(x) ((x).pgd) diff --git a/include/asm-avr32/pgalloc.h b/include/asm-avr32/pgalloc.h index b77e364b4c4..51fc1f6e4b1 100644 --- a/include/asm-avr32/pgalloc.h +++ b/include/asm-avr32/pgalloc.h @@ -17,10 +17,11 @@ set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte))) static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd, - struct page *pte) + pgtable_t pte) { set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte))); } +#define pmd_pgtable(pmd) pmd_page(pmd) /* * Allocate and free page tables @@ -51,7 +52,9 @@ static inline struct page *pte_alloc_one(struct mm_struct *mm, struct page *pte; pte = alloc_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO); - + if (!pte) + return NULL; + pgtable_page_ctor(pte); return pte; } @@ -60,12 +63,17 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) free_page((unsigned long)pte); } -static inline void pte_free(struct mm_struct *mm, struct page *pte) +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) { + pgtable_page_dtor(pte); __free_page(pte); } -#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) +#define __pte_free_tlb(tlb,pte) \ +do { \ + pgtable_page_dtor(pte); \ + tlb_remove_page((tlb), pte); \ +} while (0) #define check_pgt_cache() do { } while(0) diff --git a/include/asm-avr32/posix_types.h b/include/asm-avr32/posix_types.h index 9e255b99963..fe0c0c01438 100644 --- a/include/asm-avr32/posix_types.h +++ b/include/asm-avr32/posix_types.h @@ -46,11 +46,7 @@ typedef long long __kernel_loff_t; #endif typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; #if defined(__KERNEL__) diff --git a/include/asm-avr32/processor.h b/include/asm-avr32/processor.h index 4212551c1cd..49a88f5a9d2 100644 --- a/include/asm-avr32/processor.h +++ b/include/asm-avr32/processor.h @@ -13,6 +13,11 @@ #define TASK_SIZE 0x80000000 +#ifdef __KERNEL__ +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP +#endif + #ifndef __ASSEMBLY__ static inline void *current_text_addr(void) diff --git a/include/asm-blackfin/a.out.h b/include/asm-blackfin/a.out.h index d37a6849bf7..6c3d652ebd3 100644 --- a/include/asm-blackfin/a.out.h +++ b/include/asm-blackfin/a.out.h @@ -16,10 +16,4 @@ struct exec { #define N_DRSIZE(a) ((a).a_drsize) #define N_SYMSIZE(a) ((a).a_syms) -#ifdef __KERNEL__ - -#define STACK_TOP TASK_SIZE - -#endif - #endif /* __BFIN_A_OUT_H__ */ diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h index 6ae0619d769..5dba3a73559 100644 --- a/include/asm-blackfin/bfin-global.h +++ b/include/asm-blackfin/bfin-global.h @@ -70,6 +70,7 @@ extern void program_IAR(void); extern void evt14_softirq(void); extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type); +extern int bfin_internal_set_wake(unsigned int irq, unsigned int state); extern asmlinkage void finish_atomic_sections (struct pt_regs *regs); extern char fixed_code_start; @@ -121,6 +122,7 @@ extern unsigned long dpdt_swapcount_table[]; extern unsigned long table_start, table_end; +extern unsigned long bfin_sic_iwr[]; extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ extern struct file_operations dpmc_fops; extern char _start; diff --git a/include/asm-blackfin/bfin5xx_spi.h b/include/asm-blackfin/bfin5xx_spi.h index 1a0b57f6a3d..9fa19158e38 100644 --- a/include/asm-blackfin/bfin5xx_spi.h +++ b/include/asm-blackfin/bfin5xx_spi.h @@ -1,6 +1,6 @@ /************************************************************ -* -* Copyright (C) 2004, Analog Devices. All Rights Reserved + +* Copyright (C) 2006-2008, Analog Devices. All Rights Reserved * * FILE bfin5xx_spi.h * PROGRAMMER(S): Luke Yang (Analog Devices Inc.) @@ -32,42 +32,6 @@ #define SPI_BAUD_OFF 0x14 #define SPI_SHAW_OFF 0x18 -#define CMD_SPI_OUT_ENABLE 1 -#define CMD_SPI_SET_BAUDRATE 2 -#define CMD_SPI_SET_POLAR 3 -#define CMD_SPI_SET_PHASE 4 -#define CMD_SPI_SET_MASTER 5 -#define CMD_SPI_SET_SENDOPT 6 -#define CMD_SPI_SET_RECVOPT 7 -#define CMD_SPI_SET_ORDER 8 -#define CMD_SPI_SET_LENGTH16 9 -#define CMD_SPI_GET_STAT 11 -#define CMD_SPI_GET_CFG 12 -#define CMD_SPI_SET_CSAVAIL 13 -#define CMD_SPI_SET_CSHIGH 14 /* CS unavail */ -#define CMD_SPI_SET_CSLOW 15 /* CS avail */ -#define CMD_SPI_MISO_ENABLE 16 -#define CMD_SPI_SET_CSENABLE 17 -#define CMD_SPI_SET_CSDISABLE 18 - -#define CMD_SPI_SET_TRIGGER_MODE 19 -#define CMD_SPI_SET_TRIGGER_SENSE 20 -#define CMD_SPI_SET_TRIGGER_EDGE 21 -#define CMD_SPI_SET_TRIGGER_LEVEL 22 - -#define CMD_SPI_SET_TIME_SPS 23 -#define CMD_SPI_SET_TIME_SAMPLES 24 -#define CMD_SPI_GET_SYSTEMCLOCK 25 - -#define CMD_SPI_SET_WRITECONTINUOUS 26 -#define CMD_SPI_SET_SKFS 27 - -#define CMD_SPI_GET_ALLCONFIG 32 /* For debug */ - -#define SPI_DEFAULT_BARD 0x0100 - -#define SPI0_IRQ_NUM IRQ_SPI -#define SPI_ERR_TRIG -1 #define BIT_CTL_ENABLE 0x4000 #define BIT_CTL_OPENDRAIN 0x2000 @@ -148,6 +112,10 @@ #define CFG_SPI_CS6VALUE 6 #define CFG_SPI_CS7VALUE 7 +#define CMD_SPI_SET_BAUDRATE 2 +#define CMD_SPI_GET_SYSTEMCLOCK 25 +#define CMD_SPI_SET_WRITECONTINUOUS 26 + /* device.platform_data for SSP controller devices */ struct bfin5xx_spi_master { u16 num_chipselect; diff --git a/include/asm-blackfin/dpmc.h b/include/asm-blackfin/dpmc.h index f162edb2303..686cf83a526 100644 --- a/include/asm-blackfin/dpmc.h +++ b/include/asm-blackfin/dpmc.h @@ -53,10 +53,10 @@ unsigned long get_pll_status(void); void change_baud(int baud); void fullon_mode(void); void active_mode(void); -void sleep_mode(u32 sic_iwr); -void deep_sleep(u32 sic_iwr); -void hibernate_mode(u32 sic_iwr); -void sleep_deeper(u32 sic_iwr); +void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); +void deep_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); +void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); +void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); void program_wdog_timer(unsigned long); void unmask_wdog_wakeup_evt(void); void clear_wdog_wakeup_evt(void); diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h index d0426c10826..27ff532a806 100644 --- a/include/asm-blackfin/gpio.h +++ b/include/asm-blackfin/gpio.h @@ -376,16 +376,19 @@ struct gpio_port_t { #endif #ifdef CONFIG_PM +unsigned int bfin_pm_setup(void); +void bfin_pm_restore(void); + +#ifndef CONFIG_BF54x #define PM_WAKE_RISING 0x1 #define PM_WAKE_FALLING 0x2 #define PM_WAKE_HIGH 0x4 #define PM_WAKE_LOW 0x8 #define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING) +#define PM_WAKE_IGNORE 0xF0 int gpio_pm_wakeup_request(unsigned gpio, unsigned char type); void gpio_pm_wakeup_free(unsigned gpio); -unsigned int gpio_pm_setup(void); -void gpio_pm_restore(void); struct gpio_port_s { unsigned short data; @@ -409,6 +412,7 @@ struct gpio_port_s { unsigned short fer; unsigned short reserved; }; +#endif /*CONFIG_BF54x*/ #endif /*CONFIG_PM*/ /*********************************************************** diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h index 19e84dd4c99..3bd67da8605 100644 --- a/include/asm-blackfin/mach-bf548/blackfin.h +++ b/include/asm-blackfin/mach-bf548/blackfin.h @@ -46,6 +46,10 @@ #include "defBF544.h" #endif +#ifdef CONFIG_BF547 +#include "defBF547.h" +#endif + #ifdef CONFIG_BF548 #include "defBF548.h" #endif @@ -58,10 +62,12 @@ #ifdef CONFIG_BF542 #include "cdefBF542.h" #endif - #ifdef CONFIG_BF544 #include "cdefBF544.h" #endif +#ifdef CONFIG_BF547 +#include "cdefBF547.h" +#endif #ifdef CONFIG_BF548 #include "cdefBF548.h" #endif diff --git a/include/asm-blackfin/mach-bf548/cdefBF547.h b/include/asm-blackfin/mach-bf548/cdefBF547.h new file mode 100644 index 00000000000..d0a200b08ab --- /dev/null +++ b/include/asm-blackfin/mach-bf548/cdefBF547.h @@ -0,0 +1,865 @@ +/* + * File: include/asm-blackfin/mach-bf548/cdefBF547.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _CDEF_BF548_H +#define _CDEF_BF548_H + +/* include all Core registers and bit definitions */ +#include "defBF548.h" + +/* include core sbfin_read_()ecific register pointer definitions */ +#include <asm/mach-common/cdef_LPBlackfin.h> + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ + +/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ +#include "cdefBF54x_base.h" + +/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ + +/* Timer Registers */ + +#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) +#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) +#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) +#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) +#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) +#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) +#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) +#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) +#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) +#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) +#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) +#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) +#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) +#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) +#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) +#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) +#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) +#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) +#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) +#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) +#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) +#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) +#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) +#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) + +/* Timer Groubfin_read_() of 3 */ + +#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) +#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) +#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) +#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) +#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) +#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) + +/* SPORT0 Registers */ + +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) + +/* EPPI0 Registers */ + +#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) +#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) +#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) +#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) +#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) +#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) +#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) +#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) +#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) +#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) +#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) +#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) +#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) +#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) +#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) +#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) +#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) +#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) +#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) +#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) +#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) +#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) +#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) +#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) +#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) +#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) +#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) +#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) + +/* UART2 Registers */ + +#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) +#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) +#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) +#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) +#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) +#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) +#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) +#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) +#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) +#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) +#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) +#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) +#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) +#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) +#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) +#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) +#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) +#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) +#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) +#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) +#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) +#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) + +/* Two Wire Interface Registers (TWI1) */ + +#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) +#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) +#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) +#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) +#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) +#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) +#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) +#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) +#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) +#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) +#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL) +#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val) +#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) +#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) +#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) +#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) +#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) +#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) +#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) +#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) +#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL) +#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val) +#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) +#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) +#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) +#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) +#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) +#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) +#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) +#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) +#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) +#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) + +/* SPI2 Registers */ + +#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) +#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) +#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) +#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) +#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) +#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) +#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) +#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) +#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) +#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) +#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) +#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) +#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) +#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) + +/* ATAPI Registers */ + +#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) +#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) +#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) +#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) +#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) +#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) +#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) +#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) +#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) +#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) +#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) +#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) +#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) +#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) +#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) +#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) +#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) +#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) +#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) +#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) +#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) +#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) +#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) +#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) +#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) +#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) +#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) +#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) +#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) +#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) +#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) +#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) +#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) +#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) +#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) +#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) +#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) +#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) +#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) +#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) +#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) +#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) +#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) +#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) + +/* SDH Registers */ + +#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) +#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) +#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) +#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) +#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) +#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) +#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) +#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) +#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) +#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) +#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) +#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) +#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) +#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) +#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) +#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) +#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) +#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) +#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) +#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) +#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) +#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) +#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) +#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) +#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) +#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) +#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) +#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) +#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) +#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) +#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) +#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) +#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) +#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) +#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) +#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) +#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) +#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) +#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) +#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) +#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) +#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) +#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) +#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) +#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) +#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) +#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) +#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) +#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) +#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) +#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) +#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) +#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) +#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) +#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) +#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) +#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) +#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) +#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) +#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) +#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) +#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) + +/* HOST Port Registers */ + +#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) +#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) +#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) +#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) +#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) +#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) + +/* USB Control Registers */ + +#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) +#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) +#define bfin_read_USB_POWER() bfin_read16(USB_POWER) +#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) +#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) +#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) +#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) +#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) +#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) +#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) +#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) +#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) +#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) +#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) +#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) +#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) +#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) +#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) +#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) +#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) +#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) +#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) +#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) +#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) +#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) +#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) + +/* USB Packet Control Registers */ + +#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) +#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) +#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) +#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) +#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) +#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) +#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) +#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) +#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) +#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) +#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) +#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) +#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) +#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) +#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) +#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) +#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) +#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) +#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) +#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) +#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) +#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) +#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) +#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) +#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) +#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) + +/* USB Endbfin_read_()oint FIFO Registers */ + +#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) +#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) +#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) +#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) +#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) +#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) +#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) +#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) +#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) +#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) +#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) +#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) +#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) +#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) +#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) +#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) + +/* USB OTG Control Registers */ + +#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) +#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) +#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) +#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) +#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) +#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) + +/* USB Phy Control Registers */ + +#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) +#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) +#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) +#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) +#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) +#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) +#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) +#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) +#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) +#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) + +/* (APHY_CNTRL is for ADI usage only) */ + +#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) +#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) + +/* (APHY_CALIB is for ADI usage only) */ + +#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) +#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) +#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) +#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) + +/* (PHY_TEST is for ADI usage only) */ + +#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) +#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) +#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) +#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) +#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) +#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) + +/* USB Endbfin_read_()oint 0 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) +#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) +#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) +#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) +#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) +#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) +#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) +#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) +#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) +#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) +#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) +#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) +#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) +#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) +#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) +#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) +#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) +#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 1 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) +#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) +#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) +#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) +#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) +#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) +#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) +#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) +#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) +#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) +#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) +#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) +#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) +#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) +#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) +#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) +#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) +#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 2 Control Registers */ + +#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) +#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) +#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) +#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) +#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) +#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) +#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) +#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) +#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) +#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) +#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) +#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) +#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) +#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) +#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) +#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) +#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) +#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 3 Control Registers */ + +#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) +#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) +#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) +#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) +#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) +#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) +#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) +#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) +#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) +#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) +#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) +#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) +#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) +#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) +#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) +#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) +#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) +#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 4 Control Registers */ + +#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) +#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) +#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) +#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) +#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) +#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) +#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) +#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) +#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) +#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) +#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) +#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) +#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) +#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) +#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) +#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) +#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) +#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 5 Control Registers */ + +#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) +#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) +#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) +#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) +#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) +#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) +#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) +#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) +#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) +#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) +#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) +#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) +#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) +#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) +#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) +#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) +#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) +#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 6 Control Registers */ + +#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) +#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) +#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) +#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) +#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) +#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) +#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) +#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) +#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) +#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) +#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) +#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) +#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) +#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) +#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) +#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) +#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) +#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 7 Control Registers */ + +#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) +#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) +#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) +#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) +#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) +#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) +#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) +#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) +#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) +#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) +#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) +#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) +#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) +#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) +#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) +#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) +#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) +#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) +#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) +#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) +#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) +#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) + +/* USB Channel 0 Config Registers */ + +#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) +#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) +#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) +#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) +#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) +#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) +#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) +#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) +#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) +#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) + +/* USB Channel 1 Config Registers */ + +#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) +#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) +#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) +#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) +#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) +#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) +#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) +#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) +#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) +#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) + +/* USB Channel 2 Config Registers */ + +#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) +#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) +#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) +#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) +#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) +#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) +#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) +#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) +#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) +#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) + +/* USB Channel 3 Config Registers */ + +#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) +#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) +#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) +#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) +#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) +#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) +#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) +#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) +#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) +#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) + +/* USB Channel 4 Config Registers */ + +#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) +#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) +#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) +#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) +#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) +#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) +#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) +#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) +#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) +#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) + +/* USB Channel 5 Config Registers */ + +#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) +#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) +#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) +#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) +#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) +#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) +#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) +#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) +#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) +#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) + +/* USB Channel 6 Config Registers */ + +#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) +#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) +#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) +#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) +#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) +#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) +#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) +#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) +#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) +#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) + +/* USB Channel 7 Config Registers */ + +#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) +#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) +#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) +#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) +#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) +#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) +#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) +#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) +#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) +#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) + +/* Keybfin_read_()ad Registers */ + +#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) +#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) +#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) +#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) +#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) +#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) +#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) +#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) +#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) +#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) +#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) +#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) + +/* Pixel Combfin_read_()ositor (PIXC) Registers */ + +#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) +#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) +#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) +#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) +#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) +#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) +#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) +#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) +#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) +#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) +#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) +#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) +#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) +#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) +#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) +#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) +#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) +#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) +#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) +#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) +#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) +#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) +#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) +#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) +#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) +#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) +#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) +#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) +#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) +#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) +#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) +#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) +#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) +#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) +#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) +#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) +#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) +#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) + +/* Handshake MDMA 0 Registers */ + +#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) +#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) +#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) +#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) +#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) +#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) +#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) +#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) +#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) +#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) +#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) +#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) +#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) +#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) + +/* Handshake MDMA 1 Registers */ + +#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) +#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) +#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) +#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) +#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) +#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) +#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) +#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) +#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) +#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) +#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) +#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) +#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) +#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) + +#endif /* _CDEF_BF548_H */ diff --git a/include/asm-blackfin/mach-bf548/defBF547.h b/include/asm-blackfin/mach-bf548/defBF547.h new file mode 100644 index 00000000000..3a3a18ebb10 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/defBF547.h @@ -0,0 +1,1244 @@ +/* + * File: include/asm-blackfin/mach-bf548/defBF547.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _DEF_BF548_H +#define _DEF_BF548_H + +/* Include all Core registers and bit definitions */ +#include <asm/mach-common/def_LPBlackfin.h> + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ + +/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ +#include "defBF54x_base.h" + +/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ + +/* Timer Registers */ + +#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */ +#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */ +#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */ +#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */ +#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */ +#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */ +#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */ +#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */ +#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */ +#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */ +#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */ +#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */ + +/* Timer Group of 3 Registers */ + +#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */ +#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */ +#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */ + +/* SPORT0 Registers */ + +#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */ +#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */ +#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */ +#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */ +#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */ +#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */ +#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */ +#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */ + +/* EPPI0 Registers */ + +#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */ +#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */ +#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */ +#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */ +#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */ +#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */ +#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */ +#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ +#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */ +#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ +#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ +#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ +#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ +#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */ + +/* UART2 Registers */ + +#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */ +#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */ +#define UART2_GCTL 0xffc02108 /* Global Control Register */ +#define UART2_LCR 0xffc0210c /* Line Control Register */ +#define UART2_MCR 0xffc02110 /* Modem Control Register */ +#define UART2_LSR 0xffc02114 /* Line Status Register */ +#define UART2_MSR 0xffc02118 /* Modem Status Register */ +#define UART2_SCR 0xffc0211c /* Scratch Register */ +#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */ +#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */ +#define UART2_RBR 0xffc0212c /* Receive Buffer Register */ + +/* Two Wire Interface Registers (TWI1) */ + +#define TWI1_REGBASE 0xffc02200 +#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ +#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ +#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ +#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ +#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ +#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ +#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ +#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ +#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ +#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ +#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ +#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ +#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ +#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ +#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */ +#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */ + +/* SPI2 Registers */ + +#define SPI2_REGBASE 0xffc02400 +#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ +#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ +#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ +#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */ +#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */ +#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */ +#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */ + +/* ATAPI Registers */ + +#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ +#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ +#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ +#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ +#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ +#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ +#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ +#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ +#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ +#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ +#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ +#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ +#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ +#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ +#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ +#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ +#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ +#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ +#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ +#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ +#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ +#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ +#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ + +/* SDH Registers */ + +#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ +#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ +#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ +#define SDH_COMMAND 0xffc0390c /* SDH Command */ +#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ +#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ +#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ +#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ +#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ +#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ +#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ +#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ +#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ +#define SDH_STATUS 0xffc03934 /* SDH Status */ +#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ +#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ +#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ +#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ +#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ +#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ +#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ +#define SDH_CFG 0xffc039c8 /* SDH Configuration */ +#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ +#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ +#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ +#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ +#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ +#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ +#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ +#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ +#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ + +/* HOST Port Registers */ + +#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */ +#define HOST_STATUS 0xffc03a04 /* HOST Status Register */ +#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */ + +/* USB Control Registers */ + +#define USB_FADDR 0xffc03c00 /* Function address register */ +#define USB_POWER 0xffc03c04 /* Power management register */ +#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ +#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ +#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ +#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ +#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ +#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ +#define USB_FRAME 0xffc03c20 /* USB frame number */ +#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ +#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ +#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ +#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ + +/* USB Packet Control Registers */ + +#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ +#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ +#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ +#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ +#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ +#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ +#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* USB Endpoint FIFO Registers */ + +#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ +#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ +#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ +#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ +#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ +#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ +#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ +#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ + +/* USB OTG Control Registers */ + +#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ +#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ +#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ + +/* USB Phy Control Registers */ + +#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ +#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ +#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ +#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ +#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ + +/* (APHY_CNTRL is for ADI usage only) */ + +#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ + +/* (APHY_CALIB is for ADI usage only) */ + +#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ +#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ + +/* (PHY_TEST is for ADI usage only) */ + +#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */ +#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ +#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ + +/* USB Endpoint 0 Control Registers */ + +#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ +#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ +#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ +#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ +#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ +#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ +#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ + +/* USB Endpoint 1 Control Registers */ + +#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ +#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ +#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ +#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ +#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ +#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ +#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ +#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ + +/* USB Endpoint 2 Control Registers */ + +#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ +#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ +#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ +#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ +#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ +#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ +#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ +#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ + +/* USB Endpoint 3 Control Registers */ + +#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ +#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ +#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ +#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ +#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ +#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ +#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ +#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ + +/* USB Endpoint 4 Control Registers */ + +#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ +#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ +#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ +#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ +#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ +#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ +#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ +#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ + +/* USB Endpoint 5 Control Registers */ + +#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ +#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ +#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ +#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ +#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ +#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ +#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ +#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ + +/* USB Endpoint 6 Control Registers */ + +#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ +#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ +#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ +#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ +#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ +#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ +#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ +#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ + +/* USB Endpoint 7 Control Registers */ + +#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ +#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ +#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ +#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ +#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ +#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ +#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ +#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ +#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ +#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ + +/* USB Channel 0 Config Registers */ + +#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ +#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ +#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ + +/* USB Channel 1 Config Registers */ + +#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ +#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ +#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ + +/* USB Channel 2 Config Registers */ + +#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ +#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ +#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ + +/* USB Channel 3 Config Registers */ + +#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ +#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ +#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ + +/* USB Channel 4 Config Registers */ + +#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ +#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ +#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ + +/* USB Channel 5 Config Registers */ + +#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ +#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ +#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ + +/* USB Channel 6 Config Registers */ + +#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ +#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ +#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ + +/* USB Channel 7 Config Registers */ + +#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ +#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ +#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ + +/* Keypad Registers */ + +#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ +#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ +#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ +#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ +#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ +#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ + +/* Pixel Compositor (PIXC) Registers */ + +#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ +#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */ +#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */ +#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */ +#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */ +#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */ +#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */ +#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */ +#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */ +#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */ +#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */ +#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */ +#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */ +#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */ +#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ +#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ +#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ +#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */ +#define PIXC_TC 0xffc04450 /* Holds the transparent color value */ + +/* Handshake MDMA 0 Registers */ + +#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ +#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ +#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ +#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ +#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ +#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ +#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ + +/* Handshake MDMA 1 Registers */ + +#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ +#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ +#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ +#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ +#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ +#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ +#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ + + +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for PIXC_CTL */ + +#define PIXC_EN 0x1 /* Pixel Compositor Enable */ +#define OVR_A_EN 0x2 /* Overlay A Enable */ +#define OVR_B_EN 0x4 /* Overlay B Enable */ +#define IMG_FORM 0x8 /* Image Data Format */ +#define OVR_FORM 0x10 /* Overlay Data Format */ +#define OUT_FORM 0x20 /* Output Data Format */ +#define UDS_MOD 0x40 /* Resampling Mode */ +#define TC_EN 0x80 /* Transparent Color Enable */ +#define IMG_STAT 0x300 /* Image FIFO Status */ +#define OVR_STAT 0xc00 /* Overlay FIFO Status */ +#define WM_LVL 0x3000 /* FIFO Watermark Level */ + +/* Bit masks for PIXC_AHSTART */ + +#define A_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_AHEND */ + +#define A_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_AVSTART */ + +#define A_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_AVEND */ + +#define A_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_ATRANSP */ + +#define A_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_BHSTART */ + +#define B_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_BHEND */ + +#define B_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_BVSTART */ + +#define B_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_BVEND */ + +#define B_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_BTRANSP */ + +#define B_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_INTRSTAT */ + +#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ +#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ +#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ +#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ + +/* Bit masks for PIXC_RYCON */ + +#define A11 0x3ff /* A11 in the Coefficient Matrix */ +#define A12 0xffc00 /* A12 in the Coefficient Matrix */ +#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ +#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_GUCON */ + +#define A21 0x3ff /* A21 in the Coefficient Matrix */ +#define A22 0xffc00 /* A22 in the Coefficient Matrix */ +#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ +#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_BVCON */ + +#define A31 0x3ff /* A31 in the Coefficient Matrix */ +#define A32 0xffc00 /* A32 in the Coefficient Matrix */ +#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ +#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_CCBIAS */ + +#define A14 0x3ff /* A14 in the Bias Vector */ +#define A24 0xffc00 /* A24 in the Bias Vector */ +#define A34 0x3ff00000 /* A34 in the Bias Vector */ + +/* Bit masks for PIXC_TC */ + +#define RY_TRANS 0xff /* Transparent Color - R/Y Component */ +#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ +#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ + +/* Bit masks for HOST_CONTROL */ + +#define HOST_EN 0x1 /* Host Enable */ +#define HOST_END 0x2 /* Host Endianess */ +#define DATA_SIZE 0x4 /* Data Size */ +#define HOST_RST 0x8 /* Host Reset */ +#define HRDY_OVR 0x20 /* Host Ready Override */ +#define INT_MODE 0x40 /* Interrupt Mode */ +#define BT_EN 0x80 /* Bus Timeout Enable */ +#define EHW 0x100 /* Enable Host Write */ +#define EHR 0x200 /* Enable Host Read */ +#define BDR 0x400 /* Burst DMA Requests */ + +/* Bit masks for HOST_STATUS */ + +#define DMA_READY 0x1 /* DMA Ready */ +#define FIFOFULL 0x2 /* FIFO Full */ +#define FIFOEMPTY 0x4 /* FIFO Empty */ +#define DMA_COMPLETE 0x8 /* DMA Complete */ +#define HSHK 0x10 /* Host Handshake */ +#define HSTIMEOUT 0x20 /* Host Timeout */ +#define HIRQ 0x40 /* Host Interrupt Request */ +#define ALLOW_CNFG 0x80 /* Allow New Configuration */ +#define DMA_DIR 0x100 /* DMA Direction */ +#define BTE 0x200 /* Bus Timeout Enabled */ + +/* Bit masks for HOST_TIMEOUT */ + +#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ + +/* Bit masks for KPAD_CTL */ + +#define KPAD_EN 0x1 /* Keypad Enable */ +#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ +#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ +#define KPAD_COLEN 0xe000 /* Column Enable Width */ + +/* Bit masks for KPAD_PRESCALE */ + +#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ + +/* Bit masks for KPAD_MSEL */ + +#define DBON_SCALE 0xff /* Debounce Scale Value */ +#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ + +/* Bit masks for KPAD_ROWCOL */ + +#define KPAD_ROW 0xff /* Rows Pressed */ +#define KPAD_COL 0xff00 /* Columns Pressed */ + +/* Bit masks for KPAD_STAT */ + +#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ +#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ +#define KPAD_PRESSED 0x8 /* Key press current status */ + +/* Bit masks for KPAD_SOFTEVAL */ + +#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ + +/* Bit masks for SDH_COMMAND */ + +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP 0x40 /* Response */ +#define CMD_L_RSP 0x80 /* Long Response */ +#define CMD_INT_E 0x100 /* Command Interrupt */ +#define CMD_PEND_E 0x200 /* Command Pending */ +#define CMD_E 0x400 /* Command Enable */ + +/* Bit masks for SDH_PWR_CTL */ + +#define PWR_ON 0x3 /* Power On */ +#if 0 +#define TBD 0x3c /* TBD */ +#endif +#define SD_CMD_OD 0x40 /* Open Drain Output */ +#define ROD_CTL 0x80 /* Rod Control */ + +/* Bit masks for SDH_CLK_CTL */ + +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E 0x200 /* Power Save Enable */ +#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ +#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ + +/* Bit masks for SDH_RESP_CMD */ + +#define RESP_CMD 0x3f /* Response Command */ + +/* Bit masks for SDH_DATA_CTL */ + +#define DTX_E 0x1 /* Data Transfer Enable */ +#define DTX_DIR 0x2 /* Data Transfer Direction */ +#define DTX_MODE 0x4 /* Data Transfer Mode */ +#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ + +/* Bit masks for SDH_STATUS */ + +#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ +#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ +#define TX_UNDERRUN 0x10 /* Transmit Underrun */ +#define RX_OVERRUN 0x20 /* Receive Overrun */ +#define CMD_RESP_END 0x40 /* CMD Response End */ +#define CMD_SENT 0x80 /* CMD Sent */ +#define DAT_END 0x100 /* Data End */ +#define START_BIT_ERR 0x200 /* Start Bit Error */ +#define DAT_BLK_END 0x400 /* Data Block End */ +#define CMD_ACT 0x800 /* CMD Active */ +#define TX_ACT 0x1000 /* Transmit Active */ +#define RX_ACT 0x2000 /* Receive Active */ +#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ +#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ +#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ +#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ +#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ +#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ +#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ +#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ + +/* Bit masks for SDH_STATUS_CLR */ + +#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ +#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ +#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ +#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ +#define DAT_END_STAT 0x100 /* Data End Status */ +#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ +#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ + +/* Bit masks for SDH_MASK0 */ + +#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ +#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ +#define DAT_END_MASK 0x100 /* Data End Mask */ +#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ +#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ +#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ +#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ + +/* Bit masks for SDH_FIFO_CNT */ + +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* Bit masks for SDH_E_STATUS */ + +#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ +#define SD_CARD_DET 0x10 /* SD Card Detect */ + +/* Bit masks for SDH_E_MASK */ + +#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ +#define SCD_MSK 0x40 /* Mask Card Detect */ + +/* Bit masks for SDH_CFG */ + +#define CLKS_EN 0x1 /* Clocks Enable */ +#define SD4E 0x4 /* SDIO 4-Bit Enable */ +#define MWE 0x8 /* Moving Window Enable */ +#define SD_RST 0x10 /* SDMMC Reset */ +#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ +#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ + +/* Bit masks for SDH_RD_WAIT_EN */ + +#define RWR 0x1 /* Read Wait Request */ + +/* Bit masks for ATAPI_CONTROL */ + +#define PIO_START 0x1 /* Start PIO/Reg Op */ +#define MULTI_START 0x2 /* Start Multi-DMA Op */ +#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ +#define XFER_DIR 0x8 /* Transfer Direction */ +#define IORDY_EN 0x10 /* IORDY Enable */ +#define FIFO_FLUSH 0x20 /* Flush FIFOs */ +#define SOFT_RST 0x40 /* Soft Reset */ +#define DEV_RST 0x80 /* Device Reset */ +#define TFRCNT_RST 0x100 /* Trans Count Reset */ +#define END_ON_TERM 0x200 /* End/Terminate Select */ +#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ +#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ + +/* Bit masks for ATAPI_STATUS */ + +#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ +#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ +#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ +#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ + +/* Bit masks for ATAPI_DEV_ADDR */ + +#define DEV_ADDR 0x1f /* Device Address */ + +/* Bit masks for ATAPI_INT_MASK */ + +#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ +#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ +#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ +#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ +#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ +#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ +#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ +#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ +#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ + +/* Bit masks for ATAPI_INT_STATUS */ + +#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ +#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ +#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ +#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ +#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ +#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ +#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ +#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ +#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ + +/* Bit masks for ATAPI_LINE_STATUS */ + +#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ +#define ATAPI_DASP 0x2 /* Device dasp to host line status */ +#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ +#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ +#define ATAPI_ADDR 0x70 /* ATAPI address line status */ +#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ +#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ +#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ +#define ATAPI_DIORN 0x400 /* ATAPI read line status */ +#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_SM_STATE */ + +#define PIO_CSTATE 0xf /* PIO mode state machine current state */ +#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ +#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ +#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_TERMINATE */ + +#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ + +/* Bit masks for ATAPI_REG_TIM_0 */ + +#define T2_REG 0xff /* End of cycle time for register access transfers */ +#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ + +/* Bit masks for ATAPI_PIO_TIM_0 */ + +#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ +#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ +#define T4_REG 0xf000 /* DIOW data hold */ + +/* Bit masks for ATAPI_PIO_TIM_1 */ + +#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ + +/* Bit masks for ATAPI_MULTI_TIM_0 */ + +#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ +#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ + +/* Bit masks for ATAPI_MULTI_TIM_1 */ + +#define TKW 0xff /* Selects DIOW negated pulsewidth */ +#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ + +/* Bit masks for ATAPI_MULTI_TIM_2 */ + +#define TH 0xff /* Selects DIOW data hold */ +#define TEOC 0xff00 /* Selects end of cycle for DMA */ + +/* Bit masks for ATAPI_ULTRA_TIM_0 */ + +#define TACK 0xff /* Selects setup and hold times for TACK */ +#define TENV 0xff00 /* Selects envelope time */ + +/* Bit masks for ATAPI_ULTRA_TIM_1 */ + +#define TDVS 0xff /* Selects data valid setup time */ +#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ + +/* Bit masks for ATAPI_ULTRA_TIM_2 */ + +#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ +#define TMLI 0xff00 /* Selects interlock time */ + +/* Bit masks for ATAPI_ULTRA_TIM_3 */ + +#define TZAH 0xff /* Selects minimum delay required for output */ +#define READY_PAUSE 0xff00 /* Selects ready to pause */ + +/* Bit masks for TIMER_ENABLE1 */ + +#define TIMEN8 0x1 /* Timer 8 Enable */ +#define TIMEN9 0x2 /* Timer 9 Enable */ +#define TIMEN10 0x4 /* Timer 10 Enable */ + +/* Bit masks for TIMER_DISABLE1 */ + +#define TIMDIS8 0x1 /* Timer 8 Disable */ +#define TIMDIS9 0x2 /* Timer 9 Disable */ +#define TIMDIS10 0x4 /* Timer 10 Disable */ + +/* Bit masks for TIMER_STATUS1 */ + +#define TIMIL8 0x1 /* Timer 8 Interrupt */ +#define TIMIL9 0x2 /* Timer 9 Interrupt */ +#define TIMIL10 0x4 /* Timer 10 Interrupt */ +#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ +#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ +#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ +#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ +#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ +#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ + +/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ + +/* Bit masks for USB_FADDR */ + +#define FUNCTION_ADDRESS 0x7f /* Function address */ + +/* Bit masks for USB_POWER */ + +#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ +#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ +#define RESUME_MODE 0x4 /* DMA Mode */ +#define RESET 0x8 /* Reset indicator */ +#define HS_MODE 0x10 /* High Speed mode indicator */ +#define HS_ENABLE 0x20 /* high Speed Enable */ +#define SOFT_CONN 0x40 /* Soft connect */ +#define ISO_UPDATE 0x80 /* Isochronous update */ + +/* Bit masks for USB_INTRTX */ + +#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ +#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ +#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ +#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ +#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ +#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ +#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ +#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRRX */ + +#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ +#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ +#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ +#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ +#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ +#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ +#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRTXE */ + +#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ +#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ +#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ +#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ +#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ +#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ +#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ +#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRRXE */ + +#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ +#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ +#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ +#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ +#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ +#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ +#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRUSB */ + +#define SUSPEND_B 0x1 /* Suspend indicator */ +#define RESUME_B 0x2 /* Resume indicator */ +#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ +#define SOF_B 0x8 /* Start of frame */ +#define CONN_B 0x10 /* Connection indicator */ +#define DISCON_B 0x20 /* Disconnect indicator */ +#define SESSION_REQ_B 0x40 /* Session Request */ +#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ + +/* Bit masks for USB_INTRUSBE */ + +#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ +#define RESUME_BE 0x2 /* Resume indicator int enable */ +#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ +#define SOF_BE 0x8 /* Start of frame int enable */ +#define CONN_BE 0x10 /* Connection indicator int enable */ +#define DISCON_BE 0x20 /* Disconnect indicator int enable */ +#define SESSION_REQ_BE 0x40 /* Session Request int enable */ +#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ + +/* Bit masks for USB_FRAME */ + +#define FRAME_NUMBER 0x7ff /* Frame number */ + +/* Bit masks for USB_INDEX */ + +#define SELECTED_ENDPOINT 0xf /* selected endpoint */ + +/* Bit masks for USB_GLOBAL_CTL */ + +#define GLOBAL_ENA 0x1 /* enables USB module */ +#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ +#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ +#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ +#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ +#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ +#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ +#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ +#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ +#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ +#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ +#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ +#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ +#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ +#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ + +/* Bit masks for USB_OTG_DEV_CTL */ + +#define SESSION 0x1 /* session indicator */ +#define HOST_REQ 0x2 /* Host negotiation request */ +#define HOST_MODE 0x4 /* indicates USBDRC is a host */ +#define VBUS0 0x8 /* Vbus level indicator[0] */ +#define VBUS1 0x10 /* Vbus level indicator[1] */ +#define LSDEV 0x20 /* Low-speed indicator */ +#define FSDEV 0x40 /* Full or High-speed indicator */ +#define B_DEVICE 0x80 /* A' or 'B' device indicator */ + +/* Bit masks for USB_OTG_VBUS_IRQ */ + +#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ +#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ +#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ +#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ +#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ +#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ + +/* Bit masks for USB_OTG_VBUS_MASK */ + +#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ +#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ +#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ +#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ +#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ +#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ + +/* Bit masks for USB_CSR0 */ + +#define RXPKTRDY 0x1 /* data packet receive indicator */ +#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ +#define STALL_SENT 0x4 /* STALL handshake sent */ +#define DATAEND 0x8 /* Data end indicator */ +#define SETUPEND 0x10 /* Setup end */ +#define SENDSTALL 0x20 /* Send STALL handshake */ +#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ +#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ +#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ +#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ +#define SETUPPKT_H 0x8 /* send Setup token host mode */ +#define ERROR_H 0x10 /* timeout error indicator host mode */ +#define REQPKT_H 0x20 /* Request an IN transaction host mode */ +#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ +#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ + +/* Bit masks for USB_COUNT0 */ + +#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ + +/* Bit masks for USB_NAKLIMIT0 */ + +#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ + +/* Bit masks for USB_TX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_RX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_TXCSR */ + +#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ +#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ +#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ +#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ +#define STALL_SEND_T 0x10 /* issue a Stall handshake */ +#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ +#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ +#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ +#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ +#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ +#define ISO_T 0x4000 /* enable Isochronous transfers */ +#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_TH 0x4 /* error condition host mode */ +#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ +#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ + +/* Bit masks for USB_TXCOUNT */ + +#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* Bit masks for USB_RXCSR */ + +#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ +#define FIFO_FULL_R 0x2 /* FIFO not empty */ +#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ +#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ +#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ +#define STALL_SEND_R 0x20 /* issue a Stall handshake */ +#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ +#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ +#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ +#define DISNYET_R 0x1000 /* disable Nyet handshakes */ +#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ +#define ISO_R 0x4000 /* enable Isochronous transfers */ +#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ +#define REQPKT_RH 0x20 /* request an IN transaction host mode */ +#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ +#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ +#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ +#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ + +/* Bit masks for USB_RXCOUNT */ + +#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ + +/* Bit masks for USB_TXTYPE */ + +#define TARGET_EP_NO_T 0xf /* EP number */ +#define PROTOCOL_T 0xc /* transfer type */ + +/* Bit masks for USB_TXINTERVAL */ + +#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ + +/* Bit masks for USB_RXTYPE */ + +#define TARGET_EP_NO_R 0xf /* EP number */ +#define PROTOCOL_R 0xc /* transfer type */ + +/* Bit masks for USB_RXINTERVAL */ + +#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ + +/* Bit masks for USB_DMA_INTERRUPT */ + +#define DMA0_INT 0x1 /* DMA0 pending interrupt */ +#define DMA1_INT 0x2 /* DMA1 pending interrupt */ +#define DMA2_INT 0x4 /* DMA2 pending interrupt */ +#define DMA3_INT 0x8 /* DMA3 pending interrupt */ +#define DMA4_INT 0x10 /* DMA4 pending interrupt */ +#define DMA5_INT 0x20 /* DMA5 pending interrupt */ +#define DMA6_INT 0x40 /* DMA6 pending interrupt */ +#define DMA7_INT 0x80 /* DMA7 pending interrupt */ + +/* Bit masks for USB_DMAxCONTROL */ + +#define DMA_ENA 0x1 /* DMA enable */ +#define DIRECTION 0x2 /* direction of DMA transfer */ +#define MODE 0x4 /* DMA Bus error */ +#define INT_ENA 0x8 /* Interrupt enable */ +#define EPNUM 0xf0 /* EP number */ +#define BUSERROR 0x100 /* DMA Bus error */ + +/* Bit masks for USB_DMAxADDRHIGH */ + +#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxADDRLOW */ + +#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTHIGH */ + +#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTLOW */ + +#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for HMDMAx_CONTROL */ + +#define HMDMAEN 0x1 /* Handshake MDMA Enable */ +#define REP 0x2 /* Handshake MDMA Request Polarity */ +#define UTE 0x8 /* Urgency Threshold Enable */ +#define OIE 0x10 /* Overflow Interrupt Enable */ +#define BDIE 0x20 /* Block Done Interrupt Enable */ +#define MBDI 0x40 /* Mask Block Done Interrupt */ +#define DRQ 0x300 /* Handshake MDMA Request Type */ +#define RBC 0x1000 /* Force Reload of BCOUNT */ +#define PS 0x2000 /* Pin Status */ +#define OI 0x4000 /* Overflow Interrupt Generated */ +#define BDI 0x8000 /* Block Done Interrupt Generated */ + +/* ******************************************* */ +/* MULTI BIT MACRO ENUMERATIONS */ +/* ******************************************* */ + + +#endif /* _DEF_BF548_H */ diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h index e46f56891e6..1d7c96edb03 100644 --- a/include/asm-blackfin/mach-bf548/defBF548.h +++ b/include/asm-blackfin/mach-bf548/defBF548.h @@ -1010,9 +1010,9 @@ #define DMA_READY 0x1 /* DMA Ready */ #define FIFOFULL 0x2 /* FIFO Full */ #define FIFOEMPTY 0x4 /* FIFO Empty */ -#define COMPLETE 0x8 /* DMA Complete */ +#define DMA_COMPLETE 0x8 /* DMA Complete */ #define HSHK 0x10 /* Host Handshake */ -#define TIMEOUT 0x20 /* Host Timeout */ +#define HSTIMEOUT 0x20 /* Host Timeout */ #define HIRQ 0x40 /* Host Interrupt Request */ #define ALLOW_CNFG 0x80 /* Allow New Configuration */ #define DMA_DIR 0x100 /* DMA Direction */ diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h index 4d97d3aa97c..46ff31f20ae 100644 --- a/include/asm-blackfin/mach-bf548/dma.h +++ b/include/asm-blackfin/mach-bf548/dma.h @@ -51,9 +51,13 @@ #define CH_PIXC_OVERLAY 16 #define CH_PIXC_OUTPUT 17 #define CH_SPORT2_RX 18 +#define CH_UART2_RX 18 #define CH_SPORT2_TX 19 +#define CH_UART2_TX 19 #define CH_SPORT3_RX 20 +#define CH_UART3_RX 20 #define CH_SPORT3_TX 21 +#define CH_UART3_TX 21 #define CH_SDH 22 #define CH_NFC 22 #define CH_SPI2 23 diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index c34507a3f1d..ad380d1f587 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h @@ -99,9 +99,13 @@ Events (highest priority) EMU 0 #define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ #define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ #define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ +#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */ #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ +#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */ #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ +#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */ #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ +#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */ #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ @@ -421,9 +425,13 @@ Events (highest priority) EMU 0 /* IAR4 BIT FILEDS */ #define IRQ_CAN0_ERR_POS 0 #define IRQ_SPORT2_RX_POS 4 +#define IRQ_UART2_RX_POS 4 #define IRQ_SPORT2_TX_POS 8 +#define IRQ_UART2_TX_POS 8 #define IRQ_SPORT3_RX_POS 12 +#define IRQ_UART3_RX_POS 12 #define IRQ_SPORT3_TX_POS 16 +#define IRQ_UART3_TX_POS 16 #define IRQ_EPPI1_POS 20 #define IRQ_EPPI2_POS 24 #define IRQ_SPI1_POS 28 diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h index 562aee39895..362617f9384 100644 --- a/include/asm-blackfin/mach-bf561/blackfin.h +++ b/include/asm-blackfin/mach-bf561/blackfin.h @@ -49,4 +49,24 @@ #define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) + +#define SIC_IAR0 SICA_IAR0 +#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0 +#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1 +#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0 +#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1 + +#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0 +#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1 +#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0 +#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1 +#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0 +#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1 + +#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2)) +#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val) +#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) +#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) + + #endif /* _MACH_BLACKFIN_H_ */ diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h index c3fa50fa50b..23aa1f8c1bd 100644 --- a/include/asm-blackfin/posix_types.h +++ b/include/asm-blackfin/posix_types.h @@ -39,14 +39,10 @@ typedef long long __kernel_loff_t; #endif typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) +#if defined(__KERNEL__) #undef __FD_SET #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) @@ -60,6 +56,6 @@ typedef struct { #undef __FD_ZERO #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* defined(__KERNEL__) */ #endif diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h index c571e958558..1033e5c7601 100644 --- a/include/asm-blackfin/processor.h +++ b/include/asm-blackfin/processor.h @@ -30,6 +30,10 @@ static inline void wrusp(unsigned long usp) extern unsigned long memory_end; #define TASK_SIZE (memory_end) +#ifdef __KERNEL__ +#define STACK_TOP TASK_SIZE +#endif + #define TASK_UNMAPPED_BASE 0 struct thread_struct { diff --git a/include/asm-blackfin/termios.h b/include/asm-blackfin/termios.h index e31fe859650..d50d063c605 100644 --- a/include/asm-blackfin/termios.h +++ b/include/asm-blackfin/termios.h @@ -39,24 +39,6 @@ struct termio { /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ -/* line disciplines */ -#define N_TTY 0 -#define N_SLIP 1 -#define N_MOUSE 2 -#define N_PPP 3 -#define N_STRIP 4 -#define N_AX25 5 -#define N_X25 6 /* X.25 async */ -#define N_6PACK 7 -#define N_MASC 8 /* Reserved for Mobitex module <kaz@cafe.net> */ -#define N_R3964 9 /* Reserved for Simatic R3964 module */ -#define N_PROFIBUS_FDL 10 /* Reserved for Profibus <Dave@mvhi.com> */ -#define N_IRDA 11 /* Linux IR - http://irda.sourceforge.net/ */ -#define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data cards about SMS messages */ -#define N_HDLC 13 /* synchronous HDLC */ -#define N_SYNC_PPP 14 /* synchronous PPP */ -#define N_HCI 15 /* Bluetooth HCI UART */ - #ifdef __KERNEL__ /* intr=^C quit=^\ erase=del kill=^U diff --git a/include/asm-blackfin/trace.h b/include/asm-blackfin/trace.h index 6313aace9d5..ef18afbc210 100644 --- a/include/asm-blackfin/trace.h +++ b/include/asm-blackfin/trace.h @@ -46,42 +46,47 @@ extern unsigned long software_trace_buff[]; #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON -#define TRACE_BUFFER_START(preg, dreg) trace_buffer_start(preg, dreg) -#define TRACE_BUFFER_STOP(preg, dreg) trace_buffer_stop(preg, dreg) - #define trace_buffer_stop(preg, dreg) \ preg.L = LO(TBUFCTL); \ preg.H = HI(TBUFCTL); \ dreg = 0x1; \ [preg] = dreg; -#define trace_buffer_start(preg, dreg) \ - preg.L = LO(TBUFCTL); \ - preg.H = HI(TBUFCTL); \ - dreg = BFIN_TRACE_ON; \ - [preg] = dreg; - #define trace_buffer_init(preg, dreg) \ preg.L = LO(TBUFCTL); \ preg.H = HI(TBUFCTL); \ dreg = BFIN_TRACE_INIT; \ [preg] = dreg; +#define trace_buffer_save(preg, dreg) \ + preg.L = LO(TBUFCTL); \ + preg.H = HI(TBUFCTL); \ + dreg = [preg]; \ + [sp++] = dreg; \ + dreg = 0x1; \ + [preg] = dreg; + +#define trace_buffer_restore(preg, dreg) \ + preg.L = LO(TBUFCTL); \ + preg.H = HI(TBUFCTL); \ + dreg = [sp--]; \ + [preg] = dreg; + #else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ #define trace_buffer_stop(preg, dreg) -#define trace_buffer_start(preg, dreg) #define trace_buffer_init(preg, dreg) +#define trace_buffer_save(preg, dreg) +#define trace_buffer_restore(preg, dreg) #endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ #ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE -# define DEBUG_START_HWTRACE(preg, dreg) trace_buffer_start(preg, dreg) -# define DEBUG_STOP_HWTRACE(preg, dreg) trace_buffer_stop(preg, dreg) - +# define DEBUG_HWTRACE_SAVE(preg, dreg) trace_buffer_save(preg, dreg) +# define DEBUG_HWTRACE_RESTORE(preg, dreg) trace_buffer_restore(preg, dreg) #else -# define DEBUG_START_HWTRACE(preg, dreg) -# define DEBUG_STOP_HWTRACE(preg, dreg) +# define DEBUG_HWTRACE_SAVE(preg, dreg) +# define DEBUG_HWTRACE_RESTORE(preg, dreg) #endif #endif /* __ASSEMBLY__ */ diff --git a/include/asm-cris/Kbuild b/include/asm-cris/Kbuild index 14498d5a2f6..17455459c43 100644 --- a/include/asm-cris/Kbuild +++ b/include/asm-cris/Kbuild @@ -1,5 +1,11 @@ include include/asm-generic/Kbuild.asm -header-y += arch-v10/ arch-v32/ +header-$(CONFIG_ETRAX_ARCH_V10) += arch-v10/ +header-$(CONFIG_ETRAX_ARCH_V32) += arch-v32/ +header-y += ethernet.h +header-y += rtc.h +header-y += sync_serial.h + +unifdef-y += etraxgpio.h unifdef-y += rs485.h diff --git a/include/asm-cris/a.out.h b/include/asm-cris/a.out.h index 919b34a084f..c82e9f9b75f 100644 --- a/include/asm-cris/a.out.h +++ b/include/asm-cris/a.out.h @@ -6,11 +6,6 @@ * wants to know about a.out even if there is no interpreter available... */ -/* grabbed from the intel stuff */ -#define STACK_TOP TASK_SIZE -#define STACK_TOP_MAX STACK_TOP - - struct exec { unsigned long a_info; /* Use macros N_MAGIC, etc for access */ @@ -28,5 +23,4 @@ struct exec #define N_DRSIZE(a) ((a).a_drsize) #define N_SYMSIZE(a) ((a).a_syms) - #endif diff --git a/include/asm-cris/arch-v10/Kbuild b/include/asm-cris/arch-v10/Kbuild index d7f27dc0941..60e7e1b73ce 100644 --- a/include/asm-cris/arch-v10/Kbuild +++ b/include/asm-cris/arch-v10/Kbuild @@ -1,2 +1,5 @@ header-y += ptrace.h header-y += user.h +header-y += svinto.h +header-y += sv_addr_ag.h +header-y += sv_addr.agh diff --git a/include/asm-cris/arch-v10/bug.h b/include/asm-cris/arch-v10/bug.h new file mode 100644 index 00000000000..3485d6b34bb --- /dev/null +++ b/include/asm-cris/arch-v10/bug.h @@ -0,0 +1,66 @@ +#ifndef __ASM_CRISv10_ARCH_BUG_H +#define __ASM_CRISv10_ARCH_BUG_H + +#include <linux/stringify.h> + +#ifdef CONFIG_BUG +#ifdef CONFIG_DEBUG_BUGVERBOSE +/* The BUG() macro is used for marking obviously incorrect code paths. + * It will cause a message with the file name and line number to be printed, + * and then cause an oops. The message is actually printed by handle_BUG() + * in arch/cris/kernel/traps.c, and the reason we use this method of storing + * the file name and line number is that we do not want to affect the registers + * by calling printk() before causing the oops. + */ + +#define BUG_PREFIX 0x0D7F +#define BUG_MAGIC 0x00001234 + +struct bug_frame { + unsigned short prefix; + unsigned int magic; + unsigned short clear; + unsigned short movu; + unsigned short line; + unsigned short jump; + unsigned char *filename; +}; + +#if 0 +/* Unfortunately this version of the macro does not work due to a problem + * with the compiler (aka a bug) when compiling with -O2, which sometimes + * erroneously causes the second input to be stored in a register... + */ +#define BUG() \ + __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ + "movu.w %0,$r0\n\t" \ + "jump %1\n\t" \ + : : "i" (__LINE__), "i" (__FILE__)) +#else +/* This version will have to do for now, until the compiler is fixed. + * The drawbacks of this version are that the file name will appear multiple + * times in the .rodata section, and that __LINE__ and __FILE__ can probably + * not be used like this with newer versions of gcc. + */ +#define BUG() \ + __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ + "movu.w " __stringify(__LINE__) ",$r0\n\t"\ + "jump 0f\n\t" \ + ".section .rodata\n" \ + "0:\t.string \"" __FILE__ "\"\n\t" \ + ".previous") +#endif + +#else + +/* This just causes an oops. */ +#define BUG() (*(int *)0 = 0) + +#endif + +#define HAVE_ARCH_BUG +#endif + +#include <asm-generic/bug.h> + +#endif diff --git a/include/asm-cris/arch-v10/io.h b/include/asm-cris/arch-v10/io.h index 11ef5b53d84..c08c2426529 100644 --- a/include/asm-cris/arch-v10/io.h +++ b/include/asm-cris/arch-v10/io.h @@ -23,7 +23,7 @@ extern volatile unsigned long *port_cse1_addr; extern volatile unsigned long *port_csp0_addr; extern volatile unsigned long *port_csp4_addr; -/* macro for setting regs through a shadow - +/* macro for setting regs through a shadow - * r = register name (like R_PORT_PA_DATA) * s = shadow name (like port_pa_data_shadow) * b = bit number @@ -38,83 +38,89 @@ extern volatile unsigned long *port_csp4_addr; #undef CONFIG_ETRAX_PA_LEDS #undef CONFIG_ETRAX_PB_LEDS #undef CONFIG_ETRAX_CSP0_LEDS -#define LED_NETWORK_SET_G(x) -#define LED_NETWORK_SET_R(x) -#define LED_ACTIVE_SET_G(x) -#define LED_ACTIVE_SET_R(x) -#define LED_DISK_WRITE(x) -#define LED_DISK_READ(x) +#define CRIS_LED_NETWORK_SET_G(x) +#define CRIS_LED_NETWORK_SET_R(x) +#define CRIS_LED_ACTIVE_SET_G(x) +#define CRIS_LED_ACTIVE_SET_R(x) +#define CRIS_LED_DISK_WRITE(x) +#define CRIS_LED_DISK_READ(x) #endif #if !defined(CONFIG_ETRAX_CSP0_LEDS) -#define LED_BIT_SET(x) -#define LED_BIT_CLR(x) +#define CRIS_LED_BIT_SET(x) +#define CRIS_LED_BIT_CLR(x) #endif -#define LED_OFF 0x00 -#define LED_GREEN 0x01 -#define LED_RED 0x02 -#define LED_ORANGE (LED_GREEN | LED_RED) +#define CRIS_LED_OFF 0x00 +#define CRIS_LED_GREEN 0x01 +#define CRIS_LED_RED 0x02 +#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) -#if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R -#define LED_NETWORK_SET(x) \ +#if defined(CONFIG_ETRAX_NO_LEDS) +#define CRIS_LED_NETWORK_SET(x) +#else +#if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R +#define CRIS_LED_NETWORK_SET(x) \ do { \ - LED_NETWORK_SET_G((x) & LED_GREEN); \ + CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ } while (0) #else -#define LED_NETWORK_SET(x) \ +#define CRIS_LED_NETWORK_SET(x) \ do { \ - LED_NETWORK_SET_G((x) & LED_GREEN); \ - LED_NETWORK_SET_R((x) & LED_RED); \ + CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ + CRIS_LED_NETWORK_SET_R((x) & CRIS_LED_RED); \ } while (0) #endif -#if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R -#define LED_ACTIVE_SET(x) \ +#if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R +#define CRIS_LED_ACTIVE_SET(x) \ do { \ - LED_ACTIVE_SET_G((x) & LED_GREEN); \ + CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ } while (0) #else -#define LED_ACTIVE_SET(x) \ +#define CRIS_LED_ACTIVE_SET(x) \ do { \ - LED_ACTIVE_SET_G((x) & LED_GREEN); \ - LED_ACTIVE_SET_R((x) & LED_RED); \ + CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ + CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ } while (0) #endif +#endif #ifdef CONFIG_ETRAX_PA_LEDS -#define LED_NETWORK_SET_G(x) \ +#define CRIS_LED_NETWORK_SET_G(x) \ REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x)) -#define LED_NETWORK_SET_R(x) \ +#define CRIS_LED_NETWORK_SET_R(x) \ REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x)) -#define LED_ACTIVE_SET_G(x) \ +#define CRIS_LED_ACTIVE_SET_G(x) \ REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x)) -#define LED_ACTIVE_SET_R(x) \ +#define CRIS_LED_ACTIVE_SET_R(x) \ REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x)) -#define LED_DISK_WRITE(x) \ +#define CRIS_LED_DISK_WRITE(x) \ do{\ REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ }while(0) -#define LED_DISK_READ(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x)) +#define CRIS_LED_DISK_READ(x) \ + REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, \ + CONFIG_ETRAX_LED3G, !(x)) #endif #ifdef CONFIG_ETRAX_PB_LEDS -#define LED_NETWORK_SET_G(x) \ +#define CRIS_LED_NETWORK_SET_G(x) \ REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x)) -#define LED_NETWORK_SET_R(x) \ +#define CRIS_LED_NETWORK_SET_R(x) \ REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x)) -#define LED_ACTIVE_SET_G(x) \ +#define CRIS_LED_ACTIVE_SET_G(x) \ REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x)) -#define LED_ACTIVE_SET_R(x) \ +#define CRIS_LED_ACTIVE_SET_R(x) \ REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x)) -#define LED_DISK_WRITE(x) \ +#define CRIS_LED_DISK_WRITE(x) \ do{\ REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ }while(0) -#define LED_DISK_READ(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x)) +#define CRIS_LED_DISK_READ(x) \ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, \ + CONFIG_ETRAX_LED3G, !(x)) #endif #ifdef CONFIG_ETRAX_CSP0_LEDS @@ -130,27 +136,27 @@ extern volatile unsigned long *port_csp4_addr; (1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\ (1 << CONFIG_ETRAX_LED12R )) -#define LED_NETWORK_SET_G(x) \ +#define CRIS_LED_NETWORK_SET_G(x) \ REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x)) -#define LED_NETWORK_SET_R(x) \ +#define CRIS_LED_NETWORK_SET_R(x) \ REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x)) -#define LED_ACTIVE_SET_G(x) \ +#define CRIS_LED_ACTIVE_SET_G(x) \ REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x)) -#define LED_ACTIVE_SET_R(x) \ +#define CRIS_LED_ACTIVE_SET_R(x) \ REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x)) -#define LED_DISK_WRITE(x) \ +#define CRIS_LED_DISK_WRITE(x) \ do{\ REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\ REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\ }while(0) -#define LED_DISK_READ(x) \ +#define CRIS_LED_DISK_READ(x) \ REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x)) -#define LED_BIT_SET(x)\ +#define CRIS_LED_BIT_SET(x)\ do{\ if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\ }while(0) -#define LED_BIT_CLR(x)\ +#define CRIS_LED_BIT_CLR(x)\ do{\ if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\ diff --git a/include/asm-cris/arch-v10/page.h b/include/asm-cris/arch-v10/page.h index 7d8307aed7f..ffafc99c347 100644 --- a/include/asm-cris/arch-v10/page.h +++ b/include/asm-cris/arch-v10/page.h @@ -12,8 +12,8 @@ #endif /* macros to convert between really physical and virtual addresses - * by stripping a selected bit, we can convert between KSEG_x and 0x40000000 where - * the DRAM really resides + * by stripping a selected bit, we can convert between KSEG_x and + * 0x40000000 where the DRAM really resides */ #ifdef CONFIG_CRIS_LOW_MAP diff --git a/include/asm-cris/arch-v32/Kbuild b/include/asm-cris/arch-v32/Kbuild index d7f27dc0941..a0ec545e242 100644 --- a/include/asm-cris/arch-v32/Kbuild +++ b/include/asm-cris/arch-v32/Kbuild @@ -1,2 +1,3 @@ header-y += ptrace.h header-y += user.h +header-y += cryptocop.h diff --git a/include/asm-cris/arch-v32/atomic.h b/include/asm-cris/arch-v32/atomic.h index bbfb7a5ae31..852ceff8013 100644 --- a/include/asm-cris/arch-v32/atomic.h +++ b/include/asm-cris/arch-v32/atomic.h @@ -1,7 +1,7 @@ #ifndef __ASM_CRIS_ARCH_ATOMIC__ #define __ASM_CRIS_ARCH_ATOMIC__ -#include <asm/system.h> +#include <linux/spinlock_types.h> extern void cris_spin_unlock(void *l, int val); extern void cris_spin_lock(void *l); @@ -18,15 +18,15 @@ extern spinlock_t cris_atomic_locks[]; #define cris_atomic_save(addr, flags) \ local_irq_save(flags); \ - cris_spin_lock((void*)&cris_atomic_locks[HASH_ADDR(addr)].lock); + cris_spin_lock((void *)&cris_atomic_locks[HASH_ADDR(addr)].raw_lock.slock); #define cris_atomic_restore(addr, flags) \ { \ spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \ __asm__ volatile ("move.d %1,%0" \ - : "=m" (lock->lock) \ - : "r" (1) \ - : "memory"); \ + : "=m" (lock->raw_lock.slock) \ + : "r" (1) \ + : "memory"); \ local_irq_restore(flags); \ } diff --git a/include/asm-cris/arch-v32/bug.h b/include/asm-cris/arch-v32/bug.h new file mode 100644 index 00000000000..0f211e13524 --- /dev/null +++ b/include/asm-cris/arch-v32/bug.h @@ -0,0 +1,33 @@ +#ifndef __ASM_CRISv32_ARCH_BUG_H +#define __ASM_CRISv32_ARCH_BUG_H + +#include <linux/stringify.h> + +#ifdef CONFIG_BUG +#ifdef CONFIG_DEBUG_BUGVERBOSE +/* + * The penalty for the in-band code path will be the size of break 14. + * All other stuff is done out-of-band with exception handlers. + */ +#define BUG() \ + __asm__ __volatile__ ("0: break 14\n\t" \ + ".section .fixup,\"ax\"\n" \ + "1:\n\t" \ + "move.d %0, $r10\n\t" \ + "move.d %1, $r11\n\t" \ + "jump do_BUG\n\t" \ + "nop\n\t" \ + ".previous\n\t" \ + ".section __ex_table,\"a\"\n\t" \ + ".dword 0b, 1b\n\t" \ + ".previous\n\t" \ + : : "ri" (__FILE__), "i" (__LINE__)) +#else +#define BUG() __asm__ __volatile__ ("break 14\n\t") +#endif + +#define HAVE_ARCH_BUG +#endif + +#include <asm-generic/bug.h> +#endif diff --git a/include/asm-cris/arch-v32/cache.h b/include/asm-cris/arch-v32/cache.h index 80b236b1531..b3d752dfe15 100644 --- a/include/asm-cris/arch-v32/cache.h +++ b/include/asm-cris/arch-v32/cache.h @@ -1,8 +1,19 @@ #ifndef _ASM_CRIS_ARCH_CACHE_H #define _ASM_CRIS_ARCH_CACHE_H +#include <asm/arch/hwregs/dma.h> + /* A cache-line is 32 bytes. */ #define L1_CACHE_BYTES 32 #define L1_CACHE_SHIFT 5 +void flush_dma_list(dma_descr_data *descr); +void flush_dma_descr(dma_descr_data *descr, int flush_buf); + +#define flush_dma_context(c) \ + flush_dma_list(phys_to_virt((c)->saved_data)); + +void cris_flush_cache_range(void *buf, unsigned long len); +void cris_flush_cache(void); + #endif /* _ASM_CRIS_ARCH_CACHE_H */ diff --git a/include/asm-cris/arch-v32/delay.h b/include/asm-cris/arch-v32/delay.h index b6e941e637d..e9fda03810a 100644 --- a/include/asm-cris/arch-v32/delay.h +++ b/include/asm-cris/arch-v32/delay.h @@ -1,6 +1,16 @@ #ifndef _ASM_CRIS_ARCH_DELAY_H #define _ASM_CRIS_ARCH_DELAY_H +extern void cris_delay10ns(u32 n10ns); +#define udelay(u) cris_delay10ns((u)*100) +#define ndelay(n) cris_delay10ns(((n)+9)/10) + +/* + * Not used anymore for udelay or ndelay. Referenced by + * e.g. init/calibrate.c. All other references are likely bugs; + * should be replaced by mdelay, udelay or ndelay. + */ + static inline void __delay(int loops) { diff --git a/include/asm-cris/arch-v32/hwregs/Makefile b/include/asm-cris/arch-v32/hwregs/Makefile index c9160f9949a..f9a05d2aa06 100644 --- a/include/asm-cris/arch-v32/hwregs/Makefile +++ b/include/asm-cris/arch-v32/hwregs/Makefile @@ -1,4 +1,3 @@ -# $Id: Makefile,v 1.8 2004/01/07 21:16:18 johana Exp $ # Makefile to generate or copy the latest register definitions # and related datastructures and helpermacros. # The offical place for these files is at: diff --git a/include/asm-cris/arch-v32/hwregs/dma.h b/include/asm-cris/arch-v32/hwregs/dma.h index c31832d3d6b..3ce322b5c73 100644 --- a/include/asm-cris/arch-v32/hwregs/dma.h +++ b/include/asm-cris/arch-v32/hwregs/dma.h @@ -1,5 +1,4 @@ -/* $Id: dma.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ - * +/* * DMA C definitions and help macros * */ @@ -98,11 +97,11 @@ typedef struct dma_descr_data { // give stream command #define DMA_WR_CMD( inst, cmd_par ) \ - do { reg_dma_rw_stream_cmd r = {0}; \ - do { r = REG_RD( dma, inst, rw_stream_cmd ); } while( r.busy ); \ - r.cmd = (cmd_par); \ - REG_WR( dma, inst, rw_stream_cmd, r ); \ - } while( 0 ) + do { reg_dma_rw_stream_cmd __x = {0}; \ + do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \ + __x.cmd = (cmd_par); \ + REG_WR(dma, inst, rw_stream_cmd, __x); \ + } while (0) // load: g,c,d:burst #define DMA_START_GROUP( inst, group_descr ) \ diff --git a/include/asm-cris/arch-v32/hwregs/eth_defs.h b/include/asm-cris/arch-v32/hwregs/eth_defs.h index 1196d7cc783..90fe8a28894 100644 --- a/include/asm-cris/arch-v32/hwregs/eth_defs.h +++ b/include/asm-cris/arch-v32/hwregs/eth_defs.h @@ -3,12 +3,12 @@ /* * This file is autogenerated from - * file: ../../inst/eth/rtl/eth_regs.r - * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp - * last modfied: Mon Apr 11 16:07:03 2005 + * file: eth.r + * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp + * last modfied: Mon Jan 9 06:06:41 2006 * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile eth_defs.h ../../inst/eth/rtl/eth_regs.r - * id: $Id: eth_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ + * by /n/asic/design/tools/rdesc/rdes2c eth.r + * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $ * Any changes here will be lost. * * -*- buffer-read-only: t -*- @@ -116,26 +116,28 @@ typedef struct { /* Register rw_ga_lo, scope eth, type rw */ typedef struct { - unsigned int table : 32; + unsigned int tbl : 32; } reg_eth_rw_ga_lo; #define REG_RD_ADDR_eth_rw_ga_lo 16 #define REG_WR_ADDR_eth_rw_ga_lo 16 /* Register rw_ga_hi, scope eth, type rw */ typedef struct { - unsigned int table : 32; + unsigned int tbl : 32; } reg_eth_rw_ga_hi; #define REG_RD_ADDR_eth_rw_ga_hi 20 #define REG_WR_ADDR_eth_rw_ga_hi 20 /* Register rw_gen_ctrl, scope eth, type rw */ typedef struct { - unsigned int en : 1; - unsigned int phy : 2; - unsigned int protocol : 1; - unsigned int loopback : 1; - unsigned int flow_ctrl_dis : 1; - unsigned int dummy1 : 26; + unsigned int en : 1; + unsigned int phy : 2; + unsigned int protocol : 1; + unsigned int loopback : 1; + unsigned int flow_ctrl : 1; + unsigned int gtxclk_out : 1; + unsigned int phyrst_n : 1; + unsigned int dummy1 : 24; } reg_eth_rw_gen_ctrl; #define REG_RD_ADDR_eth_rw_gen_ctrl 24 #define REG_WR_ADDR_eth_rw_gen_ctrl 24 @@ -150,22 +152,23 @@ typedef struct { unsigned int oversize : 1; unsigned int bad_crc : 1; unsigned int duplex : 1; - unsigned int max_size : 1; - unsigned int dummy1 : 23; + unsigned int max_size : 16; + unsigned int dummy1 : 8; } reg_eth_rw_rec_ctrl; #define REG_RD_ADDR_eth_rw_rec_ctrl 28 #define REG_WR_ADDR_eth_rw_rec_ctrl 28 /* Register rw_tr_ctrl, scope eth, type rw */ typedef struct { - unsigned int crc : 1; - unsigned int pad : 1; - unsigned int retry : 1; - unsigned int ignore_col : 1; - unsigned int cancel : 1; - unsigned int hsh_delay : 1; - unsigned int ignore_crs : 1; - unsigned int dummy1 : 25; + unsigned int crc : 1; + unsigned int pad : 1; + unsigned int retry : 1; + unsigned int ignore_col : 1; + unsigned int cancel : 1; + unsigned int hsh_delay : 1; + unsigned int ignore_crs : 1; + unsigned int carrier_ext : 1; + unsigned int dummy1 : 24; } reg_eth_rw_tr_ctrl; #define REG_RD_ADDR_eth_rw_tr_ctrl 32 #define REG_WR_ADDR_eth_rw_tr_ctrl 32 @@ -180,13 +183,10 @@ typedef struct { /* Register rw_mgm_ctrl, scope eth, type rw */ typedef struct { - unsigned int mdio : 1; - unsigned int mdoe : 1; - unsigned int mdc : 1; - unsigned int phyclk : 1; - unsigned int txdata : 4; - unsigned int txen : 1; - unsigned int dummy1 : 23; + unsigned int mdio : 1; + unsigned int mdoe : 1; + unsigned int mdc : 1; + unsigned int dummy1 : 29; } reg_eth_rw_mgm_ctrl; #define REG_RD_ADDR_eth_rw_mgm_ctrl 40 #define REG_WR_ADDR_eth_rw_mgm_ctrl 40 @@ -196,17 +196,8 @@ typedef struct { unsigned int mdio : 1; unsigned int exc_col : 1; unsigned int urun : 1; - unsigned int phyclk : 1; - unsigned int txdata : 4; - unsigned int txen : 1; - unsigned int col : 1; - unsigned int crs : 1; - unsigned int txclk : 1; - unsigned int rxdata : 4; - unsigned int rxer : 1; - unsigned int rxdv : 1; - unsigned int rxclk : 1; - unsigned int dummy1 : 13; + unsigned int clk_125 : 1; + unsigned int dummy1 : 28; } reg_eth_r_stat; #define REG_RD_ADDR_eth_r_stat 44 @@ -274,83 +265,83 @@ typedef struct { /* Register rw_intr_mask, scope eth, type rw */ typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int excessive_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int exc_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; } reg_eth_rw_intr_mask; #define REG_RD_ADDR_eth_rw_intr_mask 76 #define REG_WR_ADDR_eth_rw_intr_mask 76 /* Register rw_ack_intr, scope eth, type rw */ typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int excessive_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int exc_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; } reg_eth_rw_ack_intr; #define REG_RD_ADDR_eth_rw_ack_intr 80 #define REG_WR_ADDR_eth_rw_ack_intr 80 /* Register r_intr, scope eth, type r */ typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int excessive_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int exc_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; } reg_eth_r_intr; #define REG_RD_ADDR_eth_r_intr 84 /* Register r_masked_intr, scope eth, type r */ typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int excessive_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int exc_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; } reg_eth_r_masked_intr; #define REG_RD_ADDR_eth_r_masked_intr 88 @@ -360,12 +351,15 @@ enum { regk_eth_discard = 0x00000000, regk_eth_ether = 0x00000000, regk_eth_full = 0x00000001, + regk_eth_gmii = 0x00000003, + regk_eth_gtxclk = 0x00000001, regk_eth_half = 0x00000000, regk_eth_hsh = 0x00000001, regk_eth_mii = 0x00000001, + regk_eth_mii_arec = 0x00000002, regk_eth_mii_clk = 0x00000000, - regk_eth_mii_rec = 0x00000002, regk_eth_no = 0x00000000, + regk_eth_phyrst = 0x00000000, regk_eth_rec = 0x00000001, regk_eth_rw_ga_hi_default = 0x00000000, regk_eth_rw_ga_lo_default = 0x00000000, @@ -377,8 +371,8 @@ enum { regk_eth_rw_ma1_lo_default = 0x00000000, regk_eth_rw_mgm_ctrl_default = 0x00000000, regk_eth_rw_test_ctrl_default = 0x00000000, - regk_eth_size1518 = 0x00000000, - regk_eth_size1522 = 0x00000001, + regk_eth_size1518 = 0x000005ee, + regk_eth_size1522 = 0x000005f2, regk_eth_yes = 0x00000001 }; #endif /* __eth_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h index 44e60233c68..236f91efe7e 100644 --- a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h +++ b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h @@ -1,15 +1,17 @@ -/* $Id: reg_rdwr.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ - * +/* * Read/write register macros used by *_defs.h */ #ifndef reg_rdwr_h #define reg_rdwr_h +#ifndef REG_READ +#define REG_READ(type, addr) (*((volatile type *) (addr))) +#endif -#define REG_READ(type, addr) *((volatile type *) (addr)) - +#ifndef REG_WRITE #define REG_WRITE(type, addr, val) \ do { *((volatile type *) (addr)) = (val); } while(0) +#endif #endif diff --git a/include/asm-cris/arch-v32/io.h b/include/asm-cris/arch-v32/io.h index 5efe4d94900..6b38912f29b 100644 --- a/include/asm-cris/arch-v32/io.h +++ b/include/asm-cris/arch-v32/io.h @@ -1,9 +1,10 @@ #ifndef _ASM_ARCH_CRIS_IO_H #define _ASM_ARCH_CRIS_IO_H -#include <asm/arch/hwregs/reg_map.h> -#include <asm/arch/hwregs/reg_rdwr.h> -#include <asm/arch/hwregs/gio_defs.h> +#include <linux/spinlock.h> +#include <hwregs/reg_map.h> +#include <hwregs/reg_rdwr.h> +#include <hwregs/gio_defs.h> enum crisv32_io_dir { @@ -13,10 +14,11 @@ enum crisv32_io_dir struct crisv32_ioport { - unsigned long* oe; - unsigned long* data; - unsigned long* data_in; + volatile unsigned long *oe; + volatile unsigned long *data; + volatile unsigned long *data_in; unsigned int pin_count; + spinlock_t lock; }; struct crisv32_iopin @@ -34,22 +36,36 @@ extern struct crisv32_iopin crisv32_led2_red; extern struct crisv32_iopin crisv32_led3_green; extern struct crisv32_iopin crisv32_led3_red; -static inline void crisv32_io_set(struct crisv32_iopin* iopin, - int val) +extern struct crisv32_iopin crisv32_led_net0_green; +extern struct crisv32_iopin crisv32_led_net0_red; +extern struct crisv32_iopin crisv32_led_net1_green; +extern struct crisv32_iopin crisv32_led_net1_red; + +static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val) { + long flags; + spin_lock_irqsave(&iopin->port->lock, flags); + if (val) *iopin->port->data |= iopin->bit; else *iopin->port->data &= ~iopin->bit; + + spin_unlock_irqrestore(&iopin->port->lock, flags); } static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin, enum crisv32_io_dir dir) { + long flags; + spin_lock_irqsave(&iopin->port->lock, flags); + if (dir == crisv32_io_dir_in) *iopin->port->oe &= ~iopin->bit; else *iopin->port->oe |= iopin->bit; + + spin_unlock_irqrestore(&iopin->port->lock, flags); } static inline int crisv32_io_rd(struct crisv32_iopin* iopin) @@ -60,38 +76,61 @@ static inline int crisv32_io_rd(struct crisv32_iopin* iopin) int crisv32_io_get(struct crisv32_iopin* iopin, unsigned int port, unsigned int pin); int crisv32_io_get_name(struct crisv32_iopin* iopin, - char* name); + const char *name); -#define LED_OFF 0x00 -#define LED_GREEN 0x01 -#define LED_RED 0x02 -#define LED_ORANGE (LED_GREEN | LED_RED) +#define CRIS_LED_OFF 0x00 +#define CRIS_LED_GREEN 0x01 +#define CRIS_LED_RED 0x02 +#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) -#define LED_NETWORK_SET(x) \ - do { \ - LED_NETWORK_SET_G((x) & LED_GREEN); \ - LED_NETWORK_SET_R((x) & LED_RED); \ +#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)) +#define CRIS_LED_NETWORK_GRP0_SET(x) \ + do { \ + CRIS_LED_NETWORK_GRP0_SET_G((x) & CRIS_LED_GREEN); \ + CRIS_LED_NETWORK_GRP0_SET_R((x) & CRIS_LED_RED); \ } while (0) -#define LED_ACTIVE_SET(x) \ +#else +#define CRIS_LED_NETWORK_GRP0_SET(x) while (0) {} +#endif + +#define CRIS_LED_NETWORK_GRP0_SET_G(x) \ + crisv32_io_set(&crisv32_led_net0_green, !(x)); + +#define CRIS_LED_NETWORK_GRP0_SET_R(x) \ + crisv32_io_set(&crisv32_led_net0_red, !(x)); + +#if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO) +#define CRIS_LED_NETWORK_GRP1_SET(x) \ + do { \ + CRIS_LED_NETWORK_GRP1_SET_G((x) & CRIS_LED_GREEN); \ + CRIS_LED_NETWORK_GRP1_SET_R((x) & CRIS_LED_RED); \ + } while (0) +#else +#define CRIS_LED_NETWORK_GRP1_SET(x) while (0) {} +#endif + +#define CRIS_LED_NETWORK_GRP1_SET_G(x) \ + crisv32_io_set(&crisv32_led_net1_green, !(x)); + +#define CRIS_LED_NETWORK_GRP1_SET_R(x) \ + crisv32_io_set(&crisv32_led_net1_red, !(x)); + +#define CRIS_LED_ACTIVE_SET(x) \ do { \ - LED_ACTIVE_SET_G((x) & LED_GREEN); \ - LED_ACTIVE_SET_R((x) & LED_RED); \ + CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ + CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ } while (0) -#define LED_NETWORK_SET_G(x) \ - crisv32_io_set(&crisv32_led1_green, !(x)); -#define LED_NETWORK_SET_R(x) \ - crisv32_io_set(&crisv32_led1_red, !(x)); -#define LED_ACTIVE_SET_G(x) \ +#define CRIS_LED_ACTIVE_SET_G(x) \ crisv32_io_set(&crisv32_led2_green, !(x)); -#define LED_ACTIVE_SET_R(x) \ +#define CRIS_LED_ACTIVE_SET_R(x) \ crisv32_io_set(&crisv32_led2_red, !(x)); -#define LED_DISK_WRITE(x) \ +#define CRIS_LED_DISK_WRITE(x) \ do{\ crisv32_io_set(&crisv32_led3_green, !(x)); \ crisv32_io_set(&crisv32_led3_red, !(x)); \ }while(0) -#define LED_DISK_READ(x) \ +#define CRIS_LED_DISK_READ(x) \ crisv32_io_set(&crisv32_led3_green, !(x)); #endif diff --git a/include/asm-cris/arch-v32/irq.h b/include/asm-cris/arch-v32/irq.h index bac94ee6bc9..9e4c9fbdfdd 100644 --- a/include/asm-cris/arch-v32/irq.h +++ b/include/asm-cris/arch-v32/irq.h @@ -1,12 +1,17 @@ #ifndef _ASM_ARCH_IRQ_H #define _ASM_ARCH_IRQ_H -#include "hwregs/intr_vect.h" +#include <hwregs/intr_vect.h> /* Number of non-cpu interrupts. */ -#define NR_IRQS 0x50 /* Exceptions + IRQs */ -#define NR_REAL_IRQS 0x20 /* IRQs */ +#define NR_IRQS NBR_INTR_VECT /* Exceptions + IRQs */ #define FIRST_IRQ 0x31 /* Exception number for first IRQ */ +#define NR_REAL_IRQS (NBR_INTR_VECT - FIRST_IRQ) /* IRQs */ +#if NR_REAL_IRQS > 32 +#define MACH_IRQS 64 +#else +#define MACH_IRQS 32 +#endif #ifndef __ASSEMBLY__ /* Global IRQ vector. */ @@ -73,7 +78,7 @@ void set_exception_vector(int n, irqvectptr addr); * which will acknowledge the interrupt, is run. The actual blocking is made * by crisv32_do_IRQ. */ -#define BUILD_IRQ(nr, mask) \ +#define BUILD_IRQ(nr) \ void IRQ_NAME(nr); \ __asm__ ( \ ".text\n\t" \ @@ -81,7 +86,7 @@ __asm__ ( \ SAVE_ALL \ KGDB_FIXUP \ "move.d "#nr",$r10\n\t" \ - "move.d $sp,$r12\n\t" \ + "move.d $sp, $r12\n\t" \ "jsr crisv32_do_IRQ\n\t" \ "moveq 1, $r11\n\t" \ "jump ret_from_intr\n\t" \ diff --git a/include/asm-cris/arch-v32/juliette.h b/include/asm-cris/arch-v32/juliette.h deleted file mode 100644 index f1f81725e57..00000000000 --- a/include/asm-cris/arch-v32/juliette.h +++ /dev/null @@ -1,326 +0,0 @@ -#ifndef _ASM_JULIETTE_H -#define _ASM_JULIETTE_H - -/* juliette _IOC_TYPE, bits 8 to 15 in ioctl cmd */ - -#define JULIOCTYPE 42 - -/* supported ioctl _IOC_NR's */ - -#define JULSTARTDMA 0x1 /* start a picture asynchronously */ - -/* set parameters */ - -#define SETDEFAULT 0x2 /* CCD/VIDEO/SS1M */ -#define SETPARAMETERS 0x3 /* CCD/VIDEO */ -#define SETSIZE 0x4 /* CCD/VIDEO/SS1M */ -#define SETCOMPRESSION 0x5 /* CCD/VIDEO/SS1M */ -#define SETCOLORLEVEL 0x6 /* CCD/VIDEO */ -#define SETBRIGHTNESS 0x7 /* CCD */ -#define SETROTATION 0x8 /* CCD */ -#define SETTEXT 0x9 /* CCD/VIDEO/SS1M */ -#define SETCLOCK 0xa /* CCD/VIDEO/SS1M */ -#define SETDATE 0xb /* CCD/VIDEO/SS1M */ -#define SETTIMEFORMAT 0xc /* CCD/VIDEO/SS1M */ -#define SETDATEFORMAT 0xd /* VIDEO */ -#define SETTEXTALIGNMENT 0xe /* VIDEO */ -#define SETFPS 0xf /* CCD/VIDEO/SS1M */ -#define SETVGA 0xff /* VIDEO */ -#define SETCOMMENT 0xfe /* CCD/VIDEO */ - -/* get parameters */ - -#define GETDRIVERTYPE 0x10 /* CCD/VIDEO/SS1M */ -#define GETNBROFCAMERAS 0x11 /* CCD/VIDEO/SS1M */ -#define GETPARAMETERS 0x12 /* CCD/VIDEO/SS1M */ -#define GETBUFFERSIZE 0x13 /* CCD/VIDEO/SS1M */ -#define GETVIDEOTYPE 0x14 /* VIDEO/SS1M */ -#define GETVIDEOSIGNAL 0x15 /* VIDEO */ -#define GETMODULATION 0x16 /* VIDEO */ -#define GETDCYVALUES 0xa0 /* CCD /SS1M */ -#define GETDCYWIDTH 0xa1 /* CCD /SS1M */ -#define GETDCYHEIGHT 0xa2 /* CCD /SS1M */ -#define GETSIZE 0xa3 /* CCD/VIDEO */ -#define GETCOMPRESSION 0xa4 /* CCD/VIDEO */ - -/* detect and get parameters */ - -#define DETECTMODULATION 0x17 /* VIDEO */ -#define DETECTVIDEOTYPE 0x18 /* VIDEO */ -#define DETECTVIDEOSIGNAL 0x19 /* VIDEO */ - -/* configure default parameters */ - -#define CONFIGUREDEFAULT 0x20 /* CCD/VIDEO/SS1M */ -#define DEFSIZE 0x21 /* CCD/VIDEO/SS1M */ -#define DEFCOMPRESSION 0x22 /* CCD/VIDEO/SS1M */ -#define DEFCOLORLEVEL 0x23 /* CCD/VIDEO */ -#define DEFBRIGHTNESS 0x24 /* CCD */ -#define DEFROTATION 0x25 /* CCD */ -#define DEFWHITEBALANCE 0x26 /* CCD */ -#define DEFEXPOSURE 0x27 /* CCD */ -#define DEFAUTOEXPWINDOW 0x28 /* CCD */ -#define DEFTEXT 0x29 /* CCD/VIDEO/SS1M */ -#define DEFCLOCK 0x2a /* CCD/VIDEO/SS1M */ -#define DEFDATE 0x2b /* CCD/VIDEO/SS1M */ -#define DEFTIMEFORMAT 0x2c /* CCD/VIDEO/SS1M */ -#define DEFDATEFORMAT 0x2d /* VIDEO */ -#define DEFTEXTALIGNMENT 0x2e /* VIDEO */ -#define DEFFPS 0x2f /* CCD/VIDEO/SS1M */ -#define DEFTEXTSTRING 0x30 /* CCD/VIDEO/SS1M */ -#define DEFHEADERINFO 0x31 /* CCD/VIDEO/SS1M */ -#define DEFWEXAR 0x32 /* CCD */ -#define DEFLINEDELAY 0x33 /* CCD */ -#define DEFDISABLEDVIDEO 0x34 /* VIDEO */ -#define DEFVIDEOTYPE 0x35 /* VIDEO */ -#define DEFMODULATION 0x36 /* VIDEO */ -#define DEFXOFFSET 0x37 /* VIDEO */ -#define DEFYOFFSET 0x38 /* VIDEO */ -#define DEFYCMODE 0x39 /* VIDEO */ -#define DEFVCRMODE 0x3a /* VIDEO */ -#define DEFSTOREDCYVALUES 0x3b /* CCD/VIDEO/SS1M */ -#define DEFWCDS 0x3c /* CCD */ -#define DEFVGA 0x3d /* VIDEO */ -#define DEFCOMMENT 0x3e /* CCD/VIDEO */ -#define DEFCOMMENTSIZE 0x3f /* CCD/VIDEO */ -#define DEFCOMMENTTEXT 0x50 /* CCD/VIDEO */ -#define DEFSTOREDCYTEXT 0x51 /* VIDEO */ - - -#define JULABORTDMA 0x70 /* Abort current DMA transfer */ - -/* juliette general i/o port */ - -#define JIO_READBITS 0x40 /* read and return current port bits */ -#define JIO_SETBITS 0x41 /* set bits marked by 1 in the argument */ -#define JIO_CLRBITS 0x42 /* clr bits marked by 1 in the argument */ -#define JIO_READDIR 0x43 /* read direction, 0=input 1=output */ -#define JIO_SETINPUT 0x44 /* set direction, 0=unchanged 1=input - returns current dir */ -#define JIO_SETOUTPUT 0x45 /* set direction, 0=unchanged 1=output - returns current dir */ - -/**** YumYum internal adresses ****/ - -/* Juliette buffer addresses */ - -#define BUFFER1_VIDEO 0x1100 -#define BUFFER2_VIDEO 0x2800 -#define ACDC_BUFF_VIDEO 0x0aaa -#define BUFFER1 0x1700 -#define BUFFER2 0x2b01 -#define ACDC_BUFFER 0x1200 -#define BUFFER1_SS1M 0x1100 -#define BUFFER2_SS1M 0x2800 -#define ACDC_BUFF_SS1M 0x0900 - -/* Juliette parameter memory addresses */ - -#define PA_BUFFER_CNT 0x3f09 /* CCD/VIDEO */ -#define PA_CCD_BUFFER 0x3f10 /* CCD */ -#define PA_VIDEO_BUFFER 0x3f10 /* VIDEO */ -#define PA_DCT_BUFFER 0x3f11 /* CCD/VIDEO */ -#define PA_TEMP 0x3f12 /* CCD/VIDEO */ -#define PA_VIDEOLINE_RD 0x3f13 /* VIDEO */ -#define PA_VIDEOLINE_WR 0x3f14 /* VIDEO */ -#define PA_VI_HDELAY0 0x3f15 /* VIDEO */ -#define PA_VI_VDELAY0 0x3f16 /* VIDEO */ -#define PA_VI_HDELAY1 0x3f17 /* VIDEO */ -#define PA_VI_VDELAY1 0x3f18 /* VIDEO */ -#define PA_VI_HDELAY2 0x3f19 /* VIDEO */ -#define PA_VI_VDELAY2 0x3f1a /* VIDEO */ -#define PA_VI_HDELAY3 0x3f1b /* VIDEO */ -#define PA_VI_VDELAY3 0x3f1c /* VIDEO */ -#define PA_VI_CTRL 0x3f20 /* VIDEO */ -#define PA_JPEG_CTRL 0x3f22 /* CCD/VIDEO */ -#define PA_BUFFER_SIZE 0x3f24 /* CCD/VIDEO */ -#define PA_PAL_NTSC 0x3f25 /* VIDEO */ -#define PA_MACROBLOCKS 0x3f26 /* CCD/VIDEO */ -#define PA_COLOR 0x3f27 /* VIDEO */ -#define PA_MEMCH1CNT2 0x3f28 /* CCD/VIDEO */ -#define PA_MEMCH1CNT3 0x3f29 /* VIDEO */ -#define PA_MEMCH1STR2 0x3f2a /* CCD/VIDEO */ -#define PA_MEMCH1STR3 0x3f2b /* VIDEO */ -#define PA_BUFFERS 0x3f2c /* CCD/VIDEO */ -#define PA_PROGRAM 0x3f2d /* CCD/VIDEO */ -#define PA_ROTATION 0x3f2e /* CCD */ -#define PA_PC 0x3f30 /* CCD/VIDEO */ -#define PA_PC2 0x3f31 /* VIDEO */ -#define PA_ODD_LINE 0x3f32 /* VIDEO */ -#define PA_EXP_DELAY 0x3f34 /* CCD */ -#define PA_MACROBLOCK_CNT 0x3f35 /* CCD/VIDEO */ -#define PA_DRAM_PTR1_L 0x3f36 /* CCD/VIDEO */ -#define PA_CLPOB_CNT 0x3f37 /* CCD */ -#define PA_DRAM_PTR1_H 0x3f38 /* CCD/VIDEO */ -#define PA_DRAM_PTR2_L 0x3f3a /* VIDEO */ -#define PA_DRAM_PTR2_H 0x3f3c /* VIDEO */ -#define PA_CCD_LINE_CNT 0x3f3f /* CCD */ -#define PA_VIDEO_LINE_CNT 0x3f3f /* VIDEO */ -#define PA_TEXT 0x3f41 /* CCD/VIDEO */ -#define PA_CAMERA_CHANGED 0x3f42 /* VIDEO */ -#define PA_TEXTALIGNMENT 0x3f43 /* VIDEO */ -#define PA_DISABLED 0x3f44 /* VIDEO */ -#define PA_MACROBLOCKTEXT 0x3f45 /* VIDEO */ -#define PA_VGA 0x3f46 /* VIDEO */ -#define PA_ZERO 0x3ffe /* VIDEO */ -#define PA_NULL 0x3fff /* CCD/VIDEO */ - -typedef enum { - jpeg = 0, - dummy = 1 -} request_type; - -typedef enum { - hugesize = 0, - fullsize = 1, - halfsize = 2, - fieldsize = 3 -} size_type; - -typedef enum { - min = 0, - low = 1, - medium = 2, - high = 3, - very_high = 4, - very_low = 5, - q1 = 6, - q2 = 7, - q3 = 8, - q4 = 9, - q5 = 10, - q6 = 11 -} compr_type; - -typedef enum { - deg_0 = 0, - deg_180 = 1, - deg_90 = 2, - deg_270 = 3 -} rotation_type; - -typedef enum { - auto_white = 0, - hold = 1, - fixed_outdoor = 2, - fixed_indoor = 3, - fixed_fluor = 4 -} white_balance_type; - -typedef enum { - auto_exp = 0, - fixed_exp = 1 -} exposure_type; - -typedef enum { - no_window = 0, - center = 1, - top = 2, - lower = 3, - left = 4, - right = 5, - spot = 6, - cw = 7 -} exp_window_type; - -typedef enum { - h_24 = 0, - h_12 = 1, - h_24P = 2 -} hour_type; - -typedef enum { - standard = 0, - YYYY_MM_DD = 1, - Www_Mmm_DD_YYYY = 2, - Www_DD_MM_YYYY = 3 -} date_type; - -typedef enum { - left_align = 0, - center_align = 1, - right_align = 2 -} alignment_type; - -typedef enum { - off = 0, - on = 1, - no = 0, - yes = 1 -} enable_type; - -typedef enum { - disabled = 0, - enabled = 1, - extended = 2 -} comment_type; - -typedef enum { - pal = 0, - ntsc = 1 -} video_type; - -typedef enum { - pal_bghi_ntsc_m = 0, - ntsc_4_43_50hz_pal_4_43_60hz = 1, - pal_n_ntsc_4_43_60hz = 2, - ntsc_n_pal_m = 3, - secam_pal_4_43_60hz = 4 -} modulation_type; - -typedef enum { - cam0 = 0, - cam1 = 1, - cam2 = 2, - cam3 = 3, - quad = 32 -} camera_type; - -typedef enum { - video_driver = 0, - ccd_driver = 1 -} driver_type; - -struct jul_param { - request_type req_type; - size_type size; - compr_type compression; - rotation_type rotation; - int color_level; - int brightness; - white_balance_type white_balance; - exposure_type exposure; - exp_window_type auto_exp_window; - hour_type time_format; - date_type date_format; - alignment_type text_alignment; - enable_type text; - enable_type clock; - enable_type date; - enable_type fps; - enable_type vga; - enable_type comment; -}; - -struct video_param { - enable_type disabled; - modulation_type modulation; - video_type video; - enable_type signal; - enable_type vcr; - int xoffset; - int yoffset; -}; - -/* The juliette_request structure is used during the JULSTARTDMA asynchronous - * picture-taking ioctl call as an argument to specify a buffer which will get - * the final picture. - */ - -struct juliette_request { - char *buf; /* Pointer to the buffer to hold picture data */ - unsigned int buflen; /* Length of the above buffer */ - unsigned int size; /* Resulting length, 0 if the picture is not ready */ -}; - -#endif diff --git a/include/asm-cris/arch-v32/mach-a3/arbiter.h b/include/asm-cris/arch-v32/mach-a3/arbiter.h new file mode 100644 index 00000000000..65e9d6ff052 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/arbiter.h @@ -0,0 +1,34 @@ +#ifndef _ASM_CRIS_ARCH_ARBITER_H +#define _ASM_CRIS_ARCH_ARBITER_H + +#define EXT_REGION 0 +#define INT_REGION 1 + +typedef void (watch_callback)(void); + +enum { + arbiter_all_dmas = 0x7fe, + arbiter_cpu = 0x1800, + arbiter_all_clients = 0x7fff +}; + +enum { + arbiter_bar_all_clients = 0x1ff +}; + +enum { + arbiter_all_read = 0x55, + arbiter_all_write = 0xaa, + arbiter_all_accesses = 0xff +}; + +#define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli)) + +int crisv32_arbiter_allocate_bandwidth(int client, int region, + unsigned long bandwidth); +int crisv32_arbiter_watch(unsigned long start, unsigned long size, + unsigned long clients, unsigned long accesses, + watch_callback * cb); +int crisv32_arbiter_unwatch(int id); + +#endif diff --git a/include/asm-cris/arch-v32/mach-a3/dma.h b/include/asm-cris/arch-v32/mach-a3/dma.h new file mode 100644 index 00000000000..9e8eb13b601 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/dma.h @@ -0,0 +1,31 @@ +#ifndef _ASM_ARCH_CRIS_DMA_H +#define _ASM_ARCH_CRIS_DMA_H + +/* Defines for using and allocating dma channels. */ + +#define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */ + +enum dma_owner { + dma_eth, + dma_ser0, + dma_ser1, + dma_ser2, + dma_ser3, + dma_ser4, + dma_iop, + dma_sser, + dma_strp, + dma_h264, + dma_jpeg +}; + +int crisv32_request_dma(unsigned int dmanr, const char *device_id, + unsigned options, unsigned bandwidth, enum dma_owner owner); +void crisv32_free_dma(unsigned int dmanr); + +/* Masks used by crisv32_request_dma options: */ +#define DMA_VERBOSE_ON_ERROR 1 +#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) +#define DMA_INT_MEM 4 + +#endif /* _ASM_ARCH_CRIS_DMA_H */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h new file mode 100644 index 00000000000..02855adf63e --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h @@ -0,0 +1,164 @@ +#ifndef __clkgen_defs_asm_h +#define __clkgen_defs_asm_h + +/* + * This file is autogenerated from + * file: clkgen.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_bootsel, scope clkgen, type r */ +#define reg_clkgen_r_bootsel___boot_mode___lsb 0 +#define reg_clkgen_r_bootsel___boot_mode___width 5 +#define reg_clkgen_r_bootsel___intern_main_clk___lsb 5 +#define reg_clkgen_r_bootsel___intern_main_clk___width 1 +#define reg_clkgen_r_bootsel___intern_main_clk___bit 5 +#define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6 +#define reg_clkgen_r_bootsel___extern_usb2_clk___width 1 +#define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6 +#define reg_clkgen_r_bootsel_offset 0 + +/* Register rw_clk_ctrl, scope clkgen, type rw */ +#define reg_clkgen_rw_clk_ctrl___pll___lsb 0 +#define reg_clkgen_rw_clk_ctrl___pll___width 1 +#define reg_clkgen_rw_clk_ctrl___pll___bit 0 +#define reg_clkgen_rw_clk_ctrl___cpu___lsb 1 +#define reg_clkgen_rw_clk_ctrl___cpu___width 1 +#define reg_clkgen_rw_clk_ctrl___cpu___bit 1 +#define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2 +#define reg_clkgen_rw_clk_ctrl___iop_usb___width 1 +#define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2 +#define reg_clkgen_rw_clk_ctrl___vin___lsb 3 +#define reg_clkgen_rw_clk_ctrl___vin___width 1 +#define reg_clkgen_rw_clk_ctrl___vin___bit 3 +#define reg_clkgen_rw_clk_ctrl___sclr___lsb 4 +#define reg_clkgen_rw_clk_ctrl___sclr___width 1 +#define reg_clkgen_rw_clk_ctrl___sclr___bit 4 +#define reg_clkgen_rw_clk_ctrl___h264___lsb 5 +#define reg_clkgen_rw_clk_ctrl___h264___width 1 +#define reg_clkgen_rw_clk_ctrl___h264___bit 5 +#define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6 +#define reg_clkgen_rw_clk_ctrl___ddr2___width 1 +#define reg_clkgen_rw_clk_ctrl___ddr2___bit 6 +#define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7 +#define reg_clkgen_rw_clk_ctrl___vout_hist___width 1 +#define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7 +#define reg_clkgen_rw_clk_ctrl___eth___lsb 8 +#define reg_clkgen_rw_clk_ctrl___eth___width 1 +#define reg_clkgen_rw_clk_ctrl___eth___bit 8 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9 +#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10 +#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1 +#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11 +#define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12 +#define reg_clkgen_rw_clk_ctrl___jpeg___width 1 +#define reg_clkgen_rw_clk_ctrl___jpeg___bit 12 +#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13 +#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1 +#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13 +#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14 +#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1 +#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14 +#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15 +#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1 +#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15 +#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16 +#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1 +#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16 +#define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17 +#define reg_clkgen_rw_clk_ctrl___dma9_11___width 1 +#define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17 +#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18 +#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1 +#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18 +#define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19 +#define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1 +#define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19 +#define reg_clkgen_rw_clk_ctrl_offset 4 + + +/* Constants */ +#define regk_clkgen_eth1000_rx 0x0000000c +#define regk_clkgen_eth1000_tx 0x0000000e +#define regk_clkgen_eth100_rx 0x0000001d +#define regk_clkgen_eth100_rx_half 0x0000001c +#define regk_clkgen_eth100_tx 0x0000001f +#define regk_clkgen_eth100_tx_half 0x0000001e +#define regk_clkgen_nand_3_2 0x00000000 +#define regk_clkgen_nand_3_2_0x30 0x00000002 +#define regk_clkgen_nand_3_2_0x30_pll 0x00000012 +#define regk_clkgen_nand_3_2_pll 0x00000010 +#define regk_clkgen_nand_3_3 0x00000001 +#define regk_clkgen_nand_3_3_0x30 0x00000003 +#define regk_clkgen_nand_3_3_0x30_pll 0x00000013 +#define regk_clkgen_nand_3_3_pll 0x00000011 +#define regk_clkgen_nand_4_2 0x00000004 +#define regk_clkgen_nand_4_2_0x30 0x00000006 +#define regk_clkgen_nand_4_2_0x30_pll 0x00000016 +#define regk_clkgen_nand_4_2_pll 0x00000014 +#define regk_clkgen_nand_4_3 0x00000005 +#define regk_clkgen_nand_4_3_0x30 0x00000007 +#define regk_clkgen_nand_4_3_0x30_pll 0x00000017 +#define regk_clkgen_nand_4_3_pll 0x00000015 +#define regk_clkgen_nand_5_2 0x00000008 +#define regk_clkgen_nand_5_2_0x30 0x0000000a +#define regk_clkgen_nand_5_2_0x30_pll 0x0000001a +#define regk_clkgen_nand_5_2_pll 0x00000018 +#define regk_clkgen_nand_5_3 0x00000009 +#define regk_clkgen_nand_5_3_0x30 0x0000000b +#define regk_clkgen_nand_5_3_0x30_pll 0x0000001b +#define regk_clkgen_nand_5_3_pll 0x00000019 +#define regk_clkgen_no 0x00000000 +#define regk_clkgen_rw_clk_ctrl_default 0x00000002 +#define regk_clkgen_ser 0x0000000d +#define regk_clkgen_ser_pll 0x0000000f +#define regk_clkgen_yes 0x00000001 +#endif /* __clkgen_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h new file mode 100644 index 00000000000..b12be03edac --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h @@ -0,0 +1,266 @@ +#ifndef __ddr2_defs_asm_h +#define __ddr2_defs_asm_h + +/* + * This file is autogenerated from + * file: ddr2.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope ddr2, type rw */ +#define reg_ddr2_rw_cfg___col_width___lsb 0 +#define reg_ddr2_rw_cfg___col_width___width 4 +#define reg_ddr2_rw_cfg___nr_banks___lsb 4 +#define reg_ddr2_rw_cfg___nr_banks___width 1 +#define reg_ddr2_rw_cfg___nr_banks___bit 4 +#define reg_ddr2_rw_cfg___bw___lsb 5 +#define reg_ddr2_rw_cfg___bw___width 1 +#define reg_ddr2_rw_cfg___bw___bit 5 +#define reg_ddr2_rw_cfg___nr_ref___lsb 6 +#define reg_ddr2_rw_cfg___nr_ref___width 4 +#define reg_ddr2_rw_cfg___ref_interval___lsb 10 +#define reg_ddr2_rw_cfg___ref_interval___width 11 +#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21 +#define reg_ddr2_rw_cfg___odt_ctrl___width 2 +#define reg_ddr2_rw_cfg___odt_mem___lsb 23 +#define reg_ddr2_rw_cfg___odt_mem___width 1 +#define reg_ddr2_rw_cfg___odt_mem___bit 23 +#define reg_ddr2_rw_cfg___imp_strength___lsb 24 +#define reg_ddr2_rw_cfg___imp_strength___width 1 +#define reg_ddr2_rw_cfg___imp_strength___bit 24 +#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25 +#define reg_ddr2_rw_cfg___auto_imp_cal___width 1 +#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25 +#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26 +#define reg_ddr2_rw_cfg___imp_cal_override___width 1 +#define reg_ddr2_rw_cfg___imp_cal_override___bit 26 +#define reg_ddr2_rw_cfg___dll_override___lsb 27 +#define reg_ddr2_rw_cfg___dll_override___width 1 +#define reg_ddr2_rw_cfg___dll_override___bit 27 +#define reg_ddr2_rw_cfg_offset 0 + +/* Register rw_timing, scope ddr2, type rw */ +#define reg_ddr2_rw_timing___wr___lsb 0 +#define reg_ddr2_rw_timing___wr___width 3 +#define reg_ddr2_rw_timing___rcd___lsb 3 +#define reg_ddr2_rw_timing___rcd___width 3 +#define reg_ddr2_rw_timing___rp___lsb 6 +#define reg_ddr2_rw_timing___rp___width 3 +#define reg_ddr2_rw_timing___ras___lsb 9 +#define reg_ddr2_rw_timing___ras___width 4 +#define reg_ddr2_rw_timing___rfc___lsb 13 +#define reg_ddr2_rw_timing___rfc___width 7 +#define reg_ddr2_rw_timing___rc___lsb 20 +#define reg_ddr2_rw_timing___rc___width 5 +#define reg_ddr2_rw_timing___rtp___lsb 25 +#define reg_ddr2_rw_timing___rtp___width 2 +#define reg_ddr2_rw_timing___rtw___lsb 27 +#define reg_ddr2_rw_timing___rtw___width 3 +#define reg_ddr2_rw_timing___wtr___lsb 30 +#define reg_ddr2_rw_timing___wtr___width 2 +#define reg_ddr2_rw_timing_offset 4 + +/* Register rw_latency, scope ddr2, type rw */ +#define reg_ddr2_rw_latency___cas___lsb 0 +#define reg_ddr2_rw_latency___cas___width 3 +#define reg_ddr2_rw_latency___additive___lsb 3 +#define reg_ddr2_rw_latency___additive___width 3 +#define reg_ddr2_rw_latency_offset 8 + +/* Register rw_phy_cfg, scope ddr2, type rw */ +#define reg_ddr2_rw_phy_cfg___en___lsb 0 +#define reg_ddr2_rw_phy_cfg___en___width 1 +#define reg_ddr2_rw_phy_cfg___en___bit 0 +#define reg_ddr2_rw_phy_cfg_offset 12 + +/* Register rw_phy_ctrl, scope ddr2, type rw */ +#define reg_ddr2_rw_phy_ctrl___rst___lsb 0 +#define reg_ddr2_rw_phy_ctrl___rst___width 1 +#define reg_ddr2_rw_phy_ctrl___rst___bit 0 +#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1 +#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1 +#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1 +#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2 +#define reg_ddr2_rw_phy_ctrl___cal_start___width 1 +#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2 +#define reg_ddr2_rw_phy_ctrl_offset 16 + +/* Register rw_ctrl, scope ddr2, type rw */ +#define reg_ddr2_rw_ctrl___mrs_data___lsb 0 +#define reg_ddr2_rw_ctrl___mrs_data___width 16 +#define reg_ddr2_rw_ctrl___cmd___lsb 16 +#define reg_ddr2_rw_ctrl___cmd___width 8 +#define reg_ddr2_rw_ctrl_offset 20 + +/* Register rw_pwr_down, scope ddr2, type rw */ +#define reg_ddr2_rw_pwr_down___self_ref___lsb 0 +#define reg_ddr2_rw_pwr_down___self_ref___width 2 +#define reg_ddr2_rw_pwr_down___phy_en___lsb 2 +#define reg_ddr2_rw_pwr_down___phy_en___width 1 +#define reg_ddr2_rw_pwr_down___phy_en___bit 2 +#define reg_ddr2_rw_pwr_down_offset 24 + +/* Register r_stat, scope ddr2, type r */ +#define reg_ddr2_r_stat___dll_lock___lsb 0 +#define reg_ddr2_r_stat___dll_lock___width 1 +#define reg_ddr2_r_stat___dll_lock___bit 0 +#define reg_ddr2_r_stat___dll_delay_code___lsb 1 +#define reg_ddr2_r_stat___dll_delay_code___width 7 +#define reg_ddr2_r_stat___imp_cal_done___lsb 8 +#define reg_ddr2_r_stat___imp_cal_done___width 1 +#define reg_ddr2_r_stat___imp_cal_done___bit 8 +#define reg_ddr2_r_stat___imp_cal_fault___lsb 9 +#define reg_ddr2_r_stat___imp_cal_fault___width 1 +#define reg_ddr2_r_stat___imp_cal_fault___bit 9 +#define reg_ddr2_r_stat___cal_imp_pu___lsb 10 +#define reg_ddr2_r_stat___cal_imp_pu___width 4 +#define reg_ddr2_r_stat___cal_imp_pd___lsb 14 +#define reg_ddr2_r_stat___cal_imp_pd___width 4 +#define reg_ddr2_r_stat_offset 28 + +/* Register rw_imp_ctrl, scope ddr2, type rw */ +#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0 +#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4 +#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4 +#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4 +#define reg_ddr2_rw_imp_ctrl_offset 32 + +#define STRIDE_ddr2_rw_dll_ctrl 4 +/* Register rw_dll_ctrl, scope ddr2, type rw */ +#define reg_ddr2_rw_dll_ctrl___mode___lsb 0 +#define reg_ddr2_rw_dll_ctrl___mode___width 1 +#define reg_ddr2_rw_dll_ctrl___mode___bit 0 +#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1 +#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7 +#define reg_ddr2_rw_dll_ctrl_offset 36 + +#define STRIDE_ddr2_rw_dqs_dll_ctrl 4 +/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ +#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7 +#define reg_ddr2_rw_dqs_dll_ctrl_offset 52 + + +/* Constants */ +#define regk_ddr2_al0 0x00000000 +#define regk_ddr2_al1 0x00000008 +#define regk_ddr2_al2 0x00000010 +#define regk_ddr2_al3 0x00000018 +#define regk_ddr2_al4 0x00000020 +#define regk_ddr2_auto 0x00000003 +#define regk_ddr2_bank4 0x00000000 +#define regk_ddr2_bank8 0x00000001 +#define regk_ddr2_bl4 0x00000002 +#define regk_ddr2_bl8 0x00000003 +#define regk_ddr2_bt_il 0x00000008 +#define regk_ddr2_bt_seq 0x00000000 +#define regk_ddr2_bw16 0x00000001 +#define regk_ddr2_bw32 0x00000000 +#define regk_ddr2_cas2 0x00000020 +#define regk_ddr2_cas3 0x00000030 +#define regk_ddr2_cas4 0x00000040 +#define regk_ddr2_cas5 0x00000050 +#define regk_ddr2_deselect 0x000000c0 +#define regk_ddr2_dic_weak 0x00000002 +#define regk_ddr2_direct 0x00000001 +#define regk_ddr2_dis 0x00000000 +#define regk_ddr2_dll_dis 0x00000001 +#define regk_ddr2_dll_en 0x00000000 +#define regk_ddr2_dll_rst 0x00000100 +#define regk_ddr2_emrs 0x00000081 +#define regk_ddr2_emrs2 0x00000082 +#define regk_ddr2_emrs3 0x00000083 +#define regk_ddr2_full 0x00000001 +#define regk_ddr2_hi_ref_rate 0x00000080 +#define regk_ddr2_mrs 0x00000080 +#define regk_ddr2_no 0x00000000 +#define regk_ddr2_nop 0x000000b8 +#define regk_ddr2_ocd_adj 0x00000200 +#define regk_ddr2_ocd_default 0x00000380 +#define regk_ddr2_ocd_drive0 0x00000100 +#define regk_ddr2_ocd_drive1 0x00000080 +#define regk_ddr2_ocd_exit 0x00000000 +#define regk_ddr2_odt_dis 0x00000000 +#define regk_ddr2_offs 0x00000000 +#define regk_ddr2_pre 0x00000090 +#define regk_ddr2_pre_all 0x00000400 +#define regk_ddr2_pwr_down_fast 0x00000000 +#define regk_ddr2_pwr_down_slow 0x00001000 +#define regk_ddr2_ref 0x00000088 +#define regk_ddr2_rtt150 0x00000040 +#define regk_ddr2_rtt50 0x00000044 +#define regk_ddr2_rtt75 0x00000004 +#define regk_ddr2_rw_cfg_default 0x00186000 +#define regk_ddr2_rw_dll_ctrl_default 0x00000000 +#define regk_ddr2_rw_dll_ctrl_size 0x00000004 +#define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000 +#define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004 +#define regk_ddr2_rw_latency_default 0x00000000 +#define regk_ddr2_rw_phy_cfg_default 0x00000000 +#define regk_ddr2_rw_pwr_down_default 0x00000000 +#define regk_ddr2_rw_timing_default 0x00000000 +#define regk_ddr2_s1Gb 0x0000001a +#define regk_ddr2_s256Mb 0x0000000f +#define regk_ddr2_s2Gb 0x00000027 +#define regk_ddr2_s4Gb 0x00000042 +#define regk_ddr2_s512Mb 0x00000015 +#define regk_ddr2_temp0_85 0x00000618 +#define regk_ddr2_temp85_95 0x0000030c +#define regk_ddr2_term150 0x00000002 +#define regk_ddr2_term50 0x00000003 +#define regk_ddr2_term75 0x00000001 +#define regk_ddr2_test 0x00000080 +#define regk_ddr2_weak 0x00000000 +#define regk_ddr2_wr2 0x00000200 +#define regk_ddr2_wr3 0x00000400 +#define regk_ddr2_yes 0x00000001 +#endif /* __ddr2_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h new file mode 100644 index 00000000000..df6714fda17 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h @@ -0,0 +1,849 @@ +#ifndef __gio_defs_asm_h +#define __gio_defs_asm_h + +/* + * This file is autogenerated from + * file: gio.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_pa_din, scope gio, type r */ +#define reg_gio_r_pa_din___data___lsb 0 +#define reg_gio_r_pa_din___data___width 32 +#define reg_gio_r_pa_din_offset 0 + +/* Register rw_pa_dout, scope gio, type rw */ +#define reg_gio_rw_pa_dout___data___lsb 0 +#define reg_gio_rw_pa_dout___data___width 32 +#define reg_gio_rw_pa_dout_offset 4 + +/* Register rw_pa_oe, scope gio, type rw */ +#define reg_gio_rw_pa_oe___oe___lsb 0 +#define reg_gio_rw_pa_oe___oe___width 32 +#define reg_gio_rw_pa_oe_offset 8 + +/* Register rw_pa_byte0_dout, scope gio, type rw */ +#define reg_gio_rw_pa_byte0_dout___data___lsb 0 +#define reg_gio_rw_pa_byte0_dout___data___width 8 +#define reg_gio_rw_pa_byte0_dout_offset 12 + +/* Register rw_pa_byte0_oe, scope gio, type rw */ +#define reg_gio_rw_pa_byte0_oe___oe___lsb 0 +#define reg_gio_rw_pa_byte0_oe___oe___width 8 +#define reg_gio_rw_pa_byte0_oe_offset 16 + +/* Register rw_pa_byte1_dout, scope gio, type rw */ +#define reg_gio_rw_pa_byte1_dout___data___lsb 0 +#define reg_gio_rw_pa_byte1_dout___data___width 8 +#define reg_gio_rw_pa_byte1_dout_offset 20 + +/* Register rw_pa_byte1_oe, scope gio, type rw */ +#define reg_gio_rw_pa_byte1_oe___oe___lsb 0 +#define reg_gio_rw_pa_byte1_oe___oe___width 8 +#define reg_gio_rw_pa_byte1_oe_offset 24 + +/* Register rw_pa_byte2_dout, scope gio, type rw */ +#define reg_gio_rw_pa_byte2_dout___data___lsb 0 +#define reg_gio_rw_pa_byte2_dout___data___width 8 +#define reg_gio_rw_pa_byte2_dout_offset 28 + +/* Register rw_pa_byte2_oe, scope gio, type rw */ +#define reg_gio_rw_pa_byte2_oe___oe___lsb 0 +#define reg_gio_rw_pa_byte2_oe___oe___width 8 +#define reg_gio_rw_pa_byte2_oe_offset 32 + +/* Register rw_pa_byte3_dout, scope gio, type rw */ +#define reg_gio_rw_pa_byte3_dout___data___lsb 0 +#define reg_gio_rw_pa_byte3_dout___data___width 8 +#define reg_gio_rw_pa_byte3_dout_offset 36 + +/* Register rw_pa_byte3_oe, scope gio, type rw */ +#define reg_gio_rw_pa_byte3_oe___oe___lsb 0 +#define reg_gio_rw_pa_byte3_oe___oe___width 8 +#define reg_gio_rw_pa_byte3_oe_offset 40 + +/* Register r_pb_din, scope gio, type r */ +#define reg_gio_r_pb_din___data___lsb 0 +#define reg_gio_r_pb_din___data___width 32 +#define reg_gio_r_pb_din_offset 44 + +/* Register rw_pb_dout, scope gio, type rw */ +#define reg_gio_rw_pb_dout___data___lsb 0 +#define reg_gio_rw_pb_dout___data___width 32 +#define reg_gio_rw_pb_dout_offset 48 + +/* Register rw_pb_oe, scope gio, type rw */ +#define reg_gio_rw_pb_oe___oe___lsb 0 +#define reg_gio_rw_pb_oe___oe___width 32 +#define reg_gio_rw_pb_oe_offset 52 + +/* Register rw_pb_byte0_dout, scope gio, type rw */ +#define reg_gio_rw_pb_byte0_dout___data___lsb 0 +#define reg_gio_rw_pb_byte0_dout___data___width 8 +#define reg_gio_rw_pb_byte0_dout_offset 56 + +/* Register rw_pb_byte0_oe, scope gio, type rw */ +#define reg_gio_rw_pb_byte0_oe___oe___lsb 0 +#define reg_gio_rw_pb_byte0_oe___oe___width 8 +#define reg_gio_rw_pb_byte0_oe_offset 60 + +/* Register rw_pb_byte1_dout, scope gio, type rw */ +#define reg_gio_rw_pb_byte1_dout___data___lsb 0 +#define reg_gio_rw_pb_byte1_dout___data___width 8 +#define reg_gio_rw_pb_byte1_dout_offset 64 + +/* Register rw_pb_byte1_oe, scope gio, type rw */ +#define reg_gio_rw_pb_byte1_oe___oe___lsb 0 +#define reg_gio_rw_pb_byte1_oe___oe___width 8 +#define reg_gio_rw_pb_byte1_oe_offset 68 + +/* Register rw_pb_byte2_dout, scope gio, type rw */ +#define reg_gio_rw_pb_byte2_dout___data___lsb 0 +#define reg_gio_rw_pb_byte2_dout___data___width 8 +#define reg_gio_rw_pb_byte2_dout_offset 72 + +/* Register rw_pb_byte2_oe, scope gio, type rw */ +#define reg_gio_rw_pb_byte2_oe___oe___lsb 0 +#define reg_gio_rw_pb_byte2_oe___oe___width 8 +#define reg_gio_rw_pb_byte2_oe_offset 76 + +/* Register rw_pb_byte3_dout, scope gio, type rw */ +#define reg_gio_rw_pb_byte3_dout___data___lsb 0 +#define reg_gio_rw_pb_byte3_dout___data___width 8 +#define reg_gio_rw_pb_byte3_dout_offset 80 + +/* Register rw_pb_byte3_oe, scope gio, type rw */ +#define reg_gio_rw_pb_byte3_oe___oe___lsb 0 +#define reg_gio_rw_pb_byte3_oe___oe___width 8 +#define reg_gio_rw_pb_byte3_oe_offset 84 + +/* Register r_pc_din, scope gio, type r */ +#define reg_gio_r_pc_din___data___lsb 0 +#define reg_gio_r_pc_din___data___width 16 +#define reg_gio_r_pc_din_offset 88 + +/* Register rw_pc_dout, scope gio, type rw */ +#define reg_gio_rw_pc_dout___data___lsb 0 +#define reg_gio_rw_pc_dout___data___width 16 +#define reg_gio_rw_pc_dout_offset 92 + +/* Register rw_pc_oe, scope gio, type rw */ +#define reg_gio_rw_pc_oe___oe___lsb 0 +#define reg_gio_rw_pc_oe___oe___width 16 +#define reg_gio_rw_pc_oe_offset 96 + +/* Register rw_pc_byte0_dout, scope gio, type rw */ +#define reg_gio_rw_pc_byte0_dout___data___lsb 0 +#define reg_gio_rw_pc_byte0_dout___data___width 8 +#define reg_gio_rw_pc_byte0_dout_offset 100 + +/* Register rw_pc_byte0_oe, scope gio, type rw */ +#define reg_gio_rw_pc_byte0_oe___oe___lsb 0 +#define reg_gio_rw_pc_byte0_oe___oe___width 8 +#define reg_gio_rw_pc_byte0_oe_offset 104 + +/* Register rw_pc_byte1_dout, scope gio, type rw */ +#define reg_gio_rw_pc_byte1_dout___data___lsb 0 +#define reg_gio_rw_pc_byte1_dout___data___width 8 +#define reg_gio_rw_pc_byte1_dout_offset 108 + +/* Register rw_pc_byte1_oe, scope gio, type rw */ +#define reg_gio_rw_pc_byte1_oe___oe___lsb 0 +#define reg_gio_rw_pc_byte1_oe___oe___width 8 +#define reg_gio_rw_pc_byte1_oe_offset 112 + +/* Register r_pd_din, scope gio, type r */ +#define reg_gio_r_pd_din___data___lsb 0 +#define reg_gio_r_pd_din___data___width 32 +#define reg_gio_r_pd_din_offset 116 + +/* Register rw_intr_cfg, scope gio, type rw */ +#define reg_gio_rw_intr_cfg___intr0___lsb 0 +#define reg_gio_rw_intr_cfg___intr0___width 3 +#define reg_gio_rw_intr_cfg___intr1___lsb 3 +#define reg_gio_rw_intr_cfg___intr1___width 3 +#define reg_gio_rw_intr_cfg___intr2___lsb 6 +#define reg_gio_rw_intr_cfg___intr2___width 3 +#define reg_gio_rw_intr_cfg___intr3___lsb 9 +#define reg_gio_rw_intr_cfg___intr3___width 3 +#define reg_gio_rw_intr_cfg___intr4___lsb 12 +#define reg_gio_rw_intr_cfg___intr4___width 3 +#define reg_gio_rw_intr_cfg___intr5___lsb 15 +#define reg_gio_rw_intr_cfg___intr5___width 3 +#define reg_gio_rw_intr_cfg___intr6___lsb 18 +#define reg_gio_rw_intr_cfg___intr6___width 3 +#define reg_gio_rw_intr_cfg___intr7___lsb 21 +#define reg_gio_rw_intr_cfg___intr7___width 3 +#define reg_gio_rw_intr_cfg_offset 120 + +/* Register rw_intr_pins, scope gio, type rw */ +#define reg_gio_rw_intr_pins___intr0___lsb 0 +#define reg_gio_rw_intr_pins___intr0___width 4 +#define reg_gio_rw_intr_pins___intr1___lsb 4 +#define reg_gio_rw_intr_pins___intr1___width 4 +#define reg_gio_rw_intr_pins___intr2___lsb 8 +#define reg_gio_rw_intr_pins___intr2___width 4 +#define reg_gio_rw_intr_pins___intr3___lsb 12 +#define reg_gio_rw_intr_pins___intr3___width 4 +#define reg_gio_rw_intr_pins___intr4___lsb 16 +#define reg_gio_rw_intr_pins___intr4___width 4 +#define reg_gio_rw_intr_pins___intr5___lsb 20 +#define reg_gio_rw_intr_pins___intr5___width 4 +#define reg_gio_rw_intr_pins___intr6___lsb 24 +#define reg_gio_rw_intr_pins___intr6___width 4 +#define reg_gio_rw_intr_pins___intr7___lsb 28 +#define reg_gio_rw_intr_pins___intr7___width 4 +#define reg_gio_rw_intr_pins_offset 124 + +/* Register rw_intr_mask, scope gio, type rw */ +#define reg_gio_rw_intr_mask___intr0___lsb 0 +#define reg_gio_rw_intr_mask___intr0___width 1 +#define reg_gio_rw_intr_mask___intr0___bit 0 +#define reg_gio_rw_intr_mask___intr1___lsb 1 +#define reg_gio_rw_intr_mask___intr1___width 1 +#define reg_gio_rw_intr_mask___intr1___bit 1 +#define reg_gio_rw_intr_mask___intr2___lsb 2 +#define reg_gio_rw_intr_mask___intr2___width 1 +#define reg_gio_rw_intr_mask___intr2___bit 2 +#define reg_gio_rw_intr_mask___intr3___lsb 3 +#define reg_gio_rw_intr_mask___intr3___width 1 +#define reg_gio_rw_intr_mask___intr3___bit 3 +#define reg_gio_rw_intr_mask___intr4___lsb 4 +#define reg_gio_rw_intr_mask___intr4___width 1 +#define reg_gio_rw_intr_mask___intr4___bit 4 +#define reg_gio_rw_intr_mask___intr5___lsb 5 +#define reg_gio_rw_intr_mask___intr5___width 1 +#define reg_gio_rw_intr_mask___intr5___bit 5 +#define reg_gio_rw_intr_mask___intr6___lsb 6 +#define reg_gio_rw_intr_mask___intr6___width 1 +#define reg_gio_rw_intr_mask___intr6___bit 6 +#define reg_gio_rw_intr_mask___intr7___lsb 7 +#define reg_gio_rw_intr_mask___intr7___width 1 +#define reg_gio_rw_intr_mask___intr7___bit 7 +#define reg_gio_rw_intr_mask___i2c0_done___lsb 8 +#define reg_gio_rw_intr_mask___i2c0_done___width 1 +#define reg_gio_rw_intr_mask___i2c0_done___bit 8 +#define reg_gio_rw_intr_mask___i2c1_done___lsb 9 +#define reg_gio_rw_intr_mask___i2c1_done___width 1 +#define reg_gio_rw_intr_mask___i2c1_done___bit 9 +#define reg_gio_rw_intr_mask_offset 128 + +/* Register rw_ack_intr, scope gio, type rw */ +#define reg_gio_rw_ack_intr___intr0___lsb 0 +#define reg_gio_rw_ack_intr___intr0___width 1 +#define reg_gio_rw_ack_intr___intr0___bit 0 +#define reg_gio_rw_ack_intr___intr1___lsb 1 +#define reg_gio_rw_ack_intr___intr1___width 1 +#define reg_gio_rw_ack_intr___intr1___bit 1 +#define reg_gio_rw_ack_intr___intr2___lsb 2 +#define reg_gio_rw_ack_intr___intr2___width 1 +#define reg_gio_rw_ack_intr___intr2___bit 2 +#define reg_gio_rw_ack_intr___intr3___lsb 3 +#define reg_gio_rw_ack_intr___intr3___width 1 +#define reg_gio_rw_ack_intr___intr3___bit 3 +#define reg_gio_rw_ack_intr___intr4___lsb 4 +#define reg_gio_rw_ack_intr___intr4___width 1 +#define reg_gio_rw_ack_intr___intr4___bit 4 +#define reg_gio_rw_ack_intr___intr5___lsb 5 +#define reg_gio_rw_ack_intr___intr5___width 1 +#define reg_gio_rw_ack_intr___intr5___bit 5 +#define reg_gio_rw_ack_intr___intr6___lsb 6 +#define reg_gio_rw_ack_intr___intr6___width 1 +#define reg_gio_rw_ack_intr___intr6___bit 6 +#define reg_gio_rw_ack_intr___intr7___lsb 7 +#define reg_gio_rw_ack_intr___intr7___width 1 +#define reg_gio_rw_ack_intr___intr7___bit 7 +#define reg_gio_rw_ack_intr___i2c0_done___lsb 8 +#define reg_gio_rw_ack_intr___i2c0_done___width 1 +#define reg_gio_rw_ack_intr___i2c0_done___bit 8 +#define reg_gio_rw_ack_intr___i2c1_done___lsb 9 +#define reg_gio_rw_ack_intr___i2c1_done___width 1 +#define reg_gio_rw_ack_intr___i2c1_done___bit 9 +#define reg_gio_rw_ack_intr_offset 132 + +/* Register r_intr, scope gio, type r */ +#define reg_gio_r_intr___intr0___lsb 0 +#define reg_gio_r_intr___intr0___width 1 +#define reg_gio_r_intr___intr0___bit 0 +#define reg_gio_r_intr___intr1___lsb 1 +#define reg_gio_r_intr___intr1___width 1 +#define reg_gio_r_intr___intr1___bit 1 +#define reg_gio_r_intr___intr2___lsb 2 +#define reg_gio_r_intr___intr2___width 1 +#define reg_gio_r_intr___intr2___bit 2 +#define reg_gio_r_intr___intr3___lsb 3 +#define reg_gio_r_intr___intr3___width 1 +#define reg_gio_r_intr___intr3___bit 3 +#define reg_gio_r_intr___intr4___lsb 4 +#define reg_gio_r_intr___intr4___width 1 +#define reg_gio_r_intr___intr4___bit 4 +#define reg_gio_r_intr___intr5___lsb 5 +#define reg_gio_r_intr___intr5___width 1 +#define reg_gio_r_intr___intr5___bit 5 +#define reg_gio_r_intr___intr6___lsb 6 +#define reg_gio_r_intr___intr6___width 1 +#define reg_gio_r_intr___intr6___bit 6 +#define reg_gio_r_intr___intr7___lsb 7 +#define reg_gio_r_intr___intr7___width 1 +#define reg_gio_r_intr___intr7___bit 7 +#define reg_gio_r_intr___i2c0_done___lsb 8 +#define reg_gio_r_intr___i2c0_done___width 1 +#define reg_gio_r_intr___i2c0_done___bit 8 +#define reg_gio_r_intr___i2c1_done___lsb 9 +#define reg_gio_r_intr___i2c1_done___width 1 +#define reg_gio_r_intr___i2c1_done___bit 9 +#define reg_gio_r_intr_offset 136 + +/* Register r_masked_intr, scope gio, type r */ +#define reg_gio_r_masked_intr___intr0___lsb 0 +#define reg_gio_r_masked_intr___intr0___width 1 +#define reg_gio_r_masked_intr___intr0___bit 0 +#define reg_gio_r_masked_intr___intr1___lsb 1 +#define reg_gio_r_masked_intr___intr1___width 1 +#define reg_gio_r_masked_intr___intr1___bit 1 +#define reg_gio_r_masked_intr___intr2___lsb 2 +#define reg_gio_r_masked_intr___intr2___width 1 +#define reg_gio_r_masked_intr___intr2___bit 2 +#define reg_gio_r_masked_intr___intr3___lsb 3 +#define reg_gio_r_masked_intr___intr3___width 1 +#define reg_gio_r_masked_intr___intr3___bit 3 +#define reg_gio_r_masked_intr___intr4___lsb 4 +#define reg_gio_r_masked_intr___intr4___width 1 +#define reg_gio_r_masked_intr___intr4___bit 4 +#define reg_gio_r_masked_intr___intr5___lsb 5 +#define reg_gio_r_masked_intr___intr5___width 1 +#define reg_gio_r_masked_intr___intr5___bit 5 +#define reg_gio_r_masked_intr___intr6___lsb 6 +#define reg_gio_r_masked_intr___intr6___width 1 +#define reg_gio_r_masked_intr___intr6___bit 6 +#define reg_gio_r_masked_intr___intr7___lsb 7 +#define reg_gio_r_masked_intr___intr7___width 1 +#define reg_gio_r_masked_intr___intr7___bit 7 +#define reg_gio_r_masked_intr___i2c0_done___lsb 8 +#define reg_gio_r_masked_intr___i2c0_done___width 1 +#define reg_gio_r_masked_intr___i2c0_done___bit 8 +#define reg_gio_r_masked_intr___i2c1_done___lsb 9 +#define reg_gio_r_masked_intr___i2c1_done___width 1 +#define reg_gio_r_masked_intr___i2c1_done___bit 9 +#define reg_gio_r_masked_intr_offset 140 + +/* Register rw_i2c0_start, scope gio, type rw */ +#define reg_gio_rw_i2c0_start___run___lsb 0 +#define reg_gio_rw_i2c0_start___run___width 1 +#define reg_gio_rw_i2c0_start___run___bit 0 +#define reg_gio_rw_i2c0_start_offset 144 + +/* Register rw_i2c0_cfg, scope gio, type rw */ +#define reg_gio_rw_i2c0_cfg___en___lsb 0 +#define reg_gio_rw_i2c0_cfg___en___width 1 +#define reg_gio_rw_i2c0_cfg___en___bit 0 +#define reg_gio_rw_i2c0_cfg___bit_order___lsb 1 +#define reg_gio_rw_i2c0_cfg___bit_order___width 1 +#define reg_gio_rw_i2c0_cfg___bit_order___bit 1 +#define reg_gio_rw_i2c0_cfg___scl_io___lsb 2 +#define reg_gio_rw_i2c0_cfg___scl_io___width 1 +#define reg_gio_rw_i2c0_cfg___scl_io___bit 2 +#define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3 +#define reg_gio_rw_i2c0_cfg___scl_inv___width 1 +#define reg_gio_rw_i2c0_cfg___scl_inv___bit 3 +#define reg_gio_rw_i2c0_cfg___sda_io___lsb 4 +#define reg_gio_rw_i2c0_cfg___sda_io___width 1 +#define reg_gio_rw_i2c0_cfg___sda_io___bit 4 +#define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5 +#define reg_gio_rw_i2c0_cfg___sda_idle___width 1 +#define reg_gio_rw_i2c0_cfg___sda_idle___bit 5 +#define reg_gio_rw_i2c0_cfg_offset 148 + +/* Register rw_i2c0_ctrl, scope gio, type rw */ +#define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0 +#define reg_gio_rw_i2c0_ctrl___trf_bits___width 6 +#define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6 +#define reg_gio_rw_i2c0_ctrl___switch_dir___width 6 +#define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12 +#define reg_gio_rw_i2c0_ctrl___extra_start___width 3 +#define reg_gio_rw_i2c0_ctrl___early_end___lsb 15 +#define reg_gio_rw_i2c0_ctrl___early_end___width 1 +#define reg_gio_rw_i2c0_ctrl___early_end___bit 15 +#define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16 +#define reg_gio_rw_i2c0_ctrl___start_stop___width 1 +#define reg_gio_rw_i2c0_ctrl___start_stop___bit 16 +#define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17 +#define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17 +#define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18 +#define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18 +#define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19 +#define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19 +#define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20 +#define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20 +#define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21 +#define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21 +#define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22 +#define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22 +#define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23 +#define reg_gio_rw_i2c0_ctrl___ack_bit___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23 +#define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24 +#define reg_gio_rw_i2c0_ctrl___start_bit___width 1 +#define reg_gio_rw_i2c0_ctrl___start_bit___bit 24 +#define reg_gio_rw_i2c0_ctrl___freq___lsb 25 +#define reg_gio_rw_i2c0_ctrl___freq___width 2 +#define reg_gio_rw_i2c0_ctrl_offset 152 + +/* Register rw_i2c0_data, scope gio, type rw */ +#define reg_gio_rw_i2c0_data___data0___lsb 0 +#define reg_gio_rw_i2c0_data___data0___width 8 +#define reg_gio_rw_i2c0_data___data1___lsb 8 +#define reg_gio_rw_i2c0_data___data1___width 8 +#define reg_gio_rw_i2c0_data___data2___lsb 16 +#define reg_gio_rw_i2c0_data___data2___width 8 +#define reg_gio_rw_i2c0_data___data3___lsb 24 +#define reg_gio_rw_i2c0_data___data3___width 8 +#define reg_gio_rw_i2c0_data_offset 156 + +/* Register rw_i2c0_data2, scope gio, type rw */ +#define reg_gio_rw_i2c0_data2___data4___lsb 0 +#define reg_gio_rw_i2c0_data2___data4___width 8 +#define reg_gio_rw_i2c0_data2___data5___lsb 8 +#define reg_gio_rw_i2c0_data2___data5___width 8 +#define reg_gio_rw_i2c0_data2___start_val___lsb 16 +#define reg_gio_rw_i2c0_data2___start_val___width 6 +#define reg_gio_rw_i2c0_data2___ack_val___lsb 22 +#define reg_gio_rw_i2c0_data2___ack_val___width 6 +#define reg_gio_rw_i2c0_data2_offset 160 + +/* Register rw_i2c1_start, scope gio, type rw */ +#define reg_gio_rw_i2c1_start___run___lsb 0 +#define reg_gio_rw_i2c1_start___run___width 1 +#define reg_gio_rw_i2c1_start___run___bit 0 +#define reg_gio_rw_i2c1_start_offset 164 + +/* Register rw_i2c1_cfg, scope gio, type rw */ +#define reg_gio_rw_i2c1_cfg___en___lsb 0 +#define reg_gio_rw_i2c1_cfg___en___width 1 +#define reg_gio_rw_i2c1_cfg___en___bit 0 +#define reg_gio_rw_i2c1_cfg___bit_order___lsb 1 +#define reg_gio_rw_i2c1_cfg___bit_order___width 1 +#define reg_gio_rw_i2c1_cfg___bit_order___bit 1 +#define reg_gio_rw_i2c1_cfg___scl_io___lsb 2 +#define reg_gio_rw_i2c1_cfg___scl_io___width 1 +#define reg_gio_rw_i2c1_cfg___scl_io___bit 2 +#define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3 +#define reg_gio_rw_i2c1_cfg___scl_inv___width 1 +#define reg_gio_rw_i2c1_cfg___scl_inv___bit 3 +#define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4 +#define reg_gio_rw_i2c1_cfg___sda0_io___width 1 +#define reg_gio_rw_i2c1_cfg___sda0_io___bit 4 +#define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5 +#define reg_gio_rw_i2c1_cfg___sda0_idle___width 1 +#define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5 +#define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6 +#define reg_gio_rw_i2c1_cfg___sda1_io___width 1 +#define reg_gio_rw_i2c1_cfg___sda1_io___bit 6 +#define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7 +#define reg_gio_rw_i2c1_cfg___sda1_idle___width 1 +#define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7 +#define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8 +#define reg_gio_rw_i2c1_cfg___sda2_io___width 1 +#define reg_gio_rw_i2c1_cfg___sda2_io___bit 8 +#define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9 +#define reg_gio_rw_i2c1_cfg___sda2_idle___width 1 +#define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9 +#define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10 +#define reg_gio_rw_i2c1_cfg___sda3_io___width 1 +#define reg_gio_rw_i2c1_cfg___sda3_io___bit 10 +#define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11 +#define reg_gio_rw_i2c1_cfg___sda3_idle___width 1 +#define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11 +#define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12 +#define reg_gio_rw_i2c1_cfg___sda_sel___width 2 +#define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14 +#define reg_gio_rw_i2c1_cfg___sen_idle___width 1 +#define reg_gio_rw_i2c1_cfg___sen_idle___bit 14 +#define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15 +#define reg_gio_rw_i2c1_cfg___sen_inv___width 1 +#define reg_gio_rw_i2c1_cfg___sen_inv___bit 15 +#define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16 +#define reg_gio_rw_i2c1_cfg___sen_sel___width 2 +#define reg_gio_rw_i2c1_cfg_offset 168 + +/* Register rw_i2c1_ctrl, scope gio, type rw */ +#define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0 +#define reg_gio_rw_i2c1_ctrl___trf_bits___width 6 +#define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6 +#define reg_gio_rw_i2c1_ctrl___switch_dir___width 6 +#define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12 +#define reg_gio_rw_i2c1_ctrl___extra_start___width 3 +#define reg_gio_rw_i2c1_ctrl___early_end___lsb 15 +#define reg_gio_rw_i2c1_ctrl___early_end___width 1 +#define reg_gio_rw_i2c1_ctrl___early_end___bit 15 +#define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16 +#define reg_gio_rw_i2c1_ctrl___start_stop___width 1 +#define reg_gio_rw_i2c1_ctrl___start_stop___bit 16 +#define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17 +#define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17 +#define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18 +#define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18 +#define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19 +#define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19 +#define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20 +#define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20 +#define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21 +#define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21 +#define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22 +#define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22 +#define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23 +#define reg_gio_rw_i2c1_ctrl___ack_bit___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23 +#define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24 +#define reg_gio_rw_i2c1_ctrl___start_bit___width 1 +#define reg_gio_rw_i2c1_ctrl___start_bit___bit 24 +#define reg_gio_rw_i2c1_ctrl___freq___lsb 25 +#define reg_gio_rw_i2c1_ctrl___freq___width 2 +#define reg_gio_rw_i2c1_ctrl_offset 172 + +/* Register rw_i2c1_data, scope gio, type rw */ +#define reg_gio_rw_i2c1_data___data0___lsb 0 +#define reg_gio_rw_i2c1_data___data0___width 8 +#define reg_gio_rw_i2c1_data___data1___lsb 8 +#define reg_gio_rw_i2c1_data___data1___width 8 +#define reg_gio_rw_i2c1_data___data2___lsb 16 +#define reg_gio_rw_i2c1_data___data2___width 8 +#define reg_gio_rw_i2c1_data___data3___lsb 24 +#define reg_gio_rw_i2c1_data___data3___width 8 +#define reg_gio_rw_i2c1_data_offset 176 + +/* Register rw_i2c1_data2, scope gio, type rw */ +#define reg_gio_rw_i2c1_data2___data4___lsb 0 +#define reg_gio_rw_i2c1_data2___data4___width 8 +#define reg_gio_rw_i2c1_data2___data5___lsb 8 +#define reg_gio_rw_i2c1_data2___data5___width 8 +#define reg_gio_rw_i2c1_data2___start_val___lsb 16 +#define reg_gio_rw_i2c1_data2___start_val___width 6 +#define reg_gio_rw_i2c1_data2___ack_val___lsb 22 +#define reg_gio_rw_i2c1_data2___ack_val___width 6 +#define reg_gio_rw_i2c1_data2_offset 180 + +/* Register r_ppwm_stat, scope gio, type r */ +#define reg_gio_r_ppwm_stat___freq___lsb 0 +#define reg_gio_r_ppwm_stat___freq___width 2 +#define reg_gio_r_ppwm_stat_offset 184 + +/* Register rw_ppwm_data, scope gio, type rw */ +#define reg_gio_rw_ppwm_data___data___lsb 0 +#define reg_gio_rw_ppwm_data___data___width 8 +#define reg_gio_rw_ppwm_data_offset 188 + +/* Register rw_pwm0_ctrl, scope gio, type rw */ +#define reg_gio_rw_pwm0_ctrl___mode___lsb 0 +#define reg_gio_rw_pwm0_ctrl___mode___width 2 +#define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2 +#define reg_gio_rw_pwm0_ctrl___ccd_override___width 1 +#define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2 +#define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3 +#define reg_gio_rw_pwm0_ctrl___ccd_val___width 1 +#define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3 +#define reg_gio_rw_pwm0_ctrl_offset 192 + +/* Register rw_pwm0_var, scope gio, type rw */ +#define reg_gio_rw_pwm0_var___lo___lsb 0 +#define reg_gio_rw_pwm0_var___lo___width 13 +#define reg_gio_rw_pwm0_var___hi___lsb 13 +#define reg_gio_rw_pwm0_var___hi___width 13 +#define reg_gio_rw_pwm0_var_offset 196 + +/* Register rw_pwm0_data, scope gio, type rw */ +#define reg_gio_rw_pwm0_data___data___lsb 0 +#define reg_gio_rw_pwm0_data___data___width 8 +#define reg_gio_rw_pwm0_data_offset 200 + +/* Register rw_pwm1_ctrl, scope gio, type rw */ +#define reg_gio_rw_pwm1_ctrl___mode___lsb 0 +#define reg_gio_rw_pwm1_ctrl___mode___width 2 +#define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2 +#define reg_gio_rw_pwm1_ctrl___ccd_override___width 1 +#define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2 +#define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3 +#define reg_gio_rw_pwm1_ctrl___ccd_val___width 1 +#define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3 +#define reg_gio_rw_pwm1_ctrl_offset 204 + +/* Register rw_pwm1_var, scope gio, type rw */ +#define reg_gio_rw_pwm1_var___lo___lsb 0 +#define reg_gio_rw_pwm1_var___lo___width 13 +#define reg_gio_rw_pwm1_var___hi___lsb 13 +#define reg_gio_rw_pwm1_var___hi___width 13 +#define reg_gio_rw_pwm1_var_offset 208 + +/* Register rw_pwm1_data, scope gio, type rw */ +#define reg_gio_rw_pwm1_data___data___lsb 0 +#define reg_gio_rw_pwm1_data___data___width 8 +#define reg_gio_rw_pwm1_data_offset 212 + +/* Register rw_pwm2_ctrl, scope gio, type rw */ +#define reg_gio_rw_pwm2_ctrl___mode___lsb 0 +#define reg_gio_rw_pwm2_ctrl___mode___width 2 +#define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2 +#define reg_gio_rw_pwm2_ctrl___ccd_override___width 1 +#define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2 +#define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3 +#define reg_gio_rw_pwm2_ctrl___ccd_val___width 1 +#define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3 +#define reg_gio_rw_pwm2_ctrl_offset 216 + +/* Register rw_pwm2_var, scope gio, type rw */ +#define reg_gio_rw_pwm2_var___lo___lsb 0 +#define reg_gio_rw_pwm2_var___lo___width 13 +#define reg_gio_rw_pwm2_var___hi___lsb 13 +#define reg_gio_rw_pwm2_var___hi___width 13 +#define reg_gio_rw_pwm2_var_offset 220 + +/* Register rw_pwm2_data, scope gio, type rw */ +#define reg_gio_rw_pwm2_data___data___lsb 0 +#define reg_gio_rw_pwm2_data___data___width 8 +#define reg_gio_rw_pwm2_data_offset 224 + +/* Register rw_pwm_in_cfg, scope gio, type rw */ +#define reg_gio_rw_pwm_in_cfg___pin___lsb 0 +#define reg_gio_rw_pwm_in_cfg___pin___width 3 +#define reg_gio_rw_pwm_in_cfg_offset 228 + +/* Register r_pwm_in_lo, scope gio, type r */ +#define reg_gio_r_pwm_in_lo___data___lsb 0 +#define reg_gio_r_pwm_in_lo___data___width 32 +#define reg_gio_r_pwm_in_lo_offset 232 + +/* Register r_pwm_in_hi, scope gio, type r */ +#define reg_gio_r_pwm_in_hi___data___lsb 0 +#define reg_gio_r_pwm_in_hi___data___width 32 +#define reg_gio_r_pwm_in_hi_offset 236 + +/* Register r_pwm_in_cnt, scope gio, type r */ +#define reg_gio_r_pwm_in_cnt___data___lsb 0 +#define reg_gio_r_pwm_in_cnt___data___width 32 +#define reg_gio_r_pwm_in_cnt_offset 240 + + +/* Constants */ +#define regk_gio_anyedge 0x00000007 +#define regk_gio_f100k 0x00000000 +#define regk_gio_f1562 0x00000000 +#define regk_gio_f195 0x00000003 +#define regk_gio_f1m 0x00000002 +#define regk_gio_f390 0x00000002 +#define regk_gio_f400k 0x00000001 +#define regk_gio_f5m 0x00000003 +#define regk_gio_f781 0x00000001 +#define regk_gio_hi 0x00000001 +#define regk_gio_in 0x00000000 +#define regk_gio_intr_pa0 0x00000000 +#define regk_gio_intr_pa1 0x00000000 +#define regk_gio_intr_pa10 0x00000001 +#define regk_gio_intr_pa11 0x00000001 +#define regk_gio_intr_pa12 0x00000001 +#define regk_gio_intr_pa13 0x00000001 +#define regk_gio_intr_pa14 0x00000001 +#define regk_gio_intr_pa15 0x00000001 +#define regk_gio_intr_pa16 0x00000002 +#define regk_gio_intr_pa17 0x00000002 +#define regk_gio_intr_pa18 0x00000002 +#define regk_gio_intr_pa19 0x00000002 +#define regk_gio_intr_pa2 0x00000000 +#define regk_gio_intr_pa20 0x00000002 +#define regk_gio_intr_pa21 0x00000002 +#define regk_gio_intr_pa22 0x00000002 +#define regk_gio_intr_pa23 0x00000002 +#define regk_gio_intr_pa24 0x00000003 +#define regk_gio_intr_pa25 0x00000003 +#define regk_gio_intr_pa26 0x00000003 +#define regk_gio_intr_pa27 0x00000003 +#define regk_gio_intr_pa28 0x00000003 +#define regk_gio_intr_pa29 0x00000003 +#define regk_gio_intr_pa3 0x00000000 +#define regk_gio_intr_pa30 0x00000003 +#define regk_gio_intr_pa31 0x00000003 +#define regk_gio_intr_pa4 0x00000000 +#define regk_gio_intr_pa5 0x00000000 +#define regk_gio_intr_pa6 0x00000000 +#define regk_gio_intr_pa7 0x00000000 +#define regk_gio_intr_pa8 0x00000001 +#define regk_gio_intr_pa9 0x00000001 +#define regk_gio_intr_pb0 0x00000004 +#define regk_gio_intr_pb1 0x00000004 +#define regk_gio_intr_pb10 0x00000005 +#define regk_gio_intr_pb11 0x00000005 +#define regk_gio_intr_pb12 0x00000005 +#define regk_gio_intr_pb13 0x00000005 +#define regk_gio_intr_pb14 0x00000005 +#define regk_gio_intr_pb15 0x00000005 +#define regk_gio_intr_pb16 0x00000006 +#define regk_gio_intr_pb17 0x00000006 +#define regk_gio_intr_pb18 0x00000006 +#define regk_gio_intr_pb19 0x00000006 +#define regk_gio_intr_pb2 0x00000004 +#define regk_gio_intr_pb20 0x00000006 +#define regk_gio_intr_pb21 0x00000006 +#define regk_gio_intr_pb22 0x00000006 +#define regk_gio_intr_pb23 0x00000006 +#define regk_gio_intr_pb24 0x00000007 +#define regk_gio_intr_pb25 0x00000007 +#define regk_gio_intr_pb26 0x00000007 +#define regk_gio_intr_pb27 0x00000007 +#define regk_gio_intr_pb28 0x00000007 +#define regk_gio_intr_pb29 0x00000007 +#define regk_gio_intr_pb3 0x00000004 +#define regk_gio_intr_pb30 0x00000007 +#define regk_gio_intr_pb31 0x00000007 +#define regk_gio_intr_pb4 0x00000004 +#define regk_gio_intr_pb5 0x00000004 +#define regk_gio_intr_pb6 0x00000004 +#define regk_gio_intr_pb7 0x00000004 +#define regk_gio_intr_pb8 0x00000005 +#define regk_gio_intr_pb9 0x00000005 +#define regk_gio_intr_pc0 0x00000008 +#define regk_gio_intr_pc1 0x00000008 +#define regk_gio_intr_pc10 0x00000009 +#define regk_gio_intr_pc11 0x00000009 +#define regk_gio_intr_pc12 0x00000009 +#define regk_gio_intr_pc13 0x00000009 +#define regk_gio_intr_pc14 0x00000009 +#define regk_gio_intr_pc15 0x00000009 +#define regk_gio_intr_pc2 0x00000008 +#define regk_gio_intr_pc3 0x00000008 +#define regk_gio_intr_pc4 0x00000008 +#define regk_gio_intr_pc5 0x00000008 +#define regk_gio_intr_pc6 0x00000008 +#define regk_gio_intr_pc7 0x00000008 +#define regk_gio_intr_pc8 0x00000009 +#define regk_gio_intr_pc9 0x00000009 +#define regk_gio_intr_pd0 0x0000000c +#define regk_gio_intr_pd1 0x0000000c +#define regk_gio_intr_pd10 0x0000000d +#define regk_gio_intr_pd11 0x0000000d +#define regk_gio_intr_pd12 0x0000000d +#define regk_gio_intr_pd13 0x0000000d +#define regk_gio_intr_pd14 0x0000000d +#define regk_gio_intr_pd15 0x0000000d +#define regk_gio_intr_pd16 0x0000000e +#define regk_gio_intr_pd17 0x0000000e +#define regk_gio_intr_pd18 0x0000000e +#define regk_gio_intr_pd19 0x0000000e +#define regk_gio_intr_pd2 0x0000000c +#define regk_gio_intr_pd20 0x0000000e +#define regk_gio_intr_pd21 0x0000000e +#define regk_gio_intr_pd22 0x0000000e +#define regk_gio_intr_pd23 0x0000000e +#define regk_gio_intr_pd24 0x0000000f +#define regk_gio_intr_pd25 0x0000000f +#define regk_gio_intr_pd26 0x0000000f +#define regk_gio_intr_pd27 0x0000000f +#define regk_gio_intr_pd28 0x0000000f +#define regk_gio_intr_pd29 0x0000000f +#define regk_gio_intr_pd3 0x0000000c +#define regk_gio_intr_pd30 0x0000000f +#define regk_gio_intr_pd31 0x0000000f +#define regk_gio_intr_pd4 0x0000000c +#define regk_gio_intr_pd5 0x0000000c +#define regk_gio_intr_pd6 0x0000000c +#define regk_gio_intr_pd7 0x0000000c +#define regk_gio_intr_pd8 0x0000000d +#define regk_gio_intr_pd9 0x0000000d +#define regk_gio_lo 0x00000002 +#define regk_gio_lsb 0x00000000 +#define regk_gio_msb 0x00000001 +#define regk_gio_negedge 0x00000006 +#define regk_gio_no 0x00000000 +#define regk_gio_no_switch 0x0000003f +#define regk_gio_none 0x00000007 +#define regk_gio_off 0x00000000 +#define regk_gio_opendrain 0x00000000 +#define regk_gio_out 0x00000001 +#define regk_gio_posedge 0x00000005 +#define regk_gio_pwm_hfp 0x00000002 +#define regk_gio_pwm_pa0 0x00000001 +#define regk_gio_pwm_pa19 0x00000004 +#define regk_gio_pwm_pa6 0x00000002 +#define regk_gio_pwm_pa7 0x00000003 +#define regk_gio_pwm_pb26 0x00000005 +#define regk_gio_pwm_pd23 0x00000006 +#define regk_gio_pwm_pd31 0x00000007 +#define regk_gio_pwm_std 0x00000001 +#define regk_gio_pwm_var 0x00000003 +#define regk_gio_rw_i2c0_cfg_default 0x00000020 +#define regk_gio_rw_i2c0_ctrl_default 0x00010000 +#define regk_gio_rw_i2c0_start_default 0x00000000 +#define regk_gio_rw_i2c1_cfg_default 0x00000aa0 +#define regk_gio_rw_i2c1_ctrl_default 0x00010000 +#define regk_gio_rw_i2c1_start_default 0x00000000 +#define regk_gio_rw_intr_cfg_default 0x00000000 +#define regk_gio_rw_intr_mask_default 0x00000000 +#define regk_gio_rw_pa_oe_default 0x00000000 +#define regk_gio_rw_pb_oe_default 0x00000000 +#define regk_gio_rw_pc_oe_default 0x00000000 +#define regk_gio_rw_ppwm_data_default 0x00000000 +#define regk_gio_rw_pwm0_ctrl_default 0x00000000 +#define regk_gio_rw_pwm1_ctrl_default 0x00000000 +#define regk_gio_rw_pwm2_ctrl_default 0x00000000 +#define regk_gio_rw_pwm_in_cfg_default 0x00000000 +#define regk_gio_sda0 0x00000000 +#define regk_gio_sda1 0x00000001 +#define regk_gio_sda2 0x00000002 +#define regk_gio_sda3 0x00000003 +#define regk_gio_sen 0x00000000 +#define regk_gio_set 0x00000003 +#define regk_gio_yes 0x00000001 +#endif /* __gio_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h new file mode 100644 index 00000000000..c3dc9c666c4 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h @@ -0,0 +1,572 @@ +#ifndef __pinmux_defs_asm_h +#define __pinmux_defs_asm_h + +/* + * This file is autogenerated from + * file: pinmux.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pinmux_defs_asm.h pinmux.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_hwprot, scope pinmux, type rw */ +#define reg_pinmux_rw_hwprot___eth___lsb 0 +#define reg_pinmux_rw_hwprot___eth___width 1 +#define reg_pinmux_rw_hwprot___eth___bit 0 +#define reg_pinmux_rw_hwprot___eth_mdio___lsb 1 +#define reg_pinmux_rw_hwprot___eth_mdio___width 1 +#define reg_pinmux_rw_hwprot___eth_mdio___bit 1 +#define reg_pinmux_rw_hwprot___geth___lsb 2 +#define reg_pinmux_rw_hwprot___geth___width 1 +#define reg_pinmux_rw_hwprot___geth___bit 2 +#define reg_pinmux_rw_hwprot___tg___lsb 3 +#define reg_pinmux_rw_hwprot___tg___width 1 +#define reg_pinmux_rw_hwprot___tg___bit 3 +#define reg_pinmux_rw_hwprot___tg_clk___lsb 4 +#define reg_pinmux_rw_hwprot___tg_clk___width 1 +#define reg_pinmux_rw_hwprot___tg_clk___bit 4 +#define reg_pinmux_rw_hwprot___vout___lsb 5 +#define reg_pinmux_rw_hwprot___vout___width 1 +#define reg_pinmux_rw_hwprot___vout___bit 5 +#define reg_pinmux_rw_hwprot___vout_sync___lsb 6 +#define reg_pinmux_rw_hwprot___vout_sync___width 1 +#define reg_pinmux_rw_hwprot___vout_sync___bit 6 +#define reg_pinmux_rw_hwprot___ser1___lsb 7 +#define reg_pinmux_rw_hwprot___ser1___width 1 +#define reg_pinmux_rw_hwprot___ser1___bit 7 +#define reg_pinmux_rw_hwprot___ser2___lsb 8 +#define reg_pinmux_rw_hwprot___ser2___width 1 +#define reg_pinmux_rw_hwprot___ser2___bit 8 +#define reg_pinmux_rw_hwprot___ser3___lsb 9 +#define reg_pinmux_rw_hwprot___ser3___width 1 +#define reg_pinmux_rw_hwprot___ser3___bit 9 +#define reg_pinmux_rw_hwprot___ser4___lsb 10 +#define reg_pinmux_rw_hwprot___ser4___width 1 +#define reg_pinmux_rw_hwprot___ser4___bit 10 +#define reg_pinmux_rw_hwprot___sser___lsb 11 +#define reg_pinmux_rw_hwprot___sser___width 1 +#define reg_pinmux_rw_hwprot___sser___bit 11 +#define reg_pinmux_rw_hwprot___pwm0___lsb 12 +#define reg_pinmux_rw_hwprot___pwm0___width 1 +#define reg_pinmux_rw_hwprot___pwm0___bit 12 +#define reg_pinmux_rw_hwprot___pwm1___lsb 13 +#define reg_pinmux_rw_hwprot___pwm1___width 1 +#define reg_pinmux_rw_hwprot___pwm1___bit 13 +#define reg_pinmux_rw_hwprot___pwm2___lsb 14 +#define reg_pinmux_rw_hwprot___pwm2___width 1 +#define reg_pinmux_rw_hwprot___pwm2___bit 14 +#define reg_pinmux_rw_hwprot___timer0___lsb 15 +#define reg_pinmux_rw_hwprot___timer0___width 1 +#define reg_pinmux_rw_hwprot___timer0___bit 15 +#define reg_pinmux_rw_hwprot___timer1___lsb 16 +#define reg_pinmux_rw_hwprot___timer1___width 1 +#define reg_pinmux_rw_hwprot___timer1___bit 16 +#define reg_pinmux_rw_hwprot___pio___lsb 17 +#define reg_pinmux_rw_hwprot___pio___width 1 +#define reg_pinmux_rw_hwprot___pio___bit 17 +#define reg_pinmux_rw_hwprot___i2c0___lsb 18 +#define reg_pinmux_rw_hwprot___i2c0___width 1 +#define reg_pinmux_rw_hwprot___i2c0___bit 18 +#define reg_pinmux_rw_hwprot___i2c1___lsb 19 +#define reg_pinmux_rw_hwprot___i2c1___width 1 +#define reg_pinmux_rw_hwprot___i2c1___bit 19 +#define reg_pinmux_rw_hwprot___i2c1_sda1___lsb 20 +#define reg_pinmux_rw_hwprot___i2c1_sda1___width 1 +#define reg_pinmux_rw_hwprot___i2c1_sda1___bit 20 +#define reg_pinmux_rw_hwprot___i2c1_sda2___lsb 21 +#define reg_pinmux_rw_hwprot___i2c1_sda2___width 1 +#define reg_pinmux_rw_hwprot___i2c1_sda2___bit 21 +#define reg_pinmux_rw_hwprot___i2c1_sda3___lsb 22 +#define reg_pinmux_rw_hwprot___i2c1_sda3___width 1 +#define reg_pinmux_rw_hwprot___i2c1_sda3___bit 22 +#define reg_pinmux_rw_hwprot___i2c1_sen___lsb 23 +#define reg_pinmux_rw_hwprot___i2c1_sen___width 1 +#define reg_pinmux_rw_hwprot___i2c1_sen___bit 23 +#define reg_pinmux_rw_hwprot_offset 0 + +/* Register rw_gio_pa, scope pinmux, type rw */ +#define reg_pinmux_rw_gio_pa___pa0___lsb 0 +#define reg_pinmux_rw_gio_pa___pa0___width 1 +#define reg_pinmux_rw_gio_pa___pa0___bit 0 +#define reg_pinmux_rw_gio_pa___pa1___lsb 1 +#define reg_pinmux_rw_gio_pa___pa1___width 1 +#define reg_pinmux_rw_gio_pa___pa1___bit 1 +#define reg_pinmux_rw_gio_pa___pa2___lsb 2 +#define reg_pinmux_rw_gio_pa___pa2___width 1 +#define reg_pinmux_rw_gio_pa___pa2___bit 2 +#define reg_pinmux_rw_gio_pa___pa3___lsb 3 +#define reg_pinmux_rw_gio_pa___pa3___width 1 +#define reg_pinmux_rw_gio_pa___pa3___bit 3 +#define reg_pinmux_rw_gio_pa___pa4___lsb 4 +#define reg_pinmux_rw_gio_pa___pa4___width 1 +#define reg_pinmux_rw_gio_pa___pa4___bit 4 +#define reg_pinmux_rw_gio_pa___pa5___lsb 5 +#define reg_pinmux_rw_gio_pa___pa5___width 1 +#define reg_pinmux_rw_gio_pa___pa5___bit 5 +#define reg_pinmux_rw_gio_pa___pa6___lsb 6 +#define reg_pinmux_rw_gio_pa___pa6___width 1 +#define reg_pinmux_rw_gio_pa___pa6___bit 6 +#define reg_pinmux_rw_gio_pa___pa7___lsb 7 +#define reg_pinmux_rw_gio_pa___pa7___width 1 +#define reg_pinmux_rw_gio_pa___pa7___bit 7 +#define reg_pinmux_rw_gio_pa___pa8___lsb 8 +#define reg_pinmux_rw_gio_pa___pa8___width 1 +#define reg_pinmux_rw_gio_pa___pa8___bit 8 +#define reg_pinmux_rw_gio_pa___pa9___lsb 9 +#define reg_pinmux_rw_gio_pa___pa9___width 1 +#define reg_pinmux_rw_gio_pa___pa9___bit 9 +#define reg_pinmux_rw_gio_pa___pa10___lsb 10 +#define reg_pinmux_rw_gio_pa___pa10___width 1 +#define reg_pinmux_rw_gio_pa___pa10___bit 10 +#define reg_pinmux_rw_gio_pa___pa11___lsb 11 +#define reg_pinmux_rw_gio_pa___pa11___width 1 +#define reg_pinmux_rw_gio_pa___pa11___bit 11 +#define reg_pinmux_rw_gio_pa___pa12___lsb 12 +#define reg_pinmux_rw_gio_pa___pa12___width 1 +#define reg_pinmux_rw_gio_pa___pa12___bit 12 +#define reg_pinmux_rw_gio_pa___pa13___lsb 13 +#define reg_pinmux_rw_gio_pa___pa13___width 1 +#define reg_pinmux_rw_gio_pa___pa13___bit 13 +#define reg_pinmux_rw_gio_pa___pa14___lsb 14 +#define reg_pinmux_rw_gio_pa___pa14___width 1 +#define reg_pinmux_rw_gio_pa___pa14___bit 14 +#define reg_pinmux_rw_gio_pa___pa15___lsb 15 +#define reg_pinmux_rw_gio_pa___pa15___width 1 +#define reg_pinmux_rw_gio_pa___pa15___bit 15 +#define reg_pinmux_rw_gio_pa___pa16___lsb 16 +#define reg_pinmux_rw_gio_pa___pa16___width 1 +#define reg_pinmux_rw_gio_pa___pa16___bit 16 +#define reg_pinmux_rw_gio_pa___pa17___lsb 17 +#define reg_pinmux_rw_gio_pa___pa17___width 1 +#define reg_pinmux_rw_gio_pa___pa17___bit 17 +#define reg_pinmux_rw_gio_pa___pa18___lsb 18 +#define reg_pinmux_rw_gio_pa___pa18___width 1 +#define reg_pinmux_rw_gio_pa___pa18___bit 18 +#define reg_pinmux_rw_gio_pa___pa19___lsb 19 +#define reg_pinmux_rw_gio_pa___pa19___width 1 +#define reg_pinmux_rw_gio_pa___pa19___bit 19 +#define reg_pinmux_rw_gio_pa___pa20___lsb 20 +#define reg_pinmux_rw_gio_pa___pa20___width 1 +#define reg_pinmux_rw_gio_pa___pa20___bit 20 +#define reg_pinmux_rw_gio_pa___pa21___lsb 21 +#define reg_pinmux_rw_gio_pa___pa21___width 1 +#define reg_pinmux_rw_gio_pa___pa21___bit 21 +#define reg_pinmux_rw_gio_pa___pa22___lsb 22 +#define reg_pinmux_rw_gio_pa___pa22___width 1 +#define reg_pinmux_rw_gio_pa___pa22___bit 22 +#define reg_pinmux_rw_gio_pa___pa23___lsb 23 +#define reg_pinmux_rw_gio_pa___pa23___width 1 +#define reg_pinmux_rw_gio_pa___pa23___bit 23 +#define reg_pinmux_rw_gio_pa___pa24___lsb 24 +#define reg_pinmux_rw_gio_pa___pa24___width 1 +#define reg_pinmux_rw_gio_pa___pa24___bit 24 +#define reg_pinmux_rw_gio_pa___pa25___lsb 25 +#define reg_pinmux_rw_gio_pa___pa25___width 1 +#define reg_pinmux_rw_gio_pa___pa25___bit 25 +#define reg_pinmux_rw_gio_pa___pa26___lsb 26 +#define reg_pinmux_rw_gio_pa___pa26___width 1 +#define reg_pinmux_rw_gio_pa___pa26___bit 26 +#define reg_pinmux_rw_gio_pa___pa27___lsb 27 +#define reg_pinmux_rw_gio_pa___pa27___width 1 +#define reg_pinmux_rw_gio_pa___pa27___bit 27 +#define reg_pinmux_rw_gio_pa___pa28___lsb 28 +#define reg_pinmux_rw_gio_pa___pa28___width 1 +#define reg_pinmux_rw_gio_pa___pa28___bit 28 +#define reg_pinmux_rw_gio_pa___pa29___lsb 29 +#define reg_pinmux_rw_gio_pa___pa29___width 1 +#define reg_pinmux_rw_gio_pa___pa29___bit 29 +#define reg_pinmux_rw_gio_pa___pa30___lsb 30 +#define reg_pinmux_rw_gio_pa___pa30___width 1 +#define reg_pinmux_rw_gio_pa___pa30___bit 30 +#define reg_pinmux_rw_gio_pa___pa31___lsb 31 +#define reg_pinmux_rw_gio_pa___pa31___width 1 +#define reg_pinmux_rw_gio_pa___pa31___bit 31 +#define reg_pinmux_rw_gio_pa_offset 4 + +/* Register rw_gio_pb, scope pinmux, type rw */ +#define reg_pinmux_rw_gio_pb___pb0___lsb 0 +#define reg_pinmux_rw_gio_pb___pb0___width 1 +#define reg_pinmux_rw_gio_pb___pb0___bit 0 +#define reg_pinmux_rw_gio_pb___pb1___lsb 1 +#define reg_pinmux_rw_gio_pb___pb1___width 1 +#define reg_pinmux_rw_gio_pb___pb1___bit 1 +#define reg_pinmux_rw_gio_pb___pb2___lsb 2 +#define reg_pinmux_rw_gio_pb___pb2___width 1 +#define reg_pinmux_rw_gio_pb___pb2___bit 2 +#define reg_pinmux_rw_gio_pb___pb3___lsb 3 +#define reg_pinmux_rw_gio_pb___pb3___width 1 +#define reg_pinmux_rw_gio_pb___pb3___bit 3 +#define reg_pinmux_rw_gio_pb___pb4___lsb 4 +#define reg_pinmux_rw_gio_pb___pb4___width 1 +#define reg_pinmux_rw_gio_pb___pb4___bit 4 +#define reg_pinmux_rw_gio_pb___pb5___lsb 5 +#define reg_pinmux_rw_gio_pb___pb5___width 1 +#define reg_pinmux_rw_gio_pb___pb5___bit 5 +#define reg_pinmux_rw_gio_pb___pb6___lsb 6 +#define reg_pinmux_rw_gio_pb___pb6___width 1 +#define reg_pinmux_rw_gio_pb___pb6___bit 6 +#define reg_pinmux_rw_gio_pb___pb7___lsb 7 +#define reg_pinmux_rw_gio_pb___pb7___width 1 +#define reg_pinmux_rw_gio_pb___pb7___bit 7 +#define reg_pinmux_rw_gio_pb___pb8___lsb 8 +#define reg_pinmux_rw_gio_pb___pb8___width 1 +#define reg_pinmux_rw_gio_pb___pb8___bit 8 +#define reg_pinmux_rw_gio_pb___pb9___lsb 9 +#define reg_pinmux_rw_gio_pb___pb9___width 1 +#define reg_pinmux_rw_gio_pb___pb9___bit 9 +#define reg_pinmux_rw_gio_pb___pb10___lsb 10 +#define reg_pinmux_rw_gio_pb___pb10___width 1 +#define reg_pinmux_rw_gio_pb___pb10___bit 10 +#define reg_pinmux_rw_gio_pb___pb11___lsb 11 +#define reg_pinmux_rw_gio_pb___pb11___width 1 +#define reg_pinmux_rw_gio_pb___pb11___bit 11 +#define reg_pinmux_rw_gio_pb___pb12___lsb 12 +#define reg_pinmux_rw_gio_pb___pb12___width 1 +#define reg_pinmux_rw_gio_pb___pb12___bit 12 +#define reg_pinmux_rw_gio_pb___pb13___lsb 13 +#define reg_pinmux_rw_gio_pb___pb13___width 1 +#define reg_pinmux_rw_gio_pb___pb13___bit 13 +#define reg_pinmux_rw_gio_pb___pb14___lsb 14 +#define reg_pinmux_rw_gio_pb___pb14___width 1 +#define reg_pinmux_rw_gio_pb___pb14___bit 14 +#define reg_pinmux_rw_gio_pb___pb15___lsb 15 +#define reg_pinmux_rw_gio_pb___pb15___width 1 +#define reg_pinmux_rw_gio_pb___pb15___bit 15 +#define reg_pinmux_rw_gio_pb___pb16___lsb 16 +#define reg_pinmux_rw_gio_pb___pb16___width 1 +#define reg_pinmux_rw_gio_pb___pb16___bit 16 +#define reg_pinmux_rw_gio_pb___pb17___lsb 17 +#define reg_pinmux_rw_gio_pb___pb17___width 1 +#define reg_pinmux_rw_gio_pb___pb17___bit 17 +#define reg_pinmux_rw_gio_pb___pb18___lsb 18 +#define reg_pinmux_rw_gio_pb___pb18___width 1 +#define reg_pinmux_rw_gio_pb___pb18___bit 18 +#define reg_pinmux_rw_gio_pb___pb19___lsb 19 +#define reg_pinmux_rw_gio_pb___pb19___width 1 +#define reg_pinmux_rw_gio_pb___pb19___bit 19 +#define reg_pinmux_rw_gio_pb___pb20___lsb 20 +#define reg_pinmux_rw_gio_pb___pb20___width 1 +#define reg_pinmux_rw_gio_pb___pb20___bit 20 +#define reg_pinmux_rw_gio_pb___pb21___lsb 21 +#define reg_pinmux_rw_gio_pb___pb21___width 1 +#define reg_pinmux_rw_gio_pb___pb21___bit 21 +#define reg_pinmux_rw_gio_pb___pb22___lsb 22 +#define reg_pinmux_rw_gio_pb___pb22___width 1 +#define reg_pinmux_rw_gio_pb___pb22___bit 22 +#define reg_pinmux_rw_gio_pb___pb23___lsb 23 +#define reg_pinmux_rw_gio_pb___pb23___width 1 +#define reg_pinmux_rw_gio_pb___pb23___bit 23 +#define reg_pinmux_rw_gio_pb___pb24___lsb 24 +#define reg_pinmux_rw_gio_pb___pb24___width 1 +#define reg_pinmux_rw_gio_pb___pb24___bit 24 +#define reg_pinmux_rw_gio_pb___pb25___lsb 25 +#define reg_pinmux_rw_gio_pb___pb25___width 1 +#define reg_pinmux_rw_gio_pb___pb25___bit 25 +#define reg_pinmux_rw_gio_pb___pb26___lsb 26 +#define reg_pinmux_rw_gio_pb___pb26___width 1 +#define reg_pinmux_rw_gio_pb___pb26___bit 26 +#define reg_pinmux_rw_gio_pb___pb27___lsb 27 +#define reg_pinmux_rw_gio_pb___pb27___width 1 +#define reg_pinmux_rw_gio_pb___pb27___bit 27 +#define reg_pinmux_rw_gio_pb___pb28___lsb 28 +#define reg_pinmux_rw_gio_pb___pb28___width 1 +#define reg_pinmux_rw_gio_pb___pb28___bit 28 +#define reg_pinmux_rw_gio_pb___pb29___lsb 29 +#define reg_pinmux_rw_gio_pb___pb29___width 1 +#define reg_pinmux_rw_gio_pb___pb29___bit 29 +#define reg_pinmux_rw_gio_pb___pb30___lsb 30 +#define reg_pinmux_rw_gio_pb___pb30___width 1 +#define reg_pinmux_rw_gio_pb___pb30___bit 30 +#define reg_pinmux_rw_gio_pb___pb31___lsb 31 +#define reg_pinmux_rw_gio_pb___pb31___width 1 +#define reg_pinmux_rw_gio_pb___pb31___bit 31 +#define reg_pinmux_rw_gio_pb_offset 8 + +/* Register rw_gio_pc, scope pinmux, type rw */ +#define reg_pinmux_rw_gio_pc___pc0___lsb 0 +#define reg_pinmux_rw_gio_pc___pc0___width 1 +#define reg_pinmux_rw_gio_pc___pc0___bit 0 +#define reg_pinmux_rw_gio_pc___pc1___lsb 1 +#define reg_pinmux_rw_gio_pc___pc1___width 1 +#define reg_pinmux_rw_gio_pc___pc1___bit 1 +#define reg_pinmux_rw_gio_pc___pc2___lsb 2 +#define reg_pinmux_rw_gio_pc___pc2___width 1 +#define reg_pinmux_rw_gio_pc___pc2___bit 2 +#define reg_pinmux_rw_gio_pc___pc3___lsb 3 +#define reg_pinmux_rw_gio_pc___pc3___width 1 +#define reg_pinmux_rw_gio_pc___pc3___bit 3 +#define reg_pinmux_rw_gio_pc___pc4___lsb 4 +#define reg_pinmux_rw_gio_pc___pc4___width 1 +#define reg_pinmux_rw_gio_pc___pc4___bit 4 +#define reg_pinmux_rw_gio_pc___pc5___lsb 5 +#define reg_pinmux_rw_gio_pc___pc5___width 1 +#define reg_pinmux_rw_gio_pc___pc5___bit 5 +#define reg_pinmux_rw_gio_pc___pc6___lsb 6 +#define reg_pinmux_rw_gio_pc___pc6___width 1 +#define reg_pinmux_rw_gio_pc___pc6___bit 6 +#define reg_pinmux_rw_gio_pc___pc7___lsb 7 +#define reg_pinmux_rw_gio_pc___pc7___width 1 +#define reg_pinmux_rw_gio_pc___pc7___bit 7 +#define reg_pinmux_rw_gio_pc___pc8___lsb 8 +#define reg_pinmux_rw_gio_pc___pc8___width 1 +#define reg_pinmux_rw_gio_pc___pc8___bit 8 +#define reg_pinmux_rw_gio_pc___pc9___lsb 9 +#define reg_pinmux_rw_gio_pc___pc9___width 1 +#define reg_pinmux_rw_gio_pc___pc9___bit 9 +#define reg_pinmux_rw_gio_pc___pc10___lsb 10 +#define reg_pinmux_rw_gio_pc___pc10___width 1 +#define reg_pinmux_rw_gio_pc___pc10___bit 10 +#define reg_pinmux_rw_gio_pc___pc11___lsb 11 +#define reg_pinmux_rw_gio_pc___pc11___width 1 +#define reg_pinmux_rw_gio_pc___pc11___bit 11 +#define reg_pinmux_rw_gio_pc___pc12___lsb 12 +#define reg_pinmux_rw_gio_pc___pc12___width 1 +#define reg_pinmux_rw_gio_pc___pc12___bit 12 +#define reg_pinmux_rw_gio_pc___pc13___lsb 13 +#define reg_pinmux_rw_gio_pc___pc13___width 1 +#define reg_pinmux_rw_gio_pc___pc13___bit 13 +#define reg_pinmux_rw_gio_pc___pc14___lsb 14 +#define reg_pinmux_rw_gio_pc___pc14___width 1 +#define reg_pinmux_rw_gio_pc___pc14___bit 14 +#define reg_pinmux_rw_gio_pc___pc15___lsb 15 +#define reg_pinmux_rw_gio_pc___pc15___width 1 +#define reg_pinmux_rw_gio_pc___pc15___bit 15 +#define reg_pinmux_rw_gio_pc_offset 12 + +/* Register rw_iop_pa, scope pinmux, type rw */ +#define reg_pinmux_rw_iop_pa___pa0___lsb 0 +#define reg_pinmux_rw_iop_pa___pa0___width 1 +#define reg_pinmux_rw_iop_pa___pa0___bit 0 +#define reg_pinmux_rw_iop_pa___pa1___lsb 1 +#define reg_pinmux_rw_iop_pa___pa1___width 1 +#define reg_pinmux_rw_iop_pa___pa1___bit 1 +#define reg_pinmux_rw_iop_pa___pa2___lsb 2 +#define reg_pinmux_rw_iop_pa___pa2___width 1 +#define reg_pinmux_rw_iop_pa___pa2___bit 2 +#define reg_pinmux_rw_iop_pa___pa3___lsb 3 +#define reg_pinmux_rw_iop_pa___pa3___width 1 +#define reg_pinmux_rw_iop_pa___pa3___bit 3 +#define reg_pinmux_rw_iop_pa___pa4___lsb 4 +#define reg_pinmux_rw_iop_pa___pa4___width 1 +#define reg_pinmux_rw_iop_pa___pa4___bit 4 +#define reg_pinmux_rw_iop_pa___pa5___lsb 5 +#define reg_pinmux_rw_iop_pa___pa5___width 1 +#define reg_pinmux_rw_iop_pa___pa5___bit 5 +#define reg_pinmux_rw_iop_pa___pa6___lsb 6 +#define reg_pinmux_rw_iop_pa___pa6___width 1 +#define reg_pinmux_rw_iop_pa___pa6___bit 6 +#define reg_pinmux_rw_iop_pa___pa7___lsb 7 +#define reg_pinmux_rw_iop_pa___pa7___width 1 +#define reg_pinmux_rw_iop_pa___pa7___bit 7 +#define reg_pinmux_rw_iop_pa___pa8___lsb 8 +#define reg_pinmux_rw_iop_pa___pa8___width 1 +#define reg_pinmux_rw_iop_pa___pa8___bit 8 +#define reg_pinmux_rw_iop_pa___pa9___lsb 9 +#define reg_pinmux_rw_iop_pa___pa9___width 1 +#define reg_pinmux_rw_iop_pa___pa9___bit 9 +#define reg_pinmux_rw_iop_pa___pa10___lsb 10 +#define reg_pinmux_rw_iop_pa___pa10___width 1 +#define reg_pinmux_rw_iop_pa___pa10___bit 10 +#define reg_pinmux_rw_iop_pa___pa11___lsb 11 +#define reg_pinmux_rw_iop_pa___pa11___width 1 +#define reg_pinmux_rw_iop_pa___pa11___bit 11 +#define reg_pinmux_rw_iop_pa___pa12___lsb 12 +#define reg_pinmux_rw_iop_pa___pa12___width 1 +#define reg_pinmux_rw_iop_pa___pa12___bit 12 +#define reg_pinmux_rw_iop_pa___pa13___lsb 13 +#define reg_pinmux_rw_iop_pa___pa13___width 1 +#define reg_pinmux_rw_iop_pa___pa13___bit 13 +#define reg_pinmux_rw_iop_pa___pa14___lsb 14 +#define reg_pinmux_rw_iop_pa___pa14___width 1 +#define reg_pinmux_rw_iop_pa___pa14___bit 14 +#define reg_pinmux_rw_iop_pa___pa15___lsb 15 +#define reg_pinmux_rw_iop_pa___pa15___width 1 +#define reg_pinmux_rw_iop_pa___pa15___bit 15 +#define reg_pinmux_rw_iop_pa___pa16___lsb 16 +#define reg_pinmux_rw_iop_pa___pa16___width 1 +#define reg_pinmux_rw_iop_pa___pa16___bit 16 +#define reg_pinmux_rw_iop_pa___pa17___lsb 17 +#define reg_pinmux_rw_iop_pa___pa17___width 1 +#define reg_pinmux_rw_iop_pa___pa17___bit 17 +#define reg_pinmux_rw_iop_pa___pa18___lsb 18 +#define reg_pinmux_rw_iop_pa___pa18___width 1 +#define reg_pinmux_rw_iop_pa___pa18___bit 18 +#define reg_pinmux_rw_iop_pa___pa19___lsb 19 +#define reg_pinmux_rw_iop_pa___pa19___width 1 +#define reg_pinmux_rw_iop_pa___pa19___bit 19 +#define reg_pinmux_rw_iop_pa___pa20___lsb 20 +#define reg_pinmux_rw_iop_pa___pa20___width 1 +#define reg_pinmux_rw_iop_pa___pa20___bit 20 +#define reg_pinmux_rw_iop_pa___pa21___lsb 21 +#define reg_pinmux_rw_iop_pa___pa21___width 1 +#define reg_pinmux_rw_iop_pa___pa21___bit 21 +#define reg_pinmux_rw_iop_pa___pa22___lsb 22 +#define reg_pinmux_rw_iop_pa___pa22___width 1 +#define reg_pinmux_rw_iop_pa___pa22___bit 22 +#define reg_pinmux_rw_iop_pa___pa23___lsb 23 +#define reg_pinmux_rw_iop_pa___pa23___width 1 +#define reg_pinmux_rw_iop_pa___pa23___bit 23 +#define reg_pinmux_rw_iop_pa___pa24___lsb 24 +#define reg_pinmux_rw_iop_pa___pa24___width 1 +#define reg_pinmux_rw_iop_pa___pa24___bit 24 +#define reg_pinmux_rw_iop_pa___pa25___lsb 25 +#define reg_pinmux_rw_iop_pa___pa25___width 1 +#define reg_pinmux_rw_iop_pa___pa25___bit 25 +#define reg_pinmux_rw_iop_pa___pa26___lsb 26 +#define reg_pinmux_rw_iop_pa___pa26___width 1 +#define reg_pinmux_rw_iop_pa___pa26___bit 26 +#define reg_pinmux_rw_iop_pa___pa27___lsb 27 +#define reg_pinmux_rw_iop_pa___pa27___width 1 +#define reg_pinmux_rw_iop_pa___pa27___bit 27 +#define reg_pinmux_rw_iop_pa___pa28___lsb 28 +#define reg_pinmux_rw_iop_pa___pa28___width 1 +#define reg_pinmux_rw_iop_pa___pa28___bit 28 +#define reg_pinmux_rw_iop_pa___pa29___lsb 29 +#define reg_pinmux_rw_iop_pa___pa29___width 1 +#define reg_pinmux_rw_iop_pa___pa29___bit 29 +#define reg_pinmux_rw_iop_pa___pa30___lsb 30 +#define reg_pinmux_rw_iop_pa___pa30___width 1 +#define reg_pinmux_rw_iop_pa___pa30___bit 30 +#define reg_pinmux_rw_iop_pa___pa31___lsb 31 +#define reg_pinmux_rw_iop_pa___pa31___width 1 +#define reg_pinmux_rw_iop_pa___pa31___bit 31 +#define reg_pinmux_rw_iop_pa_offset 16 + +/* Register rw_iop_pb, scope pinmux, type rw */ +#define reg_pinmux_rw_iop_pb___pb0___lsb 0 +#define reg_pinmux_rw_iop_pb___pb0___width 1 +#define reg_pinmux_rw_iop_pb___pb0___bit 0 +#define reg_pinmux_rw_iop_pb___pb1___lsb 1 +#define reg_pinmux_rw_iop_pb___pb1___width 1 +#define reg_pinmux_rw_iop_pb___pb1___bit 1 +#define reg_pinmux_rw_iop_pb___pb2___lsb 2 +#define reg_pinmux_rw_iop_pb___pb2___width 1 +#define reg_pinmux_rw_iop_pb___pb2___bit 2 +#define reg_pinmux_rw_iop_pb___pb3___lsb 3 +#define reg_pinmux_rw_iop_pb___pb3___width 1 +#define reg_pinmux_rw_iop_pb___pb3___bit 3 +#define reg_pinmux_rw_iop_pb___pb4___lsb 4 +#define reg_pinmux_rw_iop_pb___pb4___width 1 +#define reg_pinmux_rw_iop_pb___pb4___bit 4 +#define reg_pinmux_rw_iop_pb___pb5___lsb 5 +#define reg_pinmux_rw_iop_pb___pb5___width 1 +#define reg_pinmux_rw_iop_pb___pb5___bit 5 +#define reg_pinmux_rw_iop_pb___pb6___lsb 6 +#define reg_pinmux_rw_iop_pb___pb6___width 1 +#define reg_pinmux_rw_iop_pb___pb6___bit 6 +#define reg_pinmux_rw_iop_pb___pb7___lsb 7 +#define reg_pinmux_rw_iop_pb___pb7___width 1 +#define reg_pinmux_rw_iop_pb___pb7___bit 7 +#define reg_pinmux_rw_iop_pb_offset 20 + +/* Register rw_iop_pio, scope pinmux, type rw */ +#define reg_pinmux_rw_iop_pio___d0___lsb 0 +#define reg_pinmux_rw_iop_pio___d0___width 1 +#define reg_pinmux_rw_iop_pio___d0___bit 0 +#define reg_pinmux_rw_iop_pio___d1___lsb 1 +#define reg_pinmux_rw_iop_pio___d1___width 1 +#define reg_pinmux_rw_iop_pio___d1___bit 1 +#define reg_pinmux_rw_iop_pio___d2___lsb 2 +#define reg_pinmux_rw_iop_pio___d2___width 1 +#define reg_pinmux_rw_iop_pio___d2___bit 2 +#define reg_pinmux_rw_iop_pio___d3___lsb 3 +#define reg_pinmux_rw_iop_pio___d3___width 1 +#define reg_pinmux_rw_iop_pio___d3___bit 3 +#define reg_pinmux_rw_iop_pio___d4___lsb 4 +#define reg_pinmux_rw_iop_pio___d4___width 1 +#define reg_pinmux_rw_iop_pio___d4___bit 4 +#define reg_pinmux_rw_iop_pio___d5___lsb 5 +#define reg_pinmux_rw_iop_pio___d5___width 1 +#define reg_pinmux_rw_iop_pio___d5___bit 5 +#define reg_pinmux_rw_iop_pio___d6___lsb 6 +#define reg_pinmux_rw_iop_pio___d6___width 1 +#define reg_pinmux_rw_iop_pio___d6___bit 6 +#define reg_pinmux_rw_iop_pio___d7___lsb 7 +#define reg_pinmux_rw_iop_pio___d7___width 1 +#define reg_pinmux_rw_iop_pio___d7___bit 7 +#define reg_pinmux_rw_iop_pio___rd_n___lsb 8 +#define reg_pinmux_rw_iop_pio___rd_n___width 1 +#define reg_pinmux_rw_iop_pio___rd_n___bit 8 +#define reg_pinmux_rw_iop_pio___wr_n___lsb 9 +#define reg_pinmux_rw_iop_pio___wr_n___width 1 +#define reg_pinmux_rw_iop_pio___wr_n___bit 9 +#define reg_pinmux_rw_iop_pio___a0___lsb 10 +#define reg_pinmux_rw_iop_pio___a0___width 1 +#define reg_pinmux_rw_iop_pio___a0___bit 10 +#define reg_pinmux_rw_iop_pio___a1___lsb 11 +#define reg_pinmux_rw_iop_pio___a1___width 1 +#define reg_pinmux_rw_iop_pio___a1___bit 11 +#define reg_pinmux_rw_iop_pio___ce0_n___lsb 12 +#define reg_pinmux_rw_iop_pio___ce0_n___width 1 +#define reg_pinmux_rw_iop_pio___ce0_n___bit 12 +#define reg_pinmux_rw_iop_pio___ce1_n___lsb 13 +#define reg_pinmux_rw_iop_pio___ce1_n___width 1 +#define reg_pinmux_rw_iop_pio___ce1_n___bit 13 +#define reg_pinmux_rw_iop_pio___ce2_n___lsb 14 +#define reg_pinmux_rw_iop_pio___ce2_n___width 1 +#define reg_pinmux_rw_iop_pio___ce2_n___bit 14 +#define reg_pinmux_rw_iop_pio___rdy___lsb 15 +#define reg_pinmux_rw_iop_pio___rdy___width 1 +#define reg_pinmux_rw_iop_pio___rdy___bit 15 +#define reg_pinmux_rw_iop_pio_offset 24 + +/* Register rw_iop_usb, scope pinmux, type rw */ +#define reg_pinmux_rw_iop_usb___usb0___lsb 0 +#define reg_pinmux_rw_iop_usb___usb0___width 1 +#define reg_pinmux_rw_iop_usb___usb0___bit 0 +#define reg_pinmux_rw_iop_usb_offset 28 + + +/* Constants */ +#define regk_pinmux_no 0x00000000 +#define regk_pinmux_rw_gio_pa_default 0x00000000 +#define regk_pinmux_rw_gio_pb_default 0x00000000 +#define regk_pinmux_rw_gio_pc_default 0x00000000 +#define regk_pinmux_rw_hwprot_default 0x00000000 +#define regk_pinmux_rw_iop_pa_default 0x00000000 +#define regk_pinmux_rw_iop_pb_default 0x00000000 +#define regk_pinmux_rw_iop_pio_default 0x00000000 +#define regk_pinmux_rw_iop_usb_default 0x00000001 +#define regk_pinmux_yes 0x00000001 +#endif /* __pinmux_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h new file mode 100644 index 00000000000..3907ef4921c --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h @@ -0,0 +1,337 @@ +#ifndef __pio_defs_asm_h +#define __pio_defs_asm_h + +/* + * This file is autogenerated from + * file: pio.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_data, scope pio, type rw */ +#define reg_pio_rw_data_offset 64 + +/* Register rw_io_access0, scope pio, type rw */ +#define reg_pio_rw_io_access0___data___lsb 0 +#define reg_pio_rw_io_access0___data___width 8 +#define reg_pio_rw_io_access0_offset 0 + +/* Register rw_io_access1, scope pio, type rw */ +#define reg_pio_rw_io_access1___data___lsb 0 +#define reg_pio_rw_io_access1___data___width 8 +#define reg_pio_rw_io_access1_offset 4 + +/* Register rw_io_access2, scope pio, type rw */ +#define reg_pio_rw_io_access2___data___lsb 0 +#define reg_pio_rw_io_access2___data___width 8 +#define reg_pio_rw_io_access2_offset 8 + +/* Register rw_io_access3, scope pio, type rw */ +#define reg_pio_rw_io_access3___data___lsb 0 +#define reg_pio_rw_io_access3___data___width 8 +#define reg_pio_rw_io_access3_offset 12 + +/* Register rw_io_access4, scope pio, type rw */ +#define reg_pio_rw_io_access4___data___lsb 0 +#define reg_pio_rw_io_access4___data___width 8 +#define reg_pio_rw_io_access4_offset 16 + +/* Register rw_io_access5, scope pio, type rw */ +#define reg_pio_rw_io_access5___data___lsb 0 +#define reg_pio_rw_io_access5___data___width 8 +#define reg_pio_rw_io_access5_offset 20 + +/* Register rw_io_access6, scope pio, type rw */ +#define reg_pio_rw_io_access6___data___lsb 0 +#define reg_pio_rw_io_access6___data___width 8 +#define reg_pio_rw_io_access6_offset 24 + +/* Register rw_io_access7, scope pio, type rw */ +#define reg_pio_rw_io_access7___data___lsb 0 +#define reg_pio_rw_io_access7___data___width 8 +#define reg_pio_rw_io_access7_offset 28 + +/* Register rw_io_access8, scope pio, type rw */ +#define reg_pio_rw_io_access8___data___lsb 0 +#define reg_pio_rw_io_access8___data___width 8 +#define reg_pio_rw_io_access8_offset 32 + +/* Register rw_io_access9, scope pio, type rw */ +#define reg_pio_rw_io_access9___data___lsb 0 +#define reg_pio_rw_io_access9___data___width 8 +#define reg_pio_rw_io_access9_offset 36 + +/* Register rw_io_access10, scope pio, type rw */ +#define reg_pio_rw_io_access10___data___lsb 0 +#define reg_pio_rw_io_access10___data___width 8 +#define reg_pio_rw_io_access10_offset 40 + +/* Register rw_io_access11, scope pio, type rw */ +#define reg_pio_rw_io_access11___data___lsb 0 +#define reg_pio_rw_io_access11___data___width 8 +#define reg_pio_rw_io_access11_offset 44 + +/* Register rw_io_access12, scope pio, type rw */ +#define reg_pio_rw_io_access12___data___lsb 0 +#define reg_pio_rw_io_access12___data___width 8 +#define reg_pio_rw_io_access12_offset 48 + +/* Register rw_io_access13, scope pio, type rw */ +#define reg_pio_rw_io_access13___data___lsb 0 +#define reg_pio_rw_io_access13___data___width 8 +#define reg_pio_rw_io_access13_offset 52 + +/* Register rw_io_access14, scope pio, type rw */ +#define reg_pio_rw_io_access14___data___lsb 0 +#define reg_pio_rw_io_access14___data___width 8 +#define reg_pio_rw_io_access14_offset 56 + +/* Register rw_io_access15, scope pio, type rw */ +#define reg_pio_rw_io_access15___data___lsb 0 +#define reg_pio_rw_io_access15___data___width 8 +#define reg_pio_rw_io_access15_offset 60 + +/* Register rw_ce0_cfg, scope pio, type rw */ +#define reg_pio_rw_ce0_cfg___lw___lsb 0 +#define reg_pio_rw_ce0_cfg___lw___width 6 +#define reg_pio_rw_ce0_cfg___ew___lsb 6 +#define reg_pio_rw_ce0_cfg___ew___width 3 +#define reg_pio_rw_ce0_cfg___zw___lsb 9 +#define reg_pio_rw_ce0_cfg___zw___width 3 +#define reg_pio_rw_ce0_cfg___aw___lsb 12 +#define reg_pio_rw_ce0_cfg___aw___width 2 +#define reg_pio_rw_ce0_cfg___mode___lsb 14 +#define reg_pio_rw_ce0_cfg___mode___width 2 +#define reg_pio_rw_ce0_cfg_offset 68 + +/* Register rw_ce1_cfg, scope pio, type rw */ +#define reg_pio_rw_ce1_cfg___lw___lsb 0 +#define reg_pio_rw_ce1_cfg___lw___width 6 +#define reg_pio_rw_ce1_cfg___ew___lsb 6 +#define reg_pio_rw_ce1_cfg___ew___width 3 +#define reg_pio_rw_ce1_cfg___zw___lsb 9 +#define reg_pio_rw_ce1_cfg___zw___width 3 +#define reg_pio_rw_ce1_cfg___aw___lsb 12 +#define reg_pio_rw_ce1_cfg___aw___width 2 +#define reg_pio_rw_ce1_cfg___mode___lsb 14 +#define reg_pio_rw_ce1_cfg___mode___width 2 +#define reg_pio_rw_ce1_cfg_offset 72 + +/* Register rw_ce2_cfg, scope pio, type rw */ +#define reg_pio_rw_ce2_cfg___lw___lsb 0 +#define reg_pio_rw_ce2_cfg___lw___width 6 +#define reg_pio_rw_ce2_cfg___ew___lsb 6 +#define reg_pio_rw_ce2_cfg___ew___width 3 +#define reg_pio_rw_ce2_cfg___zw___lsb 9 +#define reg_pio_rw_ce2_cfg___zw___width 3 +#define reg_pio_rw_ce2_cfg___aw___lsb 12 +#define reg_pio_rw_ce2_cfg___aw___width 2 +#define reg_pio_rw_ce2_cfg___mode___lsb 14 +#define reg_pio_rw_ce2_cfg___mode___width 2 +#define reg_pio_rw_ce2_cfg_offset 76 + +/* Register rw_dout, scope pio, type rw */ +#define reg_pio_rw_dout___data___lsb 0 +#define reg_pio_rw_dout___data___width 8 +#define reg_pio_rw_dout___rd_n___lsb 8 +#define reg_pio_rw_dout___rd_n___width 1 +#define reg_pio_rw_dout___rd_n___bit 8 +#define reg_pio_rw_dout___wr_n___lsb 9 +#define reg_pio_rw_dout___wr_n___width 1 +#define reg_pio_rw_dout___wr_n___bit 9 +#define reg_pio_rw_dout___a0___lsb 10 +#define reg_pio_rw_dout___a0___width 1 +#define reg_pio_rw_dout___a0___bit 10 +#define reg_pio_rw_dout___a1___lsb 11 +#define reg_pio_rw_dout___a1___width 1 +#define reg_pio_rw_dout___a1___bit 11 +#define reg_pio_rw_dout___ce0_n___lsb 12 +#define reg_pio_rw_dout___ce0_n___width 1 +#define reg_pio_rw_dout___ce0_n___bit 12 +#define reg_pio_rw_dout___ce1_n___lsb 13 +#define reg_pio_rw_dout___ce1_n___width 1 +#define reg_pio_rw_dout___ce1_n___bit 13 +#define reg_pio_rw_dout___ce2_n___lsb 14 +#define reg_pio_rw_dout___ce2_n___width 1 +#define reg_pio_rw_dout___ce2_n___bit 14 +#define reg_pio_rw_dout___rdy___lsb 15 +#define reg_pio_rw_dout___rdy___width 1 +#define reg_pio_rw_dout___rdy___bit 15 +#define reg_pio_rw_dout_offset 80 + +/* Register rw_oe, scope pio, type rw */ +#define reg_pio_rw_oe___data___lsb 0 +#define reg_pio_rw_oe___data___width 8 +#define reg_pio_rw_oe___rd_n___lsb 8 +#define reg_pio_rw_oe___rd_n___width 1 +#define reg_pio_rw_oe___rd_n___bit 8 +#define reg_pio_rw_oe___wr_n___lsb 9 +#define reg_pio_rw_oe___wr_n___width 1 +#define reg_pio_rw_oe___wr_n___bit 9 +#define reg_pio_rw_oe___a0___lsb 10 +#define reg_pio_rw_oe___a0___width 1 +#define reg_pio_rw_oe___a0___bit 10 +#define reg_pio_rw_oe___a1___lsb 11 +#define reg_pio_rw_oe___a1___width 1 +#define reg_pio_rw_oe___a1___bit 11 +#define reg_pio_rw_oe___ce0_n___lsb 12 +#define reg_pio_rw_oe___ce0_n___width 1 +#define reg_pio_rw_oe___ce0_n___bit 12 +#define reg_pio_rw_oe___ce1_n___lsb 13 +#define reg_pio_rw_oe___ce1_n___width 1 +#define reg_pio_rw_oe___ce1_n___bit 13 +#define reg_pio_rw_oe___ce2_n___lsb 14 +#define reg_pio_rw_oe___ce2_n___width 1 +#define reg_pio_rw_oe___ce2_n___bit 14 +#define reg_pio_rw_oe___rdy___lsb 15 +#define reg_pio_rw_oe___rdy___width 1 +#define reg_pio_rw_oe___rdy___bit 15 +#define reg_pio_rw_oe_offset 84 + +/* Register rw_man_ctrl, scope pio, type rw */ +#define reg_pio_rw_man_ctrl___data___lsb 0 +#define reg_pio_rw_man_ctrl___data___width 8 +#define reg_pio_rw_man_ctrl___rd_n___lsb 8 +#define reg_pio_rw_man_ctrl___rd_n___width 1 +#define reg_pio_rw_man_ctrl___rd_n___bit 8 +#define reg_pio_rw_man_ctrl___wr_n___lsb 9 +#define reg_pio_rw_man_ctrl___wr_n___width 1 +#define reg_pio_rw_man_ctrl___wr_n___bit 9 +#define reg_pio_rw_man_ctrl___a0___lsb 10 +#define reg_pio_rw_man_ctrl___a0___width 1 +#define reg_pio_rw_man_ctrl___a0___bit 10 +#define reg_pio_rw_man_ctrl___a1___lsb 11 +#define reg_pio_rw_man_ctrl___a1___width 1 +#define reg_pio_rw_man_ctrl___a1___bit 11 +#define reg_pio_rw_man_ctrl___ce0_n___lsb 12 +#define reg_pio_rw_man_ctrl___ce0_n___width 1 +#define reg_pio_rw_man_ctrl___ce0_n___bit 12 +#define reg_pio_rw_man_ctrl___ce1_n___lsb 13 +#define reg_pio_rw_man_ctrl___ce1_n___width 1 +#define reg_pio_rw_man_ctrl___ce1_n___bit 13 +#define reg_pio_rw_man_ctrl___ce2_n___lsb 14 +#define reg_pio_rw_man_ctrl___ce2_n___width 1 +#define reg_pio_rw_man_ctrl___ce2_n___bit 14 +#define reg_pio_rw_man_ctrl___rdy___lsb 15 +#define reg_pio_rw_man_ctrl___rdy___width 1 +#define reg_pio_rw_man_ctrl___rdy___bit 15 +#define reg_pio_rw_man_ctrl_offset 88 + +/* Register r_din, scope pio, type r */ +#define reg_pio_r_din___data___lsb 0 +#define reg_pio_r_din___data___width 8 +#define reg_pio_r_din___rd_n___lsb 8 +#define reg_pio_r_din___rd_n___width 1 +#define reg_pio_r_din___rd_n___bit 8 +#define reg_pio_r_din___wr_n___lsb 9 +#define reg_pio_r_din___wr_n___width 1 +#define reg_pio_r_din___wr_n___bit 9 +#define reg_pio_r_din___a0___lsb 10 +#define reg_pio_r_din___a0___width 1 +#define reg_pio_r_din___a0___bit 10 +#define reg_pio_r_din___a1___lsb 11 +#define reg_pio_r_din___a1___width 1 +#define reg_pio_r_din___a1___bit 11 +#define reg_pio_r_din___ce0_n___lsb 12 +#define reg_pio_r_din___ce0_n___width 1 +#define reg_pio_r_din___ce0_n___bit 12 +#define reg_pio_r_din___ce1_n___lsb 13 +#define reg_pio_r_din___ce1_n___width 1 +#define reg_pio_r_din___ce1_n___bit 13 +#define reg_pio_r_din___ce2_n___lsb 14 +#define reg_pio_r_din___ce2_n___width 1 +#define reg_pio_r_din___ce2_n___bit 14 +#define reg_pio_r_din___rdy___lsb 15 +#define reg_pio_r_din___rdy___width 1 +#define reg_pio_r_din___rdy___bit 15 +#define reg_pio_r_din_offset 92 + +/* Register r_stat, scope pio, type r */ +#define reg_pio_r_stat___busy___lsb 0 +#define reg_pio_r_stat___busy___width 1 +#define reg_pio_r_stat___busy___bit 0 +#define reg_pio_r_stat_offset 96 + +/* Register rw_intr_mask, scope pio, type rw */ +#define reg_pio_rw_intr_mask___rdy___lsb 0 +#define reg_pio_rw_intr_mask___rdy___width 1 +#define reg_pio_rw_intr_mask___rdy___bit 0 +#define reg_pio_rw_intr_mask_offset 100 + +/* Register rw_ack_intr, scope pio, type rw */ +#define reg_pio_rw_ack_intr___rdy___lsb 0 +#define reg_pio_rw_ack_intr___rdy___width 1 +#define reg_pio_rw_ack_intr___rdy___bit 0 +#define reg_pio_rw_ack_intr_offset 104 + +/* Register r_intr, scope pio, type r */ +#define reg_pio_r_intr___rdy___lsb 0 +#define reg_pio_r_intr___rdy___width 1 +#define reg_pio_r_intr___rdy___bit 0 +#define reg_pio_r_intr_offset 108 + +/* Register r_masked_intr, scope pio, type r */ +#define reg_pio_r_masked_intr___rdy___lsb 0 +#define reg_pio_r_masked_intr___rdy___width 1 +#define reg_pio_r_masked_intr___rdy___bit 0 +#define reg_pio_r_masked_intr_offset 112 + + +/* Constants */ +#define regk_pio_a2 0x00000003 +#define regk_pio_no 0x00000000 +#define regk_pio_normal 0x00000000 +#define regk_pio_rd 0x00000001 +#define regk_pio_rw_ce0_cfg_default 0x00000000 +#define regk_pio_rw_ce1_cfg_default 0x00000000 +#define regk_pio_rw_ce2_cfg_default 0x00000000 +#define regk_pio_rw_intr_mask_default 0x00000000 +#define regk_pio_rw_man_ctrl_default 0x00000000 +#define regk_pio_rw_oe_default 0x00000000 +#define regk_pio_wr 0x00000002 +#define regk_pio_wr_ce2 0x00000003 +#define regk_pio_yes 0x00000001 +#define regk_pio_yes_all 0x000000ff +#endif /* __pio_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h new file mode 100644 index 00000000000..89439e9610e --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h @@ -0,0 +1,99 @@ +#ifndef __reg_map_asm_h +#define __reg_map_asm_h + +/* + * This file is autogenerated from + * file: reg.rmap + * + * by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +#define regi_ccd 0xb0000000 +#define regi_ccd_top 0xb0000000 +#define regi_ccd_dp 0xb0000400 +#define regi_ccd_stat 0xb0000800 +#define regi_ccd_tg 0xb0001000 +#define regi_cfg 0xb0002000 +#define regi_clkgen 0xb0004000 +#define regi_ddr2_ctrl 0xb0006000 +#define regi_dma0 0xb0008000 +#define regi_dma1 0xb000a000 +#define regi_dma11 0xb000c000 +#define regi_dma2 0xb000e000 +#define regi_dma3 0xb0010000 +#define regi_dma4 0xb0012000 +#define regi_dma5 0xb0014000 +#define regi_dma6 0xb0016000 +#define regi_dma7 0xb0018000 +#define regi_dma9 0xb001a000 +#define regi_eth 0xb001c000 +#define regi_gio 0xb0020000 +#define regi_h264 0xb0022000 +#define regi_hist 0xb0026000 +#define regi_iop 0xb0028000 +#define regi_iop_version 0xb0028000 +#define regi_iop_fifo_in_extra 0xb0028040 +#define regi_iop_fifo_out_extra 0xb0028080 +#define regi_iop_trigger_grp0 0xb00280c0 +#define regi_iop_trigger_grp1 0xb0028100 +#define regi_iop_trigger_grp2 0xb0028140 +#define regi_iop_trigger_grp3 0xb0028180 +#define regi_iop_trigger_grp4 0xb00281c0 +#define regi_iop_trigger_grp5 0xb0028200 +#define regi_iop_trigger_grp6 0xb0028240 +#define regi_iop_trigger_grp7 0xb0028280 +#define regi_iop_crc_par 0xb0028300 +#define regi_iop_dmc_in 0xb0028380 +#define regi_iop_dmc_out 0xb0028400 +#define regi_iop_fifo_in 0xb0028480 +#define regi_iop_fifo_out 0xb0028500 +#define regi_iop_scrc_in 0xb0028580 +#define regi_iop_scrc_out 0xb0028600 +#define regi_iop_timer_grp0 0xb0028680 +#define regi_iop_timer_grp1 0xb0028700 +#define regi_iop_sap_in 0xb0028800 +#define regi_iop_sap_out 0xb0028900 +#define regi_iop_spu 0xb0028a00 +#define regi_iop_sw_cfg 0xb0028b00 +#define regi_iop_sw_cpu 0xb0028c00 +#define regi_iop_sw_mpu 0xb0028d00 +#define regi_iop_sw_spu 0xb0028e00 +#define regi_iop_mpu 0xb0029000 +#define regi_irq 0xb002a000 +#define regi_jpeg 0xb002c000 +#define regi_l2cache 0xb0030000 +#define regi_marb_bar 0xb0032000 +#define regi_marb_bar_bp0 0xb0032140 +#define regi_marb_bar_bp1 0xb0032180 +#define regi_marb_bar_bp2 0xb00321c0 +#define regi_marb_bar_bp3 0xb0032200 +#define regi_marb_foo 0xb0034000 +#define regi_marb_foo_bp0 0xb0034280 +#define regi_marb_foo_bp1 0xb00342c0 +#define regi_marb_foo_bp2 0xb0034300 +#define regi_marb_foo_bp3 0xb0034340 +#define regi_pinmux 0xb0038000 +#define regi_pio 0xb0036000 +#define regi_sclr 0xb003a000 +#define regi_sclr_fifo 0xb003c000 +#define regi_ser0 0xb003e000 +#define regi_ser1 0xb0040000 +#define regi_ser2 0xb0042000 +#define regi_ser3 0xb0044000 +#define regi_ser4 0xb0046000 +#define regi_sser 0xb0048000 +#define regi_strcop 0xb004a000 +#define regi_strdma0 0xb004e000 +#define regi_strdma1 0xb0050000 +#define regi_strdma2 0xb0052000 +#define regi_strdma3 0xb0054000 +#define regi_strdma5 0xb0056000 +#define regi_strmux 0xb004c000 +#define regi_timer0 0xb0058000 +#define regi_timer1 0xb005a000 +#define regi_trace 0xb005c000 +#define regi_vin 0xb005e000 +#define regi_vout 0xb0060000 +#endif /* __reg_map_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h new file mode 100644 index 00000000000..b129e826fc3 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h @@ -0,0 +1,228 @@ +#ifndef __timer_defs_asm_h +#define __timer_defs_asm_h + +/* + * This file is autogenerated from + * file: timer.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_tmr0_div, scope timer, type rw */ +#define reg_timer_rw_tmr0_div_offset 0 + +/* Register r_tmr0_data, scope timer, type r */ +#define reg_timer_r_tmr0_data_offset 4 + +/* Register rw_tmr0_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr0_ctrl___op___lsb 0 +#define reg_timer_rw_tmr0_ctrl___op___width 2 +#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr0_ctrl___freq___width 3 +#define reg_timer_rw_tmr0_ctrl_offset 8 + +/* Register rw_tmr1_div, scope timer, type rw */ +#define reg_timer_rw_tmr1_div_offset 16 + +/* Register r_tmr1_data, scope timer, type r */ +#define reg_timer_r_tmr1_data_offset 20 + +/* Register rw_tmr1_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr1_ctrl___op___lsb 0 +#define reg_timer_rw_tmr1_ctrl___op___width 2 +#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr1_ctrl___freq___width 3 +#define reg_timer_rw_tmr1_ctrl_offset 24 + +/* Register rs_cnt_data, scope timer, type rs */ +#define reg_timer_rs_cnt_data___tmr___lsb 0 +#define reg_timer_rs_cnt_data___tmr___width 24 +#define reg_timer_rs_cnt_data___cnt___lsb 24 +#define reg_timer_rs_cnt_data___cnt___width 8 +#define reg_timer_rs_cnt_data_offset 32 + +/* Register r_cnt_data, scope timer, type r */ +#define reg_timer_r_cnt_data___tmr___lsb 0 +#define reg_timer_r_cnt_data___tmr___width 24 +#define reg_timer_r_cnt_data___cnt___lsb 24 +#define reg_timer_r_cnt_data___cnt___width 8 +#define reg_timer_r_cnt_data_offset 36 + +/* Register rw_cnt_cfg, scope timer, type rw */ +#define reg_timer_rw_cnt_cfg___clk___lsb 0 +#define reg_timer_rw_cnt_cfg___clk___width 2 +#define reg_timer_rw_cnt_cfg_offset 40 + +/* Register rw_trig, scope timer, type rw */ +#define reg_timer_rw_trig_offset 48 + +/* Register rw_trig_cfg, scope timer, type rw */ +#define reg_timer_rw_trig_cfg___tmr___lsb 0 +#define reg_timer_rw_trig_cfg___tmr___width 2 +#define reg_timer_rw_trig_cfg_offset 52 + +/* Register r_time, scope timer, type r */ +#define reg_timer_r_time_offset 56 + +/* Register rw_out, scope timer, type rw */ +#define reg_timer_rw_out___tmr___lsb 0 +#define reg_timer_rw_out___tmr___width 2 +#define reg_timer_rw_out_offset 60 + +/* Register rw_wd_ctrl, scope timer, type rw */ +#define reg_timer_rw_wd_ctrl___cnt___lsb 0 +#define reg_timer_rw_wd_ctrl___cnt___width 8 +#define reg_timer_rw_wd_ctrl___cmd___lsb 8 +#define reg_timer_rw_wd_ctrl___cmd___width 1 +#define reg_timer_rw_wd_ctrl___cmd___bit 8 +#define reg_timer_rw_wd_ctrl___key___lsb 9 +#define reg_timer_rw_wd_ctrl___key___width 7 +#define reg_timer_rw_wd_ctrl_offset 64 + +/* Register r_wd_stat, scope timer, type r */ +#define reg_timer_r_wd_stat___cnt___lsb 0 +#define reg_timer_r_wd_stat___cnt___width 8 +#define reg_timer_r_wd_stat___cmd___lsb 8 +#define reg_timer_r_wd_stat___cmd___width 1 +#define reg_timer_r_wd_stat___cmd___bit 8 +#define reg_timer_r_wd_stat_offset 68 + +/* Register rw_intr_mask, scope timer, type rw */ +#define reg_timer_rw_intr_mask___tmr0___lsb 0 +#define reg_timer_rw_intr_mask___tmr0___width 1 +#define reg_timer_rw_intr_mask___tmr0___bit 0 +#define reg_timer_rw_intr_mask___tmr1___lsb 1 +#define reg_timer_rw_intr_mask___tmr1___width 1 +#define reg_timer_rw_intr_mask___tmr1___bit 1 +#define reg_timer_rw_intr_mask___cnt___lsb 2 +#define reg_timer_rw_intr_mask___cnt___width 1 +#define reg_timer_rw_intr_mask___cnt___bit 2 +#define reg_timer_rw_intr_mask___trig___lsb 3 +#define reg_timer_rw_intr_mask___trig___width 1 +#define reg_timer_rw_intr_mask___trig___bit 3 +#define reg_timer_rw_intr_mask_offset 72 + +/* Register rw_ack_intr, scope timer, type rw */ +#define reg_timer_rw_ack_intr___tmr0___lsb 0 +#define reg_timer_rw_ack_intr___tmr0___width 1 +#define reg_timer_rw_ack_intr___tmr0___bit 0 +#define reg_timer_rw_ack_intr___tmr1___lsb 1 +#define reg_timer_rw_ack_intr___tmr1___width 1 +#define reg_timer_rw_ack_intr___tmr1___bit 1 +#define reg_timer_rw_ack_intr___cnt___lsb 2 +#define reg_timer_rw_ack_intr___cnt___width 1 +#define reg_timer_rw_ack_intr___cnt___bit 2 +#define reg_timer_rw_ack_intr___trig___lsb 3 +#define reg_timer_rw_ack_intr___trig___width 1 +#define reg_timer_rw_ack_intr___trig___bit 3 +#define reg_timer_rw_ack_intr_offset 76 + +/* Register r_intr, scope timer, type r */ +#define reg_timer_r_intr___tmr0___lsb 0 +#define reg_timer_r_intr___tmr0___width 1 +#define reg_timer_r_intr___tmr0___bit 0 +#define reg_timer_r_intr___tmr1___lsb 1 +#define reg_timer_r_intr___tmr1___width 1 +#define reg_timer_r_intr___tmr1___bit 1 +#define reg_timer_r_intr___cnt___lsb 2 +#define reg_timer_r_intr___cnt___width 1 +#define reg_timer_r_intr___cnt___bit 2 +#define reg_timer_r_intr___trig___lsb 3 +#define reg_timer_r_intr___trig___width 1 +#define reg_timer_r_intr___trig___bit 3 +#define reg_timer_r_intr_offset 80 + +/* Register r_masked_intr, scope timer, type r */ +#define reg_timer_r_masked_intr___tmr0___lsb 0 +#define reg_timer_r_masked_intr___tmr0___width 1 +#define reg_timer_r_masked_intr___tmr0___bit 0 +#define reg_timer_r_masked_intr___tmr1___lsb 1 +#define reg_timer_r_masked_intr___tmr1___width 1 +#define reg_timer_r_masked_intr___tmr1___bit 1 +#define reg_timer_r_masked_intr___cnt___lsb 2 +#define reg_timer_r_masked_intr___cnt___width 1 +#define reg_timer_r_masked_intr___cnt___bit 2 +#define reg_timer_r_masked_intr___trig___lsb 3 +#define reg_timer_r_masked_intr___trig___width 1 +#define reg_timer_r_masked_intr___trig___bit 3 +#define reg_timer_r_masked_intr_offset 84 + +/* Register rw_test, scope timer, type rw */ +#define reg_timer_rw_test___dis___lsb 0 +#define reg_timer_rw_test___dis___width 1 +#define reg_timer_rw_test___dis___bit 0 +#define reg_timer_rw_test___en___lsb 1 +#define reg_timer_rw_test___en___width 1 +#define reg_timer_rw_test___en___bit 1 +#define reg_timer_rw_test_offset 88 + + +/* Constants */ +#define regk_timer_ext 0x00000001 +#define regk_timer_f100 0x00000007 +#define regk_timer_f29_493 0x00000004 +#define regk_timer_f32 0x00000005 +#define regk_timer_f32_768 0x00000006 +#define regk_timer_f90 0x00000003 +#define regk_timer_hold 0x00000001 +#define regk_timer_ld 0x00000000 +#define regk_timer_no 0x00000000 +#define regk_timer_off 0x00000000 +#define regk_timer_run 0x00000002 +#define regk_timer_rw_cnt_cfg_default 0x00000000 +#define regk_timer_rw_intr_mask_default 0x00000000 +#define regk_timer_rw_out_default 0x00000000 +#define regk_timer_rw_test_default 0x00000000 +#define regk_timer_rw_tmr0_ctrl_default 0x00000000 +#define regk_timer_rw_tmr1_ctrl_default 0x00000000 +#define regk_timer_rw_trig_cfg_default 0x00000000 +#define regk_timer_start 0x00000001 +#define regk_timer_stop 0x00000000 +#define regk_timer_time 0x00000001 +#define regk_timer_tmr0 0x00000002 +#define regk_timer_tmr1 0x00000003 +#define regk_timer_vclk 0x00000002 +#define regk_timer_yes 0x00000001 +#endif /* __timer_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h new file mode 100644 index 00000000000..c1e9ba93b3a --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h @@ -0,0 +1,159 @@ +#ifndef __clkgen_defs_h +#define __clkgen_defs_h + +/* + * This file is autogenerated from + * file: clkgen.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope clkgen */ + +/* Register r_bootsel, scope clkgen, type r */ +typedef struct { + unsigned int boot_mode : 5; + unsigned int intern_main_clk : 1; + unsigned int extern_usb2_clk : 1; + unsigned int dummy1 : 25; +} reg_clkgen_r_bootsel; +#define REG_RD_ADDR_clkgen_r_bootsel 0 + +/* Register rw_clk_ctrl, scope clkgen, type rw */ +typedef struct { + unsigned int pll : 1; + unsigned int cpu : 1; + unsigned int iop_usb : 1; + unsigned int vin : 1; + unsigned int sclr : 1; + unsigned int h264 : 1; + unsigned int ddr2 : 1; + unsigned int vout_hist : 1; + unsigned int eth : 1; + unsigned int ccd_tg_200 : 1; + unsigned int dma0_1_eth : 1; + unsigned int ccd_tg_100 : 1; + unsigned int jpeg : 1; + unsigned int sser_ser_dma6_7 : 1; + unsigned int strdma0_2_video : 1; + unsigned int dma2_3_strcop : 1; + unsigned int dma4_5_iop : 1; + unsigned int dma9_11 : 1; + unsigned int memarb_bar_ddr : 1; + unsigned int sclr_h264 : 1; + unsigned int dummy1 : 12; +} reg_clkgen_rw_clk_ctrl; +#define REG_RD_ADDR_clkgen_rw_clk_ctrl 4 +#define REG_WR_ADDR_clkgen_rw_clk_ctrl 4 + + +/* Constants */ +enum { + regk_clkgen_eth1000_rx = 0x0000000c, + regk_clkgen_eth1000_tx = 0x0000000e, + regk_clkgen_eth100_rx = 0x0000001d, + regk_clkgen_eth100_rx_half = 0x0000001c, + regk_clkgen_eth100_tx = 0x0000001f, + regk_clkgen_eth100_tx_half = 0x0000001e, + regk_clkgen_nand_3_2 = 0x00000000, + regk_clkgen_nand_3_2_0x30 = 0x00000002, + regk_clkgen_nand_3_2_0x30_pll = 0x00000012, + regk_clkgen_nand_3_2_pll = 0x00000010, + regk_clkgen_nand_3_3 = 0x00000001, + regk_clkgen_nand_3_3_0x30 = 0x00000003, + regk_clkgen_nand_3_3_0x30_pll = 0x00000013, + regk_clkgen_nand_3_3_pll = 0x00000011, + regk_clkgen_nand_4_2 = 0x00000004, + regk_clkgen_nand_4_2_0x30 = 0x00000006, + regk_clkgen_nand_4_2_0x30_pll = 0x00000016, + regk_clkgen_nand_4_2_pll = 0x00000014, + regk_clkgen_nand_4_3 = 0x00000005, + regk_clkgen_nand_4_3_0x30 = 0x00000007, + regk_clkgen_nand_4_3_0x30_pll = 0x00000017, + regk_clkgen_nand_4_3_pll = 0x00000015, + regk_clkgen_nand_5_2 = 0x00000008, + regk_clkgen_nand_5_2_0x30 = 0x0000000a, + regk_clkgen_nand_5_2_0x30_pll = 0x0000001a, + regk_clkgen_nand_5_2_pll = 0x00000018, + regk_clkgen_nand_5_3 = 0x00000009, + regk_clkgen_nand_5_3_0x30 = 0x0000000b, + regk_clkgen_nand_5_3_0x30_pll = 0x0000001b, + regk_clkgen_nand_5_3_pll = 0x00000019, + regk_clkgen_no = 0x00000000, + regk_clkgen_rw_clk_ctrl_default = 0x00000002, + regk_clkgen_ser = 0x0000000d, + regk_clkgen_ser_pll = 0x0000000f, + regk_clkgen_yes = 0x00000001 +}; +#endif /* __clkgen_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h new file mode 100644 index 00000000000..0f30e8bf946 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h @@ -0,0 +1,281 @@ +#ifndef __ddr2_defs_h +#define __ddr2_defs_h + +/* + * This file is autogenerated from + * file: ddr2.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope ddr2 */ + +/* Register rw_cfg, scope ddr2, type rw */ +typedef struct { + unsigned int col_width : 4; + unsigned int nr_banks : 1; + unsigned int bw : 1; + unsigned int nr_ref : 4; + unsigned int ref_interval : 11; + unsigned int odt_ctrl : 2; + unsigned int odt_mem : 1; + unsigned int imp_strength : 1; + unsigned int auto_imp_cal : 1; + unsigned int imp_cal_override : 1; + unsigned int dll_override : 1; + unsigned int dummy1 : 4; +} reg_ddr2_rw_cfg; +#define REG_RD_ADDR_ddr2_rw_cfg 0 +#define REG_WR_ADDR_ddr2_rw_cfg 0 + +/* Register rw_timing, scope ddr2, type rw */ +typedef struct { + unsigned int wr : 3; + unsigned int rcd : 3; + unsigned int rp : 3; + unsigned int ras : 4; + unsigned int rfc : 7; + unsigned int rc : 5; + unsigned int rtp : 2; + unsigned int rtw : 3; + unsigned int wtr : 2; +} reg_ddr2_rw_timing; +#define REG_RD_ADDR_ddr2_rw_timing 4 +#define REG_WR_ADDR_ddr2_rw_timing 4 + +/* Register rw_latency, scope ddr2, type rw */ +typedef struct { + unsigned int cas : 3; + unsigned int additive : 3; + unsigned int dummy1 : 26; +} reg_ddr2_rw_latency; +#define REG_RD_ADDR_ddr2_rw_latency 8 +#define REG_WR_ADDR_ddr2_rw_latency 8 + +/* Register rw_phy_cfg, scope ddr2, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_ddr2_rw_phy_cfg; +#define REG_RD_ADDR_ddr2_rw_phy_cfg 12 +#define REG_WR_ADDR_ddr2_rw_phy_cfg 12 + +/* Register rw_phy_ctrl, scope ddr2, type rw */ +typedef struct { + unsigned int rst : 1; + unsigned int cal_rst : 1; + unsigned int cal_start : 1; + unsigned int dummy1 : 29; +} reg_ddr2_rw_phy_ctrl; +#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16 +#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16 + +/* Register rw_ctrl, scope ddr2, type rw */ +typedef struct { + unsigned int mrs_data : 16; + unsigned int cmd : 8; + unsigned int dummy1 : 8; +} reg_ddr2_rw_ctrl; +#define REG_RD_ADDR_ddr2_rw_ctrl 20 +#define REG_WR_ADDR_ddr2_rw_ctrl 20 + +/* Register rw_pwr_down, scope ddr2, type rw */ +typedef struct { + unsigned int self_ref : 2; + unsigned int phy_en : 1; + unsigned int dummy1 : 29; +} reg_ddr2_rw_pwr_down; +#define REG_RD_ADDR_ddr2_rw_pwr_down 24 +#define REG_WR_ADDR_ddr2_rw_pwr_down 24 + +/* Register r_stat, scope ddr2, type r */ +typedef struct { + unsigned int dll_lock : 1; + unsigned int dll_delay_code : 7; + unsigned int imp_cal_done : 1; + unsigned int imp_cal_fault : 1; + unsigned int cal_imp_pu : 4; + unsigned int cal_imp_pd : 4; + unsigned int dummy1 : 14; +} reg_ddr2_r_stat; +#define REG_RD_ADDR_ddr2_r_stat 28 + +/* Register rw_imp_ctrl, scope ddr2, type rw */ +typedef struct { + unsigned int imp_pu : 4; + unsigned int imp_pd : 4; + unsigned int dummy1 : 24; +} reg_ddr2_rw_imp_ctrl; +#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32 +#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32 + +#define STRIDE_ddr2_rw_dll_ctrl 4 +/* Register rw_dll_ctrl, scope ddr2, type rw */ +typedef struct { + unsigned int mode : 1; + unsigned int clk_delay : 7; + unsigned int dummy1 : 24; +} reg_ddr2_rw_dll_ctrl; +#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36 +#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36 + +#define STRIDE_ddr2_rw_dqs_dll_ctrl 4 +/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ +typedef struct { + unsigned int dqs90_delay : 7; + unsigned int dqs180_delay : 7; + unsigned int dqs270_delay : 7; + unsigned int dqs360_delay : 7; + unsigned int dummy1 : 4; +} reg_ddr2_rw_dqs_dll_ctrl; +#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52 +#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52 + + +/* Constants */ +enum { + regk_ddr2_al0 = 0x00000000, + regk_ddr2_al1 = 0x00000008, + regk_ddr2_al2 = 0x00000010, + regk_ddr2_al3 = 0x00000018, + regk_ddr2_al4 = 0x00000020, + regk_ddr2_auto = 0x00000003, + regk_ddr2_bank4 = 0x00000000, + regk_ddr2_bank8 = 0x00000001, + regk_ddr2_bl4 = 0x00000002, + regk_ddr2_bl8 = 0x00000003, + regk_ddr2_bt_il = 0x00000008, + regk_ddr2_bt_seq = 0x00000000, + regk_ddr2_bw16 = 0x00000001, + regk_ddr2_bw32 = 0x00000000, + regk_ddr2_cas2 = 0x00000020, + regk_ddr2_cas3 = 0x00000030, + regk_ddr2_cas4 = 0x00000040, + regk_ddr2_cas5 = 0x00000050, + regk_ddr2_deselect = 0x000000c0, + regk_ddr2_dic_weak = 0x00000002, + regk_ddr2_direct = 0x00000001, + regk_ddr2_dis = 0x00000000, + regk_ddr2_dll_dis = 0x00000001, + regk_ddr2_dll_en = 0x00000000, + regk_ddr2_dll_rst = 0x00000100, + regk_ddr2_emrs = 0x00000081, + regk_ddr2_emrs2 = 0x00000082, + regk_ddr2_emrs3 = 0x00000083, + regk_ddr2_full = 0x00000001, + regk_ddr2_hi_ref_rate = 0x00000080, + regk_ddr2_mrs = 0x00000080, + regk_ddr2_no = 0x00000000, + regk_ddr2_nop = 0x000000b8, + regk_ddr2_ocd_adj = 0x00000200, + regk_ddr2_ocd_default = 0x00000380, + regk_ddr2_ocd_drive0 = 0x00000100, + regk_ddr2_ocd_drive1 = 0x00000080, + regk_ddr2_ocd_exit = 0x00000000, + regk_ddr2_odt_dis = 0x00000000, + regk_ddr2_offs = 0x00000000, + regk_ddr2_pre = 0x00000090, + regk_ddr2_pre_all = 0x00000400, + regk_ddr2_pwr_down_fast = 0x00000000, + regk_ddr2_pwr_down_slow = 0x00001000, + regk_ddr2_ref = 0x00000088, + regk_ddr2_rtt150 = 0x00000040, + regk_ddr2_rtt50 = 0x00000044, + regk_ddr2_rtt75 = 0x00000004, + regk_ddr2_rw_cfg_default = 0x00186000, + regk_ddr2_rw_dll_ctrl_default = 0x00000000, + regk_ddr2_rw_dll_ctrl_size = 0x00000004, + regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000, + regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004, + regk_ddr2_rw_latency_default = 0x00000000, + regk_ddr2_rw_phy_cfg_default = 0x00000000, + regk_ddr2_rw_pwr_down_default = 0x00000000, + regk_ddr2_rw_timing_default = 0x00000000, + regk_ddr2_s1Gb = 0x0000001a, + regk_ddr2_s256Mb = 0x0000000f, + regk_ddr2_s2Gb = 0x00000027, + regk_ddr2_s4Gb = 0x00000042, + regk_ddr2_s512Mb = 0x00000015, + regk_ddr2_temp0_85 = 0x00000618, + regk_ddr2_temp85_95 = 0x0000030c, + regk_ddr2_term150 = 0x00000002, + regk_ddr2_term50 = 0x00000003, + regk_ddr2_term75 = 0x00000001, + regk_ddr2_test = 0x00000080, + regk_ddr2_weak = 0x00000000, + regk_ddr2_wr2 = 0x00000200, + regk_ddr2_wr3 = 0x00000400, + regk_ddr2_yes = 0x00000001 +}; +#endif /* __ddr2_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h new file mode 100644 index 00000000000..5d88e0db23a --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h @@ -0,0 +1,837 @@ +#ifndef __gio_defs_h +#define __gio_defs_h + +/* + * This file is autogenerated from + * file: gio.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope gio */ + +/* Register r_pa_din, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pa_din; +#define REG_RD_ADDR_gio_r_pa_din 0 + +/* Register rw_pa_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 32; +} reg_gio_rw_pa_dout; +#define REG_RD_ADDR_gio_rw_pa_dout 4 +#define REG_WR_ADDR_gio_rw_pa_dout 4 + +/* Register rw_pa_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 32; +} reg_gio_rw_pa_oe; +#define REG_RD_ADDR_gio_rw_pa_oe 8 +#define REG_WR_ADDR_gio_rw_pa_oe 8 + +/* Register rw_pa_byte0_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte0_dout; +#define REG_RD_ADDR_gio_rw_pa_byte0_dout 12 +#define REG_WR_ADDR_gio_rw_pa_byte0_dout 12 + +/* Register rw_pa_byte0_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte0_oe; +#define REG_RD_ADDR_gio_rw_pa_byte0_oe 16 +#define REG_WR_ADDR_gio_rw_pa_byte0_oe 16 + +/* Register rw_pa_byte1_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte1_dout; +#define REG_RD_ADDR_gio_rw_pa_byte1_dout 20 +#define REG_WR_ADDR_gio_rw_pa_byte1_dout 20 + +/* Register rw_pa_byte1_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte1_oe; +#define REG_RD_ADDR_gio_rw_pa_byte1_oe 24 +#define REG_WR_ADDR_gio_rw_pa_byte1_oe 24 + +/* Register rw_pa_byte2_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte2_dout; +#define REG_RD_ADDR_gio_rw_pa_byte2_dout 28 +#define REG_WR_ADDR_gio_rw_pa_byte2_dout 28 + +/* Register rw_pa_byte2_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte2_oe; +#define REG_RD_ADDR_gio_rw_pa_byte2_oe 32 +#define REG_WR_ADDR_gio_rw_pa_byte2_oe 32 + +/* Register rw_pa_byte3_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte3_dout; +#define REG_RD_ADDR_gio_rw_pa_byte3_dout 36 +#define REG_WR_ADDR_gio_rw_pa_byte3_dout 36 + +/* Register rw_pa_byte3_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte3_oe; +#define REG_RD_ADDR_gio_rw_pa_byte3_oe 40 +#define REG_WR_ADDR_gio_rw_pa_byte3_oe 40 + +/* Register r_pb_din, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pb_din; +#define REG_RD_ADDR_gio_r_pb_din 44 + +/* Register rw_pb_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 32; +} reg_gio_rw_pb_dout; +#define REG_RD_ADDR_gio_rw_pb_dout 48 +#define REG_WR_ADDR_gio_rw_pb_dout 48 + +/* Register rw_pb_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 32; +} reg_gio_rw_pb_oe; +#define REG_RD_ADDR_gio_rw_pb_oe 52 +#define REG_WR_ADDR_gio_rw_pb_oe 52 + +/* Register rw_pb_byte0_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte0_dout; +#define REG_RD_ADDR_gio_rw_pb_byte0_dout 56 +#define REG_WR_ADDR_gio_rw_pb_byte0_dout 56 + +/* Register rw_pb_byte0_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte0_oe; +#define REG_RD_ADDR_gio_rw_pb_byte0_oe 60 +#define REG_WR_ADDR_gio_rw_pb_byte0_oe 60 + +/* Register rw_pb_byte1_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte1_dout; +#define REG_RD_ADDR_gio_rw_pb_byte1_dout 64 +#define REG_WR_ADDR_gio_rw_pb_byte1_dout 64 + +/* Register rw_pb_byte1_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte1_oe; +#define REG_RD_ADDR_gio_rw_pb_byte1_oe 68 +#define REG_WR_ADDR_gio_rw_pb_byte1_oe 68 + +/* Register rw_pb_byte2_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte2_dout; +#define REG_RD_ADDR_gio_rw_pb_byte2_dout 72 +#define REG_WR_ADDR_gio_rw_pb_byte2_dout 72 + +/* Register rw_pb_byte2_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte2_oe; +#define REG_RD_ADDR_gio_rw_pb_byte2_oe 76 +#define REG_WR_ADDR_gio_rw_pb_byte2_oe 76 + +/* Register rw_pb_byte3_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte3_dout; +#define REG_RD_ADDR_gio_rw_pb_byte3_dout 80 +#define REG_WR_ADDR_gio_rw_pb_byte3_dout 80 + +/* Register rw_pb_byte3_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte3_oe; +#define REG_RD_ADDR_gio_rw_pb_byte3_oe 84 +#define REG_WR_ADDR_gio_rw_pb_byte3_oe 84 + +/* Register r_pc_din, scope gio, type r */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_gio_r_pc_din; +#define REG_RD_ADDR_gio_r_pc_din 88 + +/* Register rw_pc_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_gio_rw_pc_dout; +#define REG_RD_ADDR_gio_rw_pc_dout 92 +#define REG_WR_ADDR_gio_rw_pc_dout 92 + +/* Register rw_pc_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 16; + unsigned int dummy1 : 16; +} reg_gio_rw_pc_oe; +#define REG_RD_ADDR_gio_rw_pc_oe 96 +#define REG_WR_ADDR_gio_rw_pc_oe 96 + +/* Register rw_pc_byte0_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pc_byte0_dout; +#define REG_RD_ADDR_gio_rw_pc_byte0_dout 100 +#define REG_WR_ADDR_gio_rw_pc_byte0_dout 100 + +/* Register rw_pc_byte0_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pc_byte0_oe; +#define REG_RD_ADDR_gio_rw_pc_byte0_oe 104 +#define REG_WR_ADDR_gio_rw_pc_byte0_oe 104 + +/* Register rw_pc_byte1_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pc_byte1_dout; +#define REG_RD_ADDR_gio_rw_pc_byte1_dout 108 +#define REG_WR_ADDR_gio_rw_pc_byte1_dout 108 + +/* Register rw_pc_byte1_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pc_byte1_oe; +#define REG_RD_ADDR_gio_rw_pc_byte1_oe 112 +#define REG_WR_ADDR_gio_rw_pc_byte1_oe 112 + +/* Register r_pd_din, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pd_din; +#define REG_RD_ADDR_gio_r_pd_din 116 + +/* Register rw_intr_cfg, scope gio, type rw */ +typedef struct { + unsigned int intr0 : 3; + unsigned int intr1 : 3; + unsigned int intr2 : 3; + unsigned int intr3 : 3; + unsigned int intr4 : 3; + unsigned int intr5 : 3; + unsigned int intr6 : 3; + unsigned int intr7 : 3; + unsigned int dummy1 : 8; +} reg_gio_rw_intr_cfg; +#define REG_RD_ADDR_gio_rw_intr_cfg 120 +#define REG_WR_ADDR_gio_rw_intr_cfg 120 + +/* Register rw_intr_pins, scope gio, type rw */ +typedef struct { + unsigned int intr0 : 4; + unsigned int intr1 : 4; + unsigned int intr2 : 4; + unsigned int intr3 : 4; + unsigned int intr4 : 4; + unsigned int intr5 : 4; + unsigned int intr6 : 4; + unsigned int intr7 : 4; +} reg_gio_rw_intr_pins; +#define REG_RD_ADDR_gio_rw_intr_pins 124 +#define REG_WR_ADDR_gio_rw_intr_pins 124 + +/* Register rw_intr_mask, scope gio, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int i2c0_done : 1; + unsigned int i2c1_done : 1; + unsigned int dummy1 : 22; +} reg_gio_rw_intr_mask; +#define REG_RD_ADDR_gio_rw_intr_mask 128 +#define REG_WR_ADDR_gio_rw_intr_mask 128 + +/* Register rw_ack_intr, scope gio, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int i2c0_done : 1; + unsigned int i2c1_done : 1; + unsigned int dummy1 : 22; +} reg_gio_rw_ack_intr; +#define REG_RD_ADDR_gio_rw_ack_intr 132 +#define REG_WR_ADDR_gio_rw_ack_intr 132 + +/* Register r_intr, scope gio, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int i2c0_done : 1; + unsigned int i2c1_done : 1; + unsigned int dummy1 : 22; +} reg_gio_r_intr; +#define REG_RD_ADDR_gio_r_intr 136 + +/* Register r_masked_intr, scope gio, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int i2c0_done : 1; + unsigned int i2c1_done : 1; + unsigned int dummy1 : 22; +} reg_gio_r_masked_intr; +#define REG_RD_ADDR_gio_r_masked_intr 140 + +/* Register rw_i2c0_start, scope gio, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_gio_rw_i2c0_start; +#define REG_RD_ADDR_gio_rw_i2c0_start 144 +#define REG_WR_ADDR_gio_rw_i2c0_start 144 + +/* Register rw_i2c0_cfg, scope gio, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int bit_order : 1; + unsigned int scl_io : 1; + unsigned int scl_inv : 1; + unsigned int sda_io : 1; + unsigned int sda_idle : 1; + unsigned int dummy1 : 26; +} reg_gio_rw_i2c0_cfg; +#define REG_RD_ADDR_gio_rw_i2c0_cfg 148 +#define REG_WR_ADDR_gio_rw_i2c0_cfg 148 + +/* Register rw_i2c0_ctrl, scope gio, type rw */ +typedef struct { + unsigned int trf_bits : 6; + unsigned int switch_dir : 6; + unsigned int extra_start : 3; + unsigned int early_end : 1; + unsigned int start_stop : 1; + unsigned int ack_dir0 : 1; + unsigned int ack_dir1 : 1; + unsigned int ack_dir2 : 1; + unsigned int ack_dir3 : 1; + unsigned int ack_dir4 : 1; + unsigned int ack_dir5 : 1; + unsigned int ack_bit : 1; + unsigned int start_bit : 1; + unsigned int freq : 2; + unsigned int dummy1 : 5; +} reg_gio_rw_i2c0_ctrl; +#define REG_RD_ADDR_gio_rw_i2c0_ctrl 152 +#define REG_WR_ADDR_gio_rw_i2c0_ctrl 152 + +/* Register rw_i2c0_data, scope gio, type rw */ +typedef struct { + unsigned int data0 : 8; + unsigned int data1 : 8; + unsigned int data2 : 8; + unsigned int data3 : 8; +} reg_gio_rw_i2c0_data; +#define REG_RD_ADDR_gio_rw_i2c0_data 156 +#define REG_WR_ADDR_gio_rw_i2c0_data 156 + +/* Register rw_i2c0_data2, scope gio, type rw */ +typedef struct { + unsigned int data4 : 8; + unsigned int data5 : 8; + unsigned int start_val : 6; + unsigned int ack_val : 6; + unsigned int dummy1 : 4; +} reg_gio_rw_i2c0_data2; +#define REG_RD_ADDR_gio_rw_i2c0_data2 160 +#define REG_WR_ADDR_gio_rw_i2c0_data2 160 + +/* Register rw_i2c1_start, scope gio, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_gio_rw_i2c1_start; +#define REG_RD_ADDR_gio_rw_i2c1_start 164 +#define REG_WR_ADDR_gio_rw_i2c1_start 164 + +/* Register rw_i2c1_cfg, scope gio, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int bit_order : 1; + unsigned int scl_io : 1; + unsigned int scl_inv : 1; + unsigned int sda0_io : 1; + unsigned int sda0_idle : 1; + unsigned int sda1_io : 1; + unsigned int sda1_idle : 1; + unsigned int sda2_io : 1; + unsigned int sda2_idle : 1; + unsigned int sda3_io : 1; + unsigned int sda3_idle : 1; + unsigned int sda_sel : 2; + unsigned int sen_idle : 1; + unsigned int sen_inv : 1; + unsigned int sen_sel : 2; + unsigned int dummy1 : 14; +} reg_gio_rw_i2c1_cfg; +#define REG_RD_ADDR_gio_rw_i2c1_cfg 168 +#define REG_WR_ADDR_gio_rw_i2c1_cfg 168 + +/* Register rw_i2c1_ctrl, scope gio, type rw */ +typedef struct { + unsigned int trf_bits : 6; + unsigned int switch_dir : 6; + unsigned int extra_start : 3; + unsigned int early_end : 1; + unsigned int start_stop : 1; + unsigned int ack_dir0 : 1; + unsigned int ack_dir1 : 1; + unsigned int ack_dir2 : 1; + unsigned int ack_dir3 : 1; + unsigned int ack_dir4 : 1; + unsigned int ack_dir5 : 1; + unsigned int ack_bit : 1; + unsigned int start_bit : 1; + unsigned int freq : 2; + unsigned int dummy1 : 5; +} reg_gio_rw_i2c1_ctrl; +#define REG_RD_ADDR_gio_rw_i2c1_ctrl 172 +#define REG_WR_ADDR_gio_rw_i2c1_ctrl 172 + +/* Register rw_i2c1_data, scope gio, type rw */ +typedef struct { + unsigned int data0 : 8; + unsigned int data1 : 8; + unsigned int data2 : 8; + unsigned int data3 : 8; +} reg_gio_rw_i2c1_data; +#define REG_RD_ADDR_gio_rw_i2c1_data 176 +#define REG_WR_ADDR_gio_rw_i2c1_data 176 + +/* Register rw_i2c1_data2, scope gio, type rw */ +typedef struct { + unsigned int data4 : 8; + unsigned int data5 : 8; + unsigned int start_val : 6; + unsigned int ack_val : 6; + unsigned int dummy1 : 4; +} reg_gio_rw_i2c1_data2; +#define REG_RD_ADDR_gio_rw_i2c1_data2 180 +#define REG_WR_ADDR_gio_rw_i2c1_data2 180 + +/* Register r_ppwm_stat, scope gio, type r */ +typedef struct { + unsigned int freq : 2; + unsigned int dummy1 : 30; +} reg_gio_r_ppwm_stat; +#define REG_RD_ADDR_gio_r_ppwm_stat 184 + +/* Register rw_ppwm_data, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_ppwm_data; +#define REG_RD_ADDR_gio_rw_ppwm_data 188 +#define REG_WR_ADDR_gio_rw_ppwm_data 188 + +/* Register rw_pwm0_ctrl, scope gio, type rw */ +typedef struct { + unsigned int mode : 2; + unsigned int ccd_override : 1; + unsigned int ccd_val : 1; + unsigned int dummy1 : 28; +} reg_gio_rw_pwm0_ctrl; +#define REG_RD_ADDR_gio_rw_pwm0_ctrl 192 +#define REG_WR_ADDR_gio_rw_pwm0_ctrl 192 + +/* Register rw_pwm0_var, scope gio, type rw */ +typedef struct { + unsigned int lo : 13; + unsigned int hi : 13; + unsigned int dummy1 : 6; +} reg_gio_rw_pwm0_var; +#define REG_RD_ADDR_gio_rw_pwm0_var 196 +#define REG_WR_ADDR_gio_rw_pwm0_var 196 + +/* Register rw_pwm0_data, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pwm0_data; +#define REG_RD_ADDR_gio_rw_pwm0_data 200 +#define REG_WR_ADDR_gio_rw_pwm0_data 200 + +/* Register rw_pwm1_ctrl, scope gio, type rw */ +typedef struct { + unsigned int mode : 2; + unsigned int ccd_override : 1; + unsigned int ccd_val : 1; + unsigned int dummy1 : 28; +} reg_gio_rw_pwm1_ctrl; +#define REG_RD_ADDR_gio_rw_pwm1_ctrl 204 +#define REG_WR_ADDR_gio_rw_pwm1_ctrl 204 + +/* Register rw_pwm1_var, scope gio, type rw */ +typedef struct { + unsigned int lo : 13; + unsigned int hi : 13; + unsigned int dummy1 : 6; +} reg_gio_rw_pwm1_var; +#define REG_RD_ADDR_gio_rw_pwm1_var 208 +#define REG_WR_ADDR_gio_rw_pwm1_var 208 + +/* Register rw_pwm1_data, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pwm1_data; +#define REG_RD_ADDR_gio_rw_pwm1_data 212 +#define REG_WR_ADDR_gio_rw_pwm1_data 212 + +/* Register rw_pwm2_ctrl, scope gio, type rw */ +typedef struct { + unsigned int mode : 2; + unsigned int ccd_override : 1; + unsigned int ccd_val : 1; + unsigned int dummy1 : 28; +} reg_gio_rw_pwm2_ctrl; +#define REG_RD_ADDR_gio_rw_pwm2_ctrl 216 +#define REG_WR_ADDR_gio_rw_pwm2_ctrl 216 + +/* Register rw_pwm2_var, scope gio, type rw */ +typedef struct { + unsigned int lo : 13; + unsigned int hi : 13; + unsigned int dummy1 : 6; +} reg_gio_rw_pwm2_var; +#define REG_RD_ADDR_gio_rw_pwm2_var 220 +#define REG_WR_ADDR_gio_rw_pwm2_var 220 + +/* Register rw_pwm2_data, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pwm2_data; +#define REG_RD_ADDR_gio_rw_pwm2_data 224 +#define REG_WR_ADDR_gio_rw_pwm2_data 224 + +/* Register rw_pwm_in_cfg, scope gio, type rw */ +typedef struct { + unsigned int pin : 3; + unsigned int dummy1 : 29; +} reg_gio_rw_pwm_in_cfg; +#define REG_RD_ADDR_gio_rw_pwm_in_cfg 228 +#define REG_WR_ADDR_gio_rw_pwm_in_cfg 228 + +/* Register r_pwm_in_lo, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pwm_in_lo; +#define REG_RD_ADDR_gio_r_pwm_in_lo 232 + +/* Register r_pwm_in_hi, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pwm_in_hi; +#define REG_RD_ADDR_gio_r_pwm_in_hi 236 + +/* Register r_pwm_in_cnt, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pwm_in_cnt; +#define REG_RD_ADDR_gio_r_pwm_in_cnt 240 + + +/* Constants */ +enum { + regk_gio_anyedge = 0x00000007, + regk_gio_f100k = 0x00000000, + regk_gio_f1562 = 0x00000000, + regk_gio_f195 = 0x00000003, + regk_gio_f1m = 0x00000002, + regk_gio_f390 = 0x00000002, + regk_gio_f400k = 0x00000001, + regk_gio_f5m = 0x00000003, + regk_gio_f781 = 0x00000001, + regk_gio_hi = 0x00000001, + regk_gio_in = 0x00000000, + regk_gio_intr_pa0 = 0x00000000, + regk_gio_intr_pa1 = 0x00000000, + regk_gio_intr_pa10 = 0x00000001, + regk_gio_intr_pa11 = 0x00000001, + regk_gio_intr_pa12 = 0x00000001, + regk_gio_intr_pa13 = 0x00000001, + regk_gio_intr_pa14 = 0x00000001, + regk_gio_intr_pa15 = 0x00000001, + regk_gio_intr_pa16 = 0x00000002, + regk_gio_intr_pa17 = 0x00000002, + regk_gio_intr_pa18 = 0x00000002, + regk_gio_intr_pa19 = 0x00000002, + regk_gio_intr_pa2 = 0x00000000, + regk_gio_intr_pa20 = 0x00000002, + regk_gio_intr_pa21 = 0x00000002, + regk_gio_intr_pa22 = 0x00000002, + regk_gio_intr_pa23 = 0x00000002, + regk_gio_intr_pa24 = 0x00000003, + regk_gio_intr_pa25 = 0x00000003, + regk_gio_intr_pa26 = 0x00000003, + regk_gio_intr_pa27 = 0x00000003, + regk_gio_intr_pa28 = 0x00000003, + regk_gio_intr_pa29 = 0x00000003, + regk_gio_intr_pa3 = 0x00000000, + regk_gio_intr_pa30 = 0x00000003, + regk_gio_intr_pa31 = 0x00000003, + regk_gio_intr_pa4 = 0x00000000, + regk_gio_intr_pa5 = 0x00000000, + regk_gio_intr_pa6 = 0x00000000, + regk_gio_intr_pa7 = 0x00000000, + regk_gio_intr_pa8 = 0x00000001, + regk_gio_intr_pa9 = 0x00000001, + regk_gio_intr_pb0 = 0x00000004, + regk_gio_intr_pb1 = 0x00000004, + regk_gio_intr_pb10 = 0x00000005, + regk_gio_intr_pb11 = 0x00000005, + regk_gio_intr_pb12 = 0x00000005, + regk_gio_intr_pb13 = 0x00000005, + regk_gio_intr_pb14 = 0x00000005, + regk_gio_intr_pb15 = 0x00000005, + regk_gio_intr_pb16 = 0x00000006, + regk_gio_intr_pb17 = 0x00000006, + regk_gio_intr_pb18 = 0x00000006, + regk_gio_intr_pb19 = 0x00000006, + regk_gio_intr_pb2 = 0x00000004, + regk_gio_intr_pb20 = 0x00000006, + regk_gio_intr_pb21 = 0x00000006, + regk_gio_intr_pb22 = 0x00000006, + regk_gio_intr_pb23 = 0x00000006, + regk_gio_intr_pb24 = 0x00000007, + regk_gio_intr_pb25 = 0x00000007, + regk_gio_intr_pb26 = 0x00000007, + regk_gio_intr_pb27 = 0x00000007, + regk_gio_intr_pb28 = 0x00000007, + regk_gio_intr_pb29 = 0x00000007, + regk_gio_intr_pb3 = 0x00000004, + regk_gio_intr_pb30 = 0x00000007, + regk_gio_intr_pb31 = 0x00000007, + regk_gio_intr_pb4 = 0x00000004, + regk_gio_intr_pb5 = 0x00000004, + regk_gio_intr_pb6 = 0x00000004, + regk_gio_intr_pb7 = 0x00000004, + regk_gio_intr_pb8 = 0x00000005, + regk_gio_intr_pb9 = 0x00000005, + regk_gio_intr_pc0 = 0x00000008, + regk_gio_intr_pc1 = 0x00000008, + regk_gio_intr_pc10 = 0x00000009, + regk_gio_intr_pc11 = 0x00000009, + regk_gio_intr_pc12 = 0x00000009, + regk_gio_intr_pc13 = 0x00000009, + regk_gio_intr_pc14 = 0x00000009, + regk_gio_intr_pc15 = 0x00000009, + regk_gio_intr_pc2 = 0x00000008, + regk_gio_intr_pc3 = 0x00000008, + regk_gio_intr_pc4 = 0x00000008, + regk_gio_intr_pc5 = 0x00000008, + regk_gio_intr_pc6 = 0x00000008, + regk_gio_intr_pc7 = 0x00000008, + regk_gio_intr_pc8 = 0x00000009, + regk_gio_intr_pc9 = 0x00000009, + regk_gio_intr_pd0 = 0x0000000c, + regk_gio_intr_pd1 = 0x0000000c, + regk_gio_intr_pd10 = 0x0000000d, + regk_gio_intr_pd11 = 0x0000000d, + regk_gio_intr_pd12 = 0x0000000d, + regk_gio_intr_pd13 = 0x0000000d, + regk_gio_intr_pd14 = 0x0000000d, + regk_gio_intr_pd15 = 0x0000000d, + regk_gio_intr_pd16 = 0x0000000e, + regk_gio_intr_pd17 = 0x0000000e, + regk_gio_intr_pd18 = 0x0000000e, + regk_gio_intr_pd19 = 0x0000000e, + regk_gio_intr_pd2 = 0x0000000c, + regk_gio_intr_pd20 = 0x0000000e, + regk_gio_intr_pd21 = 0x0000000e, + regk_gio_intr_pd22 = 0x0000000e, + regk_gio_intr_pd23 = 0x0000000e, + regk_gio_intr_pd24 = 0x0000000f, + regk_gio_intr_pd25 = 0x0000000f, + regk_gio_intr_pd26 = 0x0000000f, + regk_gio_intr_pd27 = 0x0000000f, + regk_gio_intr_pd28 = 0x0000000f, + regk_gio_intr_pd29 = 0x0000000f, + regk_gio_intr_pd3 = 0x0000000c, + regk_gio_intr_pd30 = 0x0000000f, + regk_gio_intr_pd31 = 0x0000000f, + regk_gio_intr_pd4 = 0x0000000c, + regk_gio_intr_pd5 = 0x0000000c, + regk_gio_intr_pd6 = 0x0000000c, + regk_gio_intr_pd7 = 0x0000000c, + regk_gio_intr_pd8 = 0x0000000d, + regk_gio_intr_pd9 = 0x0000000d, + regk_gio_lo = 0x00000002, + regk_gio_lsb = 0x00000000, + regk_gio_msb = 0x00000001, + regk_gio_negedge = 0x00000006, + regk_gio_no = 0x00000000, + regk_gio_no_switch = 0x0000003f, + regk_gio_none = 0x00000007, + regk_gio_off = 0x00000000, + regk_gio_opendrain = 0x00000000, + regk_gio_out = 0x00000001, + regk_gio_posedge = 0x00000005, + regk_gio_pwm_hfp = 0x00000002, + regk_gio_pwm_pa0 = 0x00000001, + regk_gio_pwm_pa19 = 0x00000004, + regk_gio_pwm_pa6 = 0x00000002, + regk_gio_pwm_pa7 = 0x00000003, + regk_gio_pwm_pb26 = 0x00000005, + regk_gio_pwm_pd23 = 0x00000006, + regk_gio_pwm_pd31 = 0x00000007, + regk_gio_pwm_std = 0x00000001, + regk_gio_pwm_var = 0x00000003, + regk_gio_rw_i2c0_cfg_default = 0x00000020, + regk_gio_rw_i2c0_ctrl_default = 0x00010000, + regk_gio_rw_i2c0_start_default = 0x00000000, + regk_gio_rw_i2c1_cfg_default = 0x00000aa0, + regk_gio_rw_i2c1_ctrl_default = 0x00010000, + regk_gio_rw_i2c1_start_default = 0x00000000, + regk_gio_rw_intr_cfg_default = 0x00000000, + regk_gio_rw_intr_mask_default = 0x00000000, + regk_gio_rw_pa_oe_default = 0x00000000, + regk_gio_rw_pb_oe_default = 0x00000000, + regk_gio_rw_pc_oe_default = 0x00000000, + regk_gio_rw_ppwm_data_default = 0x00000000, + regk_gio_rw_pwm0_ctrl_default = 0x00000000, + regk_gio_rw_pwm1_ctrl_default = 0x00000000, + regk_gio_rw_pwm2_ctrl_default = 0x00000000, + regk_gio_rw_pwm_in_cfg_default = 0x00000000, + regk_gio_sda0 = 0x00000000, + regk_gio_sda1 = 0x00000001, + regk_gio_sda2 = 0x00000002, + regk_gio_sda3 = 0x00000003, + regk_gio_sen = 0x00000000, + regk_gio_set = 0x00000003, + regk_gio_yes = 0x00000001 +}; +#endif /* __gio_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h new file mode 100644 index 00000000000..bea699aa480 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h @@ -0,0 +1,46 @@ +/* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr + from intr_vect.r */ + +#ifndef _INTR_VECT_R +#define _INTR_VECT_R +#define TIMER0_INTR_VECT 0x31 +#define TIMER1_INTR_VECT 0x32 +#define DMA0_INTR_VECT 0x33 +#define DMA1_INTR_VECT 0x34 +#define DMA2_INTR_VECT 0x35 +#define DMA3_INTR_VECT 0x36 +#define DMA4_INTR_VECT 0x37 +#define DMA5_INTR_VECT 0x38 +#define DMA6_INTR_VECT 0x39 +#define DMA7_INTR_VECT 0x3a +#define DMA9_INTR_VECT 0x3b +#define DMA11_INTR_VECT 0x3c +#define GIO_INTR_VECT 0x3d +#define IOP0_INTR_VECT 0x3e +#define IOP1_INTR_VECT 0x3f +#define SER0_INTR_VECT 0x40 +#define SER1_INTR_VECT 0x41 +#define SER2_INTR_VECT 0x42 +#define SER3_INTR_VECT 0x43 +#define SER4_INTR_VECT 0x44 +#define SSER_INTR_VECT 0x45 +#define STRDMA0_INTR_VECT 0x46 +#define STRDMA1_INTR_VECT 0x47 +#define STRDMA2_INTR_VECT 0x48 +#define STRDMA3_INTR_VECT 0x49 +#define STRDMA5_INTR_VECT 0x4a +#define VIN_INTR_VECT 0x4b +#define VOUT_INTR_VECT 0x4c +#define JPEG_INTR_VECT 0x4d +#define H264_INTR_VECT 0x4e +#define HISTO_INTR_VECT 0x4f +#define CCD_INTR_VECT 0x50 +#define ETH_INTR_VECT 0x51 +#define MEMARB_BAR_INTR_VECT 0x52 +#define MEMARB_FOO_INTR_VECT 0x53 +#define PIO_INTR_VECT 0x54 +#define SCLR_INTR_VECT 0x55 +#define SCLR_FIFO_INTR_VECT 0x56 +#define IPI_INTR_VECT 0x57 +#define NBR_INTR_VECT 0x58 +#endif diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h new file mode 100644 index 00000000000..b820f6347c7 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h @@ -0,0 +1,341 @@ +#ifndef __intr_vect_defs_h +#define __intr_vect_defs_h + +/* + * This file is autogenerated from + * file: intr_vect.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope intr_vect */ + + +#define STRIDE_intr_vect_rw_mask 4 +/* Register rw_mask0, scope intr_vect, type rw */ +typedef struct { + unsigned int timer0 : 1; + unsigned int timer1 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int gio : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int ser4 : 1; + unsigned int sser : 1; + unsigned int strdma0 : 1; + unsigned int strdma1 : 1; + unsigned int strdma2 : 1; + unsigned int strdma3 : 1; + unsigned int strdma5 : 1; + unsigned int vin : 1; + unsigned int vout : 1; + unsigned int jpeg : 1; + unsigned int h264 : 1; + unsigned int histo : 1; + unsigned int ccd : 1; +} reg_intr_vect_rw_mask0; +#define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0 +#define REG_RD_ADDR_intr_vect_rw_mask 0 +#define REG_WR_ADDR_intr_vect_rw_mask 0 +#define REG_RD_ADDR_intr_vect_rw_mask0 0 +#define REG_WR_ADDR_intr_vect_rw_mask0 0 + +#define STRIDE_intr_vect_r_vect 4 +/* Register r_vect0, scope intr_vect, type r */ +typedef struct { + unsigned int timer0 : 1; + unsigned int timer1 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int gio : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int ser4 : 1; + unsigned int sser : 1; + unsigned int strdma0 : 1; + unsigned int strdma1 : 1; + unsigned int strdma2 : 1; + unsigned int strdma3 : 1; + unsigned int strdma5 : 1; + unsigned int vin : 1; + unsigned int vout : 1; + unsigned int jpeg : 1; + unsigned int h264 : 1; + unsigned int histo : 1; + unsigned int ccd : 1; +} reg_intr_vect_r_vect0; +#define reg_intr_vect_r_vect reg_intr_vect_r_vect0 +#define REG_RD_ADDR_intr_vect_r_vect 8 +#define REG_RD_ADDR_intr_vect_r_vect0 8 + +#define STRIDE_intr_vect_r_masked_vect 4 +/* Register r_masked_vect0, scope intr_vect, type r */ +typedef struct { + unsigned int timer0 : 1; + unsigned int timer1 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int gio : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int ser4 : 1; + unsigned int sser : 1; + unsigned int strdma0 : 1; + unsigned int strdma1 : 1; + unsigned int strdma2 : 1; + unsigned int strdma3 : 1; + unsigned int strdma5 : 1; + unsigned int vin : 1; + unsigned int vout : 1; + unsigned int jpeg : 1; + unsigned int h264 : 1; + unsigned int histo : 1; + unsigned int ccd : 1; +} reg_intr_vect_r_masked_vect0; +#define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0 +#define REG_RD_ADDR_intr_vect_r_masked_vect0 16 +#define REG_RD_ADDR_intr_vect_r_masked_vect 16 + +#define STRIDE_intr_vect_rw_xmask 4 +/* Register rw_xmask0, scope intr_vect, type rw */ +typedef struct { + unsigned int timer0 : 1; + unsigned int timer1 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int gio : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int ser4 : 1; + unsigned int sser : 1; + unsigned int strdma0 : 1; + unsigned int strdma1 : 1; + unsigned int strdma2 : 1; + unsigned int strdma3 : 1; + unsigned int strdma5 : 1; + unsigned int vin : 1; + unsigned int vout : 1; + unsigned int jpeg : 1; + unsigned int h264 : 1; + unsigned int histo : 1; + unsigned int ccd : 1; +} reg_intr_vect_rw_xmask0; +#define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0 +#define REG_RD_ADDR_intr_vect_rw_xmask0 24 +#define REG_WR_ADDR_intr_vect_rw_xmask0 24 +#define REG_RD_ADDR_intr_vect_rw_xmask 24 +#define REG_WR_ADDR_intr_vect_rw_xmask 24 + +/* Register rw_mask1, scope intr_vect, type rw */ +typedef struct { + unsigned int eth : 1; + unsigned int memarb_bar : 1; + unsigned int memarb_foo : 1; + unsigned int pio : 1; + unsigned int sclr : 1; + unsigned int sclr_fifo : 1; + unsigned int dummy1 : 26; +} reg_intr_vect_rw_mask1; +#define REG_RD_ADDR_intr_vect_rw_mask1 4 +#define REG_WR_ADDR_intr_vect_rw_mask1 4 + +/* Register r_vect1, scope intr_vect, type r */ +typedef struct { + unsigned int eth : 1; + unsigned int memarb_bar : 1; + unsigned int memarb_foo : 1; + unsigned int pio : 1; + unsigned int sclr : 1; + unsigned int sclr_fifo : 1; + unsigned int dummy1 : 26; +} reg_intr_vect_r_vect1; +#define REG_RD_ADDR_intr_vect_r_vect1 12 + +/* Register r_masked_vect1, scope intr_vect, type r */ +typedef struct { + unsigned int eth : 1; + unsigned int memarb_bar : 1; + unsigned int memarb_foo : 1; + unsigned int pio : 1; + unsigned int sclr : 1; + unsigned int sclr_fifo : 1; + unsigned int dummy1 : 26; +} reg_intr_vect_r_masked_vect1; +#define REG_RD_ADDR_intr_vect_r_masked_vect1 20 + +/* Register rw_xmask1, scope intr_vect, type rw */ +typedef struct { + unsigned int eth : 1; + unsigned int memarb_bar : 1; + unsigned int memarb_foo : 1; + unsigned int pio : 1; + unsigned int sclr : 1; + unsigned int sclr_fifo : 1; + unsigned int dummy1 : 26; +} reg_intr_vect_rw_xmask1; +#define REG_RD_ADDR_intr_vect_rw_xmask1 28 +#define REG_WR_ADDR_intr_vect_rw_xmask1 28 + +/* Register rw_xmask_ctrl, scope intr_vect, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_intr_vect_rw_xmask_ctrl; +#define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32 +#define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32 + +/* Register r_nmi, scope intr_vect, type r */ +typedef struct { + unsigned int watchdog0 : 1; + unsigned int watchdog1 : 1; + unsigned int dummy1 : 30; +} reg_intr_vect_r_nmi; +#define REG_RD_ADDR_intr_vect_r_nmi 64 + +/* Register r_guru, scope intr_vect, type r */ +typedef struct { + unsigned int jtag : 1; + unsigned int dummy1 : 31; +} reg_intr_vect_r_guru; +#define REG_RD_ADDR_intr_vect_r_guru 68 + + +/* Register rw_ipi, scope intr_vect, type rw */ +typedef struct +{ + unsigned int vector; +} reg_intr_vect_rw_ipi; +#define REG_RD_ADDR_intr_vect_rw_ipi 72 +#define REG_WR_ADDR_intr_vect_rw_ipi 72 + +/* Constants */ +enum { + regk_intr_vect_no = 0x00000000, + regk_intr_vect_rw_mask0_default = 0x00000000, + regk_intr_vect_rw_mask1_default = 0x00000000, + regk_intr_vect_rw_xmask0_default = 0x00000000, + regk_intr_vect_rw_xmask1_default = 0x00000000, + regk_intr_vect_rw_xmask_ctrl_default = 0x00000000, + regk_intr_vect_yes = 0x00000001 +}; +#endif /* __intr_vect_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h new file mode 100644 index 00000000000..d75a74e9045 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h @@ -0,0 +1,31 @@ +/* Autogenerated Changes here will be lost! + * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg + */ +#define iop_version 0 +#define iop_fifo_in_extra 64 +#define iop_fifo_out_extra 128 +#define iop_trigger_grp0 192 +#define iop_trigger_grp1 256 +#define iop_trigger_grp2 320 +#define iop_trigger_grp3 384 +#define iop_trigger_grp4 448 +#define iop_trigger_grp5 512 +#define iop_trigger_grp6 576 +#define iop_trigger_grp7 640 +#define iop_crc_par 768 +#define iop_dmc_in 896 +#define iop_dmc_out 1024 +#define iop_fifo_in 1152 +#define iop_fifo_out 1280 +#define iop_scrc_in 1408 +#define iop_scrc_out 1536 +#define iop_timer_grp0 1664 +#define iop_timer_grp1 1792 +#define iop_sap_in 2048 +#define iop_sap_out 2304 +#define iop_spu 2560 +#define iop_sw_cfg 2816 +#define iop_sw_cpu 3072 +#define iop_sw_mpu 3328 +#define iop_sw_spu 3584 +#define iop_mpu 4096 diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h new file mode 100644 index 00000000000..7f90b5a0460 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h @@ -0,0 +1,109 @@ +#ifndef __iop_sap_in_defs_asm_h +#define __iop_sap_in_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sap_in.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +#define STRIDE_iop_sap_in_rw_bus_byte 4 +/* Register rw_bus_byte, scope iop_sap_in, type rw */ +#define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0 +#define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2 +#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2 +#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3 +#define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5 +#define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2 +#define reg_iop_sap_in_rw_bus_byte___delay___lsb 7 +#define reg_iop_sap_in_rw_bus_byte___delay___width 2 +#define reg_iop_sap_in_rw_bus_byte_offset 0 + +#define STRIDE_iop_sap_in_rw_gio 4 +/* Register rw_gio, scope iop_sap_in, type rw */ +#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 +#define reg_iop_sap_in_rw_gio___sync_sel___width 2 +#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 +#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 +#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 +#define reg_iop_sap_in_rw_gio___sync_edge___width 2 +#define reg_iop_sap_in_rw_gio___delay___lsb 7 +#define reg_iop_sap_in_rw_gio___delay___width 2 +#define reg_iop_sap_in_rw_gio___logic___lsb 9 +#define reg_iop_sap_in_rw_gio___logic___width 2 +#define reg_iop_sap_in_rw_gio_offset 16 + + +/* Constants */ +#define regk_iop_sap_in_and 0x00000002 +#define regk_iop_sap_in_ext_clk200 0x00000003 +#define regk_iop_sap_in_gio0 0x00000000 +#define regk_iop_sap_in_gio12 0x00000003 +#define regk_iop_sap_in_gio16 0x00000004 +#define regk_iop_sap_in_gio20 0x00000005 +#define regk_iop_sap_in_gio24 0x00000006 +#define regk_iop_sap_in_gio28 0x00000007 +#define regk_iop_sap_in_gio4 0x00000001 +#define regk_iop_sap_in_gio8 0x00000002 +#define regk_iop_sap_in_inv 0x00000001 +#define regk_iop_sap_in_neg 0x00000002 +#define regk_iop_sap_in_no 0x00000000 +#define regk_iop_sap_in_no_del_ext_clk200 0x00000002 +#define regk_iop_sap_in_none 0x00000000 +#define regk_iop_sap_in_one 0x00000001 +#define regk_iop_sap_in_or 0x00000003 +#define regk_iop_sap_in_pos 0x00000001 +#define regk_iop_sap_in_pos_neg 0x00000003 +#define regk_iop_sap_in_rw_bus_byte_default 0x00000000 +#define regk_iop_sap_in_rw_bus_byte_size 0x00000004 +#define regk_iop_sap_in_rw_gio_default 0x00000000 +#define regk_iop_sap_in_rw_gio_size 0x00000020 +#define regk_iop_sap_in_timer_grp0_tmr3 0x00000000 +#define regk_iop_sap_in_timer_grp1_tmr3 0x00000001 +#define regk_iop_sap_in_tmr_clk200 0x00000001 +#define regk_iop_sap_in_two 0x00000002 +#define regk_iop_sap_in_two_clk200 0x00000000 +#endif /* __iop_sap_in_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h new file mode 100644 index 00000000000..399bd656406 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h @@ -0,0 +1,276 @@ +#ifndef __iop_sap_out_defs_asm_h +#define __iop_sap_out_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sap_out.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_gen_gated, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 +#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 +#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 +#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 +#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 +#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated_offset 0 + +/* Register rw_bus, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2 +#define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4 +#define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4 +#define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5 +#define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5 +#define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6 +#define reg_iop_sap_out_rw_bus___byte0_delay___width 1 +#define reg_iop_sap_out_rw_bus___byte0_delay___bit 6 +#define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7 +#define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9 +#define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11 +#define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11 +#define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12 +#define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12 +#define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13 +#define reg_iop_sap_out_rw_bus___byte1_delay___width 1 +#define reg_iop_sap_out_rw_bus___byte1_delay___bit 13 +#define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14 +#define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16 +#define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18 +#define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18 +#define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19 +#define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20 +#define reg_iop_sap_out_rw_bus___byte2_delay___width 1 +#define reg_iop_sap_out_rw_bus___byte2_delay___bit 20 +#define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21 +#define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23 +#define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25 +#define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25 +#define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26 +#define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26 +#define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27 +#define reg_iop_sap_out_rw_bus___byte3_delay___width 1 +#define reg_iop_sap_out_rw_bus___byte3_delay___bit 27 +#define reg_iop_sap_out_rw_bus_offset 4 + +/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe_offset 8 + +/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe_offset 12 + +#define STRIDE_iop_sap_out_rw_gio 4 +/* Register rw_gio, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 +#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_gio___out_clk_ext___width 2 +#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5 +#define reg_iop_sap_out_rw_gio___out_gated_clk___width 1 +#define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5 +#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6 +#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 +#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6 +#define reg_iop_sap_out_rw_gio___out_delay___lsb 7 +#define reg_iop_sap_out_rw_gio___out_delay___width 1 +#define reg_iop_sap_out_rw_gio___out_delay___bit 7 +#define reg_iop_sap_out_rw_gio___out_logic___lsb 8 +#define reg_iop_sap_out_rw_gio___out_logic___width 2 +#define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10 +#define reg_iop_sap_out_rw_gio___out_logic_src___width 2 +#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12 +#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 +#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15 +#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2 +#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1 +#define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18 +#define reg_iop_sap_out_rw_gio___oe_delay___lsb 19 +#define reg_iop_sap_out_rw_gio___oe_delay___width 1 +#define reg_iop_sap_out_rw_gio___oe_delay___bit 19 +#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 +#define reg_iop_sap_out_rw_gio___oe_logic___width 2 +#define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22 +#define reg_iop_sap_out_rw_gio___oe_logic_src___width 2 +#define reg_iop_sap_out_rw_gio_offset 16 + + +/* Constants */ +#define regk_iop_sap_out_always 0x00000001 +#define regk_iop_sap_out_and 0x00000002 +#define regk_iop_sap_out_clk0 0x00000000 +#define regk_iop_sap_out_clk1 0x00000001 +#define regk_iop_sap_out_clk12 0x00000004 +#define regk_iop_sap_out_clk200 0x00000000 +#define regk_iop_sap_out_ext 0x00000002 +#define regk_iop_sap_out_gated 0x00000003 +#define regk_iop_sap_out_gio0 0x00000000 +#define regk_iop_sap_out_gio1 0x00000000 +#define regk_iop_sap_out_gio16 0x00000002 +#define regk_iop_sap_out_gio17 0x00000002 +#define regk_iop_sap_out_gio24 0x00000003 +#define regk_iop_sap_out_gio25 0x00000003 +#define regk_iop_sap_out_gio8 0x00000001 +#define regk_iop_sap_out_gio9 0x00000001 +#define regk_iop_sap_out_gio_out10 0x00000005 +#define regk_iop_sap_out_gio_out18 0x00000006 +#define regk_iop_sap_out_gio_out2 0x00000004 +#define regk_iop_sap_out_gio_out26 0x00000007 +#define regk_iop_sap_out_inv 0x00000001 +#define regk_iop_sap_out_nand 0x00000003 +#define regk_iop_sap_out_no 0x00000000 +#define regk_iop_sap_out_none 0x00000000 +#define regk_iop_sap_out_one 0x00000001 +#define regk_iop_sap_out_rw_bus_default 0x00000000 +#define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000 +#define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000 +#define regk_iop_sap_out_rw_gen_gated_default 0x00000000 +#define regk_iop_sap_out_rw_gio_default 0x00000000 +#define regk_iop_sap_out_rw_gio_size 0x00000020 +#define regk_iop_sap_out_spu_gio6 0x00000002 +#define regk_iop_sap_out_spu_gio7 0x00000003 +#define regk_iop_sap_out_timer_grp0_tmr2 0x00000000 +#define regk_iop_sap_out_timer_grp0_tmr3 0x00000001 +#define regk_iop_sap_out_timer_grp1_tmr2 0x00000002 +#define regk_iop_sap_out_timer_grp1_tmr3 0x00000003 +#define regk_iop_sap_out_tmr200 0x00000001 +#define regk_iop_sap_out_yes 0x00000001 +#endif /* __iop_sap_out_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h new file mode 100644 index 00000000000..3b3949b51a6 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h @@ -0,0 +1,739 @@ +#ifndef __iop_sw_cfg_defs_asm_h +#define __iop_sw_cfg_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sw_cfg.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_crc_par_owner_offset 0 + +/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4 + +/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8 + +/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12 + +/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16 + +/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20 + +/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24 + +/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_sap_in_owner_offset 28 + +/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_sap_out_owner_offset 32 + +/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36 + +/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40 + +/* Register rw_spu_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1 +#define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0 +#define reg_iop_sw_cfg_rw_spu_owner_offset 44 + +/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48 + +/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52 + +/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56 + +/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60 + +/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64 + +/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68 + +/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72 + +/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76 + +/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80 + +/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84 + +/* Register rw_bus_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8 +#define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8 +#define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8 +#define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16 +#define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8 +#define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24 +#define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8 +#define reg_iop_sw_cfg_rw_bus_mask_offset 88 + +/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3 +#define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92 + +/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 +#define reg_iop_sw_cfg_rw_gio_mask___val___width 32 +#define reg_iop_sw_cfg_rw_gio_mask_offset 96 + +/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 +#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 +#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100 + +/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8 +#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10 +#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12 +#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14 +#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16 +#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18 +#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20 +#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22 +#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 +#define reg_iop_sw_cfg_rw_pinmapping_offset 104 + +/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2 +#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108 + +/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112 + +/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116 + +/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120 + +/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124 + +/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128 + +/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132 + +/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136 + +/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140 + +/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0 +#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1 +#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0 +#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1 +#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1 +#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1 +#define reg_iop_sw_cfg_rw_spu_cfg_offset 144 + +/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148 + +/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152 + +/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156 + +/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0 +#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4 +#define reg_iop_sw_cfg_rw_pdp_cfg_offset 160 + +/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg_offset 164 + + +/* Constants */ +#define regk_iop_sw_cfg_a 0x00000001 +#define regk_iop_sw_cfg_b 0x00000002 +#define regk_iop_sw_cfg_bus 0x00000000 +#define regk_iop_sw_cfg_bus_rot16 0x00000002 +#define regk_iop_sw_cfg_bus_rot24 0x00000003 +#define regk_iop_sw_cfg_bus_rot8 0x00000001 +#define regk_iop_sw_cfg_clk12 0x00000000 +#define regk_iop_sw_cfg_cpu 0x00000000 +#define regk_iop_sw_cfg_gated_clk0 0x0000000e +#define regk_iop_sw_cfg_gated_clk1 0x0000000f +#define regk_iop_sw_cfg_gio0 0x00000004 +#define regk_iop_sw_cfg_gio1 0x00000001 +#define regk_iop_sw_cfg_gio2 0x00000005 +#define regk_iop_sw_cfg_gio3 0x00000002 +#define regk_iop_sw_cfg_gio4 0x00000006 +#define regk_iop_sw_cfg_gio5 0x00000003 +#define regk_iop_sw_cfg_gio6 0x00000007 +#define regk_iop_sw_cfg_gio7 0x00000004 +#define regk_iop_sw_cfg_gio_in18 0x00000002 +#define regk_iop_sw_cfg_gio_in19 0x00000003 +#define regk_iop_sw_cfg_gio_in20 0x00000004 +#define regk_iop_sw_cfg_gio_in21 0x00000005 +#define regk_iop_sw_cfg_gio_in26 0x00000006 +#define regk_iop_sw_cfg_gio_in27 0x00000007 +#define regk_iop_sw_cfg_gio_in4 0x00000000 +#define regk_iop_sw_cfg_gio_in5 0x00000001 +#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 +#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002 +#define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003 +#define regk_iop_sw_cfg_mpu 0x00000001 +#define regk_iop_sw_cfg_none 0x00000000 +#define regk_iop_sw_cfg_pdp_out 0x00000001 +#define regk_iop_sw_cfg_pdp_out_hi 0x00000001 +#define regk_iop_sw_cfg_pdp_out_lo 0x00000000 +#define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555 +#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 +#define regk_iop_sw_cfg_sdp_out 0x00000004 +#define regk_iop_sw_cfg_size16 0x00000002 +#define regk_iop_sw_cfg_size24 0x00000003 +#define regk_iop_sw_cfg_size32 0x00000004 +#define regk_iop_sw_cfg_size8 0x00000001 +#define regk_iop_sw_cfg_spu 0x00000002 +#define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002 +#define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002 +#define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003 +#define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003 +#define regk_iop_sw_cfg_spu_g0 0x00000007 +#define regk_iop_sw_cfg_spu_g1 0x00000007 +#define regk_iop_sw_cfg_spu_g2 0x00000007 +#define regk_iop_sw_cfg_spu_g3 0x00000007 +#define regk_iop_sw_cfg_spu_g4 0x00000007 +#define regk_iop_sw_cfg_spu_g5 0x00000007 +#define regk_iop_sw_cfg_spu_g6 0x00000007 +#define regk_iop_sw_cfg_spu_g7 0x00000007 +#define regk_iop_sw_cfg_spu_gio0 0x00000000 +#define regk_iop_sw_cfg_spu_gio1 0x00000001 +#define regk_iop_sw_cfg_spu_gio5 0x00000005 +#define regk_iop_sw_cfg_spu_gio6 0x00000006 +#define regk_iop_sw_cfg_spu_gio7 0x00000007 +#define regk_iop_sw_cfg_spu_gio_out0 0x00000008 +#define regk_iop_sw_cfg_spu_gio_out1 0x00000009 +#define regk_iop_sw_cfg_spu_gio_out2 0x0000000a +#define regk_iop_sw_cfg_spu_gio_out3 0x0000000b +#define regk_iop_sw_cfg_spu_gio_out4 0x0000000c +#define regk_iop_sw_cfg_spu_gio_out5 0x0000000d +#define regk_iop_sw_cfg_spu_gio_out6 0x0000000e +#define regk_iop_sw_cfg_spu_gio_out7 0x0000000f +#define regk_iop_sw_cfg_spu_gioout0 0x00000000 +#define regk_iop_sw_cfg_spu_gioout1 0x00000000 +#define regk_iop_sw_cfg_spu_gioout10 0x00000007 +#define regk_iop_sw_cfg_spu_gioout11 0x00000007 +#define regk_iop_sw_cfg_spu_gioout12 0x00000007 +#define regk_iop_sw_cfg_spu_gioout13 0x00000007 +#define regk_iop_sw_cfg_spu_gioout14 0x00000007 +#define regk_iop_sw_cfg_spu_gioout15 0x00000007 +#define regk_iop_sw_cfg_spu_gioout16 0x00000007 +#define regk_iop_sw_cfg_spu_gioout17 0x00000007 +#define regk_iop_sw_cfg_spu_gioout18 0x00000007 +#define regk_iop_sw_cfg_spu_gioout19 0x00000007 +#define regk_iop_sw_cfg_spu_gioout2 0x00000001 +#define regk_iop_sw_cfg_spu_gioout20 0x00000007 +#define regk_iop_sw_cfg_spu_gioout21 0x00000007 +#define regk_iop_sw_cfg_spu_gioout22 0x00000007 +#define regk_iop_sw_cfg_spu_gioout23 0x00000007 +#define regk_iop_sw_cfg_spu_gioout24 0x00000007 +#define regk_iop_sw_cfg_spu_gioout25 0x00000007 +#define regk_iop_sw_cfg_spu_gioout26 0x00000007 +#define regk_iop_sw_cfg_spu_gioout27 0x00000007 +#define regk_iop_sw_cfg_spu_gioout28 0x00000007 +#define regk_iop_sw_cfg_spu_gioout29 0x00000007 +#define regk_iop_sw_cfg_spu_gioout3 0x00000001 +#define regk_iop_sw_cfg_spu_gioout30 0x00000007 +#define regk_iop_sw_cfg_spu_gioout31 0x00000007 +#define regk_iop_sw_cfg_spu_gioout4 0x00000002 +#define regk_iop_sw_cfg_spu_gioout5 0x00000002 +#define regk_iop_sw_cfg_spu_gioout6 0x00000003 +#define regk_iop_sw_cfg_spu_gioout7 0x00000003 +#define regk_iop_sw_cfg_spu_gioout8 0x00000007 +#define regk_iop_sw_cfg_spu_gioout9 0x00000007 +#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 +#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 +#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003 +#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 +#define regk_iop_sw_cfg_timer_grp0 0x00000000 +#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005 +#define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005 +#define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005 +#define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005 +#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002 +#define regk_iop_sw_cfg_timer_grp1 0x00000000 +#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006 +#define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006 +#define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006 +#define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006 +#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003 +#define regk_iop_sw_cfg_trig0_0 0x00000000 +#define regk_iop_sw_cfg_trig0_1 0x00000000 +#define regk_iop_sw_cfg_trig0_2 0x00000000 +#define regk_iop_sw_cfg_trig0_3 0x00000000 +#define regk_iop_sw_cfg_trig1_0 0x00000000 +#define regk_iop_sw_cfg_trig1_1 0x00000000 +#define regk_iop_sw_cfg_trig1_2 0x00000000 +#define regk_iop_sw_cfg_trig1_3 0x00000000 +#define regk_iop_sw_cfg_trig2_0 0x00000001 +#define regk_iop_sw_cfg_trig2_1 0x00000001 +#define regk_iop_sw_cfg_trig2_2 0x00000001 +#define regk_iop_sw_cfg_trig2_3 0x00000001 +#define regk_iop_sw_cfg_trig3_0 0x00000001 +#define regk_iop_sw_cfg_trig3_1 0x00000001 +#define regk_iop_sw_cfg_trig3_2 0x00000001 +#define regk_iop_sw_cfg_trig3_3 0x00000001 +#define regk_iop_sw_cfg_trig4_0 0x00000002 +#define regk_iop_sw_cfg_trig4_1 0x00000002 +#define regk_iop_sw_cfg_trig4_2 0x00000002 +#define regk_iop_sw_cfg_trig4_3 0x00000002 +#define regk_iop_sw_cfg_trig5_0 0x00000002 +#define regk_iop_sw_cfg_trig5_1 0x00000002 +#define regk_iop_sw_cfg_trig5_2 0x00000002 +#define regk_iop_sw_cfg_trig5_3 0x00000002 +#define regk_iop_sw_cfg_trig6_0 0x00000003 +#define regk_iop_sw_cfg_trig6_1 0x00000003 +#define regk_iop_sw_cfg_trig6_2 0x00000003 +#define regk_iop_sw_cfg_trig6_3 0x00000003 +#define regk_iop_sw_cfg_trig7_0 0x00000003 +#define regk_iop_sw_cfg_trig7_1 0x00000003 +#define regk_iop_sw_cfg_trig7_2 0x00000003 +#define regk_iop_sw_cfg_trig7_3 0x00000003 +#endif /* __iop_sw_cfg_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h new file mode 100644 index 00000000000..3f4fe1b3181 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h @@ -0,0 +1,950 @@ +#ifndef __iop_sw_cpu_defs_asm_h +#define __iop_sw_cpu_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sw_cpu.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_mpu_trace, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_mpu_trace_offset 0 + +/* Register r_spu_trace, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_spu_trace_offset 4 + +/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8 + +/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6 +#define reg_iop_sw_cpu_rw_mc_ctrl_offset 12 + +/* Register rw_mc_data, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_cpu_rw_mc_data___val___width 32 +#define reg_iop_sw_cpu_rw_mc_data_offset 16 + +/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_addr_offset 20 + +/* Register rs_mc_data, scope iop_sw_cpu, type rs */ +#define reg_iop_sw_cpu_rs_mc_data_offset 24 + +/* Register r_mc_data, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_mc_data_offset 28 + +/* Register r_mc_stat, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5 +#define reg_iop_sw_cpu_r_mc_stat_offset 32 + +/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36 + +/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus_set_mask_offset 40 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44 + +/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48 + +/* Register r_bus_in, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_bus_in_offset 52 + +/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56 + +/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_set_mask_offset 60 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64 + +/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68 + +/* Register r_gio_in, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_gio_in_offset 72 + +/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31 +#define reg_iop_sw_cpu_rw_intr0_mask_offset 76 + +/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31 +#define reg_iop_sw_cpu_rw_ack_intr0_offset 80 + +/* Register r_intr0, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16 +#define reg_iop_sw_cpu_r_intr0___spu_0___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_0___bit 16 +#define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17 +#define reg_iop_sw_cpu_r_intr0___spu_1___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_1___bit 17 +#define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18 +#define reg_iop_sw_cpu_r_intr0___spu_2___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_2___bit 18 +#define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19 +#define reg_iop_sw_cpu_r_intr0___spu_3___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_3___bit 19 +#define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20 +#define reg_iop_sw_cpu_r_intr0___spu_4___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_4___bit 20 +#define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21 +#define reg_iop_sw_cpu_r_intr0___spu_5___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_5___bit 21 +#define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22 +#define reg_iop_sw_cpu_r_intr0___spu_6___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_6___bit 22 +#define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23 +#define reg_iop_sw_cpu_r_intr0___spu_7___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_7___bit 23 +#define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24 +#define reg_iop_sw_cpu_r_intr0___spu_8___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_8___bit 24 +#define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25 +#define reg_iop_sw_cpu_r_intr0___spu_9___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_9___bit 25 +#define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26 +#define reg_iop_sw_cpu_r_intr0___spu_10___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_10___bit 26 +#define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27 +#define reg_iop_sw_cpu_r_intr0___spu_11___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_11___bit 27 +#define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28 +#define reg_iop_sw_cpu_r_intr0___spu_12___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_12___bit 28 +#define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29 +#define reg_iop_sw_cpu_r_intr0___spu_13___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_13___bit 29 +#define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30 +#define reg_iop_sw_cpu_r_intr0___spu_14___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_14___bit 30 +#define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31 +#define reg_iop_sw_cpu_r_intr0___spu_15___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_15___bit 31 +#define reg_iop_sw_cpu_r_intr0_offset 84 + +/* Register r_masked_intr0, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16 +#define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17 +#define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18 +#define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19 +#define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20 +#define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21 +#define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22 +#define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23 +#define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24 +#define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25 +#define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26 +#define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27 +#define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28 +#define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29 +#define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30 +#define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31 +#define reg_iop_sw_cpu_r_masked_intr0_offset 88 + +/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31 +#define reg_iop_sw_cpu_rw_intr1_mask_offset 92 + +/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr1_offset 96 + +/* Register r_intr1, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16 +#define reg_iop_sw_cpu_r_intr1___dmc_in___width 1 +#define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16 +#define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17 +#define reg_iop_sw_cpu_r_intr1___dmc_out___width 1 +#define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17 +#define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18 +#define reg_iop_sw_cpu_r_intr1___fifo_in___width 1 +#define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18 +#define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19 +#define reg_iop_sw_cpu_r_intr1___fifo_out___width 1 +#define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19 +#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20 +#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1 +#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20 +#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21 +#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1 +#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21 +#define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1 +#define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30 +#define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1 +#define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31 +#define reg_iop_sw_cpu_r_intr1_offset 100 + +/* Register r_masked_intr1, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31 +#define reg_iop_sw_cpu_r_masked_intr1_offset 104 + + +/* Constants */ +#define regk_iop_sw_cpu_copy 0x00000000 +#define regk_iop_sw_cpu_no 0x00000000 +#define regk_iop_sw_cpu_rd 0x00000002 +#define regk_iop_sw_cpu_reg_copy 0x00000001 +#define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 +#define regk_iop_sw_cpu_wr 0x00000003 +#define regk_iop_sw_cpu_yes 0x00000001 +#endif /* __iop_sw_cpu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h new file mode 100644 index 00000000000..ffcc83b22d2 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h @@ -0,0 +1,1086 @@ +#ifndef __iop_sw_mpu_defs_asm_h +#define __iop_sw_mpu_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sw_mpu.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 +#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 +#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 + +/* Register r_spu_trace, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_spu_trace_offset 4 + +/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8 + +/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6 +#define reg_iop_sw_mpu_rw_mc_ctrl_offset 12 + +/* Register rw_mc_data, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_mpu_rw_mc_data___val___width 32 +#define reg_iop_sw_mpu_rw_mc_data_offset 16 + +/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_addr_offset 20 + +/* Register rs_mc_data, scope iop_sw_mpu, type rs */ +#define reg_iop_sw_mpu_rs_mc_data_offset 24 + +/* Register r_mc_data, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_mc_data_offset 28 + +/* Register r_mc_stat, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5 +#define reg_iop_sw_mpu_r_mc_stat_offset 32 + +/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36 + +/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus_set_mask_offset 40 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44 + +/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48 + +/* Register r_bus_in, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_bus_in_offset 52 + +/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56 + +/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_set_mask_offset 60 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64 + +/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68 + +/* Register r_gio_in, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_gio_in_offset 72 + +/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 +#define reg_iop_sw_mpu_rw_cpu_intr_offset 76 + +/* Register r_cpu_intr, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 +#define reg_iop_sw_mpu_r_cpu_intr_offset 80 + +/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84 + +/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88 + +/* Register r_intr_grp0, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15 +#define reg_iop_sw_mpu_r_intr_grp0_offset 92 + +/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96 + +/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100 + +/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104 + +/* Register r_intr_grp1, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15 +#define reg_iop_sw_mpu_r_intr_grp1_offset 108 + +/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112 + +/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116 + +/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120 + +/* Register r_intr_grp2, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15 +#define reg_iop_sw_mpu_r_intr_grp2_offset 124 + +/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128 + +/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132 + +/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136 + +/* Register r_intr_grp3, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15 +#define reg_iop_sw_mpu_r_intr_grp3_offset 140 + +/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144 + + +/* Constants */ +#define regk_iop_sw_mpu_copy 0x00000000 +#define regk_iop_sw_mpu_cpu 0x00000000 +#define regk_iop_sw_mpu_mpu 0x00000001 +#define regk_iop_sw_mpu_no 0x00000000 +#define regk_iop_sw_mpu_nop 0x00000000 +#define regk_iop_sw_mpu_rd 0x00000002 +#define regk_iop_sw_mpu_reg_copy 0x00000001 +#define regk_iop_sw_mpu_rw_bus_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus_oe_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 +#define regk_iop_sw_mpu_set 0x00000001 +#define regk_iop_sw_mpu_spu 0x00000002 +#define regk_iop_sw_mpu_wr 0x00000003 +#define regk_iop_sw_mpu_yes 0x00000001 +#endif /* __iop_sw_mpu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h new file mode 100644 index 00000000000..67a74533808 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h @@ -0,0 +1,523 @@ +#ifndef __iop_sw_spu_defs_asm_h +#define __iop_sw_spu_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sw_spu.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_mpu_trace, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mpu_trace_offset 0 + +/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6 +#define reg_iop_sw_spu_rw_mc_ctrl_offset 4 + +/* Register rw_mc_data, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_spu_rw_mc_data___val___width 32 +#define reg_iop_sw_spu_rw_mc_data_offset 8 + +/* Register rw_mc_addr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_addr_offset 12 + +/* Register rs_mc_data, scope iop_sw_spu, type rs */ +#define reg_iop_sw_spu_rs_mc_data_offset 16 + +/* Register r_mc_data, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mc_data_offset 20 + +/* Register r_mc_stat, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2 +#define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5 +#define reg_iop_sw_spu_r_mc_stat_offset 24 + +/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_offset 28 + +/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask_offset 32 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36 + +/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40 + +/* Register r_bus_in, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_bus_in_offset 44 + +/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_clr_mask_offset 48 + +/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_set_mask_offset 52 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56 + +/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60 + +/* Register r_gio_in, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_gio_in_offset 64 + +/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68 + +/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72 + +/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76 + +/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80 + +/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84 + +/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88 + +/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92 + +/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96 + +/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100 + +/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104 + +/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108 + +/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112 + +/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_rw_cpu_intr_offset 116 + +/* Register r_cpu_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_r_cpu_intr_offset 120 + +/* Register r_hw_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 +#define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10 +#define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10 +#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11 +#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11 +#define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12 +#define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12 +#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13 +#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13 +#define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14 +#define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14 +#define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15 +#define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15 +#define reg_iop_sw_spu_r_hw_intr_offset 124 + +/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_rw_mpu_intr_offset 128 + +/* Register r_mpu_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_r_mpu_intr_offset 132 + + +/* Constants */ +#define regk_iop_sw_spu_copy 0x00000000 +#define regk_iop_sw_spu_no 0x00000000 +#define regk_iop_sw_spu_nop 0x00000000 +#define regk_iop_sw_spu_rd 0x00000002 +#define regk_iop_sw_spu_reg_copy 0x00000001 +#define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_spu_set 0x00000001 +#define regk_iop_sw_spu_wr 0x00000003 +#define regk_iop_sw_spu_yes 0x00000001 +#endif /* __iop_sw_spu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h new file mode 100644 index 00000000000..4ad671202af --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h @@ -0,0 +1,61 @@ +#ifndef __iop_version_defs_asm_h +#define __iop_version_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_version.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_version, scope iop_version, type r */ +#define reg_iop_version_r_version___nr___lsb 0 +#define reg_iop_version_r_version___nr___width 8 +#define reg_iop_version_r_version_offset 0 + + +/* Constants */ +#define regk_iop_version_v2_0 0x00000002 +#endif /* __iop_version_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h new file mode 100644 index 00000000000..af3196c60a4 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h @@ -0,0 +1,31 @@ +/* Autogenerated Changes here will be lost! + * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg + */ +#define regi_iop_version (regi_iop + 0) +#define regi_iop_fifo_in_extra (regi_iop + 64) +#define regi_iop_fifo_out_extra (regi_iop + 128) +#define regi_iop_trigger_grp0 (regi_iop + 192) +#define regi_iop_trigger_grp1 (regi_iop + 256) +#define regi_iop_trigger_grp2 (regi_iop + 320) +#define regi_iop_trigger_grp3 (regi_iop + 384) +#define regi_iop_trigger_grp4 (regi_iop + 448) +#define regi_iop_trigger_grp5 (regi_iop + 512) +#define regi_iop_trigger_grp6 (regi_iop + 576) +#define regi_iop_trigger_grp7 (regi_iop + 640) +#define regi_iop_crc_par (regi_iop + 768) +#define regi_iop_dmc_in (regi_iop + 896) +#define regi_iop_dmc_out (regi_iop + 1024) +#define regi_iop_fifo_in (regi_iop + 1152) +#define regi_iop_fifo_out (regi_iop + 1280) +#define regi_iop_scrc_in (regi_iop + 1408) +#define regi_iop_scrc_out (regi_iop + 1536) +#define regi_iop_timer_grp0 (regi_iop + 1664) +#define regi_iop_timer_grp1 (regi_iop + 1792) +#define regi_iop_sap_in (regi_iop + 2048) +#define regi_iop_sap_out (regi_iop + 2304) +#define regi_iop_spu (regi_iop + 2560) +#define regi_iop_sw_cfg (regi_iop + 2816) +#define regi_iop_sw_cpu (regi_iop + 3072) +#define regi_iop_sw_mpu (regi_iop + 3328) +#define regi_iop_sw_spu (regi_iop + 3584) +#define regi_iop_mpu (regi_iop + 4096) diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h new file mode 100644 index 00000000000..51dde016c03 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h @@ -0,0 +1,141 @@ +#ifndef __iop_sap_in_defs_h +#define __iop_sap_in_defs_h + +/* + * This file is autogenerated from + * file: iop_sap_in.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sap_in */ + +#define STRIDE_iop_sap_in_rw_bus_byte 4 +/* Register rw_bus_byte, scope iop_sap_in, type rw */ +typedef struct { + unsigned int sync_sel : 2; + unsigned int sync_ext_src : 3; + unsigned int sync_edge : 2; + unsigned int delay : 2; + unsigned int dummy1 : 23; +} reg_iop_sap_in_rw_bus_byte; +#define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0 +#define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0 + +#define STRIDE_iop_sap_in_rw_gio 4 +/* Register rw_gio, scope iop_sap_in, type rw */ +typedef struct { + unsigned int sync_sel : 2; + unsigned int sync_ext_src : 3; + unsigned int sync_edge : 2; + unsigned int delay : 2; + unsigned int logic : 2; + unsigned int dummy1 : 21; +} reg_iop_sap_in_rw_gio; +#define REG_RD_ADDR_iop_sap_in_rw_gio 16 +#define REG_WR_ADDR_iop_sap_in_rw_gio 16 + + +/* Constants */ +enum { + regk_iop_sap_in_and = 0x00000002, + regk_iop_sap_in_ext_clk200 = 0x00000003, + regk_iop_sap_in_gio0 = 0x00000000, + regk_iop_sap_in_gio12 = 0x00000003, + regk_iop_sap_in_gio16 = 0x00000004, + regk_iop_sap_in_gio20 = 0x00000005, + regk_iop_sap_in_gio24 = 0x00000006, + regk_iop_sap_in_gio28 = 0x00000007, + regk_iop_sap_in_gio4 = 0x00000001, + regk_iop_sap_in_gio8 = 0x00000002, + regk_iop_sap_in_inv = 0x00000001, + regk_iop_sap_in_neg = 0x00000002, + regk_iop_sap_in_no = 0x00000000, + regk_iop_sap_in_no_del_ext_clk200 = 0x00000002, + regk_iop_sap_in_none = 0x00000000, + regk_iop_sap_in_one = 0x00000001, + regk_iop_sap_in_or = 0x00000003, + regk_iop_sap_in_pos = 0x00000001, + regk_iop_sap_in_pos_neg = 0x00000003, + regk_iop_sap_in_rw_bus_byte_default = 0x00000000, + regk_iop_sap_in_rw_bus_byte_size = 0x00000004, + regk_iop_sap_in_rw_gio_default = 0x00000000, + regk_iop_sap_in_rw_gio_size = 0x00000020, + regk_iop_sap_in_timer_grp0_tmr3 = 0x00000000, + regk_iop_sap_in_timer_grp1_tmr3 = 0x00000001, + regk_iop_sap_in_tmr_clk200 = 0x00000001, + regk_iop_sap_in_two = 0x00000002, + regk_iop_sap_in_two_clk200 = 0x00000000 +}; +#endif /* __iop_sap_in_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h new file mode 100644 index 00000000000..5af88baa2ac --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h @@ -0,0 +1,231 @@ +#ifndef __iop_sap_out_defs_h +#define __iop_sap_out_defs_h + +/* + * This file is autogenerated from + * file: iop_sap_out.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sap_out */ + +/* Register rw_gen_gated, scope iop_sap_out, type rw */ +typedef struct { + unsigned int clk0_src : 2; + unsigned int clk0_gate_src : 2; + unsigned int clk0_force_src : 3; + unsigned int clk1_src : 2; + unsigned int clk1_gate_src : 2; + unsigned int clk1_force_src : 3; + unsigned int dummy1 : 18; +} reg_iop_sap_out_rw_gen_gated; +#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 +#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 + +/* Register rw_bus, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 2; + unsigned int byte0_clk_ext : 2; + unsigned int byte0_gated_clk : 1; + unsigned int byte0_clk_inv : 1; + unsigned int byte0_delay : 1; + unsigned int byte1_clk_sel : 2; + unsigned int byte1_clk_ext : 2; + unsigned int byte1_gated_clk : 1; + unsigned int byte1_clk_inv : 1; + unsigned int byte1_delay : 1; + unsigned int byte2_clk_sel : 2; + unsigned int byte2_clk_ext : 2; + unsigned int byte2_gated_clk : 1; + unsigned int byte2_clk_inv : 1; + unsigned int byte2_delay : 1; + unsigned int byte3_clk_sel : 2; + unsigned int byte3_clk_ext : 2; + unsigned int byte3_gated_clk : 1; + unsigned int byte3_clk_inv : 1; + unsigned int byte3_delay : 1; + unsigned int dummy1 : 4; +} reg_iop_sap_out_rw_bus; +#define REG_RD_ADDR_iop_sap_out_rw_bus 4 +#define REG_WR_ADDR_iop_sap_out_rw_bus 4 + +/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 2; + unsigned int byte0_clk_ext : 2; + unsigned int byte0_gated_clk : 1; + unsigned int byte0_clk_inv : 1; + unsigned int byte0_delay : 1; + unsigned int byte0_logic : 2; + unsigned int byte0_logic_src : 2; + unsigned int byte1_clk_sel : 2; + unsigned int byte1_clk_ext : 2; + unsigned int byte1_gated_clk : 1; + unsigned int byte1_clk_inv : 1; + unsigned int byte1_delay : 1; + unsigned int byte1_logic : 2; + unsigned int byte1_logic_src : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus_lo_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8 +#define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8 + +/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte2_clk_sel : 2; + unsigned int byte2_clk_ext : 2; + unsigned int byte2_gated_clk : 1; + unsigned int byte2_clk_inv : 1; + unsigned int byte2_delay : 1; + unsigned int byte2_logic : 2; + unsigned int byte2_logic_src : 2; + unsigned int byte3_clk_sel : 2; + unsigned int byte3_clk_ext : 2; + unsigned int byte3_gated_clk : 1; + unsigned int byte3_clk_inv : 1; + unsigned int byte3_delay : 1; + unsigned int byte3_logic : 2; + unsigned int byte3_logic_src : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus_hi_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12 +#define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12 + +#define STRIDE_iop_sap_out_rw_gio 4 +/* Register rw_gio, scope iop_sap_out, type rw */ +typedef struct { + unsigned int out_clk_sel : 3; + unsigned int out_clk_ext : 2; + unsigned int out_gated_clk : 1; + unsigned int out_clk_inv : 1; + unsigned int out_delay : 1; + unsigned int out_logic : 2; + unsigned int out_logic_src : 2; + unsigned int oe_clk_sel : 3; + unsigned int oe_clk_ext : 2; + unsigned int oe_gated_clk : 1; + unsigned int oe_clk_inv : 1; + unsigned int oe_delay : 1; + unsigned int oe_logic : 2; + unsigned int oe_logic_src : 2; + unsigned int dummy1 : 8; +} reg_iop_sap_out_rw_gio; +#define REG_RD_ADDR_iop_sap_out_rw_gio 16 +#define REG_WR_ADDR_iop_sap_out_rw_gio 16 + + +/* Constants */ +enum { + regk_iop_sap_out_always = 0x00000001, + regk_iop_sap_out_and = 0x00000002, + regk_iop_sap_out_clk0 = 0x00000000, + regk_iop_sap_out_clk1 = 0x00000001, + regk_iop_sap_out_clk12 = 0x00000004, + regk_iop_sap_out_clk200 = 0x00000000, + regk_iop_sap_out_ext = 0x00000002, + regk_iop_sap_out_gated = 0x00000003, + regk_iop_sap_out_gio0 = 0x00000000, + regk_iop_sap_out_gio1 = 0x00000000, + regk_iop_sap_out_gio16 = 0x00000002, + regk_iop_sap_out_gio17 = 0x00000002, + regk_iop_sap_out_gio24 = 0x00000003, + regk_iop_sap_out_gio25 = 0x00000003, + regk_iop_sap_out_gio8 = 0x00000001, + regk_iop_sap_out_gio9 = 0x00000001, + regk_iop_sap_out_gio_out10 = 0x00000005, + regk_iop_sap_out_gio_out18 = 0x00000006, + regk_iop_sap_out_gio_out2 = 0x00000004, + regk_iop_sap_out_gio_out26 = 0x00000007, + regk_iop_sap_out_inv = 0x00000001, + regk_iop_sap_out_nand = 0x00000003, + regk_iop_sap_out_no = 0x00000000, + regk_iop_sap_out_none = 0x00000000, + regk_iop_sap_out_one = 0x00000001, + regk_iop_sap_out_rw_bus_default = 0x00000000, + regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000, + regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000, + regk_iop_sap_out_rw_gen_gated_default = 0x00000000, + regk_iop_sap_out_rw_gio_default = 0x00000000, + regk_iop_sap_out_rw_gio_size = 0x00000020, + regk_iop_sap_out_spu_gio6 = 0x00000002, + regk_iop_sap_out_spu_gio7 = 0x00000003, + regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000, + regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001, + regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002, + regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003, + regk_iop_sap_out_tmr200 = 0x00000001, + regk_iop_sap_out_yes = 0x00000001 +}; +#endif /* __iop_sap_out_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h new file mode 100644 index 00000000000..98ac95275a1 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h @@ -0,0 +1,725 @@ +#ifndef __iop_sw_cfg_defs_h +#define __iop_sw_cfg_defs_h + +/* + * This file is autogenerated from + * file: iop_sw_cfg.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_cfg */ + +/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_crc_par_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0 +#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0 + +/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_in_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 + +/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_out_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 + +/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 + +/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 + +/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 + +/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 + +/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_sap_in_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28 +#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28 + +/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_sap_out_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32 +#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32 + +/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_in_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 + +/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_out_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 + +/* Register rw_spu_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 1; + unsigned int dummy1 : 31; +} reg_iop_sw_cfg_rw_spu_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44 + +/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 + +/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 + +/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 + +/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 + +/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp2_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 + +/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp3_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 + +/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp4_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 + +/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp5_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 + +/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp6_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 + +/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp7_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 + +/* Register rw_bus_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cfg_rw_bus_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88 + +/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cfg_rw_bus_oe_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 + +/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cfg_rw_gio_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96 + +/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cfg_rw_gio_oe_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 + +/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus_byte0 : 2; + unsigned int bus_byte1 : 2; + unsigned int bus_byte2 : 2; + unsigned int bus_byte3 : 2; + unsigned int gio3_0 : 2; + unsigned int gio7_4 : 2; + unsigned int gio11_8 : 2; + unsigned int gio15_12 : 2; + unsigned int gio19_16 : 2; + unsigned int gio23_20 : 2; + unsigned int gio27_24 : 2; + unsigned int gio31_28 : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_pinmapping; +#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104 +#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104 + +/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus_lo : 2; + unsigned int bus_hi : 2; + unsigned int bus_lo_oe : 2; + unsigned int bus_hi_oe : 2; + unsigned int dummy1 : 24; +} reg_iop_sw_cfg_rw_bus_out_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 + +/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio0 : 3; + unsigned int gio0_oe : 1; + unsigned int gio1 : 3; + unsigned int gio1_oe : 1; + unsigned int gio2 : 3; + unsigned int gio2_oe : 1; + unsigned int gio3 : 3; + unsigned int gio3_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 + +/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio4 : 3; + unsigned int gio4_oe : 1; + unsigned int gio5 : 3; + unsigned int gio5_oe : 1; + unsigned int gio6 : 3; + unsigned int gio6_oe : 1; + unsigned int gio7 : 3; + unsigned int gio7_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 + +/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio8 : 3; + unsigned int gio8_oe : 1; + unsigned int gio9 : 3; + unsigned int gio9_oe : 1; + unsigned int gio10 : 3; + unsigned int gio10_oe : 1; + unsigned int gio11 : 3; + unsigned int gio11_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 + +/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio12 : 3; + unsigned int gio12_oe : 1; + unsigned int gio13 : 3; + unsigned int gio13_oe : 1; + unsigned int gio14 : 3; + unsigned int gio14_oe : 1; + unsigned int gio15 : 3; + unsigned int gio15_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 + +/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio16 : 3; + unsigned int gio16_oe : 1; + unsigned int gio17 : 3; + unsigned int gio17_oe : 1; + unsigned int gio18 : 3; + unsigned int gio18_oe : 1; + unsigned int gio19 : 3; + unsigned int gio19_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 + +/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio20 : 3; + unsigned int gio20_oe : 1; + unsigned int gio21 : 3; + unsigned int gio21_oe : 1; + unsigned int gio22 : 3; + unsigned int gio22_oe : 1; + unsigned int gio23 : 3; + unsigned int gio23_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 + +/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio24 : 3; + unsigned int gio24_oe : 1; + unsigned int gio25 : 3; + unsigned int gio25_oe : 1; + unsigned int gio26 : 3; + unsigned int gio26_oe : 1; + unsigned int gio27 : 3; + unsigned int gio27_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 + +/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio28 : 3; + unsigned int gio28_oe : 1; + unsigned int gio29 : 3; + unsigned int gio29_oe : 1; + unsigned int gio30 : 3; + unsigned int gio30_oe : 1; + unsigned int gio31 : 3; + unsigned int gio31_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 + +/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus0_in : 1; + unsigned int bus1_in : 1; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_spu_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144 + +/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 2; + unsigned int tmr1_en : 2; + unsigned int tmr2_en : 2; + unsigned int tmr3_en : 2; + unsigned int tmr0_dis : 2; + unsigned int tmr1_dis : 2; + unsigned int tmr2_dis : 2; + unsigned int tmr3_dis : 2; + unsigned int dummy1 : 13; +} reg_iop_sw_cfg_rw_timer_grp0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 + +/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 2; + unsigned int tmr1_en : 2; + unsigned int tmr2_en : 2; + unsigned int tmr3_en : 2; + unsigned int tmr0_dis : 2; + unsigned int tmr1_dis : 2; + unsigned int tmr2_dis : 2; + unsigned int tmr3_dis : 2; + unsigned int dummy1 : 13; +} reg_iop_sw_cfg_rw_timer_grp1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 + +/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int grp0_dis : 1; + unsigned int grp0_en : 1; + unsigned int grp1_dis : 1; + unsigned int grp1_en : 1; + unsigned int grp2_dis : 1; + unsigned int grp2_en : 1; + unsigned int grp3_dis : 1; + unsigned int grp3_en : 1; + unsigned int grp4_dis : 1; + unsigned int grp4_en : 1; + unsigned int grp5_dis : 1; + unsigned int grp5_en : 1; + unsigned int grp6_dis : 1; + unsigned int grp6_en : 1; + unsigned int grp7_dis : 1; + unsigned int grp7_en : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_trigger_grps_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 + +/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int out_strb : 4; + unsigned int in_src : 2; + unsigned int in_size : 3; + unsigned int in_last : 2; + unsigned int in_strb : 4; + unsigned int dummy1 : 17; +} reg_iop_sw_cfg_rw_pdp_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160 +#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160 + +/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int sdp_out_strb : 3; + unsigned int sdp_in_data : 3; + unsigned int sdp_in_last : 2; + unsigned int sdp_in_strb : 3; + unsigned int dummy1 : 21; +} reg_iop_sw_cfg_rw_sdp_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164 +#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164 + + +/* Constants */ +enum { + regk_iop_sw_cfg_a = 0x00000001, + regk_iop_sw_cfg_b = 0x00000002, + regk_iop_sw_cfg_bus = 0x00000000, + regk_iop_sw_cfg_bus_rot16 = 0x00000002, + regk_iop_sw_cfg_bus_rot24 = 0x00000003, + regk_iop_sw_cfg_bus_rot8 = 0x00000001, + regk_iop_sw_cfg_clk12 = 0x00000000, + regk_iop_sw_cfg_cpu = 0x00000000, + regk_iop_sw_cfg_gated_clk0 = 0x0000000e, + regk_iop_sw_cfg_gated_clk1 = 0x0000000f, + regk_iop_sw_cfg_gio0 = 0x00000004, + regk_iop_sw_cfg_gio1 = 0x00000001, + regk_iop_sw_cfg_gio2 = 0x00000005, + regk_iop_sw_cfg_gio3 = 0x00000002, + regk_iop_sw_cfg_gio4 = 0x00000006, + regk_iop_sw_cfg_gio5 = 0x00000003, + regk_iop_sw_cfg_gio6 = 0x00000007, + regk_iop_sw_cfg_gio7 = 0x00000004, + regk_iop_sw_cfg_gio_in18 = 0x00000002, + regk_iop_sw_cfg_gio_in19 = 0x00000003, + regk_iop_sw_cfg_gio_in20 = 0x00000004, + regk_iop_sw_cfg_gio_in21 = 0x00000005, + regk_iop_sw_cfg_gio_in26 = 0x00000006, + regk_iop_sw_cfg_gio_in27 = 0x00000007, + regk_iop_sw_cfg_gio_in4 = 0x00000000, + regk_iop_sw_cfg_gio_in5 = 0x00000001, + regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, + regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002, + regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003, + regk_iop_sw_cfg_mpu = 0x00000001, + regk_iop_sw_cfg_none = 0x00000000, + regk_iop_sw_cfg_pdp_out = 0x00000001, + regk_iop_sw_cfg_pdp_out_hi = 0x00000001, + regk_iop_sw_cfg_pdp_out_lo = 0x00000000, + regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555, + regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, + regk_iop_sw_cfg_sdp_out = 0x00000004, + regk_iop_sw_cfg_size16 = 0x00000002, + regk_iop_sw_cfg_size24 = 0x00000003, + regk_iop_sw_cfg_size32 = 0x00000004, + regk_iop_sw_cfg_size8 = 0x00000001, + regk_iop_sw_cfg_spu = 0x00000002, + regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002, + regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002, + regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003, + regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003, + regk_iop_sw_cfg_spu_g0 = 0x00000007, + regk_iop_sw_cfg_spu_g1 = 0x00000007, + regk_iop_sw_cfg_spu_g2 = 0x00000007, + regk_iop_sw_cfg_spu_g3 = 0x00000007, + regk_iop_sw_cfg_spu_g4 = 0x00000007, + regk_iop_sw_cfg_spu_g5 = 0x00000007, + regk_iop_sw_cfg_spu_g6 = 0x00000007, + regk_iop_sw_cfg_spu_g7 = 0x00000007, + regk_iop_sw_cfg_spu_gio0 = 0x00000000, + regk_iop_sw_cfg_spu_gio1 = 0x00000001, + regk_iop_sw_cfg_spu_gio5 = 0x00000005, + regk_iop_sw_cfg_spu_gio6 = 0x00000006, + regk_iop_sw_cfg_spu_gio7 = 0x00000007, + regk_iop_sw_cfg_spu_gio_out0 = 0x00000008, + regk_iop_sw_cfg_spu_gio_out1 = 0x00000009, + regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a, + regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b, + regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c, + regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d, + regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e, + regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f, + regk_iop_sw_cfg_spu_gioout0 = 0x00000000, + regk_iop_sw_cfg_spu_gioout1 = 0x00000000, + regk_iop_sw_cfg_spu_gioout10 = 0x00000007, + regk_iop_sw_cfg_spu_gioout11 = 0x00000007, + regk_iop_sw_cfg_spu_gioout12 = 0x00000007, + regk_iop_sw_cfg_spu_gioout13 = 0x00000007, + regk_iop_sw_cfg_spu_gioout14 = 0x00000007, + regk_iop_sw_cfg_spu_gioout15 = 0x00000007, + regk_iop_sw_cfg_spu_gioout16 = 0x00000007, + regk_iop_sw_cfg_spu_gioout17 = 0x00000007, + regk_iop_sw_cfg_spu_gioout18 = 0x00000007, + regk_iop_sw_cfg_spu_gioout19 = 0x00000007, + regk_iop_sw_cfg_spu_gioout2 = 0x00000001, + regk_iop_sw_cfg_spu_gioout20 = 0x00000007, + regk_iop_sw_cfg_spu_gioout21 = 0x00000007, + regk_iop_sw_cfg_spu_gioout22 = 0x00000007, + regk_iop_sw_cfg_spu_gioout23 = 0x00000007, + regk_iop_sw_cfg_spu_gioout24 = 0x00000007, + regk_iop_sw_cfg_spu_gioout25 = 0x00000007, + regk_iop_sw_cfg_spu_gioout26 = 0x00000007, + regk_iop_sw_cfg_spu_gioout27 = 0x00000007, + regk_iop_sw_cfg_spu_gioout28 = 0x00000007, + regk_iop_sw_cfg_spu_gioout29 = 0x00000007, + regk_iop_sw_cfg_spu_gioout3 = 0x00000001, + regk_iop_sw_cfg_spu_gioout30 = 0x00000007, + regk_iop_sw_cfg_spu_gioout31 = 0x00000007, + regk_iop_sw_cfg_spu_gioout4 = 0x00000002, + regk_iop_sw_cfg_spu_gioout5 = 0x00000002, + regk_iop_sw_cfg_spu_gioout6 = 0x00000003, + regk_iop_sw_cfg_spu_gioout7 = 0x00000003, + regk_iop_sw_cfg_spu_gioout8 = 0x00000007, + regk_iop_sw_cfg_spu_gioout9 = 0x00000007, + regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, + regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, + regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003, + regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, + regk_iop_sw_cfg_timer_grp0 = 0x00000000, + regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005, + regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005, + regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005, + regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005, + regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002, + regk_iop_sw_cfg_timer_grp1 = 0x00000000, + regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006, + regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006, + regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006, + regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006, + regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003, + regk_iop_sw_cfg_trig0_0 = 0x00000000, + regk_iop_sw_cfg_trig0_1 = 0x00000000, + regk_iop_sw_cfg_trig0_2 = 0x00000000, + regk_iop_sw_cfg_trig0_3 = 0x00000000, + regk_iop_sw_cfg_trig1_0 = 0x00000000, + regk_iop_sw_cfg_trig1_1 = 0x00000000, + regk_iop_sw_cfg_trig1_2 = 0x00000000, + regk_iop_sw_cfg_trig1_3 = 0x00000000, + regk_iop_sw_cfg_trig2_0 = 0x00000001, + regk_iop_sw_cfg_trig2_1 = 0x00000001, + regk_iop_sw_cfg_trig2_2 = 0x00000001, + regk_iop_sw_cfg_trig2_3 = 0x00000001, + regk_iop_sw_cfg_trig3_0 = 0x00000001, + regk_iop_sw_cfg_trig3_1 = 0x00000001, + regk_iop_sw_cfg_trig3_2 = 0x00000001, + regk_iop_sw_cfg_trig3_3 = 0x00000001, + regk_iop_sw_cfg_trig4_0 = 0x00000002, + regk_iop_sw_cfg_trig4_1 = 0x00000002, + regk_iop_sw_cfg_trig4_2 = 0x00000002, + regk_iop_sw_cfg_trig4_3 = 0x00000002, + regk_iop_sw_cfg_trig5_0 = 0x00000002, + regk_iop_sw_cfg_trig5_1 = 0x00000002, + regk_iop_sw_cfg_trig5_2 = 0x00000002, + regk_iop_sw_cfg_trig5_3 = 0x00000002, + regk_iop_sw_cfg_trig6_0 = 0x00000003, + regk_iop_sw_cfg_trig6_1 = 0x00000003, + regk_iop_sw_cfg_trig6_2 = 0x00000003, + regk_iop_sw_cfg_trig6_3 = 0x00000003, + regk_iop_sw_cfg_trig7_0 = 0x00000003, + regk_iop_sw_cfg_trig7_1 = 0x00000003, + regk_iop_sw_cfg_trig7_2 = 0x00000003, + regk_iop_sw_cfg_trig7_3 = 0x00000003 +}; +#endif /* __iop_sw_cfg_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h new file mode 100644 index 00000000000..a16f556370e --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h @@ -0,0 +1,522 @@ +#ifndef __iop_sw_cpu_defs_h +#define __iop_sw_cpu_defs_h + +/* + * This file is autogenerated from + * file: iop_sw_cpu.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_cpu */ + +/* Register r_mpu_trace, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_mpu_trace; +#define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0 + +/* Register r_spu_trace, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_spu_trace; +#define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4 + +/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace; +#define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8 + +/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu_mem : 1; + unsigned int dummy1 : 25; +} reg_iop_sw_cpu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12 + +/* Register rw_mc_data, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16 + +/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ +typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20 + +/* Register rs_mc_data, scope iop_sw_cpu, type rs */ +typedef unsigned int reg_iop_sw_cpu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24 + +/* Register r_mc_data, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28 + +/* Register r_mc_stat, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu : 1; + unsigned int dummy1 : 26; +} reg_iop_sw_cpu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32 + +/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 + +/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 + +/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus_oe_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 + +/* Register r_bus_in, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_bus_in; +#define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52 + +/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 + +/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 + +/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 + +/* Register r_gio_in, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_gio_in; +#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72 + +/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu_0 : 1; + unsigned int spu_1 : 1; + unsigned int spu_2 : 1; + unsigned int spu_3 : 1; + unsigned int spu_4 : 1; + unsigned int spu_5 : 1; + unsigned int spu_6 : 1; + unsigned int spu_7 : 1; + unsigned int spu_8 : 1; + unsigned int spu_9 : 1; + unsigned int spu_10 : 1; + unsigned int spu_11 : 1; + unsigned int spu_12 : 1; + unsigned int spu_13 : 1; + unsigned int spu_14 : 1; + unsigned int spu_15 : 1; +} reg_iop_sw_cpu_rw_intr0_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76 + +/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu_0 : 1; + unsigned int spu_1 : 1; + unsigned int spu_2 : 1; + unsigned int spu_3 : 1; + unsigned int spu_4 : 1; + unsigned int spu_5 : 1; + unsigned int spu_6 : 1; + unsigned int spu_7 : 1; + unsigned int spu_8 : 1; + unsigned int spu_9 : 1; + unsigned int spu_10 : 1; + unsigned int spu_11 : 1; + unsigned int spu_12 : 1; + unsigned int spu_13 : 1; + unsigned int spu_14 : 1; + unsigned int spu_15 : 1; +} reg_iop_sw_cpu_rw_ack_intr0; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80 + +/* Register r_intr0, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu_0 : 1; + unsigned int spu_1 : 1; + unsigned int spu_2 : 1; + unsigned int spu_3 : 1; + unsigned int spu_4 : 1; + unsigned int spu_5 : 1; + unsigned int spu_6 : 1; + unsigned int spu_7 : 1; + unsigned int spu_8 : 1; + unsigned int spu_9 : 1; + unsigned int spu_10 : 1; + unsigned int spu_11 : 1; + unsigned int spu_12 : 1; + unsigned int spu_13 : 1; + unsigned int spu_14 : 1; + unsigned int spu_15 : 1; +} reg_iop_sw_cpu_r_intr0; +#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84 + +/* Register r_masked_intr0, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu_0 : 1; + unsigned int spu_1 : 1; + unsigned int spu_2 : 1; + unsigned int spu_3 : 1; + unsigned int spu_4 : 1; + unsigned int spu_5 : 1; + unsigned int spu_6 : 1; + unsigned int spu_7 : 1; + unsigned int spu_8 : 1; + unsigned int spu_9 : 1; + unsigned int spu_10 : 1; + unsigned int spu_11 : 1; + unsigned int spu_12 : 1; + unsigned int spu_13 : 1; + unsigned int spu_14 : 1; + unsigned int spu_15 : 1; +} reg_iop_sw_cpu_r_masked_intr0; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88 + +/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int dmc_in : 1; + unsigned int dmc_out : 1; + unsigned int fifo_in : 1; + unsigned int fifo_out : 1; + unsigned int fifo_in_extra : 1; + unsigned int fifo_out_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_rw_intr1_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92 + +/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cpu_rw_ack_intr1; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96 + +/* Register r_intr1, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int dmc_in : 1; + unsigned int dmc_out : 1; + unsigned int fifo_in : 1; + unsigned int fifo_out : 1; + unsigned int fifo_in_extra : 1; + unsigned int fifo_out_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_r_intr1; +#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100 + +/* Register r_masked_intr1, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int dmc_in : 1; + unsigned int dmc_out : 1; + unsigned int fifo_in : 1; + unsigned int fifo_out : 1; + unsigned int fifo_in_extra : 1; + unsigned int fifo_out_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_r_masked_intr1; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104 + + +/* Constants */ +enum { + regk_iop_sw_cpu_copy = 0x00000000, + regk_iop_sw_cpu_no = 0x00000000, + regk_iop_sw_cpu_rd = 0x00000002, + regk_iop_sw_cpu_reg_copy = 0x00000001, + regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, + regk_iop_sw_cpu_wr = 0x00000003, + regk_iop_sw_cpu_yes = 0x00000001 +}; +#endif /* __iop_sw_cpu_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h new file mode 100644 index 00000000000..a2e4e1a33e5 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h @@ -0,0 +1,648 @@ +#ifndef __iop_sw_mpu_defs_h +#define __iop_sw_mpu_defs_h + +/* + * This file is autogenerated from + * file: iop_sw_mpu.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_mpu */ + +/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_mpu_rw_sw_cfg_owner; +#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 +#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 + +/* Register r_spu_trace, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_spu_trace; +#define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4 + +/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace; +#define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8 + +/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu_mem : 1; + unsigned int dummy1 : 25; +} reg_iop_sw_mpu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12 + +/* Register rw_mc_data, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16 + +/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ +typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20 + +/* Register rs_mc_data, scope iop_sw_mpu, type rs */ +typedef unsigned int reg_iop_sw_mpu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24 + +/* Register r_mc_data, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28 + +/* Register r_mc_stat, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu : 1; + unsigned int dummy1 : 26; +} reg_iop_sw_mpu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32 + +/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 + +/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 + +/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus_oe_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 + +/* Register r_bus_in, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_bus_in; +#define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52 + +/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 + +/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 + +/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 + +/* Register r_gio_in, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_gio_in; +#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72 + +/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int intr16 : 1; + unsigned int intr17 : 1; + unsigned int intr18 : 1; + unsigned int intr19 : 1; + unsigned int intr20 : 1; + unsigned int intr21 : 1; + unsigned int intr22 : 1; + unsigned int intr23 : 1; + unsigned int intr24 : 1; + unsigned int intr25 : 1; + unsigned int intr26 : 1; + unsigned int intr27 : 1; + unsigned int intr28 : 1; + unsigned int intr29 : 1; + unsigned int intr30 : 1; + unsigned int intr31 : 1; +} reg_iop_sw_mpu_rw_cpu_intr; +#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76 +#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76 + +/* Register r_cpu_intr, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int intr16 : 1; + unsigned int intr17 : 1; + unsigned int intr18 : 1; + unsigned int intr19 : 1; + unsigned int intr20 : 1; + unsigned int intr21 : 1; + unsigned int intr22 : 1; + unsigned int intr23 : 1; + unsigned int intr24 : 1; + unsigned int intr25 : 1; + unsigned int intr26 : 1; + unsigned int intr27 : 1; + unsigned int intr28 : 1; + unsigned int intr29 : 1; + unsigned int intr30 : 1; + unsigned int intr31 : 1; +} reg_iop_sw_mpu_r_cpu_intr; +#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80 + +/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_rw_intr_grp0_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 + +/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr0 : 1; + unsigned int dummy1 : 3; + unsigned int spu_intr1 : 1; + unsigned int dummy2 : 3; + unsigned int spu_intr2 : 1; + unsigned int dummy3 : 3; + unsigned int spu_intr3 : 1; + unsigned int dummy4 : 19; +} reg_iop_sw_mpu_rw_ack_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 + +/* Register r_intr_grp0, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92 + +/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_masked_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96 + +/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr4 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr5 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr6 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr7 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_rw_intr_grp1_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 + +/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr4 : 1; + unsigned int dummy1 : 3; + unsigned int spu_intr5 : 1; + unsigned int dummy2 : 3; + unsigned int spu_intr6 : 1; + unsigned int dummy3 : 3; + unsigned int spu_intr7 : 1; + unsigned int dummy4 : 19; +} reg_iop_sw_mpu_rw_ack_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 + +/* Register r_intr_grp1, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr4 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr5 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr6 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr7 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108 + +/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr4 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr5 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr6 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr7 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_masked_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112 + +/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_rw_intr_grp2_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 + +/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr8 : 1; + unsigned int dummy1 : 3; + unsigned int spu_intr9 : 1; + unsigned int dummy2 : 3; + unsigned int spu_intr10 : 1; + unsigned int dummy3 : 3; + unsigned int spu_intr11 : 1; + unsigned int dummy4 : 19; +} reg_iop_sw_mpu_rw_ack_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 + +/* Register r_intr_grp2, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124 + +/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_masked_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128 + +/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr12 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr13 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr14 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr15 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_rw_intr_grp3_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 + +/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr12 : 1; + unsigned int dummy1 : 3; + unsigned int spu_intr13 : 1; + unsigned int dummy2 : 3; + unsigned int spu_intr14 : 1; + unsigned int dummy3 : 3; + unsigned int spu_intr15 : 1; + unsigned int dummy4 : 19; +} reg_iop_sw_mpu_rw_ack_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 + +/* Register r_intr_grp3, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr12 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr13 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr14 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr15 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140 + +/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr12 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr13 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr14 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr15 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_masked_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144 + + +/* Constants */ +enum { + regk_iop_sw_mpu_copy = 0x00000000, + regk_iop_sw_mpu_cpu = 0x00000000, + regk_iop_sw_mpu_mpu = 0x00000001, + regk_iop_sw_mpu_no = 0x00000000, + regk_iop_sw_mpu_nop = 0x00000000, + regk_iop_sw_mpu_rd = 0x00000002, + regk_iop_sw_mpu_reg_copy = 0x00000001, + regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, + regk_iop_sw_mpu_set = 0x00000001, + regk_iop_sw_mpu_spu = 0x00000002, + regk_iop_sw_mpu_wr = 0x00000003, + regk_iop_sw_mpu_yes = 0x00000001 +}; +#endif /* __iop_sw_mpu_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h new file mode 100644 index 00000000000..c8560b865a1 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h @@ -0,0 +1,441 @@ +#ifndef __iop_sw_spu_defs_h +#define __iop_sw_spu_defs_h + +/* + * This file is autogenerated from + * file: iop_sw_spu.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_spu */ + +/* Register r_mpu_trace, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_mpu_trace; +#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0 + +/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu_mem : 1; + unsigned int dummy1 : 25; +} reg_iop_sw_spu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4 + +/* Register rw_mc_data, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8 + +/* Register rw_mc_addr, scope iop_sw_spu, type rw */ +typedef unsigned int reg_iop_sw_spu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12 + +/* Register rs_mc_data, scope iop_sw_spu, type rs */ +typedef unsigned int reg_iop_sw_spu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16 + +/* Register r_mc_data, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_mc_data; +#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20 + +/* Register r_mc_stat, scope iop_sw_spu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu : 1; + unsigned int dummy1 : 26; +} reg_iop_sw_spu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24 + +/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28 + +/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 + +/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus_oe_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 + +/* Register r_bus_in, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_bus_in; +#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44 + +/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48 + +/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 + +/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 + +/* Register r_gio_in, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_gio_in; +#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64 + +/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 + +/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 + +/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 + +/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 + +/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 + +/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 + +/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 + +/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 + +/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 + +/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 + +/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 + +/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 + +/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_cpu_intr; +#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116 +#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116 + +/* Register r_cpu_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_r_cpu_intr; +#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120 + +/* Register r_hw_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out : 1; + unsigned int fifo_out_extra : 1; + unsigned int fifo_in : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_out : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_r_hw_intr; +#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124 + +/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_mpu_intr; +#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128 +#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128 + +/* Register r_mpu_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_r_mpu_intr; +#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132 + + +/* Constants */ +enum { + regk_iop_sw_spu_copy = 0x00000000, + regk_iop_sw_spu_no = 0x00000000, + regk_iop_sw_spu_nop = 0x00000000, + regk_iop_sw_spu_rd = 0x00000002, + regk_iop_sw_spu_reg_copy = 0x00000001, + regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_spu_set = 0x00000001, + regk_iop_sw_spu_wr = 0x00000003, + regk_iop_sw_spu_yes = 0x00000001 +}; +#endif /* __iop_sw_spu_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h new file mode 100644 index 00000000000..20de425e652 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h @@ -0,0 +1,96 @@ +#ifndef __iop_version_defs_h +#define __iop_version_defs_h + +/* + * This file is autogenerated from + * file: iop_version.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_version */ + +/* Register r_version, scope iop_version, type r */ +typedef struct { + unsigned int nr : 8; + unsigned int dummy1 : 24; +} reg_iop_version_r_version; +#define REG_RD_ADDR_iop_version_r_version 0 + + +/* Constants */ +enum { + regk_iop_version_v2_0 = 0x00000002 +}; +#endif /* __iop_version_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h new file mode 100644 index 00000000000..243ac3c882c --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h @@ -0,0 +1,142 @@ +#ifndef __l2cache_defs_h +#define __l2cache_defs_h + +/* + * This file is autogenerated from + * file: l2cache.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope l2cache */ + +/* Register rw_cfg, scope l2cache, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_l2cache_rw_cfg; +#define REG_RD_ADDR_l2cache_rw_cfg 0 +#define REG_WR_ADDR_l2cache_rw_cfg 0 + +/* Register rw_ctrl, scope l2cache, type rw */ +typedef struct { + unsigned int dummy1 : 7; + unsigned int cbase : 9; + unsigned int dummy2 : 4; + unsigned int csize : 10; + unsigned int dummy3 : 2; +} reg_l2cache_rw_ctrl; +#define REG_RD_ADDR_l2cache_rw_ctrl 4 +#define REG_WR_ADDR_l2cache_rw_ctrl 4 + +/* Register rw_idxop, scope l2cache, type rw */ +typedef struct { + unsigned int idx : 10; + unsigned int dummy1 : 14; + unsigned int way : 3; + unsigned int dummy2 : 2; + unsigned int cmd : 3; +} reg_l2cache_rw_idxop; +#define REG_RD_ADDR_l2cache_rw_idxop 8 +#define REG_WR_ADDR_l2cache_rw_idxop 8 + +/* Register rw_addrop_addr, scope l2cache, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_l2cache_rw_addrop_addr; +#define REG_RD_ADDR_l2cache_rw_addrop_addr 12 +#define REG_WR_ADDR_l2cache_rw_addrop_addr 12 + +/* Register rw_addrop_ctrl, scope l2cache, type rw */ +typedef struct { + unsigned int size : 16; + unsigned int dummy1 : 13; + unsigned int cmd : 3; +} reg_l2cache_rw_addrop_ctrl; +#define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16 +#define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16 + + +/* Constants */ +enum { + regk_l2cache_flush = 0x00000001, + regk_l2cache_no = 0x00000000, + regk_l2cache_rw_addrop_addr_default = 0x00000000, + regk_l2cache_rw_addrop_ctrl_default = 0x00000000, + regk_l2cache_rw_cfg_default = 0x00000000, + regk_l2cache_rw_ctrl_default = 0x00000000, + regk_l2cache_rw_idxop_default = 0x00000000, + regk_l2cache_yes = 0x00000001 +}; +#endif /* __l2cache_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h new file mode 100644 index 00000000000..c0e7628cbf7 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h @@ -0,0 +1,482 @@ +#ifndef __marb_bar_defs_h +#define __marb_bar_defs_h + +/* + * This file is autogenerated from + * file: marb_bar.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_bar */ + +#define STRIDE_marb_bar_rw_ddr2_slots 4 +/* Register rw_ddr2_slots, scope marb_bar, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_bar_rw_ddr2_slots; +#define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0 +#define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0 + +/* Register rw_h264_rd_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_h264_rd_burst; +#define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256 +#define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256 + +/* Register rw_h264_wr_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_h264_wr_burst; +#define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260 +#define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260 + +/* Register rw_ccd_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_ccd_burst; +#define REG_RD_ADDR_marb_bar_rw_ccd_burst 264 +#define REG_WR_ADDR_marb_bar_rw_ccd_burst 264 + +/* Register rw_vin_wr_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_vin_wr_burst; +#define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268 +#define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268 + +/* Register rw_vin_rd_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_vin_rd_burst; +#define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272 +#define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272 + +/* Register rw_sclr_rd_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_sclr_rd_burst; +#define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276 +#define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276 + +/* Register rw_vout_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_vout_burst; +#define REG_RD_ADDR_marb_bar_rw_vout_burst 280 +#define REG_WR_ADDR_marb_bar_rw_vout_burst 280 + +/* Register rw_sclr_fifo_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_sclr_fifo_burst; +#define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284 +#define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284 + +/* Register rw_l2cache_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_l2cache_burst; +#define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288 +#define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288 + +/* Register rw_intr_mask, scope marb_bar, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_bar_rw_intr_mask; +#define REG_RD_ADDR_marb_bar_rw_intr_mask 292 +#define REG_WR_ADDR_marb_bar_rw_intr_mask 292 + +/* Register rw_ack_intr, scope marb_bar, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_bar_rw_ack_intr; +#define REG_RD_ADDR_marb_bar_rw_ack_intr 296 +#define REG_WR_ADDR_marb_bar_rw_ack_intr 296 + +/* Register r_intr, scope marb_bar, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_bar_r_intr; +#define REG_RD_ADDR_marb_bar_r_intr 300 + +/* Register r_masked_intr, scope marb_bar, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_bar_r_masked_intr; +#define REG_RD_ADDR_marb_bar_r_masked_intr 304 + +/* Register rw_stop_mask, scope marb_bar, type rw */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_rw_stop_mask; +#define REG_RD_ADDR_marb_bar_rw_stop_mask 308 +#define REG_WR_ADDR_marb_bar_rw_stop_mask 308 + +/* Register r_stopped, scope marb_bar, type r */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_r_stopped; +#define REG_RD_ADDR_marb_bar_r_stopped 312 + +/* Register rw_no_snoop, scope marb_bar, type rw */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_rw_no_snoop; +#define REG_RD_ADDR_marb_bar_rw_no_snoop 576 +#define REG_WR_ADDR_marb_bar_rw_no_snoop 576 + + +/* Constants */ +enum { + regk_marb_bar_ccd = 0x00000002, + regk_marb_bar_h264_rd = 0x00000000, + regk_marb_bar_h264_wr = 0x00000001, + regk_marb_bar_l2cache = 0x00000008, + regk_marb_bar_no = 0x00000000, + regk_marb_bar_r_stopped_default = 0x00000000, + regk_marb_bar_rw_ccd_burst_default = 0x00000000, + regk_marb_bar_rw_ddr2_slots_default = 0x00000000, + regk_marb_bar_rw_ddr2_slots_size = 0x00000040, + regk_marb_bar_rw_h264_rd_burst_default = 0x00000000, + regk_marb_bar_rw_h264_wr_burst_default = 0x00000000, + regk_marb_bar_rw_intr_mask_default = 0x00000000, + regk_marb_bar_rw_l2cache_burst_default = 0x00000000, + regk_marb_bar_rw_no_snoop_default = 0x00000000, + regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000, + regk_marb_bar_rw_sclr_rd_burst_default = 0x00000000, + regk_marb_bar_rw_stop_mask_default = 0x00000000, + regk_marb_bar_rw_vin_rd_burst_default = 0x00000000, + regk_marb_bar_rw_vin_wr_burst_default = 0x00000000, + regk_marb_bar_rw_vout_burst_default = 0x00000000, + regk_marb_bar_sclr_fifo = 0x00000007, + regk_marb_bar_sclr_rd = 0x00000005, + regk_marb_bar_vin_rd = 0x00000004, + regk_marb_bar_vin_wr = 0x00000003, + regk_marb_bar_vout = 0x00000006, + regk_marb_bar_yes = 0x00000001 +}; +#endif /* __marb_bar_defs_h */ +#ifndef __marb_bar_bp_defs_h +#define __marb_bar_bp_defs_h + +/* + * This file is autogenerated from + * file: marb_bar.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_bar_bp */ + +/* Register rw_first_addr, scope marb_bar_bp, type rw */ +typedef unsigned int reg_marb_bar_bp_rw_first_addr; +#define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_bar_bp, type rw */ +typedef unsigned int reg_marb_bar_bp_rw_last_addr; +#define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_bar_bp, type rw */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bar_bp_rw_op; +#define REG_RD_ADDR_marb_bar_bp_rw_op 8 +#define REG_WR_ADDR_marb_bar_bp_rw_op 8 + +/* Register rw_clients, scope marb_bar_bp, type rw */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_bp_rw_clients; +#define REG_RD_ADDR_marb_bar_bp_rw_clients 12 +#define REG_WR_ADDR_marb_bar_bp_rw_clients 12 + +/* Register rw_options, scope marb_bar_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_bar_bp_rw_options; +#define REG_RD_ADDR_marb_bar_bp_rw_options 16 +#define REG_WR_ADDR_marb_bar_bp_rw_options 16 + +/* Register r_brk_addr, scope marb_bar_bp, type r */ +typedef unsigned int reg_marb_bar_bp_r_brk_addr; +#define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20 + +/* Register r_brk_op, scope marb_bar_bp, type r */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bar_bp_r_brk_op; +#define REG_RD_ADDR_marb_bar_bp_r_brk_op 24 + +/* Register r_brk_clients, scope marb_bar_bp, type r */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_bp_r_brk_clients; +#define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28 + +/* Register r_brk_first_client, scope marb_bar_bp, type r */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_bp_r_brk_first_client; +#define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32 + +/* Register r_brk_size, scope marb_bar_bp, type r */ +typedef unsigned int reg_marb_bar_bp_r_brk_size; +#define REG_RD_ADDR_marb_bar_bp_r_brk_size 36 + +/* Register rw_ack, scope marb_bar_bp, type rw */ +typedef unsigned int reg_marb_bar_bp_rw_ack; +#define REG_RD_ADDR_marb_bar_bp_rw_ack 40 +#define REG_WR_ADDR_marb_bar_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_bar_bp_no = 0x00000000, + regk_marb_bar_bp_rw_op_default = 0x00000000, + regk_marb_bar_bp_rw_options_default = 0x00000000, + regk_marb_bar_bp_yes = 0x00000001 +}; +#endif /* __marb_bar_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h new file mode 100644 index 00000000000..2baa833f109 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h @@ -0,0 +1,626 @@ +#ifndef __marb_foo_defs_h +#define __marb_foo_defs_h + +/* + * This file is autogenerated from + * file: marb_foo.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_foo */ + +#define STRIDE_marb_foo_rw_intm_slots 4 +/* Register rw_intm_slots, scope marb_foo, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_intm_slots; +#define REG_RD_ADDR_marb_foo_rw_intm_slots 0 +#define REG_WR_ADDR_marb_foo_rw_intm_slots 0 + +#define STRIDE_marb_foo_rw_l2_slots 4 +/* Register rw_l2_slots, scope marb_foo, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_l2_slots; +#define REG_RD_ADDR_marb_foo_rw_l2_slots 256 +#define REG_WR_ADDR_marb_foo_rw_l2_slots 256 + +#define STRIDE_marb_foo_rw_regs_slots 4 +/* Register rw_regs_slots, scope marb_foo, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_regs_slots; +#define REG_RD_ADDR_marb_foo_rw_regs_slots 512 +#define REG_WR_ADDR_marb_foo_rw_regs_slots 512 + +/* Register rw_sclr_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_sclr_burst; +#define REG_RD_ADDR_marb_foo_rw_sclr_burst 528 +#define REG_WR_ADDR_marb_foo_rw_sclr_burst 528 + +/* Register rw_dma0_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma0_burst; +#define REG_RD_ADDR_marb_foo_rw_dma0_burst 532 +#define REG_WR_ADDR_marb_foo_rw_dma0_burst 532 + +/* Register rw_dma1_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma1_burst; +#define REG_RD_ADDR_marb_foo_rw_dma1_burst 536 +#define REG_WR_ADDR_marb_foo_rw_dma1_burst 536 + +/* Register rw_dma2_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma2_burst; +#define REG_RD_ADDR_marb_foo_rw_dma2_burst 540 +#define REG_WR_ADDR_marb_foo_rw_dma2_burst 540 + +/* Register rw_dma3_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma3_burst; +#define REG_RD_ADDR_marb_foo_rw_dma3_burst 544 +#define REG_WR_ADDR_marb_foo_rw_dma3_burst 544 + +/* Register rw_dma4_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma4_burst; +#define REG_RD_ADDR_marb_foo_rw_dma4_burst 548 +#define REG_WR_ADDR_marb_foo_rw_dma4_burst 548 + +/* Register rw_dma5_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma5_burst; +#define REG_RD_ADDR_marb_foo_rw_dma5_burst 552 +#define REG_WR_ADDR_marb_foo_rw_dma5_burst 552 + +/* Register rw_dma6_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma6_burst; +#define REG_RD_ADDR_marb_foo_rw_dma6_burst 556 +#define REG_WR_ADDR_marb_foo_rw_dma6_burst 556 + +/* Register rw_dma7_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma7_burst; +#define REG_RD_ADDR_marb_foo_rw_dma7_burst 560 +#define REG_WR_ADDR_marb_foo_rw_dma7_burst 560 + +/* Register rw_dma9_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma9_burst; +#define REG_RD_ADDR_marb_foo_rw_dma9_burst 564 +#define REG_WR_ADDR_marb_foo_rw_dma9_burst 564 + +/* Register rw_dma11_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma11_burst; +#define REG_RD_ADDR_marb_foo_rw_dma11_burst 568 +#define REG_WR_ADDR_marb_foo_rw_dma11_burst 568 + +/* Register rw_cpui_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_cpui_burst; +#define REG_RD_ADDR_marb_foo_rw_cpui_burst 572 +#define REG_WR_ADDR_marb_foo_rw_cpui_burst 572 + +/* Register rw_cpud_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_cpud_burst; +#define REG_RD_ADDR_marb_foo_rw_cpud_burst 576 +#define REG_WR_ADDR_marb_foo_rw_cpud_burst 576 + +/* Register rw_iop_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_iop_burst; +#define REG_RD_ADDR_marb_foo_rw_iop_burst 580 +#define REG_WR_ADDR_marb_foo_rw_iop_burst 580 + +/* Register rw_ccdstat_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_ccdstat_burst; +#define REG_RD_ADDR_marb_foo_rw_ccdstat_burst 584 +#define REG_WR_ADDR_marb_foo_rw_ccdstat_burst 584 + +/* Register rw_intr_mask, scope marb_foo, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_intr_mask; +#define REG_RD_ADDR_marb_foo_rw_intr_mask 588 +#define REG_WR_ADDR_marb_foo_rw_intr_mask 588 + +/* Register rw_ack_intr, scope marb_foo, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_ack_intr; +#define REG_RD_ADDR_marb_foo_rw_ack_intr 592 +#define REG_WR_ADDR_marb_foo_rw_ack_intr 592 + +/* Register r_intr, scope marb_foo, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_foo_r_intr; +#define REG_RD_ADDR_marb_foo_r_intr 596 + +/* Register r_masked_intr, scope marb_foo, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_foo_r_masked_intr; +#define REG_RD_ADDR_marb_foo_r_masked_intr 600 + +/* Register rw_stop_mask, scope marb_foo, type rw */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_rw_stop_mask; +#define REG_RD_ADDR_marb_foo_rw_stop_mask 604 +#define REG_WR_ADDR_marb_foo_rw_stop_mask 604 + +/* Register r_stopped, scope marb_foo, type r */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_r_stopped; +#define REG_RD_ADDR_marb_foo_r_stopped 608 + +/* Register rw_no_snoop, scope marb_foo, type rw */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_rw_no_snoop; +#define REG_RD_ADDR_marb_foo_rw_no_snoop 896 +#define REG_WR_ADDR_marb_foo_rw_no_snoop 896 + +/* Register rw_no_snoop_rq, scope marb_foo, type rw */ +typedef struct { + unsigned int dummy1 : 11; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int dummy2 : 19; +} reg_marb_foo_rw_no_snoop_rq; +#define REG_RD_ADDR_marb_foo_rw_no_snoop_rq 900 +#define REG_WR_ADDR_marb_foo_rw_no_snoop_rq 900 + + +/* Constants */ +enum { + regk_marb_foo_ccdstat = 0x0000000e, + regk_marb_foo_cpud = 0x0000000c, + regk_marb_foo_cpui = 0x0000000b, + regk_marb_foo_dma0 = 0x00000001, + regk_marb_foo_dma1 = 0x00000002, + regk_marb_foo_dma11 = 0x0000000a, + regk_marb_foo_dma2 = 0x00000003, + regk_marb_foo_dma3 = 0x00000004, + regk_marb_foo_dma4 = 0x00000005, + regk_marb_foo_dma5 = 0x00000006, + regk_marb_foo_dma6 = 0x00000007, + regk_marb_foo_dma7 = 0x00000008, + regk_marb_foo_dma9 = 0x00000009, + regk_marb_foo_iop = 0x0000000d, + regk_marb_foo_no = 0x00000000, + regk_marb_foo_r_stopped_default = 0x00000000, + regk_marb_foo_rw_ccdstat_burst_default = 0x00000000, + regk_marb_foo_rw_cpud_burst_default = 0x00000000, + regk_marb_foo_rw_cpui_burst_default = 0x00000000, + regk_marb_foo_rw_dma0_burst_default = 0x00000000, + regk_marb_foo_rw_dma11_burst_default = 0x00000000, + regk_marb_foo_rw_dma1_burst_default = 0x00000000, + regk_marb_foo_rw_dma2_burst_default = 0x00000000, + regk_marb_foo_rw_dma3_burst_default = 0x00000000, + regk_marb_foo_rw_dma4_burst_default = 0x00000000, + regk_marb_foo_rw_dma5_burst_default = 0x00000000, + regk_marb_foo_rw_dma6_burst_default = 0x00000000, + regk_marb_foo_rw_dma7_burst_default = 0x00000000, + regk_marb_foo_rw_dma9_burst_default = 0x00000000, + regk_marb_foo_rw_intm_slots_default = 0x00000000, + regk_marb_foo_rw_intm_slots_size = 0x00000040, + regk_marb_foo_rw_intr_mask_default = 0x00000000, + regk_marb_foo_rw_iop_burst_default = 0x00000000, + regk_marb_foo_rw_l2_slots_default = 0x00000000, + regk_marb_foo_rw_l2_slots_size = 0x00000040, + regk_marb_foo_rw_no_snoop_default = 0x00000000, + regk_marb_foo_rw_no_snoop_rq_default = 0x00000000, + regk_marb_foo_rw_regs_slots_default = 0x00000000, + regk_marb_foo_rw_regs_slots_size = 0x00000004, + regk_marb_foo_rw_sclr_burst_default = 0x00000000, + regk_marb_foo_rw_stop_mask_default = 0x00000000, + regk_marb_foo_sclr = 0x00000000, + regk_marb_foo_yes = 0x00000001 +}; +#endif /* __marb_foo_defs_h */ +#ifndef __marb_foo_bp_defs_h +#define __marb_foo_bp_defs_h + +/* + * This file is autogenerated from + * file: marb_foo.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_foo_bp */ + +/* Register rw_first_addr, scope marb_foo_bp, type rw */ +typedef unsigned int reg_marb_foo_bp_rw_first_addr; +#define REG_RD_ADDR_marb_foo_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_foo_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_foo_bp, type rw */ +typedef unsigned int reg_marb_foo_bp_rw_last_addr; +#define REG_RD_ADDR_marb_foo_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_foo_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_foo_bp, type rw */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_foo_bp_rw_op; +#define REG_RD_ADDR_marb_foo_bp_rw_op 8 +#define REG_WR_ADDR_marb_foo_bp_rw_op 8 + +/* Register rw_clients, scope marb_foo_bp, type rw */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_bp_rw_clients; +#define REG_RD_ADDR_marb_foo_bp_rw_clients 12 +#define REG_WR_ADDR_marb_foo_bp_rw_clients 12 + +/* Register rw_options, scope marb_foo_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_foo_bp_rw_options; +#define REG_RD_ADDR_marb_foo_bp_rw_options 16 +#define REG_WR_ADDR_marb_foo_bp_rw_options 16 + +/* Register r_brk_addr, scope marb_foo_bp, type r */ +typedef unsigned int reg_marb_foo_bp_r_brk_addr; +#define REG_RD_ADDR_marb_foo_bp_r_brk_addr 20 + +/* Register r_brk_op, scope marb_foo_bp, type r */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_foo_bp_r_brk_op; +#define REG_RD_ADDR_marb_foo_bp_r_brk_op 24 + +/* Register r_brk_clients, scope marb_foo_bp, type r */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_bp_r_brk_clients; +#define REG_RD_ADDR_marb_foo_bp_r_brk_clients 28 + +/* Register r_brk_first_client, scope marb_foo_bp, type r */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_bp_r_brk_first_client; +#define REG_RD_ADDR_marb_foo_bp_r_brk_first_client 32 + +/* Register r_brk_size, scope marb_foo_bp, type r */ +typedef unsigned int reg_marb_foo_bp_r_brk_size; +#define REG_RD_ADDR_marb_foo_bp_r_brk_size 36 + +/* Register rw_ack, scope marb_foo_bp, type rw */ +typedef unsigned int reg_marb_foo_bp_rw_ack; +#define REG_RD_ADDR_marb_foo_bp_rw_ack 40 +#define REG_WR_ADDR_marb_foo_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_foo_bp_no = 0x00000000, + regk_marb_foo_bp_rw_op_default = 0x00000000, + regk_marb_foo_bp_rw_options_default = 0x00000000, + regk_marb_foo_bp_yes = 0x00000001 +}; +#endif /* __marb_foo_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h new file mode 100644 index 00000000000..4b96cd2cba8 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h @@ -0,0 +1,312 @@ +#ifndef __pinmux_defs_h +#define __pinmux_defs_h + +/* + * This file is autogenerated from + * file: pinmux.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile pinmux_defs.h pinmux.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope pinmux */ + +/* Register rw_hwprot, scope pinmux, type rw */ +typedef struct { + unsigned int eth : 1; + unsigned int eth_mdio : 1; + unsigned int geth : 1; + unsigned int tg : 1; + unsigned int tg_clk : 1; + unsigned int vout : 1; + unsigned int vout_sync : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int ser4 : 1; + unsigned int sser : 1; + unsigned int pwm0 : 1; + unsigned int pwm1 : 1; + unsigned int pwm2 : 1; + unsigned int timer0 : 1; + unsigned int timer1 : 1; + unsigned int pio : 1; + unsigned int i2c0 : 1; + unsigned int i2c1 : 1; + unsigned int i2c1_sda1 : 1; + unsigned int i2c1_sda2 : 1; + unsigned int i2c1_sda3 : 1; + unsigned int i2c1_sen : 1; + unsigned int dummy1 : 8; +} reg_pinmux_rw_hwprot; +#define REG_RD_ADDR_pinmux_rw_hwprot 0 +#define REG_WR_ADDR_pinmux_rw_hwprot 0 + +/* Register rw_gio_pa, scope pinmux, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int pa8 : 1; + unsigned int pa9 : 1; + unsigned int pa10 : 1; + unsigned int pa11 : 1; + unsigned int pa12 : 1; + unsigned int pa13 : 1; + unsigned int pa14 : 1; + unsigned int pa15 : 1; + unsigned int pa16 : 1; + unsigned int pa17 : 1; + unsigned int pa18 : 1; + unsigned int pa19 : 1; + unsigned int pa20 : 1; + unsigned int pa21 : 1; + unsigned int pa22 : 1; + unsigned int pa23 : 1; + unsigned int pa24 : 1; + unsigned int pa25 : 1; + unsigned int pa26 : 1; + unsigned int pa27 : 1; + unsigned int pa28 : 1; + unsigned int pa29 : 1; + unsigned int pa30 : 1; + unsigned int pa31 : 1; +} reg_pinmux_rw_gio_pa; +#define REG_RD_ADDR_pinmux_rw_gio_pa 4 +#define REG_WR_ADDR_pinmux_rw_gio_pa 4 + +/* Register rw_gio_pb, scope pinmux, type rw */ +typedef struct { + unsigned int pb0 : 1; + unsigned int pb1 : 1; + unsigned int pb2 : 1; + unsigned int pb3 : 1; + unsigned int pb4 : 1; + unsigned int pb5 : 1; + unsigned int pb6 : 1; + unsigned int pb7 : 1; + unsigned int pb8 : 1; + unsigned int pb9 : 1; + unsigned int pb10 : 1; + unsigned int pb11 : 1; + unsigned int pb12 : 1; + unsigned int pb13 : 1; + unsigned int pb14 : 1; + unsigned int pb15 : 1; + unsigned int pb16 : 1; + unsigned int pb17 : 1; + unsigned int pb18 : 1; + unsigned int pb19 : 1; + unsigned int pb20 : 1; + unsigned int pb21 : 1; + unsigned int pb22 : 1; + unsigned int pb23 : 1; + unsigned int pb24 : 1; + unsigned int pb25 : 1; + unsigned int pb26 : 1; + unsigned int pb27 : 1; + unsigned int pb28 : 1; + unsigned int pb29 : 1; + unsigned int pb30 : 1; + unsigned int pb31 : 1; +} reg_pinmux_rw_gio_pb; +#define REG_RD_ADDR_pinmux_rw_gio_pb 8 +#define REG_WR_ADDR_pinmux_rw_gio_pb 8 + +/* Register rw_gio_pc, scope pinmux, type rw */ +typedef struct { + unsigned int pc0 : 1; + unsigned int pc1 : 1; + unsigned int pc2 : 1; + unsigned int pc3 : 1; + unsigned int pc4 : 1; + unsigned int pc5 : 1; + unsigned int pc6 : 1; + unsigned int pc7 : 1; + unsigned int pc8 : 1; + unsigned int pc9 : 1; + unsigned int pc10 : 1; + unsigned int pc11 : 1; + unsigned int pc12 : 1; + unsigned int pc13 : 1; + unsigned int pc14 : 1; + unsigned int pc15 : 1; + unsigned int dummy1 : 16; +} reg_pinmux_rw_gio_pc; +#define REG_RD_ADDR_pinmux_rw_gio_pc 12 +#define REG_WR_ADDR_pinmux_rw_gio_pc 12 + +/* Register rw_iop_pa, scope pinmux, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int pa8 : 1; + unsigned int pa9 : 1; + unsigned int pa10 : 1; + unsigned int pa11 : 1; + unsigned int pa12 : 1; + unsigned int pa13 : 1; + unsigned int pa14 : 1; + unsigned int pa15 : 1; + unsigned int pa16 : 1; + unsigned int pa17 : 1; + unsigned int pa18 : 1; + unsigned int pa19 : 1; + unsigned int pa20 : 1; + unsigned int pa21 : 1; + unsigned int pa22 : 1; + unsigned int pa23 : 1; + unsigned int pa24 : 1; + unsigned int pa25 : 1; + unsigned int pa26 : 1; + unsigned int pa27 : 1; + unsigned int pa28 : 1; + unsigned int pa29 : 1; + unsigned int pa30 : 1; + unsigned int pa31 : 1; +} reg_pinmux_rw_iop_pa; +#define REG_RD_ADDR_pinmux_rw_iop_pa 16 +#define REG_WR_ADDR_pinmux_rw_iop_pa 16 + +/* Register rw_iop_pb, scope pinmux, type rw */ +typedef struct { + unsigned int pb0 : 1; + unsigned int pb1 : 1; + unsigned int pb2 : 1; + unsigned int pb3 : 1; + unsigned int pb4 : 1; + unsigned int pb5 : 1; + unsigned int pb6 : 1; + unsigned int pb7 : 1; + unsigned int dummy1 : 24; +} reg_pinmux_rw_iop_pb; +#define REG_RD_ADDR_pinmux_rw_iop_pb 20 +#define REG_WR_ADDR_pinmux_rw_iop_pb 20 + +/* Register rw_iop_pio, scope pinmux, type rw */ +typedef struct { + unsigned int d0 : 1; + unsigned int d1 : 1; + unsigned int d2 : 1; + unsigned int d3 : 1; + unsigned int d4 : 1; + unsigned int d5 : 1; + unsigned int d6 : 1; + unsigned int d7 : 1; + unsigned int rd_n : 1; + unsigned int wr_n : 1; + unsigned int a0 : 1; + unsigned int a1 : 1; + unsigned int ce0_n : 1; + unsigned int ce1_n : 1; + unsigned int ce2_n : 1; + unsigned int rdy : 1; + unsigned int dummy1 : 16; +} reg_pinmux_rw_iop_pio; +#define REG_RD_ADDR_pinmux_rw_iop_pio 24 +#define REG_WR_ADDR_pinmux_rw_iop_pio 24 + +/* Register rw_iop_usb, scope pinmux, type rw */ +typedef struct { + unsigned int usb0 : 1; + unsigned int dummy1 : 31; +} reg_pinmux_rw_iop_usb; +#define REG_RD_ADDR_pinmux_rw_iop_usb 28 +#define REG_WR_ADDR_pinmux_rw_iop_usb 28 + + +/* Constants */ +enum { + regk_pinmux_no = 0x00000000, + regk_pinmux_rw_gio_pa_default = 0x00000000, + regk_pinmux_rw_gio_pb_default = 0x00000000, + regk_pinmux_rw_gio_pc_default = 0x00000000, + regk_pinmux_rw_hwprot_default = 0x00000000, + regk_pinmux_rw_iop_pa_default = 0x00000000, + regk_pinmux_rw_iop_pb_default = 0x00000000, + regk_pinmux_rw_iop_pio_default = 0x00000000, + regk_pinmux_rw_iop_usb_default = 0x00000001, + regk_pinmux_yes = 0x00000001 +}; +#endif /* __pinmux_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h new file mode 100644 index 00000000000..2d8e4b4cc60 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h @@ -0,0 +1,371 @@ +#ifndef __pio_defs_h +#define __pio_defs_h + +/* + * This file is autogenerated from + * file: pio.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile pio_defs.h pio.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope pio */ + +/* Register rw_data, scope pio, type rw */ +typedef unsigned int reg_pio_rw_data; +#define REG_RD_ADDR_pio_rw_data 64 +#define REG_WR_ADDR_pio_rw_data 64 + +/* Register rw_io_access0, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access0; +#define REG_RD_ADDR_pio_rw_io_access0 0 +#define REG_WR_ADDR_pio_rw_io_access0 0 + +/* Register rw_io_access1, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access1; +#define REG_RD_ADDR_pio_rw_io_access1 4 +#define REG_WR_ADDR_pio_rw_io_access1 4 + +/* Register rw_io_access2, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access2; +#define REG_RD_ADDR_pio_rw_io_access2 8 +#define REG_WR_ADDR_pio_rw_io_access2 8 + +/* Register rw_io_access3, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access3; +#define REG_RD_ADDR_pio_rw_io_access3 12 +#define REG_WR_ADDR_pio_rw_io_access3 12 + +/* Register rw_io_access4, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access4; +#define REG_RD_ADDR_pio_rw_io_access4 16 +#define REG_WR_ADDR_pio_rw_io_access4 16 + +/* Register rw_io_access5, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access5; +#define REG_RD_ADDR_pio_rw_io_access5 20 +#define REG_WR_ADDR_pio_rw_io_access5 20 + +/* Register rw_io_access6, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access6; +#define REG_RD_ADDR_pio_rw_io_access6 24 +#define REG_WR_ADDR_pio_rw_io_access6 24 + +/* Register rw_io_access7, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access7; +#define REG_RD_ADDR_pio_rw_io_access7 28 +#define REG_WR_ADDR_pio_rw_io_access7 28 + +/* Register rw_io_access8, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access8; +#define REG_RD_ADDR_pio_rw_io_access8 32 +#define REG_WR_ADDR_pio_rw_io_access8 32 + +/* Register rw_io_access9, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access9; +#define REG_RD_ADDR_pio_rw_io_access9 36 +#define REG_WR_ADDR_pio_rw_io_access9 36 + +/* Register rw_io_access10, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access10; +#define REG_RD_ADDR_pio_rw_io_access10 40 +#define REG_WR_ADDR_pio_rw_io_access10 40 + +/* Register rw_io_access11, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access11; +#define REG_RD_ADDR_pio_rw_io_access11 44 +#define REG_WR_ADDR_pio_rw_io_access11 44 + +/* Register rw_io_access12, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access12; +#define REG_RD_ADDR_pio_rw_io_access12 48 +#define REG_WR_ADDR_pio_rw_io_access12 48 + +/* Register rw_io_access13, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access13; +#define REG_RD_ADDR_pio_rw_io_access13 52 +#define REG_WR_ADDR_pio_rw_io_access13 52 + +/* Register rw_io_access14, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access14; +#define REG_RD_ADDR_pio_rw_io_access14 56 +#define REG_WR_ADDR_pio_rw_io_access14 56 + +/* Register rw_io_access15, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access15; +#define REG_RD_ADDR_pio_rw_io_access15 60 +#define REG_WR_ADDR_pio_rw_io_access15 60 + +/* Register rw_ce0_cfg, scope pio, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int mode : 2; + unsigned int dummy1 : 16; +} reg_pio_rw_ce0_cfg; +#define REG_RD_ADDR_pio_rw_ce0_cfg 68 +#define REG_WR_ADDR_pio_rw_ce0_cfg 68 + +/* Register rw_ce1_cfg, scope pio, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int mode : 2; + unsigned int dummy1 : 16; +} reg_pio_rw_ce1_cfg; +#define REG_RD_ADDR_pio_rw_ce1_cfg 72 +#define REG_WR_ADDR_pio_rw_ce1_cfg 72 + +/* Register rw_ce2_cfg, scope pio, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int mode : 2; + unsigned int dummy1 : 16; +} reg_pio_rw_ce2_cfg; +#define REG_RD_ADDR_pio_rw_ce2_cfg 76 +#define REG_WR_ADDR_pio_rw_ce2_cfg 76 + +/* Register rw_dout, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int rd_n : 1; + unsigned int wr_n : 1; + unsigned int a0 : 1; + unsigned int a1 : 1; + unsigned int ce0_n : 1; + unsigned int ce1_n : 1; + unsigned int ce2_n : 1; + unsigned int rdy : 1; + unsigned int dummy1 : 16; +} reg_pio_rw_dout; +#define REG_RD_ADDR_pio_rw_dout 80 +#define REG_WR_ADDR_pio_rw_dout 80 + +/* Register rw_oe, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int rd_n : 1; + unsigned int wr_n : 1; + unsigned int a0 : 1; + unsigned int a1 : 1; + unsigned int ce0_n : 1; + unsigned int ce1_n : 1; + unsigned int ce2_n : 1; + unsigned int rdy : 1; + unsigned int dummy1 : 16; +} reg_pio_rw_oe; +#define REG_RD_ADDR_pio_rw_oe 84 +#define REG_WR_ADDR_pio_rw_oe 84 + +/* Register rw_man_ctrl, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int rd_n : 1; + unsigned int wr_n : 1; + unsigned int a0 : 1; + unsigned int a1 : 1; + unsigned int ce0_n : 1; + unsigned int ce1_n : 1; + unsigned int ce2_n : 1; + unsigned int rdy : 1; + unsigned int dummy1 : 16; +} reg_pio_rw_man_ctrl; +#define REG_RD_ADDR_pio_rw_man_ctrl 88 +#define REG_WR_ADDR_pio_rw_man_ctrl 88 + +/* Register r_din, scope pio, type r */ +typedef struct { + unsigned int data : 8; + unsigned int rd_n : 1; + unsigned int wr_n : 1; + unsigned int a0 : 1; + unsigned int a1 : 1; + unsigned int ce0_n : 1; + unsigned int ce1_n : 1; + unsigned int ce2_n : 1; + unsigned int rdy : 1; + unsigned int dummy1 : 16; +} reg_pio_r_din; +#define REG_RD_ADDR_pio_r_din 92 + +/* Register r_stat, scope pio, type r */ +typedef struct { + unsigned int busy : 1; + unsigned int dummy1 : 31; +} reg_pio_r_stat; +#define REG_RD_ADDR_pio_r_stat 96 + +/* Register rw_intr_mask, scope pio, type rw */ +typedef struct { + unsigned int rdy : 1; + unsigned int dummy1 : 31; +} reg_pio_rw_intr_mask; +#define REG_RD_ADDR_pio_rw_intr_mask 100 +#define REG_WR_ADDR_pio_rw_intr_mask 100 + +/* Register rw_ack_intr, scope pio, type rw */ +typedef struct { + unsigned int rdy : 1; + unsigned int dummy1 : 31; +} reg_pio_rw_ack_intr; +#define REG_RD_ADDR_pio_rw_ack_intr 104 +#define REG_WR_ADDR_pio_rw_ack_intr 104 + +/* Register r_intr, scope pio, type r */ +typedef struct { + unsigned int rdy : 1; + unsigned int dummy1 : 31; +} reg_pio_r_intr; +#define REG_RD_ADDR_pio_r_intr 108 + +/* Register r_masked_intr, scope pio, type r */ +typedef struct { + unsigned int rdy : 1; + unsigned int dummy1 : 31; +} reg_pio_r_masked_intr; +#define REG_RD_ADDR_pio_r_masked_intr 112 + + +/* Constants */ +enum { + regk_pio_a2 = 0x00000003, + regk_pio_no = 0x00000000, + regk_pio_normal = 0x00000000, + regk_pio_rd = 0x00000001, + regk_pio_rw_ce0_cfg_default = 0x00000000, + regk_pio_rw_ce1_cfg_default = 0x00000000, + regk_pio_rw_ce2_cfg_default = 0x00000000, + regk_pio_rw_intr_mask_default = 0x00000000, + regk_pio_rw_man_ctrl_default = 0x00000000, + regk_pio_rw_oe_default = 0x00000000, + regk_pio_wr = 0x00000002, + regk_pio_wr_ce2 = 0x00000003, + regk_pio_yes = 0x00000001, + regk_pio_yes_all = 0x000000ff +}; +#endif /* __pio_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h b/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h new file mode 100644 index 00000000000..36e59d6e96b --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h @@ -0,0 +1,103 @@ +#ifndef __reg_map_h +#define __reg_map_h + +/* + * This file is autogenerated from + * file: reg.rmap + * + * by ../../../tools/rdesc/bin/rdes2c -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map.h reg.rmap + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +typedef enum { + regi_ccd = 0xb0000000, + regi_ccd_top = 0xb0000000, + regi_ccd_dp = 0xb0000400, + regi_ccd_stat = 0xb0000800, + regi_ccd_tg = 0xb0001000, + regi_cfg = 0xb0002000, + regi_clkgen = 0xb0004000, + regi_ddr2_ctrl = 0xb0006000, + regi_dma0 = 0xb0008000, + regi_dma1 = 0xb000a000, + regi_dma11 = 0xb000c000, + regi_dma2 = 0xb000e000, + regi_dma3 = 0xb0010000, + regi_dma4 = 0xb0012000, + regi_dma5 = 0xb0014000, + regi_dma6 = 0xb0016000, + regi_dma7 = 0xb0018000, + regi_dma9 = 0xb001a000, + regi_eth = 0xb001c000, + regi_gio = 0xb0020000, + regi_h264 = 0xb0022000, + regi_hist = 0xb0026000, + regi_iop = 0xb0028000, + regi_iop_version = 0xb0028000, + regi_iop_fifo_in_extra = 0xb0028040, + regi_iop_fifo_out_extra = 0xb0028080, + regi_iop_trigger_grp0 = 0xb00280c0, + regi_iop_trigger_grp1 = 0xb0028100, + regi_iop_trigger_grp2 = 0xb0028140, + regi_iop_trigger_grp3 = 0xb0028180, + regi_iop_trigger_grp4 = 0xb00281c0, + regi_iop_trigger_grp5 = 0xb0028200, + regi_iop_trigger_grp6 = 0xb0028240, + regi_iop_trigger_grp7 = 0xb0028280, + regi_iop_crc_par = 0xb0028300, + regi_iop_dmc_in = 0xb0028380, + regi_iop_dmc_out = 0xb0028400, + regi_iop_fifo_in = 0xb0028480, + regi_iop_fifo_out = 0xb0028500, + regi_iop_scrc_in = 0xb0028580, + regi_iop_scrc_out = 0xb0028600, + regi_iop_timer_grp0 = 0xb0028680, + regi_iop_timer_grp1 = 0xb0028700, + regi_iop_sap_in = 0xb0028800, + regi_iop_sap_out = 0xb0028900, + regi_iop_spu = 0xb0028a00, + regi_iop_sw_cfg = 0xb0028b00, + regi_iop_sw_cpu = 0xb0028c00, + regi_iop_sw_mpu = 0xb0028d00, + regi_iop_sw_spu = 0xb0028e00, + regi_iop_mpu = 0xb0029000, + regi_irq = 0xb002a000, + regi_irq2 = 0xb006a000, + regi_jpeg = 0xb002c000, + regi_l2cache = 0xb0030000, + regi_marb_bar = 0xb0032000, + regi_marb_bar_bp0 = 0xb0032140, + regi_marb_bar_bp1 = 0xb0032180, + regi_marb_bar_bp2 = 0xb00321c0, + regi_marb_bar_bp3 = 0xb0032200, + regi_marb_foo = 0xb0034000, + regi_marb_foo_bp0 = 0xb0034280, + regi_marb_foo_bp1 = 0xb00342c0, + regi_marb_foo_bp2 = 0xb0034300, + regi_marb_foo_bp3 = 0xb0034340, + regi_pinmux = 0xb0038000, + regi_pio = 0xb0036000, + regi_sclr = 0xb003a000, + regi_sclr_fifo = 0xb003c000, + regi_ser0 = 0xb003e000, + regi_ser1 = 0xb0040000, + regi_ser2 = 0xb0042000, + regi_ser3 = 0xb0044000, + regi_ser4 = 0xb0046000, + regi_sser = 0xb0048000, + regi_strcop = 0xb004a000, + regi_strdma0 = 0xb004e000, + regi_strdma1 = 0xb0050000, + regi_strdma2 = 0xb0052000, + regi_strdma3 = 0xb0054000, + regi_strdma5 = 0xb0056000, + regi_strmux = 0xb004c000, + regi_timer0 = 0xb0058000, + regi_timer1 = 0xb005a000, + regi_timer2 = 0xb006e000, + regi_trace = 0xb005c000, + regi_vin = 0xb005e000, + regi_vout = 0xb0060000 +} reg_scope_instances; +#endif /* __reg_map_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h new file mode 100644 index 00000000000..14f718a4ecc --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h @@ -0,0 +1,120 @@ +#ifndef __strmux_defs_h +#define __strmux_defs_h + +/* + * This file is autogenerated from + * file: strmux.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile strmux_defs.h strmux.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope strmux */ + +/* Register rw_cfg, scope strmux, type rw */ +typedef struct { + unsigned int dma0 : 2; + unsigned int dma1 : 2; + unsigned int dma2 : 2; + unsigned int dma3 : 2; + unsigned int dma4 : 2; + unsigned int dma5 : 2; + unsigned int dma6 : 2; + unsigned int dma7 : 2; + unsigned int dummy1 : 2; + unsigned int dma9 : 2; + unsigned int dummy2 : 2; + unsigned int dma11 : 2; + unsigned int dummy3 : 8; +} reg_strmux_rw_cfg; +#define REG_RD_ADDR_strmux_rw_cfg 0 +#define REG_WR_ADDR_strmux_rw_cfg 0 + + +/* Constants */ +enum { + regk_strmux_eth = 0x00000001, + regk_strmux_h264 = 0x00000001, + regk_strmux_iop = 0x00000001, + regk_strmux_jpeg = 0x00000001, + regk_strmux_off = 0x00000000, + regk_strmux_rw_cfg_default = 0x00000000, + regk_strmux_ser0 = 0x00000002, + regk_strmux_ser1 = 0x00000002, + regk_strmux_ser2 = 0x00000002, + regk_strmux_ser3 = 0x00000002, + regk_strmux_ser4 = 0x00000002, + regk_strmux_sser = 0x00000001, + regk_strmux_strcop = 0x00000001 +}; +#endif /* __strmux_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h new file mode 100644 index 00000000000..2c33e097d60 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h @@ -0,0 +1,265 @@ +#ifndef __timer_defs_h +#define __timer_defs_h + +/* + * This file is autogenerated from + * file: timer.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope timer */ + +/* Register rw_tmr0_div, scope timer, type rw */ +typedef unsigned int reg_timer_rw_tmr0_div; +#define REG_RD_ADDR_timer_rw_tmr0_div 0 +#define REG_WR_ADDR_timer_rw_tmr0_div 0 + +/* Register r_tmr0_data, scope timer, type r */ +typedef unsigned int reg_timer_r_tmr0_data; +#define REG_RD_ADDR_timer_r_tmr0_data 4 + +/* Register rw_tmr0_ctrl, scope timer, type rw */ +typedef struct { + unsigned int op : 2; + unsigned int freq : 3; + unsigned int dummy1 : 27; +} reg_timer_rw_tmr0_ctrl; +#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 +#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 + +/* Register rw_tmr1_div, scope timer, type rw */ +typedef unsigned int reg_timer_rw_tmr1_div; +#define REG_RD_ADDR_timer_rw_tmr1_div 16 +#define REG_WR_ADDR_timer_rw_tmr1_div 16 + +/* Register r_tmr1_data, scope timer, type r */ +typedef unsigned int reg_timer_r_tmr1_data; +#define REG_RD_ADDR_timer_r_tmr1_data 20 + +/* Register rw_tmr1_ctrl, scope timer, type rw */ +typedef struct { + unsigned int op : 2; + unsigned int freq : 3; + unsigned int dummy1 : 27; +} reg_timer_rw_tmr1_ctrl; +#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 +#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 + +/* Register rs_cnt_data, scope timer, type rs */ +typedef struct { + unsigned int tmr : 24; + unsigned int cnt : 8; +} reg_timer_rs_cnt_data; +#define REG_RD_ADDR_timer_rs_cnt_data 32 + +/* Register r_cnt_data, scope timer, type r */ +typedef struct { + unsigned int tmr : 24; + unsigned int cnt : 8; +} reg_timer_r_cnt_data; +#define REG_RD_ADDR_timer_r_cnt_data 36 + +/* Register rw_cnt_cfg, scope timer, type rw */ +typedef struct { + unsigned int clk : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_cnt_cfg; +#define REG_RD_ADDR_timer_rw_cnt_cfg 40 +#define REG_WR_ADDR_timer_rw_cnt_cfg 40 + +/* Register rw_trig, scope timer, type rw */ +typedef unsigned int reg_timer_rw_trig; +#define REG_RD_ADDR_timer_rw_trig 48 +#define REG_WR_ADDR_timer_rw_trig 48 + +/* Register rw_trig_cfg, scope timer, type rw */ +typedef struct { + unsigned int tmr : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_trig_cfg; +#define REG_RD_ADDR_timer_rw_trig_cfg 52 +#define REG_WR_ADDR_timer_rw_trig_cfg 52 + +/* Register r_time, scope timer, type r */ +typedef unsigned int reg_timer_r_time; +#define REG_RD_ADDR_timer_r_time 56 + +/* Register rw_out, scope timer, type rw */ +typedef struct { + unsigned int tmr : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_out; +#define REG_RD_ADDR_timer_rw_out 60 +#define REG_WR_ADDR_timer_rw_out 60 + +/* Register rw_wd_ctrl, scope timer, type rw */ +typedef struct { + unsigned int cnt : 8; + unsigned int cmd : 1; + unsigned int key : 7; + unsigned int dummy1 : 16; +} reg_timer_rw_wd_ctrl; +#define REG_RD_ADDR_timer_rw_wd_ctrl 64 +#define REG_WR_ADDR_timer_rw_wd_ctrl 64 + +/* Register r_wd_stat, scope timer, type r */ +typedef struct { + unsigned int cnt : 8; + unsigned int cmd : 1; + unsigned int dummy1 : 23; +} reg_timer_r_wd_stat; +#define REG_RD_ADDR_timer_r_wd_stat 68 + +/* Register rw_intr_mask, scope timer, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_rw_intr_mask; +#define REG_RD_ADDR_timer_rw_intr_mask 72 +#define REG_WR_ADDR_timer_rw_intr_mask 72 + +/* Register rw_ack_intr, scope timer, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_rw_ack_intr; +#define REG_RD_ADDR_timer_rw_ack_intr 76 +#define REG_WR_ADDR_timer_rw_ack_intr 76 + +/* Register r_intr, scope timer, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_r_intr; +#define REG_RD_ADDR_timer_r_intr 80 + +/* Register r_masked_intr, scope timer, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_r_masked_intr; +#define REG_RD_ADDR_timer_r_masked_intr 84 + +/* Register rw_test, scope timer, type rw */ +typedef struct { + unsigned int dis : 1; + unsigned int en : 1; + unsigned int dummy1 : 30; +} reg_timer_rw_test; +#define REG_RD_ADDR_timer_rw_test 88 +#define REG_WR_ADDR_timer_rw_test 88 + + +/* Constants */ +enum { + regk_timer_ext = 0x00000001, + regk_timer_f100 = 0x00000007, + regk_timer_f29_493 = 0x00000004, + regk_timer_f32 = 0x00000005, + regk_timer_f32_768 = 0x00000006, + regk_timer_f90 = 0x00000003, + regk_timer_hold = 0x00000001, + regk_timer_ld = 0x00000000, + regk_timer_no = 0x00000000, + regk_timer_off = 0x00000000, + regk_timer_run = 0x00000002, + regk_timer_rw_cnt_cfg_default = 0x00000000, + regk_timer_rw_intr_mask_default = 0x00000000, + regk_timer_rw_out_default = 0x00000000, + regk_timer_rw_test_default = 0x00000000, + regk_timer_rw_tmr0_ctrl_default = 0x00000000, + regk_timer_rw_tmr1_ctrl_default = 0x00000000, + regk_timer_rw_trig_cfg_default = 0x00000000, + regk_timer_start = 0x00000001, + regk_timer_stop = 0x00000000, + regk_timer_time = 0x00000001, + regk_timer_tmr0 = 0x00000002, + regk_timer_tmr1 = 0x00000003, + regk_timer_vclk = 0x00000002, + regk_timer_yes = 0x00000001 +}; +#endif /* __timer_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/memmap.h b/include/asm-cris/arch-v32/mach-a3/memmap.h new file mode 100644 index 00000000000..7e15c9eb4e4 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/memmap.h @@ -0,0 +1,10 @@ +#ifndef _ASM_ARCH_MEMMAP_H +#define _ASM_ARCH_MEMMAP_H + +#define MEM_INTMEM_START (0x38000000) +#define MEM_INTMEM_SIZE (0x00018000) +#define MEM_DRAM_START (0x40000000) + +#define MEM_NON_CACHEABLE (0x80000000) + +#endif diff --git a/include/asm-cris/arch-v32/mach-a3/pinmux.h b/include/asm-cris/arch-v32/mach-a3/pinmux.h new file mode 100644 index 00000000000..db42a725458 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/pinmux.h @@ -0,0 +1,45 @@ +#ifndef _ASM_CRIS_ARCH_PINMUX_H +#define _ASM_CRIS_ARCH_PINMUX_H + +#define PORT_A 0 +#define PORT_B 1 +#define PORT_C 2 + +enum pin_mode { + pinmux_none = 0, + pinmux_fixed, + pinmux_gpio, + pinmux_iop +}; + +enum fixed_function { + pinmux_eth, + pinmux_geth, + pinmux_tg_ccd, + pinmux_tg_cmos, + pinmux_vout, + pinmux_ser1, + pinmux_ser2, + pinmux_ser3, + pinmux_ser4, + pinmux_sser, + pinmux_pio, + pinmux_pwm0, + pinmux_pwm1, + pinmux_pwm2, + pinmux_i2c0, + pinmux_i2c1, + pinmux_i2c1_3wire, + pinmux_i2c1_sda1, + pinmux_i2c1_sda2, + pinmux_i2c1_sda3, +}; + +int crisv32_pinmux_init(void); +int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); +int crisv32_pinmux_alloc_fixed(enum fixed_function function); +int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); +int crisv32_pinmux_dealloc_fixed(enum fixed_function function); +void crisv32_pinmux_dump(void); + +#endif diff --git a/include/asm-cris/arch-v32/mach-a3/startup.inc b/include/asm-cris/arch-v32/mach-a3/startup.inc new file mode 100644 index 00000000000..2f23e5e16f4 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/startup.inc @@ -0,0 +1,60 @@ +#include <hwregs/asm/reg_map_asm.h> +#include <hwregs/asm/gio_defs_asm.h> +#include <hwregs/asm/pio_defs_asm.h> +#include <hwregs/asm/clkgen_defs_asm.h> +#include <hwregs/asm/pinmux_defs_asm.h> + + .macro GIO_INIT + move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 + move.d $r0, [$r1] + + move.d 0xFFFFFFFF, $r0 + move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1 + move.d $r0, [$r1] + move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1 + move.d $r0, [$r1] + move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1 + move.d $r0, [$r1] + .endm + + .macro START_CLOCKS + move.d REG_ADDR(clkgen, regi_clkgen, rw_clk_ctrl), $r1 + move.d [$r1], $r0 + or.d REG_STATE(clkgen, rw_clk_ctrl, cpu, yes) | \ + REG_STATE(clkgen, rw_clk_ctrl, ddr2, yes) | \ + REG_STATE(clkgen, rw_clk_ctrl, memarb_bar_ddr, yes), $r0 + move.d $r0, [$r1] + .endm + + .macro SETUP_WAIT_STATES + move.d REG_ADDR(pio, regi_pio, rw_ce0_cfg), $r0 + move.d CONFIG_ETRAX_PIO_CE0_CFG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(pio, regi_pio, rw_ce1_cfg), $r0 + move.d CONFIG_ETRAX_PIO_CE1_CFG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(pio, regi_pio, rw_ce2_cfg), $r0 + move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1 + move.d $r1, [$r0] + .endm diff --git a/include/asm-cris/arch-v32/mach-fs/arbiter.h b/include/asm-cris/arch-v32/mach-fs/arbiter.h new file mode 100644 index 00000000000..a2e0ec8faa7 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/arbiter.h @@ -0,0 +1,28 @@ +#ifndef _ASM_CRIS_ARCH_ARBITER_H +#define _ASM_CRIS_ARCH_ARBITER_H + +#define EXT_REGION 0 +#define INT_REGION 1 + +typedef void (watch_callback)(void); + +enum { + arbiter_all_dmas = 0x3ff, + arbiter_cpu = 0xc00, + arbiter_all_clients = 0x3fff +}; + +enum { + arbiter_all_read = 0x55, + arbiter_all_write = 0xaa, + arbiter_all_accesses = 0xff +}; + +int crisv32_arbiter_allocate_bandwidth(int client, int region, + unsigned long bandwidth); +int crisv32_arbiter_watch(unsigned long start, unsigned long size, + unsigned long clients, unsigned long accesses, + watch_callback * cb); +int crisv32_arbiter_unwatch(int id); + +#endif diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h new file mode 100644 index 00000000000..0a409c92837 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h @@ -0,0 +1,319 @@ +#ifndef __bif_core_defs_asm_h +#define __bif_core_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_core_regs.r + * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r + * id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_grp1_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp1_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp1_cfg___lw___width 6 +#define reg_bif_core_rw_grp1_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp1_cfg___ew___width 3 +#define reg_bif_core_rw_grp1_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp1_cfg___zw___width 3 +#define reg_bif_core_rw_grp1_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp1_cfg___aw___width 2 +#define reg_bif_core_rw_grp1_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp1_cfg___dw___width 2 +#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp1_cfg___ewb___width 2 +#define reg_bif_core_rw_grp1_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp1_cfg___bw___width 1 +#define reg_bif_core_rw_grp1_cfg___bw___bit 18 +#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp1_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp1_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp1_cfg___mode___width 1 +#define reg_bif_core_rw_grp1_cfg___mode___bit 21 +#define reg_bif_core_rw_grp1_cfg_offset 0 + +/* Register rw_grp2_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp2_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp2_cfg___lw___width 6 +#define reg_bif_core_rw_grp2_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp2_cfg___ew___width 3 +#define reg_bif_core_rw_grp2_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp2_cfg___zw___width 3 +#define reg_bif_core_rw_grp2_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp2_cfg___aw___width 2 +#define reg_bif_core_rw_grp2_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp2_cfg___dw___width 2 +#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp2_cfg___ewb___width 2 +#define reg_bif_core_rw_grp2_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp2_cfg___bw___width 1 +#define reg_bif_core_rw_grp2_cfg___bw___bit 18 +#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp2_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp2_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp2_cfg___mode___width 1 +#define reg_bif_core_rw_grp2_cfg___mode___bit 21 +#define reg_bif_core_rw_grp2_cfg_offset 4 + +/* Register rw_grp3_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp3_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp3_cfg___lw___width 6 +#define reg_bif_core_rw_grp3_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp3_cfg___ew___width 3 +#define reg_bif_core_rw_grp3_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp3_cfg___zw___width 3 +#define reg_bif_core_rw_grp3_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp3_cfg___aw___width 2 +#define reg_bif_core_rw_grp3_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp3_cfg___dw___width 2 +#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp3_cfg___ewb___width 2 +#define reg_bif_core_rw_grp3_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp3_cfg___bw___width 1 +#define reg_bif_core_rw_grp3_cfg___bw___bit 18 +#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp3_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp3_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp3_cfg___mode___width 1 +#define reg_bif_core_rw_grp3_cfg___mode___bit 21 +#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 +#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 +#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 +#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 +#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 +#define reg_bif_core_rw_grp3_cfg_offset 8 + +/* Register rw_grp4_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp4_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp4_cfg___lw___width 6 +#define reg_bif_core_rw_grp4_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp4_cfg___ew___width 3 +#define reg_bif_core_rw_grp4_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp4_cfg___zw___width 3 +#define reg_bif_core_rw_grp4_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp4_cfg___aw___width 2 +#define reg_bif_core_rw_grp4_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp4_cfg___dw___width 2 +#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp4_cfg___ewb___width 2 +#define reg_bif_core_rw_grp4_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp4_cfg___bw___width 1 +#define reg_bif_core_rw_grp4_cfg___bw___bit 18 +#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp4_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp4_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp4_cfg___mode___width 1 +#define reg_bif_core_rw_grp4_cfg___mode___bit 21 +#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 +#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 +#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 +#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 +#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 +#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 +#define reg_bif_core_rw_grp4_cfg_offset 12 + +/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 +#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 +#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 +#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 +#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 +#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 +#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 +#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 +#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp0_offset 16 + +/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 +#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 +#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 +#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 +#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 +#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 +#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 +#define reg_bif_core_rw_sdram_cfg_grp1_offset 20 + +/* Register rw_sdram_timing, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_timing___cl___lsb 0 +#define reg_bif_core_rw_sdram_timing___cl___width 3 +#define reg_bif_core_rw_sdram_timing___rcd___lsb 3 +#define reg_bif_core_rw_sdram_timing___rcd___width 3 +#define reg_bif_core_rw_sdram_timing___rp___lsb 6 +#define reg_bif_core_rw_sdram_timing___rp___width 3 +#define reg_bif_core_rw_sdram_timing___rc___lsb 9 +#define reg_bif_core_rw_sdram_timing___rc___width 2 +#define reg_bif_core_rw_sdram_timing___dpl___lsb 11 +#define reg_bif_core_rw_sdram_timing___dpl___width 2 +#define reg_bif_core_rw_sdram_timing___pde___lsb 13 +#define reg_bif_core_rw_sdram_timing___pde___width 1 +#define reg_bif_core_rw_sdram_timing___pde___bit 13 +#define reg_bif_core_rw_sdram_timing___ref___lsb 14 +#define reg_bif_core_rw_sdram_timing___ref___width 2 +#define reg_bif_core_rw_sdram_timing___cpd___lsb 16 +#define reg_bif_core_rw_sdram_timing___cpd___width 1 +#define reg_bif_core_rw_sdram_timing___cpd___bit 16 +#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 +#define reg_bif_core_rw_sdram_timing___sdcke___width 1 +#define reg_bif_core_rw_sdram_timing___sdcke___bit 17 +#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 +#define reg_bif_core_rw_sdram_timing___sdclk___width 1 +#define reg_bif_core_rw_sdram_timing___sdclk___bit 18 +#define reg_bif_core_rw_sdram_timing_offset 24 + +/* Register rw_sdram_cmd, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 +#define reg_bif_core_rw_sdram_cmd___cmd___width 3 +#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 +#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 +#define reg_bif_core_rw_sdram_cmd_offset 28 + +/* Register rs_sdram_ref_stat, scope bif_core, type rs */ +#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 +#define reg_bif_core_rs_sdram_ref_stat___ok___width 1 +#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 +#define reg_bif_core_rs_sdram_ref_stat_offset 32 + +/* Register r_sdram_ref_stat, scope bif_core, type r */ +#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 +#define reg_bif_core_r_sdram_ref_stat___ok___width 1 +#define reg_bif_core_r_sdram_ref_stat___ok___bit 0 +#define reg_bif_core_r_sdram_ref_stat_offset 36 + + +/* Constants */ +#define regk_bif_core_bank2 0x00000000 +#define regk_bif_core_bank4 0x00000001 +#define regk_bif_core_bit10 0x0000000a +#define regk_bif_core_bit11 0x0000000b +#define regk_bif_core_bit12 0x0000000c +#define regk_bif_core_bit13 0x0000000d +#define regk_bif_core_bit14 0x0000000e +#define regk_bif_core_bit15 0x0000000f +#define regk_bif_core_bit16 0x00000010 +#define regk_bif_core_bit17 0x00000011 +#define regk_bif_core_bit18 0x00000012 +#define regk_bif_core_bit19 0x00000013 +#define regk_bif_core_bit20 0x00000014 +#define regk_bif_core_bit21 0x00000015 +#define regk_bif_core_bit22 0x00000016 +#define regk_bif_core_bit23 0x00000017 +#define regk_bif_core_bit24 0x00000018 +#define regk_bif_core_bit25 0x00000019 +#define regk_bif_core_bit26 0x0000001a +#define regk_bif_core_bit27 0x0000001b +#define regk_bif_core_bit28 0x0000001c +#define regk_bif_core_bit29 0x0000001d +#define regk_bif_core_bit9 0x00000009 +#define regk_bif_core_bw16 0x00000001 +#define regk_bif_core_bw32 0x00000000 +#define regk_bif_core_bwe 0x00000000 +#define regk_bif_core_cwe 0x00000001 +#define regk_bif_core_e15us 0x00000001 +#define regk_bif_core_e7800ns 0x00000002 +#define regk_bif_core_grp0 0x00000000 +#define regk_bif_core_grp1 0x00000001 +#define regk_bif_core_mrs 0x00000003 +#define regk_bif_core_no 0x00000000 +#define regk_bif_core_none 0x00000000 +#define regk_bif_core_nop 0x00000000 +#define regk_bif_core_off 0x00000000 +#define regk_bif_core_pre 0x00000002 +#define regk_bif_core_r_sdram_ref_stat_default 0x00000001 +#define regk_bif_core_rd 0x00000002 +#define regk_bif_core_ref 0x00000001 +#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 +#define regk_bif_core_rw_grp1_cfg_default 0x000006cf +#define regk_bif_core_rw_grp2_cfg_default 0x000006cf +#define regk_bif_core_rw_grp3_cfg_default 0x000006cf +#define regk_bif_core_rw_grp4_cfg_default 0x000006cf +#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 +#define regk_bif_core_slf 0x00000004 +#define regk_bif_core_wr 0x00000001 +#define regk_bif_core_yes 0x00000001 +#endif /* __bif_core_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h new file mode 100644 index 00000000000..a9908dfc293 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h @@ -0,0 +1,131 @@ +#ifndef __config_defs_asm_h +#define __config_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../rtl/config_regs.r + * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp + * last modfied: Thu Mar 4 12:34:39 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r + * id: $Id: config_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_bootsel, scope config, type r */ +#define reg_config_r_bootsel___boot_mode___lsb 0 +#define reg_config_r_bootsel___boot_mode___width 3 +#define reg_config_r_bootsel___full_duplex___lsb 3 +#define reg_config_r_bootsel___full_duplex___width 1 +#define reg_config_r_bootsel___full_duplex___bit 3 +#define reg_config_r_bootsel___user___lsb 4 +#define reg_config_r_bootsel___user___width 1 +#define reg_config_r_bootsel___user___bit 4 +#define reg_config_r_bootsel___pll___lsb 5 +#define reg_config_r_bootsel___pll___width 1 +#define reg_config_r_bootsel___pll___bit 5 +#define reg_config_r_bootsel___flash_bw___lsb 6 +#define reg_config_r_bootsel___flash_bw___width 1 +#define reg_config_r_bootsel___flash_bw___bit 6 +#define reg_config_r_bootsel_offset 0 + +/* Register rw_clk_ctrl, scope config, type rw */ +#define reg_config_rw_clk_ctrl___pll___lsb 0 +#define reg_config_rw_clk_ctrl___pll___width 1 +#define reg_config_rw_clk_ctrl___pll___bit 0 +#define reg_config_rw_clk_ctrl___cpu___lsb 1 +#define reg_config_rw_clk_ctrl___cpu___width 1 +#define reg_config_rw_clk_ctrl___cpu___bit 1 +#define reg_config_rw_clk_ctrl___iop___lsb 2 +#define reg_config_rw_clk_ctrl___iop___width 1 +#define reg_config_rw_clk_ctrl___iop___bit 2 +#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 +#define reg_config_rw_clk_ctrl___dma01_eth0___width 1 +#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 +#define reg_config_rw_clk_ctrl___dma23___lsb 4 +#define reg_config_rw_clk_ctrl___dma23___width 1 +#define reg_config_rw_clk_ctrl___dma23___bit 4 +#define reg_config_rw_clk_ctrl___dma45___lsb 5 +#define reg_config_rw_clk_ctrl___dma45___width 1 +#define reg_config_rw_clk_ctrl___dma45___bit 5 +#define reg_config_rw_clk_ctrl___dma67___lsb 6 +#define reg_config_rw_clk_ctrl___dma67___width 1 +#define reg_config_rw_clk_ctrl___dma67___bit 6 +#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 +#define reg_config_rw_clk_ctrl___dma89_strcop___width 1 +#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 +#define reg_config_rw_clk_ctrl___bif___lsb 8 +#define reg_config_rw_clk_ctrl___bif___width 1 +#define reg_config_rw_clk_ctrl___bif___bit 8 +#define reg_config_rw_clk_ctrl___fix_io___lsb 9 +#define reg_config_rw_clk_ctrl___fix_io___width 1 +#define reg_config_rw_clk_ctrl___fix_io___bit 9 +#define reg_config_rw_clk_ctrl_offset 4 + +/* Register rw_pad_ctrl, scope config, type rw */ +#define reg_config_rw_pad_ctrl___usb_susp___lsb 0 +#define reg_config_rw_pad_ctrl___usb_susp___width 1 +#define reg_config_rw_pad_ctrl___usb_susp___bit 0 +#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 +#define reg_config_rw_pad_ctrl___phyrst_n___width 1 +#define reg_config_rw_pad_ctrl___phyrst_n___bit 1 +#define reg_config_rw_pad_ctrl_offset 8 + + +/* Constants */ +#define regk_config_bw16 0x00000000 +#define regk_config_bw32 0x00000001 +#define regk_config_master 0x00000005 +#define regk_config_nand 0x00000003 +#define regk_config_net_rx 0x00000001 +#define regk_config_net_tx_rx 0x00000002 +#define regk_config_no 0x00000000 +#define regk_config_none 0x00000007 +#define regk_config_nor 0x00000000 +#define regk_config_rw_clk_ctrl_default 0x00000002 +#define regk_config_rw_pad_ctrl_default 0x00000000 +#define regk_config_ser 0x00000004 +#define regk_config_slave 0x00000006 +#define regk_config_yes 0x00000001 +#endif /* __config_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h new file mode 100644 index 00000000000..be4c63936d9 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h @@ -0,0 +1,276 @@ +#ifndef __gio_defs_asm_h +#define __gio_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/gio/rtl/gio_regs.r + * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp + * last modfied: Mon Apr 11 16:07:47 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r + * id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_pa_dout, scope gio, type rw */ +#define reg_gio_rw_pa_dout___data___lsb 0 +#define reg_gio_rw_pa_dout___data___width 8 +#define reg_gio_rw_pa_dout_offset 0 + +/* Register r_pa_din, scope gio, type r */ +#define reg_gio_r_pa_din___data___lsb 0 +#define reg_gio_r_pa_din___data___width 8 +#define reg_gio_r_pa_din_offset 4 + +/* Register rw_pa_oe, scope gio, type rw */ +#define reg_gio_rw_pa_oe___oe___lsb 0 +#define reg_gio_rw_pa_oe___oe___width 8 +#define reg_gio_rw_pa_oe_offset 8 + +/* Register rw_intr_cfg, scope gio, type rw */ +#define reg_gio_rw_intr_cfg___pa0___lsb 0 +#define reg_gio_rw_intr_cfg___pa0___width 3 +#define reg_gio_rw_intr_cfg___pa1___lsb 3 +#define reg_gio_rw_intr_cfg___pa1___width 3 +#define reg_gio_rw_intr_cfg___pa2___lsb 6 +#define reg_gio_rw_intr_cfg___pa2___width 3 +#define reg_gio_rw_intr_cfg___pa3___lsb 9 +#define reg_gio_rw_intr_cfg___pa3___width 3 +#define reg_gio_rw_intr_cfg___pa4___lsb 12 +#define reg_gio_rw_intr_cfg___pa4___width 3 +#define reg_gio_rw_intr_cfg___pa5___lsb 15 +#define reg_gio_rw_intr_cfg___pa5___width 3 +#define reg_gio_rw_intr_cfg___pa6___lsb 18 +#define reg_gio_rw_intr_cfg___pa6___width 3 +#define reg_gio_rw_intr_cfg___pa7___lsb 21 +#define reg_gio_rw_intr_cfg___pa7___width 3 +#define reg_gio_rw_intr_cfg_offset 12 + +/* Register rw_intr_mask, scope gio, type rw */ +#define reg_gio_rw_intr_mask___pa0___lsb 0 +#define reg_gio_rw_intr_mask___pa0___width 1 +#define reg_gio_rw_intr_mask___pa0___bit 0 +#define reg_gio_rw_intr_mask___pa1___lsb 1 +#define reg_gio_rw_intr_mask___pa1___width 1 +#define reg_gio_rw_intr_mask___pa1___bit 1 +#define reg_gio_rw_intr_mask___pa2___lsb 2 +#define reg_gio_rw_intr_mask___pa2___width 1 +#define reg_gio_rw_intr_mask___pa2___bit 2 +#define reg_gio_rw_intr_mask___pa3___lsb 3 +#define reg_gio_rw_intr_mask___pa3___width 1 +#define reg_gio_rw_intr_mask___pa3___bit 3 +#define reg_gio_rw_intr_mask___pa4___lsb 4 +#define reg_gio_rw_intr_mask___pa4___width 1 +#define reg_gio_rw_intr_mask___pa4___bit 4 +#define reg_gio_rw_intr_mask___pa5___lsb 5 +#define reg_gio_rw_intr_mask___pa5___width 1 +#define reg_gio_rw_intr_mask___pa5___bit 5 +#define reg_gio_rw_intr_mask___pa6___lsb 6 +#define reg_gio_rw_intr_mask___pa6___width 1 +#define reg_gio_rw_intr_mask___pa6___bit 6 +#define reg_gio_rw_intr_mask___pa7___lsb 7 +#define reg_gio_rw_intr_mask___pa7___width 1 +#define reg_gio_rw_intr_mask___pa7___bit 7 +#define reg_gio_rw_intr_mask_offset 16 + +/* Register rw_ack_intr, scope gio, type rw */ +#define reg_gio_rw_ack_intr___pa0___lsb 0 +#define reg_gio_rw_ack_intr___pa0___width 1 +#define reg_gio_rw_ack_intr___pa0___bit 0 +#define reg_gio_rw_ack_intr___pa1___lsb 1 +#define reg_gio_rw_ack_intr___pa1___width 1 +#define reg_gio_rw_ack_intr___pa1___bit 1 +#define reg_gio_rw_ack_intr___pa2___lsb 2 +#define reg_gio_rw_ack_intr___pa2___width 1 +#define reg_gio_rw_ack_intr___pa2___bit 2 +#define reg_gio_rw_ack_intr___pa3___lsb 3 +#define reg_gio_rw_ack_intr___pa3___width 1 +#define reg_gio_rw_ack_intr___pa3___bit 3 +#define reg_gio_rw_ack_intr___pa4___lsb 4 +#define reg_gio_rw_ack_intr___pa4___width 1 +#define reg_gio_rw_ack_intr___pa4___bit 4 +#define reg_gio_rw_ack_intr___pa5___lsb 5 +#define reg_gio_rw_ack_intr___pa5___width 1 +#define reg_gio_rw_ack_intr___pa5___bit 5 +#define reg_gio_rw_ack_intr___pa6___lsb 6 +#define reg_gio_rw_ack_intr___pa6___width 1 +#define reg_gio_rw_ack_intr___pa6___bit 6 +#define reg_gio_rw_ack_intr___pa7___lsb 7 +#define reg_gio_rw_ack_intr___pa7___width 1 +#define reg_gio_rw_ack_intr___pa7___bit 7 +#define reg_gio_rw_ack_intr_offset 20 + +/* Register r_intr, scope gio, type r */ +#define reg_gio_r_intr___pa0___lsb 0 +#define reg_gio_r_intr___pa0___width 1 +#define reg_gio_r_intr___pa0___bit 0 +#define reg_gio_r_intr___pa1___lsb 1 +#define reg_gio_r_intr___pa1___width 1 +#define reg_gio_r_intr___pa1___bit 1 +#define reg_gio_r_intr___pa2___lsb 2 +#define reg_gio_r_intr___pa2___width 1 +#define reg_gio_r_intr___pa2___bit 2 +#define reg_gio_r_intr___pa3___lsb 3 +#define reg_gio_r_intr___pa3___width 1 +#define reg_gio_r_intr___pa3___bit 3 +#define reg_gio_r_intr___pa4___lsb 4 +#define reg_gio_r_intr___pa4___width 1 +#define reg_gio_r_intr___pa4___bit 4 +#define reg_gio_r_intr___pa5___lsb 5 +#define reg_gio_r_intr___pa5___width 1 +#define reg_gio_r_intr___pa5___bit 5 +#define reg_gio_r_intr___pa6___lsb 6 +#define reg_gio_r_intr___pa6___width 1 +#define reg_gio_r_intr___pa6___bit 6 +#define reg_gio_r_intr___pa7___lsb 7 +#define reg_gio_r_intr___pa7___width 1 +#define reg_gio_r_intr___pa7___bit 7 +#define reg_gio_r_intr_offset 24 + +/* Register r_masked_intr, scope gio, type r */ +#define reg_gio_r_masked_intr___pa0___lsb 0 +#define reg_gio_r_masked_intr___pa0___width 1 +#define reg_gio_r_masked_intr___pa0___bit 0 +#define reg_gio_r_masked_intr___pa1___lsb 1 +#define reg_gio_r_masked_intr___pa1___width 1 +#define reg_gio_r_masked_intr___pa1___bit 1 +#define reg_gio_r_masked_intr___pa2___lsb 2 +#define reg_gio_r_masked_intr___pa2___width 1 +#define reg_gio_r_masked_intr___pa2___bit 2 +#define reg_gio_r_masked_intr___pa3___lsb 3 +#define reg_gio_r_masked_intr___pa3___width 1 +#define reg_gio_r_masked_intr___pa3___bit 3 +#define reg_gio_r_masked_intr___pa4___lsb 4 +#define reg_gio_r_masked_intr___pa4___width 1 +#define reg_gio_r_masked_intr___pa4___bit 4 +#define reg_gio_r_masked_intr___pa5___lsb 5 +#define reg_gio_r_masked_intr___pa5___width 1 +#define reg_gio_r_masked_intr___pa5___bit 5 +#define reg_gio_r_masked_intr___pa6___lsb 6 +#define reg_gio_r_masked_intr___pa6___width 1 +#define reg_gio_r_masked_intr___pa6___bit 6 +#define reg_gio_r_masked_intr___pa7___lsb 7 +#define reg_gio_r_masked_intr___pa7___width 1 +#define reg_gio_r_masked_intr___pa7___bit 7 +#define reg_gio_r_masked_intr_offset 28 + +/* Register rw_pb_dout, scope gio, type rw */ +#define reg_gio_rw_pb_dout___data___lsb 0 +#define reg_gio_rw_pb_dout___data___width 18 +#define reg_gio_rw_pb_dout_offset 32 + +/* Register r_pb_din, scope gio, type r */ +#define reg_gio_r_pb_din___data___lsb 0 +#define reg_gio_r_pb_din___data___width 18 +#define reg_gio_r_pb_din_offset 36 + +/* Register rw_pb_oe, scope gio, type rw */ +#define reg_gio_rw_pb_oe___oe___lsb 0 +#define reg_gio_rw_pb_oe___oe___width 18 +#define reg_gio_rw_pb_oe_offset 40 + +/* Register rw_pc_dout, scope gio, type rw */ +#define reg_gio_rw_pc_dout___data___lsb 0 +#define reg_gio_rw_pc_dout___data___width 18 +#define reg_gio_rw_pc_dout_offset 48 + +/* Register r_pc_din, scope gio, type r */ +#define reg_gio_r_pc_din___data___lsb 0 +#define reg_gio_r_pc_din___data___width 18 +#define reg_gio_r_pc_din_offset 52 + +/* Register rw_pc_oe, scope gio, type rw */ +#define reg_gio_rw_pc_oe___oe___lsb 0 +#define reg_gio_rw_pc_oe___oe___width 18 +#define reg_gio_rw_pc_oe_offset 56 + +/* Register rw_pd_dout, scope gio, type rw */ +#define reg_gio_rw_pd_dout___data___lsb 0 +#define reg_gio_rw_pd_dout___data___width 18 +#define reg_gio_rw_pd_dout_offset 64 + +/* Register r_pd_din, scope gio, type r */ +#define reg_gio_r_pd_din___data___lsb 0 +#define reg_gio_r_pd_din___data___width 18 +#define reg_gio_r_pd_din_offset 68 + +/* Register rw_pd_oe, scope gio, type rw */ +#define reg_gio_rw_pd_oe___oe___lsb 0 +#define reg_gio_rw_pd_oe___oe___width 18 +#define reg_gio_rw_pd_oe_offset 72 + +/* Register rw_pe_dout, scope gio, type rw */ +#define reg_gio_rw_pe_dout___data___lsb 0 +#define reg_gio_rw_pe_dout___data___width 18 +#define reg_gio_rw_pe_dout_offset 80 + +/* Register r_pe_din, scope gio, type r */ +#define reg_gio_r_pe_din___data___lsb 0 +#define reg_gio_r_pe_din___data___width 18 +#define reg_gio_r_pe_din_offset 84 + +/* Register rw_pe_oe, scope gio, type rw */ +#define reg_gio_rw_pe_oe___oe___lsb 0 +#define reg_gio_rw_pe_oe___oe___width 18 +#define reg_gio_rw_pe_oe_offset 88 + + +/* Constants */ +#define regk_gio_anyedge 0x00000007 +#define regk_gio_hi 0x00000001 +#define regk_gio_lo 0x00000002 +#define regk_gio_negedge 0x00000006 +#define regk_gio_no 0x00000000 +#define regk_gio_off 0x00000000 +#define regk_gio_posedge 0x00000005 +#define regk_gio_rw_intr_cfg_default 0x00000000 +#define regk_gio_rw_intr_mask_default 0x00000000 +#define regk_gio_rw_pa_oe_default 0x00000000 +#define regk_gio_rw_pb_oe_default 0x00000000 +#define regk_gio_rw_pc_oe_default 0x00000000 +#define regk_gio_rw_pd_oe_default 0x00000000 +#define regk_gio_rw_pe_oe_default 0x00000000 +#define regk_gio_set 0x00000003 +#define regk_gio_yes 0x00000001 +#endif /* __gio_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h new file mode 100644 index 00000000000..30cf5a936b6 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h @@ -0,0 +1,632 @@ +#ifndef __pinmux_defs_asm_h +#define __pinmux_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp + * last modfied: Mon Apr 11 16:09:11 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 ricardw Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_pa, scope pinmux, type rw */ +#define reg_pinmux_rw_pa___pa0___lsb 0 +#define reg_pinmux_rw_pa___pa0___width 1 +#define reg_pinmux_rw_pa___pa0___bit 0 +#define reg_pinmux_rw_pa___pa1___lsb 1 +#define reg_pinmux_rw_pa___pa1___width 1 +#define reg_pinmux_rw_pa___pa1___bit 1 +#define reg_pinmux_rw_pa___pa2___lsb 2 +#define reg_pinmux_rw_pa___pa2___width 1 +#define reg_pinmux_rw_pa___pa2___bit 2 +#define reg_pinmux_rw_pa___pa3___lsb 3 +#define reg_pinmux_rw_pa___pa3___width 1 +#define reg_pinmux_rw_pa___pa3___bit 3 +#define reg_pinmux_rw_pa___pa4___lsb 4 +#define reg_pinmux_rw_pa___pa4___width 1 +#define reg_pinmux_rw_pa___pa4___bit 4 +#define reg_pinmux_rw_pa___pa5___lsb 5 +#define reg_pinmux_rw_pa___pa5___width 1 +#define reg_pinmux_rw_pa___pa5___bit 5 +#define reg_pinmux_rw_pa___pa6___lsb 6 +#define reg_pinmux_rw_pa___pa6___width 1 +#define reg_pinmux_rw_pa___pa6___bit 6 +#define reg_pinmux_rw_pa___pa7___lsb 7 +#define reg_pinmux_rw_pa___pa7___width 1 +#define reg_pinmux_rw_pa___pa7___bit 7 +#define reg_pinmux_rw_pa___csp2_n___lsb 8 +#define reg_pinmux_rw_pa___csp2_n___width 1 +#define reg_pinmux_rw_pa___csp2_n___bit 8 +#define reg_pinmux_rw_pa___csp3_n___lsb 9 +#define reg_pinmux_rw_pa___csp3_n___width 1 +#define reg_pinmux_rw_pa___csp3_n___bit 9 +#define reg_pinmux_rw_pa___csp5_n___lsb 10 +#define reg_pinmux_rw_pa___csp5_n___width 1 +#define reg_pinmux_rw_pa___csp5_n___bit 10 +#define reg_pinmux_rw_pa___csp6_n___lsb 11 +#define reg_pinmux_rw_pa___csp6_n___width 1 +#define reg_pinmux_rw_pa___csp6_n___bit 11 +#define reg_pinmux_rw_pa___hsh4___lsb 12 +#define reg_pinmux_rw_pa___hsh4___width 1 +#define reg_pinmux_rw_pa___hsh4___bit 12 +#define reg_pinmux_rw_pa___hsh5___lsb 13 +#define reg_pinmux_rw_pa___hsh5___width 1 +#define reg_pinmux_rw_pa___hsh5___bit 13 +#define reg_pinmux_rw_pa___hsh6___lsb 14 +#define reg_pinmux_rw_pa___hsh6___width 1 +#define reg_pinmux_rw_pa___hsh6___bit 14 +#define reg_pinmux_rw_pa___hsh7___lsb 15 +#define reg_pinmux_rw_pa___hsh7___width 1 +#define reg_pinmux_rw_pa___hsh7___bit 15 +#define reg_pinmux_rw_pa_offset 0 + +/* Register rw_hwprot, scope pinmux, type rw */ +#define reg_pinmux_rw_hwprot___ser1___lsb 0 +#define reg_pinmux_rw_hwprot___ser1___width 1 +#define reg_pinmux_rw_hwprot___ser1___bit 0 +#define reg_pinmux_rw_hwprot___ser2___lsb 1 +#define reg_pinmux_rw_hwprot___ser2___width 1 +#define reg_pinmux_rw_hwprot___ser2___bit 1 +#define reg_pinmux_rw_hwprot___ser3___lsb 2 +#define reg_pinmux_rw_hwprot___ser3___width 1 +#define reg_pinmux_rw_hwprot___ser3___bit 2 +#define reg_pinmux_rw_hwprot___sser0___lsb 3 +#define reg_pinmux_rw_hwprot___sser0___width 1 +#define reg_pinmux_rw_hwprot___sser0___bit 3 +#define reg_pinmux_rw_hwprot___sser1___lsb 4 +#define reg_pinmux_rw_hwprot___sser1___width 1 +#define reg_pinmux_rw_hwprot___sser1___bit 4 +#define reg_pinmux_rw_hwprot___ata0___lsb 5 +#define reg_pinmux_rw_hwprot___ata0___width 1 +#define reg_pinmux_rw_hwprot___ata0___bit 5 +#define reg_pinmux_rw_hwprot___ata1___lsb 6 +#define reg_pinmux_rw_hwprot___ata1___width 1 +#define reg_pinmux_rw_hwprot___ata1___bit 6 +#define reg_pinmux_rw_hwprot___ata2___lsb 7 +#define reg_pinmux_rw_hwprot___ata2___width 1 +#define reg_pinmux_rw_hwprot___ata2___bit 7 +#define reg_pinmux_rw_hwprot___ata3___lsb 8 +#define reg_pinmux_rw_hwprot___ata3___width 1 +#define reg_pinmux_rw_hwprot___ata3___bit 8 +#define reg_pinmux_rw_hwprot___ata___lsb 9 +#define reg_pinmux_rw_hwprot___ata___width 1 +#define reg_pinmux_rw_hwprot___ata___bit 9 +#define reg_pinmux_rw_hwprot___eth1___lsb 10 +#define reg_pinmux_rw_hwprot___eth1___width 1 +#define reg_pinmux_rw_hwprot___eth1___bit 10 +#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11 +#define reg_pinmux_rw_hwprot___eth1_mgm___width 1 +#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11 +#define reg_pinmux_rw_hwprot___timer___lsb 12 +#define reg_pinmux_rw_hwprot___timer___width 1 +#define reg_pinmux_rw_hwprot___timer___bit 12 +#define reg_pinmux_rw_hwprot___p21___lsb 13 +#define reg_pinmux_rw_hwprot___p21___width 1 +#define reg_pinmux_rw_hwprot___p21___bit 13 +#define reg_pinmux_rw_hwprot_offset 4 + +/* Register rw_pb_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pb_gio___pb0___lsb 0 +#define reg_pinmux_rw_pb_gio___pb0___width 1 +#define reg_pinmux_rw_pb_gio___pb0___bit 0 +#define reg_pinmux_rw_pb_gio___pb1___lsb 1 +#define reg_pinmux_rw_pb_gio___pb1___width 1 +#define reg_pinmux_rw_pb_gio___pb1___bit 1 +#define reg_pinmux_rw_pb_gio___pb2___lsb 2 +#define reg_pinmux_rw_pb_gio___pb2___width 1 +#define reg_pinmux_rw_pb_gio___pb2___bit 2 +#define reg_pinmux_rw_pb_gio___pb3___lsb 3 +#define reg_pinmux_rw_pb_gio___pb3___width 1 +#define reg_pinmux_rw_pb_gio___pb3___bit 3 +#define reg_pinmux_rw_pb_gio___pb4___lsb 4 +#define reg_pinmux_rw_pb_gio___pb4___width 1 +#define reg_pinmux_rw_pb_gio___pb4___bit 4 +#define reg_pinmux_rw_pb_gio___pb5___lsb 5 +#define reg_pinmux_rw_pb_gio___pb5___width 1 +#define reg_pinmux_rw_pb_gio___pb5___bit 5 +#define reg_pinmux_rw_pb_gio___pb6___lsb 6 +#define reg_pinmux_rw_pb_gio___pb6___width 1 +#define reg_pinmux_rw_pb_gio___pb6___bit 6 +#define reg_pinmux_rw_pb_gio___pb7___lsb 7 +#define reg_pinmux_rw_pb_gio___pb7___width 1 +#define reg_pinmux_rw_pb_gio___pb7___bit 7 +#define reg_pinmux_rw_pb_gio___pb8___lsb 8 +#define reg_pinmux_rw_pb_gio___pb8___width 1 +#define reg_pinmux_rw_pb_gio___pb8___bit 8 +#define reg_pinmux_rw_pb_gio___pb9___lsb 9 +#define reg_pinmux_rw_pb_gio___pb9___width 1 +#define reg_pinmux_rw_pb_gio___pb9___bit 9 +#define reg_pinmux_rw_pb_gio___pb10___lsb 10 +#define reg_pinmux_rw_pb_gio___pb10___width 1 +#define reg_pinmux_rw_pb_gio___pb10___bit 10 +#define reg_pinmux_rw_pb_gio___pb11___lsb 11 +#define reg_pinmux_rw_pb_gio___pb11___width 1 +#define reg_pinmux_rw_pb_gio___pb11___bit 11 +#define reg_pinmux_rw_pb_gio___pb12___lsb 12 +#define reg_pinmux_rw_pb_gio___pb12___width 1 +#define reg_pinmux_rw_pb_gio___pb12___bit 12 +#define reg_pinmux_rw_pb_gio___pb13___lsb 13 +#define reg_pinmux_rw_pb_gio___pb13___width 1 +#define reg_pinmux_rw_pb_gio___pb13___bit 13 +#define reg_pinmux_rw_pb_gio___pb14___lsb 14 +#define reg_pinmux_rw_pb_gio___pb14___width 1 +#define reg_pinmux_rw_pb_gio___pb14___bit 14 +#define reg_pinmux_rw_pb_gio___pb15___lsb 15 +#define reg_pinmux_rw_pb_gio___pb15___width 1 +#define reg_pinmux_rw_pb_gio___pb15___bit 15 +#define reg_pinmux_rw_pb_gio___pb16___lsb 16 +#define reg_pinmux_rw_pb_gio___pb16___width 1 +#define reg_pinmux_rw_pb_gio___pb16___bit 16 +#define reg_pinmux_rw_pb_gio___pb17___lsb 17 +#define reg_pinmux_rw_pb_gio___pb17___width 1 +#define reg_pinmux_rw_pb_gio___pb17___bit 17 +#define reg_pinmux_rw_pb_gio_offset 8 + +/* Register rw_pb_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pb_iop___pb0___lsb 0 +#define reg_pinmux_rw_pb_iop___pb0___width 1 +#define reg_pinmux_rw_pb_iop___pb0___bit 0 +#define reg_pinmux_rw_pb_iop___pb1___lsb 1 +#define reg_pinmux_rw_pb_iop___pb1___width 1 +#define reg_pinmux_rw_pb_iop___pb1___bit 1 +#define reg_pinmux_rw_pb_iop___pb2___lsb 2 +#define reg_pinmux_rw_pb_iop___pb2___width 1 +#define reg_pinmux_rw_pb_iop___pb2___bit 2 +#define reg_pinmux_rw_pb_iop___pb3___lsb 3 +#define reg_pinmux_rw_pb_iop___pb3___width 1 +#define reg_pinmux_rw_pb_iop___pb3___bit 3 +#define reg_pinmux_rw_pb_iop___pb4___lsb 4 +#define reg_pinmux_rw_pb_iop___pb4___width 1 +#define reg_pinmux_rw_pb_iop___pb4___bit 4 +#define reg_pinmux_rw_pb_iop___pb5___lsb 5 +#define reg_pinmux_rw_pb_iop___pb5___width 1 +#define reg_pinmux_rw_pb_iop___pb5___bit 5 +#define reg_pinmux_rw_pb_iop___pb6___lsb 6 +#define reg_pinmux_rw_pb_iop___pb6___width 1 +#define reg_pinmux_rw_pb_iop___pb6___bit 6 +#define reg_pinmux_rw_pb_iop___pb7___lsb 7 +#define reg_pinmux_rw_pb_iop___pb7___width 1 +#define reg_pinmux_rw_pb_iop___pb7___bit 7 +#define reg_pinmux_rw_pb_iop___pb8___lsb 8 +#define reg_pinmux_rw_pb_iop___pb8___width 1 +#define reg_pinmux_rw_pb_iop___pb8___bit 8 +#define reg_pinmux_rw_pb_iop___pb9___lsb 9 +#define reg_pinmux_rw_pb_iop___pb9___width 1 +#define reg_pinmux_rw_pb_iop___pb9___bit 9 +#define reg_pinmux_rw_pb_iop___pb10___lsb 10 +#define reg_pinmux_rw_pb_iop___pb10___width 1 +#define reg_pinmux_rw_pb_iop___pb10___bit 10 +#define reg_pinmux_rw_pb_iop___pb11___lsb 11 +#define reg_pinmux_rw_pb_iop___pb11___width 1 +#define reg_pinmux_rw_pb_iop___pb11___bit 11 +#define reg_pinmux_rw_pb_iop___pb12___lsb 12 +#define reg_pinmux_rw_pb_iop___pb12___width 1 +#define reg_pinmux_rw_pb_iop___pb12___bit 12 +#define reg_pinmux_rw_pb_iop___pb13___lsb 13 +#define reg_pinmux_rw_pb_iop___pb13___width 1 +#define reg_pinmux_rw_pb_iop___pb13___bit 13 +#define reg_pinmux_rw_pb_iop___pb14___lsb 14 +#define reg_pinmux_rw_pb_iop___pb14___width 1 +#define reg_pinmux_rw_pb_iop___pb14___bit 14 +#define reg_pinmux_rw_pb_iop___pb15___lsb 15 +#define reg_pinmux_rw_pb_iop___pb15___width 1 +#define reg_pinmux_rw_pb_iop___pb15___bit 15 +#define reg_pinmux_rw_pb_iop___pb16___lsb 16 +#define reg_pinmux_rw_pb_iop___pb16___width 1 +#define reg_pinmux_rw_pb_iop___pb16___bit 16 +#define reg_pinmux_rw_pb_iop___pb17___lsb 17 +#define reg_pinmux_rw_pb_iop___pb17___width 1 +#define reg_pinmux_rw_pb_iop___pb17___bit 17 +#define reg_pinmux_rw_pb_iop_offset 12 + +/* Register rw_pc_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pc_gio___pc0___lsb 0 +#define reg_pinmux_rw_pc_gio___pc0___width 1 +#define reg_pinmux_rw_pc_gio___pc0___bit 0 +#define reg_pinmux_rw_pc_gio___pc1___lsb 1 +#define reg_pinmux_rw_pc_gio___pc1___width 1 +#define reg_pinmux_rw_pc_gio___pc1___bit 1 +#define reg_pinmux_rw_pc_gio___pc2___lsb 2 +#define reg_pinmux_rw_pc_gio___pc2___width 1 +#define reg_pinmux_rw_pc_gio___pc2___bit 2 +#define reg_pinmux_rw_pc_gio___pc3___lsb 3 +#define reg_pinmux_rw_pc_gio___pc3___width 1 +#define reg_pinmux_rw_pc_gio___pc3___bit 3 +#define reg_pinmux_rw_pc_gio___pc4___lsb 4 +#define reg_pinmux_rw_pc_gio___pc4___width 1 +#define reg_pinmux_rw_pc_gio___pc4___bit 4 +#define reg_pinmux_rw_pc_gio___pc5___lsb 5 +#define reg_pinmux_rw_pc_gio___pc5___width 1 +#define reg_pinmux_rw_pc_gio___pc5___bit 5 +#define reg_pinmux_rw_pc_gio___pc6___lsb 6 +#define reg_pinmux_rw_pc_gio___pc6___width 1 +#define reg_pinmux_rw_pc_gio___pc6___bit 6 +#define reg_pinmux_rw_pc_gio___pc7___lsb 7 +#define reg_pinmux_rw_pc_gio___pc7___width 1 +#define reg_pinmux_rw_pc_gio___pc7___bit 7 +#define reg_pinmux_rw_pc_gio___pc8___lsb 8 +#define reg_pinmux_rw_pc_gio___pc8___width 1 +#define reg_pinmux_rw_pc_gio___pc8___bit 8 +#define reg_pinmux_rw_pc_gio___pc9___lsb 9 +#define reg_pinmux_rw_pc_gio___pc9___width 1 +#define reg_pinmux_rw_pc_gio___pc9___bit 9 +#define reg_pinmux_rw_pc_gio___pc10___lsb 10 +#define reg_pinmux_rw_pc_gio___pc10___width 1 +#define reg_pinmux_rw_pc_gio___pc10___bit 10 +#define reg_pinmux_rw_pc_gio___pc11___lsb 11 +#define reg_pinmux_rw_pc_gio___pc11___width 1 +#define reg_pinmux_rw_pc_gio___pc11___bit 11 +#define reg_pinmux_rw_pc_gio___pc12___lsb 12 +#define reg_pinmux_rw_pc_gio___pc12___width 1 +#define reg_pinmux_rw_pc_gio___pc12___bit 12 +#define reg_pinmux_rw_pc_gio___pc13___lsb 13 +#define reg_pinmux_rw_pc_gio___pc13___width 1 +#define reg_pinmux_rw_pc_gio___pc13___bit 13 +#define reg_pinmux_rw_pc_gio___pc14___lsb 14 +#define reg_pinmux_rw_pc_gio___pc14___width 1 +#define reg_pinmux_rw_pc_gio___pc14___bit 14 +#define reg_pinmux_rw_pc_gio___pc15___lsb 15 +#define reg_pinmux_rw_pc_gio___pc15___width 1 +#define reg_pinmux_rw_pc_gio___pc15___bit 15 +#define reg_pinmux_rw_pc_gio___pc16___lsb 16 +#define reg_pinmux_rw_pc_gio___pc16___width 1 +#define reg_pinmux_rw_pc_gio___pc16___bit 16 +#define reg_pinmux_rw_pc_gio___pc17___lsb 17 +#define reg_pinmux_rw_pc_gio___pc17___width 1 +#define reg_pinmux_rw_pc_gio___pc17___bit 17 +#define reg_pinmux_rw_pc_gio_offset 16 + +/* Register rw_pc_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pc_iop___pc0___lsb 0 +#define reg_pinmux_rw_pc_iop___pc0___width 1 +#define reg_pinmux_rw_pc_iop___pc0___bit 0 +#define reg_pinmux_rw_pc_iop___pc1___lsb 1 +#define reg_pinmux_rw_pc_iop___pc1___width 1 +#define reg_pinmux_rw_pc_iop___pc1___bit 1 +#define reg_pinmux_rw_pc_iop___pc2___lsb 2 +#define reg_pinmux_rw_pc_iop___pc2___width 1 +#define reg_pinmux_rw_pc_iop___pc2___bit 2 +#define reg_pinmux_rw_pc_iop___pc3___lsb 3 +#define reg_pinmux_rw_pc_iop___pc3___width 1 +#define reg_pinmux_rw_pc_iop___pc3___bit 3 +#define reg_pinmux_rw_pc_iop___pc4___lsb 4 +#define reg_pinmux_rw_pc_iop___pc4___width 1 +#define reg_pinmux_rw_pc_iop___pc4___bit 4 +#define reg_pinmux_rw_pc_iop___pc5___lsb 5 +#define reg_pinmux_rw_pc_iop___pc5___width 1 +#define reg_pinmux_rw_pc_iop___pc5___bit 5 +#define reg_pinmux_rw_pc_iop___pc6___lsb 6 +#define reg_pinmux_rw_pc_iop___pc6___width 1 +#define reg_pinmux_rw_pc_iop___pc6___bit 6 +#define reg_pinmux_rw_pc_iop___pc7___lsb 7 +#define reg_pinmux_rw_pc_iop___pc7___width 1 +#define reg_pinmux_rw_pc_iop___pc7___bit 7 +#define reg_pinmux_rw_pc_iop___pc8___lsb 8 +#define reg_pinmux_rw_pc_iop___pc8___width 1 +#define reg_pinmux_rw_pc_iop___pc8___bit 8 +#define reg_pinmux_rw_pc_iop___pc9___lsb 9 +#define reg_pinmux_rw_pc_iop___pc9___width 1 +#define reg_pinmux_rw_pc_iop___pc9___bit 9 +#define reg_pinmux_rw_pc_iop___pc10___lsb 10 +#define reg_pinmux_rw_pc_iop___pc10___width 1 +#define reg_pinmux_rw_pc_iop___pc10___bit 10 +#define reg_pinmux_rw_pc_iop___pc11___lsb 11 +#define reg_pinmux_rw_pc_iop___pc11___width 1 +#define reg_pinmux_rw_pc_iop___pc11___bit 11 +#define reg_pinmux_rw_pc_iop___pc12___lsb 12 +#define reg_pinmux_rw_pc_iop___pc12___width 1 +#define reg_pinmux_rw_pc_iop___pc12___bit 12 +#define reg_pinmux_rw_pc_iop___pc13___lsb 13 +#define reg_pinmux_rw_pc_iop___pc13___width 1 +#define reg_pinmux_rw_pc_iop___pc13___bit 13 +#define reg_pinmux_rw_pc_iop___pc14___lsb 14 +#define reg_pinmux_rw_pc_iop___pc14___width 1 +#define reg_pinmux_rw_pc_iop___pc14___bit 14 +#define reg_pinmux_rw_pc_iop___pc15___lsb 15 +#define reg_pinmux_rw_pc_iop___pc15___width 1 +#define reg_pinmux_rw_pc_iop___pc15___bit 15 +#define reg_pinmux_rw_pc_iop___pc16___lsb 16 +#define reg_pinmux_rw_pc_iop___pc16___width 1 +#define reg_pinmux_rw_pc_iop___pc16___bit 16 +#define reg_pinmux_rw_pc_iop___pc17___lsb 17 +#define reg_pinmux_rw_pc_iop___pc17___width 1 +#define reg_pinmux_rw_pc_iop___pc17___bit 17 +#define reg_pinmux_rw_pc_iop_offset 20 + +/* Register rw_pd_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pd_gio___pd0___lsb 0 +#define reg_pinmux_rw_pd_gio___pd0___width 1 +#define reg_pinmux_rw_pd_gio___pd0___bit 0 +#define reg_pinmux_rw_pd_gio___pd1___lsb 1 +#define reg_pinmux_rw_pd_gio___pd1___width 1 +#define reg_pinmux_rw_pd_gio___pd1___bit 1 +#define reg_pinmux_rw_pd_gio___pd2___lsb 2 +#define reg_pinmux_rw_pd_gio___pd2___width 1 +#define reg_pinmux_rw_pd_gio___pd2___bit 2 +#define reg_pinmux_rw_pd_gio___pd3___lsb 3 +#define reg_pinmux_rw_pd_gio___pd3___width 1 +#define reg_pinmux_rw_pd_gio___pd3___bit 3 +#define reg_pinmux_rw_pd_gio___pd4___lsb 4 +#define reg_pinmux_rw_pd_gio___pd4___width 1 +#define reg_pinmux_rw_pd_gio___pd4___bit 4 +#define reg_pinmux_rw_pd_gio___pd5___lsb 5 +#define reg_pinmux_rw_pd_gio___pd5___width 1 +#define reg_pinmux_rw_pd_gio___pd5___bit 5 +#define reg_pinmux_rw_pd_gio___pd6___lsb 6 +#define reg_pinmux_rw_pd_gio___pd6___width 1 +#define reg_pinmux_rw_pd_gio___pd6___bit 6 +#define reg_pinmux_rw_pd_gio___pd7___lsb 7 +#define reg_pinmux_rw_pd_gio___pd7___width 1 +#define reg_pinmux_rw_pd_gio___pd7___bit 7 +#define reg_pinmux_rw_pd_gio___pd8___lsb 8 +#define reg_pinmux_rw_pd_gio___pd8___width 1 +#define reg_pinmux_rw_pd_gio___pd8___bit 8 +#define reg_pinmux_rw_pd_gio___pd9___lsb 9 +#define reg_pinmux_rw_pd_gio___pd9___width 1 +#define reg_pinmux_rw_pd_gio___pd9___bit 9 +#define reg_pinmux_rw_pd_gio___pd10___lsb 10 +#define reg_pinmux_rw_pd_gio___pd10___width 1 +#define reg_pinmux_rw_pd_gio___pd10___bit 10 +#define reg_pinmux_rw_pd_gio___pd11___lsb 11 +#define reg_pinmux_rw_pd_gio___pd11___width 1 +#define reg_pinmux_rw_pd_gio___pd11___bit 11 +#define reg_pinmux_rw_pd_gio___pd12___lsb 12 +#define reg_pinmux_rw_pd_gio___pd12___width 1 +#define reg_pinmux_rw_pd_gio___pd12___bit 12 +#define reg_pinmux_rw_pd_gio___pd13___lsb 13 +#define reg_pinmux_rw_pd_gio___pd13___width 1 +#define reg_pinmux_rw_pd_gio___pd13___bit 13 +#define reg_pinmux_rw_pd_gio___pd14___lsb 14 +#define reg_pinmux_rw_pd_gio___pd14___width 1 +#define reg_pinmux_rw_pd_gio___pd14___bit 14 +#define reg_pinmux_rw_pd_gio___pd15___lsb 15 +#define reg_pinmux_rw_pd_gio___pd15___width 1 +#define reg_pinmux_rw_pd_gio___pd15___bit 15 +#define reg_pinmux_rw_pd_gio___pd16___lsb 16 +#define reg_pinmux_rw_pd_gio___pd16___width 1 +#define reg_pinmux_rw_pd_gio___pd16___bit 16 +#define reg_pinmux_rw_pd_gio___pd17___lsb 17 +#define reg_pinmux_rw_pd_gio___pd17___width 1 +#define reg_pinmux_rw_pd_gio___pd17___bit 17 +#define reg_pinmux_rw_pd_gio_offset 24 + +/* Register rw_pd_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pd_iop___pd0___lsb 0 +#define reg_pinmux_rw_pd_iop___pd0___width 1 +#define reg_pinmux_rw_pd_iop___pd0___bit 0 +#define reg_pinmux_rw_pd_iop___pd1___lsb 1 +#define reg_pinmux_rw_pd_iop___pd1___width 1 +#define reg_pinmux_rw_pd_iop___pd1___bit 1 +#define reg_pinmux_rw_pd_iop___pd2___lsb 2 +#define reg_pinmux_rw_pd_iop___pd2___width 1 +#define reg_pinmux_rw_pd_iop___pd2___bit 2 +#define reg_pinmux_rw_pd_iop___pd3___lsb 3 +#define reg_pinmux_rw_pd_iop___pd3___width 1 +#define reg_pinmux_rw_pd_iop___pd3___bit 3 +#define reg_pinmux_rw_pd_iop___pd4___lsb 4 +#define reg_pinmux_rw_pd_iop___pd4___width 1 +#define reg_pinmux_rw_pd_iop___pd4___bit 4 +#define reg_pinmux_rw_pd_iop___pd5___lsb 5 +#define reg_pinmux_rw_pd_iop___pd5___width 1 +#define reg_pinmux_rw_pd_iop___pd5___bit 5 +#define reg_pinmux_rw_pd_iop___pd6___lsb 6 +#define reg_pinmux_rw_pd_iop___pd6___width 1 +#define reg_pinmux_rw_pd_iop___pd6___bit 6 +#define reg_pinmux_rw_pd_iop___pd7___lsb 7 +#define reg_pinmux_rw_pd_iop___pd7___width 1 +#define reg_pinmux_rw_pd_iop___pd7___bit 7 +#define reg_pinmux_rw_pd_iop___pd8___lsb 8 +#define reg_pinmux_rw_pd_iop___pd8___width 1 +#define reg_pinmux_rw_pd_iop___pd8___bit 8 +#define reg_pinmux_rw_pd_iop___pd9___lsb 9 +#define reg_pinmux_rw_pd_iop___pd9___width 1 +#define reg_pinmux_rw_pd_iop___pd9___bit 9 +#define reg_pinmux_rw_pd_iop___pd10___lsb 10 +#define reg_pinmux_rw_pd_iop___pd10___width 1 +#define reg_pinmux_rw_pd_iop___pd10___bit 10 +#define reg_pinmux_rw_pd_iop___pd11___lsb 11 +#define reg_pinmux_rw_pd_iop___pd11___width 1 +#define reg_pinmux_rw_pd_iop___pd11___bit 11 +#define reg_pinmux_rw_pd_iop___pd12___lsb 12 +#define reg_pinmux_rw_pd_iop___pd12___width 1 +#define reg_pinmux_rw_pd_iop___pd12___bit 12 +#define reg_pinmux_rw_pd_iop___pd13___lsb 13 +#define reg_pinmux_rw_pd_iop___pd13___width 1 +#define reg_pinmux_rw_pd_iop___pd13___bit 13 +#define reg_pinmux_rw_pd_iop___pd14___lsb 14 +#define reg_pinmux_rw_pd_iop___pd14___width 1 +#define reg_pinmux_rw_pd_iop___pd14___bit 14 +#define reg_pinmux_rw_pd_iop___pd15___lsb 15 +#define reg_pinmux_rw_pd_iop___pd15___width 1 +#define reg_pinmux_rw_pd_iop___pd15___bit 15 +#define reg_pinmux_rw_pd_iop___pd16___lsb 16 +#define reg_pinmux_rw_pd_iop___pd16___width 1 +#define reg_pinmux_rw_pd_iop___pd16___bit 16 +#define reg_pinmux_rw_pd_iop___pd17___lsb 17 +#define reg_pinmux_rw_pd_iop___pd17___width 1 +#define reg_pinmux_rw_pd_iop___pd17___bit 17 +#define reg_pinmux_rw_pd_iop_offset 28 + +/* Register rw_pe_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pe_gio___pe0___lsb 0 +#define reg_pinmux_rw_pe_gio___pe0___width 1 +#define reg_pinmux_rw_pe_gio___pe0___bit 0 +#define reg_pinmux_rw_pe_gio___pe1___lsb 1 +#define reg_pinmux_rw_pe_gio___pe1___width 1 +#define reg_pinmux_rw_pe_gio___pe1___bit 1 +#define reg_pinmux_rw_pe_gio___pe2___lsb 2 +#define reg_pinmux_rw_pe_gio___pe2___width 1 +#define reg_pinmux_rw_pe_gio___pe2___bit 2 +#define reg_pinmux_rw_pe_gio___pe3___lsb 3 +#define reg_pinmux_rw_pe_gio___pe3___width 1 +#define reg_pinmux_rw_pe_gio___pe3___bit 3 +#define reg_pinmux_rw_pe_gio___pe4___lsb 4 +#define reg_pinmux_rw_pe_gio___pe4___width 1 +#define reg_pinmux_rw_pe_gio___pe4___bit 4 +#define reg_pinmux_rw_pe_gio___pe5___lsb 5 +#define reg_pinmux_rw_pe_gio___pe5___width 1 +#define reg_pinmux_rw_pe_gio___pe5___bit 5 +#define reg_pinmux_rw_pe_gio___pe6___lsb 6 +#define reg_pinmux_rw_pe_gio___pe6___width 1 +#define reg_pinmux_rw_pe_gio___pe6___bit 6 +#define reg_pinmux_rw_pe_gio___pe7___lsb 7 +#define reg_pinmux_rw_pe_gio___pe7___width 1 +#define reg_pinmux_rw_pe_gio___pe7___bit 7 +#define reg_pinmux_rw_pe_gio___pe8___lsb 8 +#define reg_pinmux_rw_pe_gio___pe8___width 1 +#define reg_pinmux_rw_pe_gio___pe8___bit 8 +#define reg_pinmux_rw_pe_gio___pe9___lsb 9 +#define reg_pinmux_rw_pe_gio___pe9___width 1 +#define reg_pinmux_rw_pe_gio___pe9___bit 9 +#define reg_pinmux_rw_pe_gio___pe10___lsb 10 +#define reg_pinmux_rw_pe_gio___pe10___width 1 +#define reg_pinmux_rw_pe_gio___pe10___bit 10 +#define reg_pinmux_rw_pe_gio___pe11___lsb 11 +#define reg_pinmux_rw_pe_gio___pe11___width 1 +#define reg_pinmux_rw_pe_gio___pe11___bit 11 +#define reg_pinmux_rw_pe_gio___pe12___lsb 12 +#define reg_pinmux_rw_pe_gio___pe12___width 1 +#define reg_pinmux_rw_pe_gio___pe12___bit 12 +#define reg_pinmux_rw_pe_gio___pe13___lsb 13 +#define reg_pinmux_rw_pe_gio___pe13___width 1 +#define reg_pinmux_rw_pe_gio___pe13___bit 13 +#define reg_pinmux_rw_pe_gio___pe14___lsb 14 +#define reg_pinmux_rw_pe_gio___pe14___width 1 +#define reg_pinmux_rw_pe_gio___pe14___bit 14 +#define reg_pinmux_rw_pe_gio___pe15___lsb 15 +#define reg_pinmux_rw_pe_gio___pe15___width 1 +#define reg_pinmux_rw_pe_gio___pe15___bit 15 +#define reg_pinmux_rw_pe_gio___pe16___lsb 16 +#define reg_pinmux_rw_pe_gio___pe16___width 1 +#define reg_pinmux_rw_pe_gio___pe16___bit 16 +#define reg_pinmux_rw_pe_gio___pe17___lsb 17 +#define reg_pinmux_rw_pe_gio___pe17___width 1 +#define reg_pinmux_rw_pe_gio___pe17___bit 17 +#define reg_pinmux_rw_pe_gio_offset 32 + +/* Register rw_pe_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pe_iop___pe0___lsb 0 +#define reg_pinmux_rw_pe_iop___pe0___width 1 +#define reg_pinmux_rw_pe_iop___pe0___bit 0 +#define reg_pinmux_rw_pe_iop___pe1___lsb 1 +#define reg_pinmux_rw_pe_iop___pe1___width 1 +#define reg_pinmux_rw_pe_iop___pe1___bit 1 +#define reg_pinmux_rw_pe_iop___pe2___lsb 2 +#define reg_pinmux_rw_pe_iop___pe2___width 1 +#define reg_pinmux_rw_pe_iop___pe2___bit 2 +#define reg_pinmux_rw_pe_iop___pe3___lsb 3 +#define reg_pinmux_rw_pe_iop___pe3___width 1 +#define reg_pinmux_rw_pe_iop___pe3___bit 3 +#define reg_pinmux_rw_pe_iop___pe4___lsb 4 +#define reg_pinmux_rw_pe_iop___pe4___width 1 +#define reg_pinmux_rw_pe_iop___pe4___bit 4 +#define reg_pinmux_rw_pe_iop___pe5___lsb 5 +#define reg_pinmux_rw_pe_iop___pe5___width 1 +#define reg_pinmux_rw_pe_iop___pe5___bit 5 +#define reg_pinmux_rw_pe_iop___pe6___lsb 6 +#define reg_pinmux_rw_pe_iop___pe6___width 1 +#define reg_pinmux_rw_pe_iop___pe6___bit 6 +#define reg_pinmux_rw_pe_iop___pe7___lsb 7 +#define reg_pinmux_rw_pe_iop___pe7___width 1 +#define reg_pinmux_rw_pe_iop___pe7___bit 7 +#define reg_pinmux_rw_pe_iop___pe8___lsb 8 +#define reg_pinmux_rw_pe_iop___pe8___width 1 +#define reg_pinmux_rw_pe_iop___pe8___bit 8 +#define reg_pinmux_rw_pe_iop___pe9___lsb 9 +#define reg_pinmux_rw_pe_iop___pe9___width 1 +#define reg_pinmux_rw_pe_iop___pe9___bit 9 +#define reg_pinmux_rw_pe_iop___pe10___lsb 10 +#define reg_pinmux_rw_pe_iop___pe10___width 1 +#define reg_pinmux_rw_pe_iop___pe10___bit 10 +#define reg_pinmux_rw_pe_iop___pe11___lsb 11 +#define reg_pinmux_rw_pe_iop___pe11___width 1 +#define reg_pinmux_rw_pe_iop___pe11___bit 11 +#define reg_pinmux_rw_pe_iop___pe12___lsb 12 +#define reg_pinmux_rw_pe_iop___pe12___width 1 +#define reg_pinmux_rw_pe_iop___pe12___bit 12 +#define reg_pinmux_rw_pe_iop___pe13___lsb 13 +#define reg_pinmux_rw_pe_iop___pe13___width 1 +#define reg_pinmux_rw_pe_iop___pe13___bit 13 +#define reg_pinmux_rw_pe_iop___pe14___lsb 14 +#define reg_pinmux_rw_pe_iop___pe14___width 1 +#define reg_pinmux_rw_pe_iop___pe14___bit 14 +#define reg_pinmux_rw_pe_iop___pe15___lsb 15 +#define reg_pinmux_rw_pe_iop___pe15___width 1 +#define reg_pinmux_rw_pe_iop___pe15___bit 15 +#define reg_pinmux_rw_pe_iop___pe16___lsb 16 +#define reg_pinmux_rw_pe_iop___pe16___width 1 +#define reg_pinmux_rw_pe_iop___pe16___bit 16 +#define reg_pinmux_rw_pe_iop___pe17___lsb 17 +#define reg_pinmux_rw_pe_iop___pe17___width 1 +#define reg_pinmux_rw_pe_iop___pe17___bit 17 +#define reg_pinmux_rw_pe_iop_offset 36 + +/* Register rw_usb_phy, scope pinmux, type rw */ +#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0 +#define reg_pinmux_rw_usb_phy___en_usb0___width 1 +#define reg_pinmux_rw_usb_phy___en_usb0___bit 0 +#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1 +#define reg_pinmux_rw_usb_phy___en_usb1___width 1 +#define reg_pinmux_rw_usb_phy___en_usb1___bit 1 +#define reg_pinmux_rw_usb_phy_offset 40 + + +/* Constants */ +#define regk_pinmux_no 0x00000000 +#define regk_pinmux_rw_hwprot_default 0x00000000 +#define regk_pinmux_rw_pa_default 0x00000000 +#define regk_pinmux_rw_pb_gio_default 0x00000000 +#define regk_pinmux_rw_pb_iop_default 0x00000000 +#define regk_pinmux_rw_pc_gio_default 0x00000000 +#define regk_pinmux_rw_pc_iop_default 0x00000000 +#define regk_pinmux_rw_pd_gio_default 0x00000000 +#define regk_pinmux_rw_pd_iop_default 0x00000000 +#define regk_pinmux_rw_pe_gio_default 0x00000000 +#define regk_pinmux_rw_pe_iop_default 0x00000000 +#define regk_pinmux_rw_usb_phy_default 0x00000000 +#define regk_pinmux_yes 0x00000001 +#endif /* __pinmux_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h new file mode 100644 index 00000000000..87517aebd2c --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h @@ -0,0 +1,96 @@ +#ifndef __reg_map_h +#define __reg_map_h + +/* + * This file is autogenerated from + * file: ../../mod/fakereg.rmap + * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp + * last modified: Wed Feb 11 20:53:25 2004 + * file: ../../rtl/global.rmap + * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp + * last modified: Mon Aug 18 17:08:23 2003 + * file: ../../mod/modreg.rmap + * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp + * last modified: Fri Feb 20 16:40:04 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap + * id: $Id: reg_map_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +#define regi_artpec_mod 0xb7044000 +#define regi_ata 0xb0032000 +#define regi_ata_mod 0xb7006000 +#define regi_barber 0xb701a000 +#define regi_bif_core 0xb0014000 +#define regi_bif_dma 0xb0016000 +#define regi_bif_slave 0xb0018000 +#define regi_bif_slave_ext 0xac000000 +#define regi_bus_master 0xb703c000 +#define regi_config 0xb003c000 +#define regi_dma0 0xb0000000 +#define regi_dma1 0xb0002000 +#define regi_dma2 0xb0004000 +#define regi_dma3 0xb0006000 +#define regi_dma4 0xb0008000 +#define regi_dma5 0xb000a000 +#define regi_dma6 0xb000c000 +#define regi_dma7 0xb000e000 +#define regi_dma8 0xb0010000 +#define regi_dma9 0xb0012000 +#define regi_eth0 0xb0034000 +#define regi_eth1 0xb0036000 +#define regi_eth_mod 0xb7004000 +#define regi_eth_mod1 0xb701c000 +#define regi_eth_strmod 0xb7008000 +#define regi_eth_strmod1 0xb7032000 +#define regi_ext_dma 0xb703a000 +#define regi_ext_mem 0xb7046000 +#define regi_gen_io 0xb7016000 +#define regi_gio 0xb001a000 +#define regi_hook 0xb7000000 +#define regi_iop 0xb0020000 +#define regi_irq 0xb001c000 +#define regi_irq_nmi 0xb701e000 +#define regi_marb 0xb003e000 +#define regi_marb_bp0 0xb003e240 +#define regi_marb_bp1 0xb003e280 +#define regi_marb_bp2 0xb003e2c0 +#define regi_marb_bp3 0xb003e300 +#define regi_nand_mod 0xb7014000 +#define regi_p21 0xb002e000 +#define regi_p21_mod 0xb7042000 +#define regi_pci_mod 0xb7010000 +#define regi_pin_test 0xb7018000 +#define regi_pinmux 0xb0038000 +#define regi_sdram_chk 0xb703e000 +#define regi_sdram_mod 0xb7012000 +#define regi_ser0 0xb0026000 +#define regi_ser1 0xb0028000 +#define regi_ser2 0xb002a000 +#define regi_ser3 0xb002c000 +#define regi_ser_mod0 0xb7020000 +#define regi_ser_mod1 0xb7022000 +#define regi_ser_mod2 0xb7024000 +#define regi_ser_mod3 0xb7026000 +#define regi_smif_stat 0xb700e000 +#define regi_sser0 0xb0022000 +#define regi_sser1 0xb0024000 +#define regi_sser_mod0 0xb700a000 +#define regi_sser_mod1 0xb700c000 +#define regi_strcop 0xb0030000 +#define regi_strmux 0xb003a000 +#define regi_strmux_tst 0xb7040000 +#define regi_tap 0xb7002000 +#define regi_timer 0xb001e000 +#define regi_timer_mod 0xb7034000 +#define regi_trace 0xb0040000 +#define regi_usb0 0xb7028000 +#define regi_usb1 0xb702a000 +#define regi_usb2 0xb702c000 +#define regi_usb3 0xb702e000 +#define regi_usb_dev 0xb7030000 +#define regi_utmi_mod0 0xb7036000 +#define regi_utmi_mod1 0xb7038000 +#endif /* __reg_map_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h new file mode 100644 index 00000000000..e1197194d5c --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h @@ -0,0 +1,229 @@ +#ifndef __timer_defs_asm_h +#define __timer_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/timer/rtl/timer_regs.r + * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp + * last modfied: Mon Apr 11 16:09:53 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r + * id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_tmr0_div, scope timer, type rw */ +#define reg_timer_rw_tmr0_div_offset 0 + +/* Register r_tmr0_data, scope timer, type r */ +#define reg_timer_r_tmr0_data_offset 4 + +/* Register rw_tmr0_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr0_ctrl___op___lsb 0 +#define reg_timer_rw_tmr0_ctrl___op___width 2 +#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr0_ctrl___freq___width 3 +#define reg_timer_rw_tmr0_ctrl_offset 8 + +/* Register rw_tmr1_div, scope timer, type rw */ +#define reg_timer_rw_tmr1_div_offset 16 + +/* Register r_tmr1_data, scope timer, type r */ +#define reg_timer_r_tmr1_data_offset 20 + +/* Register rw_tmr1_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr1_ctrl___op___lsb 0 +#define reg_timer_rw_tmr1_ctrl___op___width 2 +#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr1_ctrl___freq___width 3 +#define reg_timer_rw_tmr1_ctrl_offset 24 + +/* Register rs_cnt_data, scope timer, type rs */ +#define reg_timer_rs_cnt_data___tmr___lsb 0 +#define reg_timer_rs_cnt_data___tmr___width 24 +#define reg_timer_rs_cnt_data___cnt___lsb 24 +#define reg_timer_rs_cnt_data___cnt___width 8 +#define reg_timer_rs_cnt_data_offset 32 + +/* Register r_cnt_data, scope timer, type r */ +#define reg_timer_r_cnt_data___tmr___lsb 0 +#define reg_timer_r_cnt_data___tmr___width 24 +#define reg_timer_r_cnt_data___cnt___lsb 24 +#define reg_timer_r_cnt_data___cnt___width 8 +#define reg_timer_r_cnt_data_offset 36 + +/* Register rw_cnt_cfg, scope timer, type rw */ +#define reg_timer_rw_cnt_cfg___clk___lsb 0 +#define reg_timer_rw_cnt_cfg___clk___width 2 +#define reg_timer_rw_cnt_cfg_offset 40 + +/* Register rw_trig, scope timer, type rw */ +#define reg_timer_rw_trig_offset 48 + +/* Register rw_trig_cfg, scope timer, type rw */ +#define reg_timer_rw_trig_cfg___tmr___lsb 0 +#define reg_timer_rw_trig_cfg___tmr___width 2 +#define reg_timer_rw_trig_cfg_offset 52 + +/* Register r_time, scope timer, type r */ +#define reg_timer_r_time_offset 56 + +/* Register rw_out, scope timer, type rw */ +#define reg_timer_rw_out___tmr___lsb 0 +#define reg_timer_rw_out___tmr___width 2 +#define reg_timer_rw_out_offset 60 + +/* Register rw_wd_ctrl, scope timer, type rw */ +#define reg_timer_rw_wd_ctrl___cnt___lsb 0 +#define reg_timer_rw_wd_ctrl___cnt___width 8 +#define reg_timer_rw_wd_ctrl___cmd___lsb 8 +#define reg_timer_rw_wd_ctrl___cmd___width 1 +#define reg_timer_rw_wd_ctrl___cmd___bit 8 +#define reg_timer_rw_wd_ctrl___key___lsb 9 +#define reg_timer_rw_wd_ctrl___key___width 7 +#define reg_timer_rw_wd_ctrl_offset 64 + +/* Register r_wd_stat, scope timer, type r */ +#define reg_timer_r_wd_stat___cnt___lsb 0 +#define reg_timer_r_wd_stat___cnt___width 8 +#define reg_timer_r_wd_stat___cmd___lsb 8 +#define reg_timer_r_wd_stat___cmd___width 1 +#define reg_timer_r_wd_stat___cmd___bit 8 +#define reg_timer_r_wd_stat_offset 68 + +/* Register rw_intr_mask, scope timer, type rw */ +#define reg_timer_rw_intr_mask___tmr0___lsb 0 +#define reg_timer_rw_intr_mask___tmr0___width 1 +#define reg_timer_rw_intr_mask___tmr0___bit 0 +#define reg_timer_rw_intr_mask___tmr1___lsb 1 +#define reg_timer_rw_intr_mask___tmr1___width 1 +#define reg_timer_rw_intr_mask___tmr1___bit 1 +#define reg_timer_rw_intr_mask___cnt___lsb 2 +#define reg_timer_rw_intr_mask___cnt___width 1 +#define reg_timer_rw_intr_mask___cnt___bit 2 +#define reg_timer_rw_intr_mask___trig___lsb 3 +#define reg_timer_rw_intr_mask___trig___width 1 +#define reg_timer_rw_intr_mask___trig___bit 3 +#define reg_timer_rw_intr_mask_offset 72 + +/* Register rw_ack_intr, scope timer, type rw */ +#define reg_timer_rw_ack_intr___tmr0___lsb 0 +#define reg_timer_rw_ack_intr___tmr0___width 1 +#define reg_timer_rw_ack_intr___tmr0___bit 0 +#define reg_timer_rw_ack_intr___tmr1___lsb 1 +#define reg_timer_rw_ack_intr___tmr1___width 1 +#define reg_timer_rw_ack_intr___tmr1___bit 1 +#define reg_timer_rw_ack_intr___cnt___lsb 2 +#define reg_timer_rw_ack_intr___cnt___width 1 +#define reg_timer_rw_ack_intr___cnt___bit 2 +#define reg_timer_rw_ack_intr___trig___lsb 3 +#define reg_timer_rw_ack_intr___trig___width 1 +#define reg_timer_rw_ack_intr___trig___bit 3 +#define reg_timer_rw_ack_intr_offset 76 + +/* Register r_intr, scope timer, type r */ +#define reg_timer_r_intr___tmr0___lsb 0 +#define reg_timer_r_intr___tmr0___width 1 +#define reg_timer_r_intr___tmr0___bit 0 +#define reg_timer_r_intr___tmr1___lsb 1 +#define reg_timer_r_intr___tmr1___width 1 +#define reg_timer_r_intr___tmr1___bit 1 +#define reg_timer_r_intr___cnt___lsb 2 +#define reg_timer_r_intr___cnt___width 1 +#define reg_timer_r_intr___cnt___bit 2 +#define reg_timer_r_intr___trig___lsb 3 +#define reg_timer_r_intr___trig___width 1 +#define reg_timer_r_intr___trig___bit 3 +#define reg_timer_r_intr_offset 80 + +/* Register r_masked_intr, scope timer, type r */ +#define reg_timer_r_masked_intr___tmr0___lsb 0 +#define reg_timer_r_masked_intr___tmr0___width 1 +#define reg_timer_r_masked_intr___tmr0___bit 0 +#define reg_timer_r_masked_intr___tmr1___lsb 1 +#define reg_timer_r_masked_intr___tmr1___width 1 +#define reg_timer_r_masked_intr___tmr1___bit 1 +#define reg_timer_r_masked_intr___cnt___lsb 2 +#define reg_timer_r_masked_intr___cnt___width 1 +#define reg_timer_r_masked_intr___cnt___bit 2 +#define reg_timer_r_masked_intr___trig___lsb 3 +#define reg_timer_r_masked_intr___trig___width 1 +#define reg_timer_r_masked_intr___trig___bit 3 +#define reg_timer_r_masked_intr_offset 84 + +/* Register rw_test, scope timer, type rw */ +#define reg_timer_rw_test___dis___lsb 0 +#define reg_timer_rw_test___dis___width 1 +#define reg_timer_rw_test___dis___bit 0 +#define reg_timer_rw_test___en___lsb 1 +#define reg_timer_rw_test___en___width 1 +#define reg_timer_rw_test___en___bit 1 +#define reg_timer_rw_test_offset 88 + + +/* Constants */ +#define regk_timer_ext 0x00000001 +#define regk_timer_f100 0x00000007 +#define regk_timer_f29_493 0x00000004 +#define regk_timer_f32 0x00000005 +#define regk_timer_f32_768 0x00000006 +#define regk_timer_hold 0x00000001 +#define regk_timer_ld 0x00000000 +#define regk_timer_no 0x00000000 +#define regk_timer_off 0x00000000 +#define regk_timer_run 0x00000002 +#define regk_timer_rw_cnt_cfg_default 0x00000000 +#define regk_timer_rw_intr_mask_default 0x00000000 +#define regk_timer_rw_out_default 0x00000000 +#define regk_timer_rw_test_default 0x00000000 +#define regk_timer_rw_tmr0_ctrl_default 0x00000000 +#define regk_timer_rw_tmr1_ctrl_default 0x00000000 +#define regk_timer_rw_trig_cfg_default 0x00000000 +#define regk_timer_start 0x00000001 +#define regk_timer_stop 0x00000000 +#define regk_timer_time 0x00000001 +#define regk_timer_tmr0 0x00000002 +#define regk_timer_tmr1 0x00000003 +#define regk_timer_yes 0x00000001 +#endif /* __timer_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h new file mode 100644 index 00000000000..44362a62b47 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h @@ -0,0 +1,284 @@ +#ifndef __bif_core_defs_h +#define __bif_core_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_core_regs.r + * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r + * id: $Id: bif_core_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_core */ + +/* Register rw_grp1_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 10; +} reg_bif_core_rw_grp1_cfg; +#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 +#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 + +/* Register rw_grp2_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 10; +} reg_bif_core_rw_grp2_cfg; +#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 +#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 + +/* Register rw_grp3_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 2; + unsigned int gated_csp0 : 2; + unsigned int gated_csp1 : 2; + unsigned int gated_csp2 : 2; + unsigned int gated_csp3 : 2; +} reg_bif_core_rw_grp3_cfg; +#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 +#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 + +/* Register rw_grp4_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 4; + unsigned int gated_csp4 : 2; + unsigned int gated_csp5 : 2; + unsigned int gated_csp6 : 2; +} reg_bif_core_rw_grp4_cfg; +#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 +#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 + +/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ +typedef struct { + unsigned int bank_sel : 5; + unsigned int ca : 3; + unsigned int type : 1; + unsigned int bw : 1; + unsigned int sh : 3; + unsigned int wmm : 1; + unsigned int sh16 : 1; + unsigned int grp_sel : 5; + unsigned int dummy1 : 12; +} reg_bif_core_rw_sdram_cfg_grp0; +#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 +#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 + +/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ +typedef struct { + unsigned int bank_sel : 5; + unsigned int ca : 3; + unsigned int type : 1; + unsigned int bw : 1; + unsigned int sh : 3; + unsigned int wmm : 1; + unsigned int sh16 : 1; + unsigned int dummy1 : 17; +} reg_bif_core_rw_sdram_cfg_grp1; +#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 +#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 + +/* Register rw_sdram_timing, scope bif_core, type rw */ +typedef struct { + unsigned int cl : 3; + unsigned int rcd : 3; + unsigned int rp : 3; + unsigned int rc : 2; + unsigned int dpl : 2; + unsigned int pde : 1; + unsigned int ref : 2; + unsigned int cpd : 1; + unsigned int sdcke : 1; + unsigned int sdclk : 1; + unsigned int dummy1 : 13; +} reg_bif_core_rw_sdram_timing; +#define REG_RD_ADDR_bif_core_rw_sdram_timing 24 +#define REG_WR_ADDR_bif_core_rw_sdram_timing 24 + +/* Register rw_sdram_cmd, scope bif_core, type rw */ +typedef struct { + unsigned int cmd : 3; + unsigned int mrs_data : 15; + unsigned int dummy1 : 14; +} reg_bif_core_rw_sdram_cmd; +#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 +#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 + +/* Register rs_sdram_ref_stat, scope bif_core, type rs */ +typedef struct { + unsigned int ok : 1; + unsigned int dummy1 : 31; +} reg_bif_core_rs_sdram_ref_stat; +#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 + +/* Register r_sdram_ref_stat, scope bif_core, type r */ +typedef struct { + unsigned int ok : 1; + unsigned int dummy1 : 31; +} reg_bif_core_r_sdram_ref_stat; +#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 + + +/* Constants */ +enum { + regk_bif_core_bank2 = 0x00000000, + regk_bif_core_bank4 = 0x00000001, + regk_bif_core_bit10 = 0x0000000a, + regk_bif_core_bit11 = 0x0000000b, + regk_bif_core_bit12 = 0x0000000c, + regk_bif_core_bit13 = 0x0000000d, + regk_bif_core_bit14 = 0x0000000e, + regk_bif_core_bit15 = 0x0000000f, + regk_bif_core_bit16 = 0x00000010, + regk_bif_core_bit17 = 0x00000011, + regk_bif_core_bit18 = 0x00000012, + regk_bif_core_bit19 = 0x00000013, + regk_bif_core_bit20 = 0x00000014, + regk_bif_core_bit21 = 0x00000015, + regk_bif_core_bit22 = 0x00000016, + regk_bif_core_bit23 = 0x00000017, + regk_bif_core_bit24 = 0x00000018, + regk_bif_core_bit25 = 0x00000019, + regk_bif_core_bit26 = 0x0000001a, + regk_bif_core_bit27 = 0x0000001b, + regk_bif_core_bit28 = 0x0000001c, + regk_bif_core_bit29 = 0x0000001d, + regk_bif_core_bit9 = 0x00000009, + regk_bif_core_bw16 = 0x00000001, + regk_bif_core_bw32 = 0x00000000, + regk_bif_core_bwe = 0x00000000, + regk_bif_core_cwe = 0x00000001, + regk_bif_core_e15us = 0x00000001, + regk_bif_core_e7800ns = 0x00000002, + regk_bif_core_grp0 = 0x00000000, + regk_bif_core_grp1 = 0x00000001, + regk_bif_core_mrs = 0x00000003, + regk_bif_core_no = 0x00000000, + regk_bif_core_none = 0x00000000, + regk_bif_core_nop = 0x00000000, + regk_bif_core_off = 0x00000000, + regk_bif_core_pre = 0x00000002, + regk_bif_core_r_sdram_ref_stat_default = 0x00000001, + regk_bif_core_rd = 0x00000002, + regk_bif_core_ref = 0x00000001, + regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, + regk_bif_core_rw_grp1_cfg_default = 0x000006cf, + regk_bif_core_rw_grp2_cfg_default = 0x000006cf, + regk_bif_core_rw_grp3_cfg_default = 0x000006cf, + regk_bif_core_rw_grp4_cfg_default = 0x000006cf, + regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, + regk_bif_core_slf = 0x00000004, + regk_bif_core_wr = 0x00000001, + regk_bif_core_yes = 0x00000001 +}; +#endif /* __bif_core_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h new file mode 100644 index 00000000000..3cb51a09dba --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h @@ -0,0 +1,473 @@ +#ifndef __bif_dma_defs_h +#define __bif_dma_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_dma_regs.r + * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r + * id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_dma */ + +/* Register rw_ch0_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_pad : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int wr_all : 1; + unsigned int dummy1 : 12; +} reg_bif_dma_rw_ch0_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 +#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 + +/* Register rw_ch0_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch0_addr; +#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 +#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 + +/* Register rw_ch0_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch0_start; +#define REG_RD_ADDR_bif_dma_rw_ch0_start 8 +#define REG_WR_ADDR_bif_dma_rw_ch0_start 8 + +/* Register rw_ch0_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch0_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 +#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 + +/* Register r_ch0_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch0_stat; +#define REG_RD_ADDR_bif_dma_r_ch0_stat 16 + +/* Register rw_ch1_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_discard : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int dummy1 : 13; +} reg_bif_dma_rw_ch1_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 +#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 + +/* Register rw_ch1_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch1_addr; +#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 +#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 + +/* Register rw_ch1_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch1_start; +#define REG_RD_ADDR_bif_dma_rw_ch1_start 40 +#define REG_WR_ADDR_bif_dma_rw_ch1_start 40 + +/* Register rw_ch1_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch1_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 +#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 + +/* Register r_ch1_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch1_stat; +#define REG_RD_ADDR_bif_dma_r_ch1_stat 48 + +/* Register rw_ch2_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_pad : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int wr_all : 1; + unsigned int dummy1 : 12; +} reg_bif_dma_rw_ch2_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 +#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 + +/* Register rw_ch2_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch2_addr; +#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 +#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 + +/* Register rw_ch2_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch2_start; +#define REG_RD_ADDR_bif_dma_rw_ch2_start 72 +#define REG_WR_ADDR_bif_dma_rw_ch2_start 72 + +/* Register rw_ch2_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch2_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 +#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 + +/* Register r_ch2_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch2_stat; +#define REG_RD_ADDR_bif_dma_r_ch2_stat 80 + +/* Register rw_ch3_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_discard : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int dummy1 : 13; +} reg_bif_dma_rw_ch3_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 +#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 + +/* Register rw_ch3_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch3_addr; +#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 +#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 + +/* Register rw_ch3_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch3_start; +#define REG_RD_ADDR_bif_dma_rw_ch3_start 104 +#define REG_WR_ADDR_bif_dma_rw_ch3_start 104 + +/* Register rw_ch3_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch3_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 +#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 + +/* Register r_ch3_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch3_stat; +#define REG_RD_ADDR_bif_dma_r_ch3_stat 112 + +/* Register rw_intr_mask, scope bif_dma, type rw */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_rw_intr_mask; +#define REG_RD_ADDR_bif_dma_rw_intr_mask 128 +#define REG_WR_ADDR_bif_dma_rw_intr_mask 128 + +/* Register rw_ack_intr, scope bif_dma, type rw */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_rw_ack_intr; +#define REG_RD_ADDR_bif_dma_rw_ack_intr 132 +#define REG_WR_ADDR_bif_dma_rw_ack_intr 132 + +/* Register r_intr, scope bif_dma, type r */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_r_intr; +#define REG_RD_ADDR_bif_dma_r_intr 136 + +/* Register r_masked_intr, scope bif_dma, type r */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_r_masked_intr; +#define REG_RD_ADDR_bif_dma_r_masked_intr 140 + +/* Register rw_pin0_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin0_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 +#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 + +/* Register rw_pin1_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin1_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 +#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 + +/* Register rw_pin2_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin2_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 +#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 + +/* Register rw_pin3_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin3_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 +#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 + +/* Register rw_pin4_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin4_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 +#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 + +/* Register rw_pin5_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin5_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 +#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 + +/* Register rw_pin6_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin6_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 +#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 + +/* Register rw_pin7_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin7_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 +#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 + +/* Register r_pin_stat, scope bif_dma, type r */ +typedef struct { + unsigned int pin0 : 1; + unsigned int pin1 : 1; + unsigned int pin2 : 1; + unsigned int pin3 : 1; + unsigned int pin4 : 1; + unsigned int pin5 : 1; + unsigned int pin6 : 1; + unsigned int pin7 : 1; + unsigned int dummy1 : 24; +} reg_bif_dma_r_pin_stat; +#define REG_RD_ADDR_bif_dma_r_pin_stat 192 + + +/* Constants */ +enum { + regk_bif_dma_as_master = 0x00000001, + regk_bif_dma_as_slave = 0x00000001, + regk_bif_dma_burst1 = 0x00000000, + regk_bif_dma_burst8 = 0x00000001, + regk_bif_dma_bw16 = 0x00000001, + regk_bif_dma_bw32 = 0x00000002, + regk_bif_dma_bw8 = 0x00000000, + regk_bif_dma_dack = 0x00000006, + regk_bif_dma_dack_inv = 0x00000007, + regk_bif_dma_force = 0x00000001, + regk_bif_dma_hi = 0x00000003, + regk_bif_dma_inv = 0x00000003, + regk_bif_dma_lo = 0x00000002, + regk_bif_dma_master = 0x00000001, + regk_bif_dma_no = 0x00000000, + regk_bif_dma_norm = 0x00000002, + regk_bif_dma_off = 0x00000000, + regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch0_start_default = 0x00000000, + regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch1_start_default = 0x00000000, + regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch2_start_default = 0x00000000, + regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch3_start_default = 0x00000000, + regk_bif_dma_rw_intr_mask_default = 0x00000000, + regk_bif_dma_rw_pin0_cfg_default = 0x00000000, + regk_bif_dma_rw_pin1_cfg_default = 0x00000000, + regk_bif_dma_rw_pin2_cfg_default = 0x00000000, + regk_bif_dma_rw_pin3_cfg_default = 0x00000000, + regk_bif_dma_rw_pin4_cfg_default = 0x00000000, + regk_bif_dma_rw_pin5_cfg_default = 0x00000000, + regk_bif_dma_rw_pin6_cfg_default = 0x00000000, + regk_bif_dma_rw_pin7_cfg_default = 0x00000000, + regk_bif_dma_slave = 0x00000002, + regk_bif_dma_sreq = 0x00000006, + regk_bif_dma_sreq_inv = 0x00000007, + regk_bif_dma_tc = 0x00000004, + regk_bif_dma_tc_inv = 0x00000005, + regk_bif_dma_yes = 0x00000001 +}; +#endif /* __bif_dma_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h new file mode 100644 index 00000000000..0c434585a3f --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h @@ -0,0 +1,249 @@ +#ifndef __bif_slave_defs_h +#define __bif_slave_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_slave_regs.r + * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp + * last modfied: Mon Apr 11 16:06:34 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r + * id: $Id: bif_slave_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_slave */ + +/* Register rw_slave_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int slave_id : 3; + unsigned int use_slave_id : 1; + unsigned int boot_rdy : 1; + unsigned int loopback : 1; + unsigned int dis : 1; + unsigned int dummy1 : 25; +} reg_bif_slave_rw_slave_cfg; +#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 +#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 + +/* Register r_slave_mode, scope bif_slave, type r */ +typedef struct { + unsigned int ch0_mode : 1; + unsigned int ch1_mode : 1; + unsigned int ch2_mode : 1; + unsigned int ch3_mode : 1; + unsigned int dummy1 : 28; +} reg_bif_slave_r_slave_mode; +#define REG_RD_ADDR_bif_slave_r_slave_mode 4 + +/* Register rw_ch0_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch0_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 +#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 + +/* Register rw_ch1_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch1_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 +#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 + +/* Register rw_ch2_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch2_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 +#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 + +/* Register rw_ch3_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch3_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 +#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 + +/* Register rw_arb_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int brin_mode : 1; + unsigned int brout_mode : 3; + unsigned int bg_mode : 3; + unsigned int release : 2; + unsigned int acquire : 1; + unsigned int settle_time : 2; + unsigned int dram_ctrl : 1; + unsigned int dummy1 : 19; +} reg_bif_slave_rw_arb_cfg; +#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 +#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 + +/* Register r_arb_stat, scope bif_slave, type r */ +typedef struct { + unsigned int init_mode : 1; + unsigned int mode : 1; + unsigned int brin : 1; + unsigned int brout : 1; + unsigned int bg : 1; + unsigned int dummy1 : 27; +} reg_bif_slave_r_arb_stat; +#define REG_RD_ADDR_bif_slave_r_arb_stat 36 + +/* Register rw_intr_mask, scope bif_slave, type rw */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_rw_intr_mask; +#define REG_RD_ADDR_bif_slave_rw_intr_mask 64 +#define REG_WR_ADDR_bif_slave_rw_intr_mask 64 + +/* Register rw_ack_intr, scope bif_slave, type rw */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_rw_ack_intr; +#define REG_RD_ADDR_bif_slave_rw_ack_intr 68 +#define REG_WR_ADDR_bif_slave_rw_ack_intr 68 + +/* Register r_intr, scope bif_slave, type r */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_r_intr; +#define REG_RD_ADDR_bif_slave_r_intr 72 + +/* Register r_masked_intr, scope bif_slave, type r */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_r_masked_intr; +#define REG_RD_ADDR_bif_slave_r_masked_intr 76 + + +/* Constants */ +enum { + regk_bif_slave_active_hi = 0x00000003, + regk_bif_slave_active_lo = 0x00000002, + regk_bif_slave_addr = 0x00000000, + regk_bif_slave_always = 0x00000001, + regk_bif_slave_at_idle = 0x00000002, + regk_bif_slave_burst_end = 0x00000003, + regk_bif_slave_dma = 0x00000001, + regk_bif_slave_hi = 0x00000003, + regk_bif_slave_inv = 0x00000001, + regk_bif_slave_lo = 0x00000002, + regk_bif_slave_local = 0x00000001, + regk_bif_slave_master = 0x00000000, + regk_bif_slave_mode_reg = 0x00000001, + regk_bif_slave_no = 0x00000000, + regk_bif_slave_norm = 0x00000000, + regk_bif_slave_on_access = 0x00000000, + regk_bif_slave_rw_arb_cfg_default = 0x00000000, + regk_bif_slave_rw_ch0_cfg_default = 0x00000000, + regk_bif_slave_rw_ch1_cfg_default = 0x00000000, + regk_bif_slave_rw_ch2_cfg_default = 0x00000000, + regk_bif_slave_rw_ch3_cfg_default = 0x00000000, + regk_bif_slave_rw_intr_mask_default = 0x00000000, + regk_bif_slave_rw_slave_cfg_default = 0x00000000, + regk_bif_slave_shared = 0x00000000, + regk_bif_slave_slave = 0x00000001, + regk_bif_slave_t0ns = 0x00000003, + regk_bif_slave_t10ns = 0x00000002, + regk_bif_slave_t20ns = 0x00000003, + regk_bif_slave_t30ns = 0x00000002, + regk_bif_slave_t40ns = 0x00000001, + regk_bif_slave_t50ns = 0x00000000, + regk_bif_slave_yes = 0x00000001, + regk_bif_slave_z = 0x00000004 +}; +#endif /* __bif_slave_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h new file mode 100644 index 00000000000..abc5f20705f --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h @@ -0,0 +1,142 @@ +#ifndef __config_defs_h +#define __config_defs_h + +/* + * This file is autogenerated from + * file: ../../rtl/config_regs.r + * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp + * last modfied: Thu Mar 4 12:34:39 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r + * id: $Id: config_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope config */ + +/* Register r_bootsel, scope config, type r */ +typedef struct { + unsigned int boot_mode : 3; + unsigned int full_duplex : 1; + unsigned int user : 1; + unsigned int pll : 1; + unsigned int flash_bw : 1; + unsigned int dummy1 : 25; +} reg_config_r_bootsel; +#define REG_RD_ADDR_config_r_bootsel 0 + +/* Register rw_clk_ctrl, scope config, type rw */ +typedef struct { + unsigned int pll : 1; + unsigned int cpu : 1; + unsigned int iop : 1; + unsigned int dma01_eth0 : 1; + unsigned int dma23 : 1; + unsigned int dma45 : 1; + unsigned int dma67 : 1; + unsigned int dma89_strcop : 1; + unsigned int bif : 1; + unsigned int fix_io : 1; + unsigned int dummy1 : 22; +} reg_config_rw_clk_ctrl; +#define REG_RD_ADDR_config_rw_clk_ctrl 4 +#define REG_WR_ADDR_config_rw_clk_ctrl 4 + +/* Register rw_pad_ctrl, scope config, type rw */ +typedef struct { + unsigned int usb_susp : 1; + unsigned int phyrst_n : 1; + unsigned int dummy1 : 30; +} reg_config_rw_pad_ctrl; +#define REG_RD_ADDR_config_rw_pad_ctrl 8 +#define REG_WR_ADDR_config_rw_pad_ctrl 8 + + +/* Constants */ +enum { + regk_config_bw16 = 0x00000000, + regk_config_bw32 = 0x00000001, + regk_config_master = 0x00000005, + regk_config_nand = 0x00000003, + regk_config_net_rx = 0x00000001, + regk_config_net_tx_rx = 0x00000002, + regk_config_no = 0x00000000, + regk_config_none = 0x00000007, + regk_config_nor = 0x00000000, + regk_config_rw_clk_ctrl_default = 0x00000002, + regk_config_rw_pad_ctrl_default = 0x00000000, + regk_config_ser = 0x00000004, + regk_config_slave = 0x00000006, + regk_config_yes = 0x00000001 +}; +#endif /* __config_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h new file mode 100644 index 00000000000..26aa3efcf91 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h @@ -0,0 +1,295 @@ +#ifndef __gio_defs_h +#define __gio_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/gio/rtl/gio_regs.r + * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp + * last modfied: Mon Apr 11 16:07:47 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r + * id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope gio */ + +/* Register rw_pa_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_dout; +#define REG_RD_ADDR_gio_rw_pa_dout 0 +#define REG_WR_ADDR_gio_rw_pa_dout 0 + +/* Register r_pa_din, scope gio, type r */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_r_pa_din; +#define REG_RD_ADDR_gio_r_pa_din 4 + +/* Register rw_pa_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_oe; +#define REG_RD_ADDR_gio_rw_pa_oe 8 +#define REG_WR_ADDR_gio_rw_pa_oe 8 + +/* Register rw_intr_cfg, scope gio, type rw */ +typedef struct { + unsigned int pa0 : 3; + unsigned int pa1 : 3; + unsigned int pa2 : 3; + unsigned int pa3 : 3; + unsigned int pa4 : 3; + unsigned int pa5 : 3; + unsigned int pa6 : 3; + unsigned int pa7 : 3; + unsigned int dummy1 : 8; +} reg_gio_rw_intr_cfg; +#define REG_RD_ADDR_gio_rw_intr_cfg 12 +#define REG_WR_ADDR_gio_rw_intr_cfg 12 + +/* Register rw_intr_mask, scope gio, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_rw_intr_mask; +#define REG_RD_ADDR_gio_rw_intr_mask 16 +#define REG_WR_ADDR_gio_rw_intr_mask 16 + +/* Register rw_ack_intr, scope gio, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_rw_ack_intr; +#define REG_RD_ADDR_gio_rw_ack_intr 20 +#define REG_WR_ADDR_gio_rw_ack_intr 20 + +/* Register r_intr, scope gio, type r */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_r_intr; +#define REG_RD_ADDR_gio_r_intr 24 + +/* Register r_masked_intr, scope gio, type r */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_r_masked_intr; +#define REG_RD_ADDR_gio_r_masked_intr 28 + +/* Register rw_pb_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pb_dout; +#define REG_RD_ADDR_gio_rw_pb_dout 32 +#define REG_WR_ADDR_gio_rw_pb_dout 32 + +/* Register r_pb_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pb_din; +#define REG_RD_ADDR_gio_r_pb_din 36 + +/* Register rw_pb_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pb_oe; +#define REG_RD_ADDR_gio_rw_pb_oe 40 +#define REG_WR_ADDR_gio_rw_pb_oe 40 + +/* Register rw_pc_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pc_dout; +#define REG_RD_ADDR_gio_rw_pc_dout 48 +#define REG_WR_ADDR_gio_rw_pc_dout 48 + +/* Register r_pc_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pc_din; +#define REG_RD_ADDR_gio_r_pc_din 52 + +/* Register rw_pc_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pc_oe; +#define REG_RD_ADDR_gio_rw_pc_oe 56 +#define REG_WR_ADDR_gio_rw_pc_oe 56 + +/* Register rw_pd_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pd_dout; +#define REG_RD_ADDR_gio_rw_pd_dout 64 +#define REG_WR_ADDR_gio_rw_pd_dout 64 + +/* Register r_pd_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pd_din; +#define REG_RD_ADDR_gio_r_pd_din 68 + +/* Register rw_pd_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pd_oe; +#define REG_RD_ADDR_gio_rw_pd_oe 72 +#define REG_WR_ADDR_gio_rw_pd_oe 72 + +/* Register rw_pe_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pe_dout; +#define REG_RD_ADDR_gio_rw_pe_dout 80 +#define REG_WR_ADDR_gio_rw_pe_dout 80 + +/* Register r_pe_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pe_din; +#define REG_RD_ADDR_gio_r_pe_din 84 + +/* Register rw_pe_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pe_oe; +#define REG_RD_ADDR_gio_rw_pe_oe 88 +#define REG_WR_ADDR_gio_rw_pe_oe 88 + + +/* Constants */ +enum { + regk_gio_anyedge = 0x00000007, + regk_gio_hi = 0x00000001, + regk_gio_lo = 0x00000002, + regk_gio_negedge = 0x00000006, + regk_gio_no = 0x00000000, + regk_gio_off = 0x00000000, + regk_gio_posedge = 0x00000005, + regk_gio_rw_intr_cfg_default = 0x00000000, + regk_gio_rw_intr_mask_default = 0x00000000, + regk_gio_rw_pa_oe_default = 0x00000000, + regk_gio_rw_pb_oe_default = 0x00000000, + regk_gio_rw_pc_oe_default = 0x00000000, + regk_gio_rw_pd_oe_default = 0x00000000, + regk_gio_rw_pe_oe_default = 0x00000000, + regk_gio_set = 0x00000003, + regk_gio_yes = 0x00000001 +}; +#endif /* __gio_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h new file mode 100644 index 00000000000..bacc2a895c2 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h @@ -0,0 +1,41 @@ +/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version + from ../../inst/intr_vect/rtl/guinness/ivmask.config.r +version . */ + +#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R +#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R +#define MEMARB_INTR_VECT 0x31 +#define GEN_IO_INTR_VECT 0x32 +#define GIO_INTR_VECT GEN_IO_INTR_VECT +#define IOP0_INTR_VECT 0x33 +#define IOP1_INTR_VECT 0x34 +#define IOP2_INTR_VECT 0x35 +#define IOP3_INTR_VECT 0x36 +#define DMA0_INTR_VECT 0x37 +#define DMA1_INTR_VECT 0x38 +#define DMA2_INTR_VECT 0x39 +#define DMA3_INTR_VECT 0x3a +#define DMA4_INTR_VECT 0x3b +#define DMA5_INTR_VECT 0x3c +#define DMA6_INTR_VECT 0x3d +#define DMA7_INTR_VECT 0x3e +#define DMA8_INTR_VECT 0x3f +#define DMA9_INTR_VECT 0x40 +#define ATA_INTR_VECT 0x41 +#define SSER0_INTR_VECT 0x42 +#define SSER1_INTR_VECT 0x43 +#define SER0_INTR_VECT 0x44 +#define SER1_INTR_VECT 0x45 +#define SER2_INTR_VECT 0x46 +#define SER3_INTR_VECT 0x47 +#define P21_INTR_VECT 0x48 +#define ETH0_INTR_VECT 0x49 +#define ETH1_INTR_VECT 0x4a +#define TIMER_INTR_VECT 0x4b +#define TIMER0_INTR_VECT TIMER_INTR_VECT +#define BIF_ARB_INTR_VECT 0x4c +#define BIF_DMA_INTR_VECT 0x4d +#define EXT_INTR_VECT 0x4e +#define IPI_INTR_VECT 0x4f +#define NBR_INTR_VECT 0x50 +#endif diff --git a/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h index 535aaf1b4b5..aa65128ae1a 100644 --- a/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h @@ -4,11 +4,11 @@ /* * This file is autogenerated from * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp + * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp * last modfied: Mon Apr 11 16:08:03 2005 - * + * * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: $Id: intr_vect_defs.h,v 1.8 2005/04/24 18:30:58 starvik Exp $ + * id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ * Any changes here will be lost. * * -*- buffer-read-only: t -*- @@ -84,6 +84,7 @@ /* C-code for register scope intr_vect */ +#define STRIDE_intr_vect_rw_mask 0 /* Register rw_mask, scope intr_vect, type rw */ typedef struct { unsigned int memarb : 1; @@ -112,7 +113,7 @@ typedef struct { unsigned int p21 : 1; unsigned int eth0 : 1; unsigned int eth1 : 1; - unsigned int timer : 1; + unsigned int timer0 : 1; unsigned int bif_arb : 1; unsigned int bif_dma : 1; unsigned int ext : 1; @@ -121,6 +122,7 @@ typedef struct { #define REG_RD_ADDR_intr_vect_rw_mask 0 #define REG_WR_ADDR_intr_vect_rw_mask 0 +#define STRIDE_intr_vect_r_vect 0 /* Register r_vect, scope intr_vect, type r */ typedef struct { unsigned int memarb : 1; @@ -157,6 +159,7 @@ typedef struct { } reg_intr_vect_r_vect; #define REG_RD_ADDR_intr_vect_r_vect 4 +#define STRIDE_intr_vect_r_masked_vect 0 /* Register r_masked_vect, scope intr_vect, type r */ typedef struct { unsigned int memarb : 1; @@ -209,7 +212,7 @@ typedef struct { #define REG_RD_ADDR_intr_vect_r_guru 16 /* Register rw_ipi, scope intr_vect, type rw */ -typedef struct +typedef struct { unsigned int vector; } reg_intr_vect_rw_ipi; diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h new file mode 100644 index 00000000000..dcaaec4620b --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h @@ -0,0 +1,205 @@ +#ifndef __marb_bp_defs_h +#define __marb_bp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: <not found> + * last modfied: Fri Nov 7 15:36:04 2003 + * + * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_bp_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +/* C-code for register scope marb_bp */ + +/* Register rw_first_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_first_addr; +#define REG_RD_ADDR_marb_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_last_addr; +#define REG_RD_ADDR_marb_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_bp, type rw */ +typedef struct { + unsigned int read : 1; + unsigned int write : 1; + unsigned int read_excl : 1; + unsigned int pri_write : 1; + unsigned int us_read : 1; + unsigned int us_write : 1; + unsigned int us_read_excl : 1; + unsigned int us_pri_write : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_rw_op; +#define REG_RD_ADDR_marb_bp_rw_op 8 +#define REG_WR_ADDR_marb_bp_rw_op 8 + +/* Register rw_clients, scope marb_bp, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_rw_clients; +#define REG_RD_ADDR_marb_bp_rw_clients 12 +#define REG_WR_ADDR_marb_bp_rw_clients 12 + +/* Register rw_options, scope marb_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_bp_rw_options; +#define REG_RD_ADDR_marb_bp_rw_options 16 +#define REG_WR_ADDR_marb_bp_rw_options 16 + +/* Register r_break_addr, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_break_addr; +#define REG_RD_ADDR_marb_bp_r_break_addr 20 + +/* Register r_break_op, scope marb_bp, type r */ +typedef struct { + unsigned int read : 1; + unsigned int write : 1; + unsigned int read_excl : 1; + unsigned int pri_write : 1; + unsigned int us_read : 1; + unsigned int us_write : 1; + unsigned int us_read_excl : 1; + unsigned int us_pri_write : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_r_break_op; +#define REG_RD_ADDR_marb_bp_r_break_op 24 + +/* Register r_break_clients, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_break_clients; +#define REG_RD_ADDR_marb_bp_r_break_clients 28 + +/* Register r_break_first_client, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_break_first_client; +#define REG_RD_ADDR_marb_bp_r_break_first_client 32 + +/* Register r_break_size, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_break_size; +#define REG_RD_ADDR_marb_bp_r_break_size 36 + +/* Register rw_ack, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_ack; +#define REG_RD_ADDR_marb_bp_rw_ack 40 +#define REG_WR_ADDR_marb_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_bp_no = 0x00000000, + regk_marb_bp_rw_op_default = 0x00000000, + regk_marb_bp_rw_options_default = 0x00000000, + regk_marb_bp_yes = 0x00000001 +}; +#endif /* __marb_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h new file mode 100644 index 00000000000..254da085498 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h @@ -0,0 +1,475 @@ +#ifndef __marb_defs_h +#define __marb_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: <not found> + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb */ + +#define STRIDE_marb_rw_int_slots 4 +/* Register rw_int_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_int_slots; +#define REG_RD_ADDR_marb_rw_int_slots 0 +#define REG_WR_ADDR_marb_rw_int_slots 0 + +#define STRIDE_marb_rw_ext_slots 4 +/* Register rw_ext_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_ext_slots; +#define REG_RD_ADDR_marb_rw_ext_slots 256 +#define REG_WR_ADDR_marb_rw_ext_slots 256 + +#define STRIDE_marb_rw_regs_slots 4 +/* Register rw_regs_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_regs_slots; +#define REG_RD_ADDR_marb_rw_regs_slots 512 +#define REG_WR_ADDR_marb_rw_regs_slots 512 + +/* Register rw_intr_mask, scope marb, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_rw_intr_mask; +#define REG_RD_ADDR_marb_rw_intr_mask 528 +#define REG_WR_ADDR_marb_rw_intr_mask 528 + +/* Register rw_ack_intr, scope marb, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_rw_ack_intr; +#define REG_RD_ADDR_marb_rw_ack_intr 532 +#define REG_WR_ADDR_marb_rw_ack_intr 532 + +/* Register r_intr, scope marb, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_r_intr; +#define REG_RD_ADDR_marb_r_intr 536 + +/* Register r_masked_intr, scope marb, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_r_masked_intr; +#define REG_RD_ADDR_marb_r_masked_intr 540 + +/* Register rw_stop_mask, scope marb, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_rw_stop_mask; +#define REG_RD_ADDR_marb_rw_stop_mask 544 +#define REG_WR_ADDR_marb_rw_stop_mask 544 + +/* Register r_stopped, scope marb, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_r_stopped; +#define REG_RD_ADDR_marb_r_stopped 548 + +/* Register rw_no_snoop, scope marb, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_rw_no_snoop; +#define REG_RD_ADDR_marb_rw_no_snoop 832 +#define REG_WR_ADDR_marb_rw_no_snoop 832 + +/* Register rw_no_snoop_rq, scope marb, type rw */ +typedef struct { + unsigned int dummy1 : 10; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int dummy2 : 20; +} reg_marb_rw_no_snoop_rq; +#define REG_RD_ADDR_marb_rw_no_snoop_rq 836 +#define REG_WR_ADDR_marb_rw_no_snoop_rq 836 + + +/* Constants */ +enum { + regk_marb_cpud = 0x0000000b, + regk_marb_cpui = 0x0000000a, + regk_marb_dma0 = 0x00000000, + regk_marb_dma1 = 0x00000001, + regk_marb_dma2 = 0x00000002, + regk_marb_dma3 = 0x00000003, + regk_marb_dma4 = 0x00000004, + regk_marb_dma5 = 0x00000005, + regk_marb_dma6 = 0x00000006, + regk_marb_dma7 = 0x00000007, + regk_marb_dma8 = 0x00000008, + regk_marb_dma9 = 0x00000009, + regk_marb_iop = 0x0000000c, + regk_marb_no = 0x00000000, + regk_marb_r_stopped_default = 0x00000000, + regk_marb_rw_ext_slots_default = 0x00000000, + regk_marb_rw_ext_slots_size = 0x00000040, + regk_marb_rw_int_slots_default = 0x00000000, + regk_marb_rw_int_slots_size = 0x00000040, + regk_marb_rw_intr_mask_default = 0x00000000, + regk_marb_rw_no_snoop_default = 0x00000000, + regk_marb_rw_no_snoop_rq_default = 0x00000000, + regk_marb_rw_regs_slots_default = 0x00000000, + regk_marb_rw_regs_slots_size = 0x00000004, + regk_marb_rw_stop_mask_default = 0x00000000, + regk_marb_slave = 0x0000000d, + regk_marb_yes = 0x00000001 +}; +#endif /* __marb_defs_h */ +#ifndef __marb_bp_defs_h +#define __marb_bp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: <not found> + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_bp */ + +/* Register rw_first_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_first_addr; +#define REG_RD_ADDR_marb_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_last_addr; +#define REG_RD_ADDR_marb_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_bp, type rw */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_rw_op; +#define REG_RD_ADDR_marb_bp_rw_op 8 +#define REG_WR_ADDR_marb_bp_rw_op 8 + +/* Register rw_clients, scope marb_bp, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_rw_clients; +#define REG_RD_ADDR_marb_bp_rw_clients 12 +#define REG_WR_ADDR_marb_bp_rw_clients 12 + +/* Register rw_options, scope marb_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_bp_rw_options; +#define REG_RD_ADDR_marb_bp_rw_options 16 +#define REG_WR_ADDR_marb_bp_rw_options 16 + +/* Register r_brk_addr, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_brk_addr; +#define REG_RD_ADDR_marb_bp_r_brk_addr 20 + +/* Register r_brk_op, scope marb_bp, type r */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_r_brk_op; +#define REG_RD_ADDR_marb_bp_r_brk_op 24 + +/* Register r_brk_clients, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_brk_clients; +#define REG_RD_ADDR_marb_bp_r_brk_clients 28 + +/* Register r_brk_first_client, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_brk_first_client; +#define REG_RD_ADDR_marb_bp_r_brk_first_client 32 + +/* Register r_brk_size, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_brk_size; +#define REG_RD_ADDR_marb_bp_r_brk_size 36 + +/* Register rw_ack, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_ack; +#define REG_RD_ADDR_marb_bp_rw_ack 40 +#define REG_WR_ADDR_marb_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_bp_no = 0x00000000, + regk_marb_bp_rw_op_default = 0x00000000, + regk_marb_bp_rw_options_default = 0x00000000, + regk_marb_bp_yes = 0x00000001 +}; +#endif /* __marb_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h new file mode 100644 index 00000000000..751eab5f191 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h @@ -0,0 +1,357 @@ +#ifndef __pinmux_defs_h +#define __pinmux_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp + * last modfied: Mon Apr 11 16:09:11 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope pinmux */ + +/* Register rw_pa, scope pinmux, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int csp2_n : 1; + unsigned int csp3_n : 1; + unsigned int csp5_n : 1; + unsigned int csp6_n : 1; + unsigned int hsh4 : 1; + unsigned int hsh5 : 1; + unsigned int hsh6 : 1; + unsigned int hsh7 : 1; + unsigned int dummy1 : 16; +} reg_pinmux_rw_pa; +#define REG_RD_ADDR_pinmux_rw_pa 0 +#define REG_WR_ADDR_pinmux_rw_pa 0 + +/* Register rw_hwprot, scope pinmux, type rw */ +typedef struct { + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int sser0 : 1; + unsigned int sser1 : 1; + unsigned int ata0 : 1; + unsigned int ata1 : 1; + unsigned int ata2 : 1; + unsigned int ata3 : 1; + unsigned int ata : 1; + unsigned int eth1 : 1; + unsigned int eth1_mgm : 1; + unsigned int timer : 1; + unsigned int p21 : 1; + unsigned int dummy1 : 18; +} reg_pinmux_rw_hwprot; +#define REG_RD_ADDR_pinmux_rw_hwprot 4 +#define REG_WR_ADDR_pinmux_rw_hwprot 4 + +/* Register rw_pb_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pb0 : 1; + unsigned int pb1 : 1; + unsigned int pb2 : 1; + unsigned int pb3 : 1; + unsigned int pb4 : 1; + unsigned int pb5 : 1; + unsigned int pb6 : 1; + unsigned int pb7 : 1; + unsigned int pb8 : 1; + unsigned int pb9 : 1; + unsigned int pb10 : 1; + unsigned int pb11 : 1; + unsigned int pb12 : 1; + unsigned int pb13 : 1; + unsigned int pb14 : 1; + unsigned int pb15 : 1; + unsigned int pb16 : 1; + unsigned int pb17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pb_gio; +#define REG_RD_ADDR_pinmux_rw_pb_gio 8 +#define REG_WR_ADDR_pinmux_rw_pb_gio 8 + +/* Register rw_pb_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pb0 : 1; + unsigned int pb1 : 1; + unsigned int pb2 : 1; + unsigned int pb3 : 1; + unsigned int pb4 : 1; + unsigned int pb5 : 1; + unsigned int pb6 : 1; + unsigned int pb7 : 1; + unsigned int pb8 : 1; + unsigned int pb9 : 1; + unsigned int pb10 : 1; + unsigned int pb11 : 1; + unsigned int pb12 : 1; + unsigned int pb13 : 1; + unsigned int pb14 : 1; + unsigned int pb15 : 1; + unsigned int pb16 : 1; + unsigned int pb17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pb_iop; +#define REG_RD_ADDR_pinmux_rw_pb_iop 12 +#define REG_WR_ADDR_pinmux_rw_pb_iop 12 + +/* Register rw_pc_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pc0 : 1; + unsigned int pc1 : 1; + unsigned int pc2 : 1; + unsigned int pc3 : 1; + unsigned int pc4 : 1; + unsigned int pc5 : 1; + unsigned int pc6 : 1; + unsigned int pc7 : 1; + unsigned int pc8 : 1; + unsigned int pc9 : 1; + unsigned int pc10 : 1; + unsigned int pc11 : 1; + unsigned int pc12 : 1; + unsigned int pc13 : 1; + unsigned int pc14 : 1; + unsigned int pc15 : 1; + unsigned int pc16 : 1; + unsigned int pc17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pc_gio; +#define REG_RD_ADDR_pinmux_rw_pc_gio 16 +#define REG_WR_ADDR_pinmux_rw_pc_gio 16 + +/* Register rw_pc_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pc0 : 1; + unsigned int pc1 : 1; + unsigned int pc2 : 1; + unsigned int pc3 : 1; + unsigned int pc4 : 1; + unsigned int pc5 : 1; + unsigned int pc6 : 1; + unsigned int pc7 : 1; + unsigned int pc8 : 1; + unsigned int pc9 : 1; + unsigned int pc10 : 1; + unsigned int pc11 : 1; + unsigned int pc12 : 1; + unsigned int pc13 : 1; + unsigned int pc14 : 1; + unsigned int pc15 : 1; + unsigned int pc16 : 1; + unsigned int pc17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pc_iop; +#define REG_RD_ADDR_pinmux_rw_pc_iop 20 +#define REG_WR_ADDR_pinmux_rw_pc_iop 20 + +/* Register rw_pd_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pd0 : 1; + unsigned int pd1 : 1; + unsigned int pd2 : 1; + unsigned int pd3 : 1; + unsigned int pd4 : 1; + unsigned int pd5 : 1; + unsigned int pd6 : 1; + unsigned int pd7 : 1; + unsigned int pd8 : 1; + unsigned int pd9 : 1; + unsigned int pd10 : 1; + unsigned int pd11 : 1; + unsigned int pd12 : 1; + unsigned int pd13 : 1; + unsigned int pd14 : 1; + unsigned int pd15 : 1; + unsigned int pd16 : 1; + unsigned int pd17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pd_gio; +#define REG_RD_ADDR_pinmux_rw_pd_gio 24 +#define REG_WR_ADDR_pinmux_rw_pd_gio 24 + +/* Register rw_pd_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pd0 : 1; + unsigned int pd1 : 1; + unsigned int pd2 : 1; + unsigned int pd3 : 1; + unsigned int pd4 : 1; + unsigned int pd5 : 1; + unsigned int pd6 : 1; + unsigned int pd7 : 1; + unsigned int pd8 : 1; + unsigned int pd9 : 1; + unsigned int pd10 : 1; + unsigned int pd11 : 1; + unsigned int pd12 : 1; + unsigned int pd13 : 1; + unsigned int pd14 : 1; + unsigned int pd15 : 1; + unsigned int pd16 : 1; + unsigned int pd17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pd_iop; +#define REG_RD_ADDR_pinmux_rw_pd_iop 28 +#define REG_WR_ADDR_pinmux_rw_pd_iop 28 + +/* Register rw_pe_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pe0 : 1; + unsigned int pe1 : 1; + unsigned int pe2 : 1; + unsigned int pe3 : 1; + unsigned int pe4 : 1; + unsigned int pe5 : 1; + unsigned int pe6 : 1; + unsigned int pe7 : 1; + unsigned int pe8 : 1; + unsigned int pe9 : 1; + unsigned int pe10 : 1; + unsigned int pe11 : 1; + unsigned int pe12 : 1; + unsigned int pe13 : 1; + unsigned int pe14 : 1; + unsigned int pe15 : 1; + unsigned int pe16 : 1; + unsigned int pe17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pe_gio; +#define REG_RD_ADDR_pinmux_rw_pe_gio 32 +#define REG_WR_ADDR_pinmux_rw_pe_gio 32 + +/* Register rw_pe_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pe0 : 1; + unsigned int pe1 : 1; + unsigned int pe2 : 1; + unsigned int pe3 : 1; + unsigned int pe4 : 1; + unsigned int pe5 : 1; + unsigned int pe6 : 1; + unsigned int pe7 : 1; + unsigned int pe8 : 1; + unsigned int pe9 : 1; + unsigned int pe10 : 1; + unsigned int pe11 : 1; + unsigned int pe12 : 1; + unsigned int pe13 : 1; + unsigned int pe14 : 1; + unsigned int pe15 : 1; + unsigned int pe16 : 1; + unsigned int pe17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pe_iop; +#define REG_RD_ADDR_pinmux_rw_pe_iop 36 +#define REG_WR_ADDR_pinmux_rw_pe_iop 36 + +/* Register rw_usb_phy, scope pinmux, type rw */ +typedef struct { + unsigned int en_usb0 : 1; + unsigned int en_usb1 : 1; + unsigned int dummy1 : 30; +} reg_pinmux_rw_usb_phy; +#define REG_RD_ADDR_pinmux_rw_usb_phy 40 +#define REG_WR_ADDR_pinmux_rw_usb_phy 40 + + +/* Constants */ +enum { + regk_pinmux_no = 0x00000000, + regk_pinmux_rw_hwprot_default = 0x00000000, + regk_pinmux_rw_pa_default = 0x00000000, + regk_pinmux_rw_pb_gio_default = 0x00000000, + regk_pinmux_rw_pb_iop_default = 0x00000000, + regk_pinmux_rw_pc_gio_default = 0x00000000, + regk_pinmux_rw_pc_iop_default = 0x00000000, + regk_pinmux_rw_pd_gio_default = 0x00000000, + regk_pinmux_rw_pd_iop_default = 0x00000000, + regk_pinmux_rw_pe_gio_default = 0x00000000, + regk_pinmux_rw_pe_iop_default = 0x00000000, + regk_pinmux_rw_usb_phy_default = 0x00000000, + regk_pinmux_yes = 0x00000001 +}; +#endif /* __pinmux_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/reg_map.h b/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h index e31502838ec..4146973a58b 100644 --- a/include/asm-cris/arch-v32/hwregs/reg_map.h +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h @@ -4,17 +4,17 @@ /* * This file is autogenerated from * file: ../../mod/fakereg.rmap - * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp + * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp * last modified: Wed Feb 11 20:53:25 2004 * file: ../../rtl/global.rmap - * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp + * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp * last modified: Mon Aug 18 17:08:23 2003 * file: ../../mod/modreg.rmap - * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp + * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp * last modified: Fri Feb 20 16:40:04 2004 - * + * * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap - * id: $Id: reg_map.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ + * id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ * Any changes here will be lost. * * -*- buffer-read-only: t -*- @@ -97,6 +97,7 @@ typedef enum { regi_strcop = 0xb0030000, regi_strmux = 0xb003a000, regi_timer = 0xb001e000, + regi_timer0 = 0xb001e000, regi_timer2 = 0xb005e000, regi_trace = 0xb0040000, } reg_scope_instances; diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h new file mode 100644 index 00000000000..cbfaa867829 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h @@ -0,0 +1,127 @@ +#ifndef __strmux_defs_h +#define __strmux_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/strmux/rtl/guinness/strmux_regs.r + * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp + * last modfied: Mon Apr 11 16:09:43 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r + * id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope strmux */ + +/* Register rw_cfg, scope strmux, type rw */ +typedef struct { + unsigned int dma0 : 3; + unsigned int dma1 : 3; + unsigned int dma2 : 3; + unsigned int dma3 : 3; + unsigned int dma4 : 3; + unsigned int dma5 : 3; + unsigned int dma6 : 3; + unsigned int dma7 : 3; + unsigned int dma8 : 3; + unsigned int dma9 : 3; + unsigned int dummy1 : 2; +} reg_strmux_rw_cfg; +#define REG_RD_ADDR_strmux_rw_cfg 0 +#define REG_WR_ADDR_strmux_rw_cfg 0 + + +/* Constants */ +enum { + regk_strmux_ata = 0x00000003, + regk_strmux_eth0 = 0x00000001, + regk_strmux_eth1 = 0x00000004, + regk_strmux_ext0 = 0x00000001, + regk_strmux_ext1 = 0x00000001, + regk_strmux_ext2 = 0x00000001, + regk_strmux_ext3 = 0x00000001, + regk_strmux_iop0 = 0x00000002, + regk_strmux_iop1 = 0x00000001, + regk_strmux_off = 0x00000000, + regk_strmux_p21 = 0x00000004, + regk_strmux_rw_cfg_default = 0x00000000, + regk_strmux_ser0 = 0x00000002, + regk_strmux_ser1 = 0x00000002, + regk_strmux_ser2 = 0x00000004, + regk_strmux_ser3 = 0x00000003, + regk_strmux_sser0 = 0x00000003, + regk_strmux_sser1 = 0x00000003, + regk_strmux_strcop = 0x00000002 +}; +#endif /* __strmux_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/timer_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h index 20c8c89ec07..76bcc591921 100644 --- a/include/asm-cris/arch-v32/hwregs/timer_defs.h +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h @@ -4,11 +4,11 @@ /* * This file is autogenerated from * file: ../../inst/timer/rtl/timer_regs.r - * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp + * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp * last modfied: Mon Apr 11 16:09:53 2005 - * + * * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r - * id: $Id: timer_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ + * id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ * Any changes here will be lost. * * -*- buffer-read-only: t -*- diff --git a/include/asm-cris/arch-v32/mach-fs/pinmux.h b/include/asm-cris/arch-v32/mach-fs/pinmux.h new file mode 100644 index 00000000000..c2b3036779d --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/pinmux.h @@ -0,0 +1,38 @@ +#ifndef _ASM_CRIS_ARCH_PINMUX_H +#define _ASM_CRIS_ARCH_PINMUX_H + +#define PORT_B 0 +#define PORT_C 1 +#define PORT_D 2 +#define PORT_E 3 + +enum pin_mode { + pinmux_none = 0, + pinmux_fixed, + pinmux_gpio, + pinmux_iop +}; + +enum fixed_function { + pinmux_ser1, + pinmux_ser2, + pinmux_ser3, + pinmux_sser0, + pinmux_sser1, + pinmux_ata0, + pinmux_ata1, + pinmux_ata2, + pinmux_ata3, + pinmux_ata, + pinmux_eth1, + pinmux_timer +}; + +int crisv32_pinmux_init(void); +int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); +int crisv32_pinmux_alloc_fixed(enum fixed_function function); +int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); +int crisv32_pinmux_dealloc_fixed(enum fixed_function function); +void crisv32_pinmux_dump(void); + +#endif diff --git a/include/asm-cris/arch-v32/mach-fs/startup.inc b/include/asm-cris/arch-v32/mach-fs/startup.inc new file mode 100644 index 00000000000..4a10ccbd6cc --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/startup.inc @@ -0,0 +1,77 @@ +#include <hwregs/asm/reg_map_asm.h> +#include <hwregs/asm/bif_core_defs_asm.h> +#include <hwregs/asm/gio_defs_asm.h> +#include <hwregs/asm/config_defs_asm.h> + + .macro GIO_INIT + move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pd_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PD_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pd_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pe_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PE_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pe_oe), $r1 + move.d $r0, [$r1] + .endm + + .macro START_CLOCKS + move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1 + move.d [$r1], $r0 + or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \ + REG_STATE(config, rw_clk_ctrl, bif, yes) | \ + REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0 + move.d $r0, [$r1] + .endm + + .macro SETUP_WAIT_STATES + ;; Set up waitstates etc + move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0 + move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0 + move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0 + move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0 + move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1 + move.d $r1, [$r0] +#ifdef CONFIG_ETRAX_VCS_SIM + ;; Set up minimal flash waitstates + move.d 0, $r10 + move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r11 + move.d $r10, [$r11] +#endif + .endm diff --git a/include/asm-cris/arch-v32/offset.h b/include/asm-cris/arch-v32/offset.h index 597419b033f..4442c4bd52f 100644 --- a/include/asm-cris/arch-v32/offset.h +++ b/include/asm-cris/arch-v32/offset.h @@ -27,7 +27,7 @@ #define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ #define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */ -#define TASK_pid 149 /* offsetof(struct task_struct, pid) */ +#define TASK_pid 151 /* offsetof(struct task_struct, pid) */ #define LCLONE_VM 256 /* CLONE_VM */ #define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ diff --git a/include/asm-cris/arch-v32/page.h b/include/asm-cris/arch-v32/page.h index fa454fe1242..20f1b4806bf 100644 --- a/include/asm-cris/arch-v32/page.h +++ b/include/asm-cris/arch-v32/page.h @@ -7,11 +7,11 @@ #define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram. */ /* - * Macros to convert between physical and virtual addresses. By stripiing a + * Macros to convert between physical and virtual addresses. By stripping a * selected bit it's possible to convert between KSEG_x and 0x40000000 where the * DRAM really resides. DRAM is virtually at 0xc. */ -#ifndef CONFIG_ETRAXFS_SIM +#ifndef CONFIG_ETRAX_VCS_SIM #define __pa(x) ((unsigned long)(x) & 0x7fffffff) #define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) #else diff --git a/include/asm-cris/arch-v32/pinmux.h b/include/asm-cris/arch-v32/pinmux.h index a66dc997091..bb09bce42e7 100644 --- a/include/asm-cris/arch-v32/pinmux.h +++ b/include/asm-cris/arch-v32/pinmux.h @@ -34,6 +34,7 @@ int crisv32_pinmux_init(void); int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); int crisv32_pinmux_alloc_fixed(enum fixed_function function); int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); +int crisv32_pinmux_dealloc_fixed(enum fixed_function function); void crisv32_pinmux_dump(void); #endif diff --git a/include/asm-cris/arch-v32/processor.h b/include/asm-cris/arch-v32/processor.h index 5553b0cd02b..f80b47790ca 100644 --- a/include/asm-cris/arch-v32/processor.h +++ b/include/asm-cris/arch-v32/processor.h @@ -23,7 +23,7 @@ struct thread_struct { * User-space process size. This is hardcoded into a few places, so don't * changed it unless everything's clear! */ -#ifndef CONFIG_ETRAXFS_SIM +#ifndef CONFIG_ETRAX_VCS_SIM #define TASK_SIZE (0xB0000000UL) #else #define TASK_SIZE (0xA0000000UL) diff --git a/include/asm-cris/arch-v32/spinlock.h b/include/asm-cris/arch-v32/spinlock.h index 5f43df0a5fb..0d5709b983a 100644 --- a/include/asm-cris/arch-v32/spinlock.h +++ b/include/asm-cris/arch-v32/spinlock.h @@ -1,40 +1,47 @@ #ifndef __ASM_ARCH_SPINLOCK_H #define __ASM_ARCH_SPINLOCK_H -#include <asm/system.h> +#include <linux/spinlock_types.h> #define RW_LOCK_BIAS 0x01000000 -#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } -#define spin_lock_init(x) do { *(x) = SPIN_LOCK_UNLOCKED; } while(0) - -#define spin_is_locked(x) (*(volatile signed char *)(&(x)->lock) <= 0) -#define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x)) extern void cris_spin_unlock(void *l, int val); extern void cris_spin_lock(void *l); -extern int cris_spin_trylock(void* l); +extern int cris_spin_trylock(void *l); -static inline void _raw_spin_unlock(spinlock_t *lock) +static inline int __raw_spin_is_locked(raw_spinlock_t *x) +{ + return *(volatile signed char *)(&(x)->slock) <= 0; +} + +static inline void __raw_spin_unlock(raw_spinlock_t *lock) { __asm__ volatile ("move.d %1,%0" \ - : "=m" (lock->lock) \ + : "=m" (lock->slock) \ : "r" (1) \ : "memory"); } -static inline int _raw_spin_trylock(spinlock_t *lock) +static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock) +{ + while (__raw_spin_is_locked(lock)) + cpu_relax(); +} + +static inline int __raw_spin_trylock(raw_spinlock_t *lock) { - return cris_spin_trylock((void*)&lock->lock); + return cris_spin_trylock((void *)&lock->slock); } -static inline void _raw_spin_lock(spinlock_t *lock) +static inline void __raw_spin_lock(raw_spinlock_t *lock) { - cris_spin_lock((void*)&lock->lock); + cris_spin_lock((void *)&lock->slock); } -static inline void _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags) +static inline void +__raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags) { - _raw_spin_lock(lock); + __raw_spin_lock(lock); } /* @@ -46,120 +53,75 @@ static inline void _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags) * can "mix" irq-safe locks - any writer needs to get a * irq-safe write-lock, but readers can get non-irqsafe * read-locks. + * */ -typedef struct { - spinlock_t lock; - volatile int counter; -#ifdef CONFIG_PREEMPT - unsigned int break_lock; -#endif -} rwlock_t; - -#define RW_LOCK_UNLOCKED (rwlock_t) { {1}, 0 } - -#define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while (0) - -/** - * read_can_lock - would read_trylock() succeed? - * @lock: the rwlock in question. - */ -#define read_can_lock(x) ((int)(x)->counter >= 0) - -/** - * write_can_lock - would write_trylock() succeed? - * @lock: the rwlock in question. - */ -#define write_can_lock(x) ((x)->counter == 0) - -#define _raw_read_trylock(lock) generic_raw_read_trylock(lock) -/* read_lock, read_unlock are pretty straightforward. Of course it somehow - * sucks we end up saving/restoring flags twice for read_lock_irqsave aso. */ - -static __inline__ void _raw_read_lock(rwlock_t *rw) +static inline int __raw_read_can_lock(raw_rwlock_t *x) { - unsigned long flags; - local_irq_save(flags); - _raw_spin_lock(&rw->lock); - - rw->counter++; - - _raw_spin_unlock(&rw->lock); - local_irq_restore(flags); + return (int)(x)->lock > 0; } -static __inline__ void _raw_read_unlock(rwlock_t *rw) +static inline int __raw_write_can_lock(raw_rwlock_t *x) { - unsigned long flags; - local_irq_save(flags); - _raw_spin_lock(&rw->lock); - - rw->counter--; - - _raw_spin_unlock(&rw->lock); - local_irq_restore(flags); + return (x)->lock == RW_LOCK_BIAS; } -/* write_lock is less trivial. We optimistically grab the lock and check - * if we surprised any readers. If so we release the lock and wait till - * they're all gone before trying again - * - * Also note that we don't use the _irqsave / _irqrestore suffixes here. - * If we're called with interrupts enabled and we've got readers (or other - * writers) in interrupt handlers someone fucked up and we'd dead-lock - * sooner or later anyway. prumpf */ - -static __inline__ void _raw_write_lock(rwlock_t *rw) +static inline void __raw_read_lock(raw_rwlock_t *rw) { -retry: - _raw_spin_lock(&rw->lock); - - if(rw->counter != 0) { - /* this basically never happens */ - _raw_spin_unlock(&rw->lock); - - while(rw->counter != 0); - - goto retry; - } - - /* got it. now leave without unlocking */ - rw->counter = -1; /* remember we are locked */ + __raw_spin_lock(&rw->slock); + while (rw->lock == 0); + rw->lock--; + __raw_spin_unlock(&rw->slock); } -/* write_unlock is absolutely trivial - we don't have to wait for anything */ - -static __inline__ void _raw_write_unlock(rwlock_t *rw) +static inline void __raw_write_lock(raw_rwlock_t *rw) { - rw->counter = 0; - _raw_spin_unlock(&rw->lock); + __raw_spin_lock(&rw->slock); + while (rw->lock != RW_LOCK_BIAS); + rw->lock == 0; + __raw_spin_unlock(&rw->slock); } -static __inline__ int _raw_write_trylock(rwlock_t *rw) +static inline void __raw_read_unlock(raw_rwlock_t *rw) { - _raw_spin_lock(&rw->lock); - if (rw->counter != 0) { - /* this basically never happens */ - _raw_spin_unlock(&rw->lock); - - return 0; - } + __raw_spin_lock(&rw->slock); + rw->lock++; + __raw_spin_unlock(&rw->slock); +} - /* got it. now leave without unlocking */ - rw->counter = -1; /* remember we are locked */ - return 1; +static inline void __raw_write_unlock(raw_rwlock_t *rw) +{ + __raw_spin_lock(&rw->slock); + while (rw->lock != RW_LOCK_BIAS); + rw->lock == RW_LOCK_BIAS; + __raw_spin_unlock(&rw->slock); } -static __inline__ int is_read_locked(rwlock_t *rw) +static inline int __raw_read_trylock(raw_rwlock_t *rw) { - return rw->counter > 0; + int ret = 0; + __raw_spin_lock(&rw->slock); + if (rw->lock != 0) { + rw->lock--; + ret = 1; + } + __raw_spin_unlock(&rw->slock); + return ret; } -static __inline__ int is_write_locked(rwlock_t *rw) +static inline int __raw_write_trylock(raw_rwlock_t *rw) { - return rw->counter < 0; + int ret = 0; + __raw_spin_lock(&rw->slock); + if (rw->lock == RW_LOCK_BIAS) { + rw->lock == 0; + ret = 1; + } + __raw_spin_unlock(&rw->slock); + return 1; } + #define _raw_spin_relax(lock) cpu_relax() #define _raw_read_relax(lock) cpu_relax() #define _raw_write_relax(lock) cpu_relax() diff --git a/include/asm-cris/arch-v32/system.h b/include/asm-cris/arch-v32/system.h index d20e2d6d64a..6ca90f1f110 100644 --- a/include/asm-cris/arch-v32/system.h +++ b/include/asm-cris/arch-v32/system.h @@ -66,13 +66,4 @@ struct __xchg_dummy { unsigned long a[100]; }; #define local_irq_save(x) \ __asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory"); -#ifdef CONFIG_SMP -typedef struct { - volatile unsigned int lock __attribute__ ((aligned(4))); -#ifdef CONFIG_PREEMPT - unsigned int break_lock; -#endif -} spinlock_t; -#endif - #endif /* _ASM_CRIS_ARCH_SYSTEM_H */ diff --git a/include/asm-cris/arch-v32/timex.h b/include/asm-cris/arch-v32/timex.h index 5a4aa285d5f..2591d3c5ed9 100644 --- a/include/asm-cris/arch-v32/timex.h +++ b/include/asm-cris/arch-v32/timex.h @@ -1,9 +1,9 @@ #ifndef _ASM_CRIS_ARCH_TIMEX_H #define _ASM_CRIS_ARCH_TIMEX_H -#include <asm/arch/hwregs/reg_map.h> -#include <asm/arch/hwregs/reg_rdwr.h> -#include <asm/arch/hwregs/timer_defs.h> +#include <hwregs/reg_map.h> +#include <hwregs/reg_rdwr.h> +#include <hwregs/timer_defs.h> /* * The clock runs at 100MHz, we divide it by 1000000. If you change anything @@ -18,7 +18,7 @@ /* Convert the value in step of 10 ns to 1us without overflow: */ #define GET_JIFFIES_USEC() \ - ( (TIMER0_DIV - REG_RD(timer, regi_timer, r_tmr0_data)) /100 ) + ((TIMER0_DIV - REG_RD(timer, regi_timer0, r_tmr0_data)) / 100) extern unsigned long get_ns_in_jiffie(void); diff --git a/include/asm-cris/arch-v32/unistd.h b/include/asm-cris/arch-v32/unistd.h index 5d369d4439d..0051114c63c 100644 --- a/include/asm-cris/arch-v32/unistd.h +++ b/include/asm-cris/arch-v32/unistd.h @@ -16,7 +16,8 @@ type name(void) \ ".endif\n\t" \ "break 13" \ : "=r" (__a) \ - : "r" (__n_)); \ + : "r" (__n_) \ + : "memory"); \ if (__a >= 0) \ return (type) __a; \ errno = -__a; \ @@ -33,7 +34,8 @@ type name(type1 arg1) \ ".endif\n\t" \ "break 13" \ : "=r" (__a) \ - : "r" (__n_), "0" (__a)); \ + : "r" (__n_), "0" (__a) \ + : "memory"); \ if (__a >= 0) \ return (type) __a; \ errno = -__a; \ @@ -51,7 +53,8 @@ type name(type1 arg1,type2 arg2) \ ".endif\n\t" \ "break 13" \ : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b)); \ + : "r" (__n_), "0" (__a), "r" (__b) \ + : "memory"); \ if (__a >= 0) \ return (type) __a; \ errno = -__a; \ @@ -70,7 +73,8 @@ type name(type1 arg1,type2 arg2,type3 arg3) \ ".endif\n\t" \ "break 13" \ : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \ + : "r" (__n_), "0" (__a), "r" (__b), "r" (__c) \ + : "memory"); \ if (__a >= 0) \ return (type) __a; \ errno = -__a; \ @@ -91,7 +95,8 @@ type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ "break 13" \ : "=r" (__a) \ : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d)); \ + "r" (__c), "r" (__d)\ + : "memory"); \ if (__a >= 0) \ return (type) __a; \ errno = -__a; \ @@ -114,7 +119,8 @@ type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ "break 13" \ : "=r" (__a) \ : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "h" (__e)); \ + "r" (__c), "r" (__d), "h" (__e) \ + : "memory"); \ if (__a >= 0) \ return (type) __a; \ errno = -__a; \ @@ -138,7 +144,8 @@ type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ "break 13" \ : "=r" (__a) \ : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "h" (__e), "x" (__f)); \ + "r" (__c), "r" (__d), "h" (__e), "x" (__f) \ + : "memory"); \ if (__a >= 0) \ return (type) __a; \ errno = -__a; \ diff --git a/include/asm-cris/atomic.h b/include/asm-cris/atomic.h index 2949a945876..5fc87768774 100644 --- a/include/asm-cris/atomic.h +++ b/include/asm-cris/atomic.h @@ -91,7 +91,7 @@ static inline int atomic_inc_return(volatile atomic_t *v) unsigned long flags; int retval; cris_atomic_save(v, flags); - retval = (v->counter)++; + retval = ++(v->counter); cris_atomic_restore(v, flags); return retval; } @@ -101,7 +101,7 @@ static inline int atomic_dec_return(volatile atomic_t *v) unsigned long flags; int retval; cris_atomic_save(v, flags); - retval = (v->counter)--; + retval = --(v->counter); cris_atomic_restore(v, flags); return retval; } diff --git a/include/asm-cris/axisflashmap.h b/include/asm-cris/axisflashmap.h index 7a8d3114e68..015ca5445dd 100644 --- a/include/asm-cris/axisflashmap.h +++ b/include/asm-cris/axisflashmap.h @@ -10,23 +10,23 @@ */ #define PARTITION_TABLE_OFFSET 10 -#define PARTITION_TABLE_MAGIC 0xbeef /* Not a good magic */ +#define PARTITION_TABLE_MAGIC 0xbeef /* Not a good magic */ /* The partitiontable_head is located at offset +10: */ struct partitiontable_head { - __u16 magic; /* PARTITION_TABLE_MAGIC */ - __u16 size; /* Length of ptable block (not header) */ - __u32 checksum; /* simple longword sum */ + __u16 magic; /* PARTITION_TABLE_MAGIC */ + __u16 size; /* Length of ptable block (entries + end marker) */ + __u32 checksum; /* simple longword sum, over entries + end marker */ }; /* And followed by partition table entries */ struct partitiontable_entry { - __u32 offset; /* Offset is relative to the sector the ptable is in */ - __u32 size; - __u32 checksum; /* simple longword sum */ - __u16 type; - __u16 flags; /* bit 0: ro/rw = 1/0 */ - __u32 future0; /* 16 bytes reserved for future use */ + __u32 offset; /* relative to the sector the ptable is in */ + __u32 size; /* in bytes */ + __u32 checksum; /* simple longword sum */ + __u16 type; /* see type codes below */ + __u16 flags; /* bit 0: ro/rw = 1/0 */ + __u32 future0; /* 16 bytes reserved for future use */ __u32 future1; __u32 future2; __u32 future3; @@ -35,12 +35,27 @@ struct partitiontable_entry { #define PARTITIONTABLE_END_MARKER 0xFFFFFFFF #define PARTITIONTABLE_END_MARKER_SIZE 4 -/*#define PARTITION_TYPE_RESCUE 0x0000?*/ /* Not used, maybe it should? */ +#define PARTITIONTABLE_END_PAD 10 + +/* Complete structure for whole partition table */ +/* note that table may end before CONFIG_ETRAX_PTABLE_ENTRIES by setting + * offset of the last entry + 1 to PARTITIONTABLE_END_MARKER. + */ +struct partitiontable { + __u8 skip[PARTITION_TABLE_OFFSET]; + struct partitiontable_head head; + struct partitiontable_entry entries[]; +}; + #define PARTITION_TYPE_PARAM 0x0001 #define PARTITION_TYPE_KERNEL 0x0002 #define PARTITION_TYPE_JFFS 0x0003 +#define PARTITION_TYPE_JFFS2 0x0000 + +#define PARTITION_FLAGS_READONLY_MASK 0x0001 +#define PARTITION_FLAGS_READONLY 0x0001 /* The master mtd for the entire flash. */ -extern struct mtd_info* axisflash_mtd; +extern struct mtd_info *axisflash_mtd; #endif diff --git a/include/asm-cris/bug.h b/include/asm-cris/bug.h index 8dd6b23c15d..fee12d4ae68 100644 --- a/include/asm-cris/bug.h +++ b/include/asm-cris/bug.h @@ -1,4 +1,4 @@ #ifndef _CRIS_BUG_H #define _CRIS_BUG_H -#include <asm-generic/bug.h> +#include <asm/arch/bug.h> #endif diff --git a/include/asm-cris/delay.h b/include/asm-cris/delay.h index d3a39780371..123e19aef49 100644 --- a/include/asm-cris/delay.h +++ b/include/asm-cris/delay.h @@ -13,10 +13,13 @@ extern unsigned long loops_per_usec; /* arch/cris/mm/init.c */ +/* May be defined by arch/delay.h. */ +#ifndef udelay static inline void udelay(unsigned long usecs) { __delay(usecs * loops_per_usec); } +#endif #endif /* defined(_CRIS_DELAY_H) */ diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h index 662cea70152..edc8d1bfaae 100644 --- a/include/asm-cris/dma-mapping.h +++ b/include/asm-cris/dma-mapping.h @@ -164,16 +164,5 @@ dma_cache_sync(struct device *dev, void *vaddr, size_t size, { } -#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY -extern int -dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, - dma_addr_t device_addr, size_t size, int flags); - -extern void -dma_release_declared_memory(struct device *dev); - -extern void * -dma_mark_declared_memory_occupied(struct device *dev, - dma_addr_t device_addr, size_t size); #endif diff --git a/include/asm-cris/etraxgpio.h b/include/asm-cris/etraxgpio.h index 5d0028dba7c..38f1c8e1770 100644 --- a/include/asm-cris/etraxgpio.h +++ b/include/asm-cris/etraxgpio.h @@ -1,25 +1,34 @@ -/* $Id: etraxgpio.h,v 1.8 2002/06/17 15:53:07 johana Exp $ */ /* * The following devices are accessable using this driver using - * GPIO_MAJOR (120) and a couple of minor numbers: - * For ETRAX 100LX (ARCH_V10): + * GPIO_MAJOR (120) and a couple of minor numbers. + * + * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10): * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction * /dev/leds minor 2, Access to leds depending on kernelconfig * /dev/gpiog minor 3 - g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG - g1-g7 and g25-g31 is both input and outputs but on different pins - Also note that some bits change pins depending on what interfaces - are enabled. + * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG + * g1-g7 and g25-g31 is both input and outputs but on different pins + * Also note that some bits change pins depending on what interfaces + * are enabled. * + * For ETRAX FS (CONFIG_ETRAXFS): + * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction + * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction + * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction + * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction + * /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction + * /dev/leds minor 2, Access to leds depending on kernelconfig * - * For ETRAX FS (ARCH_V32): + * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3): * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction - * /dev/gpioc minor 2, 18 bit GPIO, each bit can change direction - * /dev/gpiod minor 3, 18 bit GPIO, each bit can change direction - * /dev/gpioe minor 4, 18 bit GPIO, each bit can change direction - * /dev/leds minor 5, Access to leds depending on kernelconfig + * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction + * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction + * /dev/leds minor 2, Access to leds depending on kernelconfig + * /dev/pwm0 minor 16, PWM channel 0 on PA30 + * /dev/pwm1 minor 17, PWM channel 1 on PA31 + * /dev/pwm2 minor 18, PWM channel 2 on PB26 * */ #ifndef _ASM_ETRAXGPIO_H @@ -34,7 +43,8 @@ #define GPIO_MINOR_G 3 #define GPIO_MINOR_LAST 3 #endif -#ifdef CONFIG_ETRAX_ARCH_V32 + +#ifdef CONFIG_ETRAXFS #define ETRAXGPIO_IOCTYPE 43 #define GPIO_MINOR_A 0 #define GPIO_MINOR_B 1 @@ -42,8 +52,32 @@ #define GPIO_MINOR_C 3 #define GPIO_MINOR_D 4 #define GPIO_MINOR_E 5 +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +#define GPIO_MINOR_V 6 +#define GPIO_MINOR_LAST 6 +#else #define GPIO_MINOR_LAST 5 #endif +#endif + +#ifdef CONFIG_CRIS_MACH_ARTPEC3 +#define ETRAXGPIO_IOCTYPE 43 +#define GPIO_MINOR_A 0 +#define GPIO_MINOR_B 1 +#define GPIO_MINOR_LEDS 2 +#define GPIO_MINOR_C 3 +#define GPIO_MINOR_D 4 +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +#define GPIO_MINOR_V 6 +#define GPIO_MINOR_LAST 6 +#else +#define GPIO_MINOR_LAST 4 +#endif +#define GPIO_MINOR_PWM0 16 +#define GPIO_MINOR_PWM1 17 +#define GPIO_MINOR_PWM2 18 +#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2 +#endif /* supported ioctl _IOC_NR's */ @@ -63,7 +97,7 @@ /* GPIO direction ioctl's */ #define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ -#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, +#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, returns mask with current inputs (obsolete) */ #define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, returns mask with current outputs (obsolete)*/ @@ -77,13 +111,13 @@ #define IO_GET_PWR_BT 0xE /* Bit toggling in driver settings */ -/* bit set in low byte0 is CLK mask (0x00FF), - bit set in byte1 is DATA mask (0xFF00) +/* bit set in low byte0 is CLK mask (0x00FF), + bit set in byte1 is DATA mask (0xFF00) msb, data_mask[7:0] , clk_mask[7:0] */ -#define IO_CFG_WRITE_MODE 0xF +#define IO_CFG_WRITE_MODE 0xF #define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ - ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) + ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) /* The following 4 ioctl's take a pointer as argument and handles * 32 bit ports (port G) properly. @@ -98,6 +132,48 @@ * *arg updated with current output pins. */ +/* The following ioctl's are applicable to the PWM channels only */ + +#define IO_PWM_SET_MODE 0x20 + +enum io_pwm_mode { + PWM_OFF = 0, /* disabled, deallocated */ + PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */ + PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */ + PWM_VARFREQ = 3 /* individually configurable high/low periods */ +}; + +struct io_pwm_set_mode { + enum io_pwm_mode mode; +}; + +/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns + * from 10ns (value = 0) to 81920ns (value = 8191) + * (Resulting frequencies range from 50 MHz (10ns + 10ns) down to + * 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty + * cycle (81920 + 10ns or 10ns + 81920ns, respectively).) + */ +#define IO_PWM_SET_PERIOD 0x21 + +struct io_pwm_set_period { + unsigned int lo; /* 0..8191 */ + unsigned int hi; /* 0..8191 */ +}; + +/* Only for modes PWM_STANDARD and PWM_FAST. + * For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from + * 0 (value = 0) to 255/256 (value = 255). + * For PWM_FAST, set duty cycle of PWM output signal from + * 0% (value = 0) to 100% (value = 255). Output signal in this mode + * is a 10ns pulse surrounded by a high or low level depending on duty + * cycle (except for 0% and 100% which result in a constant output). + * Resulting output frequency varies from 50 MHz at 50% duty cycle, + * down to 390 kHz at min/max duty cycle. + */ +#define IO_PWM_SET_DUTY 0x22 +struct io_pwm_set_duty { + int duty; /* 0..255 */ +}; #endif diff --git a/include/asm-cris/io.h b/include/asm-cris/io.h index d196dd6b2df..b87ce63f531 100644 --- a/include/asm-cris/io.h +++ b/include/asm-cris/io.h @@ -122,8 +122,8 @@ static inline void writel(unsigned int b, volatile void __iomem *addr) #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) -/* The following is junk needed for the arch-independent code but which - * we never use in the CRIS port +/* I/O port access. Normally there is no I/O space on CRIS but when + * Cardbus/PCI is enabled the request is passed through the bridge. */ #define IO_SPACE_LIMIT 0xffff diff --git a/include/asm-cris/page.h b/include/asm-cris/page.h index 3b0156c4631..c45bb1ef397 100644 --- a/include/asm-cris/page.h +++ b/include/asm-cris/page.h @@ -26,6 +26,7 @@ typedef struct { unsigned long pte; } pte_t; typedef struct { unsigned long pgd; } pgd_t; typedef struct { unsigned long pgprot; } pgprot_t; +typedef struct page *pgtable_t; #endif #define pte_val(x) ((x).pte) diff --git a/include/asm-cris/param.h b/include/asm-cris/param.h index b2497263983..0e47994e40b 100644 --- a/include/asm-cris/param.h +++ b/include/asm-cris/param.h @@ -3,7 +3,7 @@ /* Currently we assume that HZ=100 is good for CRIS. */ #ifdef __KERNEL__ -# define HZ 100 /* Internal kernel timer frequency */ +# define HZ CONFIG_HZ /* Internal kernel timer frequency */ # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ #endif diff --git a/include/asm-cris/pgalloc.h b/include/asm-cris/pgalloc.h index 8ddd66f8177..a1ba761d057 100644 --- a/include/asm-cris/pgalloc.h +++ b/include/asm-cris/pgalloc.h @@ -6,6 +6,7 @@ #define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte) #define pmd_populate(mm, pmd, pte) pmd_set(pmd, page_address(pte)) +#define pmd_pgtable(pmd) pmd_page(pmd) /* * Allocate and free page tables. @@ -27,10 +28,11 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long ad return pte; } -static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address) +static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) { struct page *pte; pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); + pgtable_page_ctor(pte); return pte; } @@ -39,13 +41,17 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) free_page((unsigned long)pte); } -static inline void pte_free(struct mm_struct *mm, struct page *pte) +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) { + pgtable_page_dtor(pte); __free_page(pte); } - -#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) +#define __pte_free_tlb(tlb,pte) \ +do { \ + pgtable_page_dtor(pte); \ + tlb_remove_page((tlb), pte); \ +} while (0) #define check_pgt_cache() do { } while (0) diff --git a/include/asm-cris/pgtable.h b/include/asm-cris/pgtable.h index 417f7111621..a2607575681 100644 --- a/include/asm-cris/pgtable.h +++ b/include/asm-cris/pgtable.h @@ -249,7 +249,7 @@ static inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address) #define pte_unmap(pte) do { } while (0) #define pte_unmap_nested(pte) do { } while (0) #define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT) -#define pfn_pte(pfn, prot) __pte((__pa((pfn) << PAGE_SHIFT)) | pgprot_val(prot)) +#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) #define pte_ERROR(e) \ printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e)) diff --git a/include/asm-cris/posix_types.h b/include/asm-cris/posix_types.h index 3a5e4c43eae..ce3fb25a460 100644 --- a/include/asm-cris/posix_types.h +++ b/include/asm-cris/posix_types.h @@ -44,11 +44,7 @@ typedef long long __kernel_loff_t; #endif typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; #ifdef __KERNEL__ diff --git a/include/asm-cris/processor.h b/include/asm-cris/processor.h index 568da1deceb..cdc0c1dce6b 100644 --- a/include/asm-cris/processor.h +++ b/include/asm-cris/processor.h @@ -17,6 +17,9 @@ struct task_struct; +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP + /* This decides where the kernel will search for a free chunk of vm * space during mmap's. */ diff --git a/include/asm-cris/rtc.h b/include/asm-cris/rtc.h index cb4bf9217fe..17d3019529e 100644 --- a/include/asm-cris/rtc.h +++ b/include/asm-cris/rtc.h @@ -1,10 +1,7 @@ -/* $Id: rtc.h,v 1.7 2002/11/04 07:32:09 starvik Exp $ */ #ifndef __RTC_H__ #define __RTC_H__ - - #ifdef CONFIG_ETRAX_DS1302 /* Dallas DS1302 clock/calendar register numbers. */ # define RTC_SECONDS 0 @@ -17,17 +14,17 @@ # define RTC_CONTROL 7 /* Bits in CONTROL register. */ -# define RTC_CONTROL_WRITEPROTECT 0x80 -# define RTC_TRICKLECHARGER 8 - +# define RTC_CONTROL_WRITEPROTECT 0x80 +# define RTC_TRICKLECHARGER 8 + /* Bits in TRICKLECHARGER register TCS TCS TCS TCS DS DS RS RS. */ -# define RTC_TCR_PATTERN 0xA0 /* 1010xxxx */ -# define RTC_TCR_1DIOD 0x04 /* xxxx01xx */ -# define RTC_TCR_2DIOD 0x08 /* xxxx10xx */ -# define RTC_TCR_DISABLED 0x00 /* xxxxxx00 Disabled */ -# define RTC_TCR_2KOHM 0x01 /* xxxxxx01 2KOhm */ -# define RTC_TCR_4KOHM 0x02 /* xxxxxx10 4kOhm */ -# define RTC_TCR_8KOHM 0x03 /* xxxxxx11 8kOhm */ +# define RTC_TCR_PATTERN 0xA0 /* 1010xxxx */ +# define RTC_TCR_1DIOD 0x04 /* xxxx01xx */ +# define RTC_TCR_2DIOD 0x08 /* xxxx10xx */ +# define RTC_TCR_DISABLED 0x00 /* xxxxxx00 Disabled */ +# define RTC_TCR_2KOHM 0x01 /* xxxxxx01 2KOhm */ +# define RTC_TCR_4KOHM 0x02 /* xxxxxx10 4kOhm */ +# define RTC_TCR_8KOHM 0x03 /* xxxxxx11 8kOhm */ #elif defined(CONFIG_ETRAX_PCF8563) /* I2C bus slave registers. */ @@ -79,7 +76,7 @@ extern int pcf8563_init(void); /* * The struct used to pass data via the following ioctl. Similar to the - * struct tm in <time.h>, but it needs to be here so that the kernel + * struct tm in <time.h>, but it needs to be here so that the kernel * source is self contained, allowing cross-compiles, etc. etc. */ struct rtc_time { @@ -96,11 +93,15 @@ struct rtc_time { /* ioctl() calls that are permitted to the /dev/rtc interface. */ #define RTC_MAGIC 'p' -#define RTC_RD_TIME _IOR(RTC_MAGIC, 0x09, struct rtc_time) /* Read RTC time. */ -#define RTC_SET_TIME _IOW(RTC_MAGIC, 0x0a, struct rtc_time) /* Set RTC time. */ -#define RTC_SET_CHARGE _IOW(RTC_MAGIC, 0x0b, int) -#define RTC_VLOW_RD _IOR(RTC_MAGIC, 0x11, int) /* Voltage Low detector */ -#define RTC_VLOW_SET _IO(RTC_MAGIC, 0x12) /* Clear voltage low information */ -#define RTC_MAX_IOCTL 0x12 +/* Read RTC time. */ +#define RTC_RD_TIME _IOR(RTC_MAGIC, 0x09, struct rtc_time) +/* Set RTC time. */ +#define RTC_SET_TIME _IOW(RTC_MAGIC, 0x0a, struct rtc_time) +#define RTC_SET_CHARGE _IOW(RTC_MAGIC, 0x0b, int) +/* Voltage low detector */ +#define RTC_VL_READ _IOR(RTC_MAGIC, 0x13, int) +/* Clear voltage low information */ +#define RTC_VL_CLR _IO(RTC_MAGIC, 0x14) +#define RTC_MAX_IOCTL 0x14 #endif /* __RTC_H__ */ diff --git a/include/asm-cris/smp.h b/include/asm-cris/smp.h index dca5ef1d8c9..dba33aba3e9 100644 --- a/include/asm-cris/smp.h +++ b/include/asm-cris/smp.h @@ -4,8 +4,8 @@ #include <linux/cpumask.h> extern cpumask_t phys_cpu_present_map; -#define cpu_possible_map phys_cpu_present_map +extern cpumask_t cpu_possible_map; -#define __smp_processor_id() (current_thread_info()->cpu) +#define raw_smp_processor_id() (current_thread_info()->cpu) #endif diff --git a/include/asm-cris/sync_serial.h b/include/asm-cris/sync_serial.h index f930b6e0066..d87c24df2b3 100644 --- a/include/asm-cris/sync_serial.h +++ b/include/asm-cris/sync_serial.h @@ -67,6 +67,7 @@ /* Values for SSP_FRAME_SYNC */ #define NORMAL_SYNC 1 #define EARLY_SYNC 2 +#define SECOND_WORD_SYNC 0x40000 #define BIT_SYNC 4 #define WORD_SYNC 8 diff --git a/include/asm-cris/unistd.h b/include/asm-cris/unistd.h index bd57a794917..007cb16a6b5 100644 --- a/include/asm-cris/unistd.h +++ b/include/asm-cris/unistd.h @@ -326,9 +326,11 @@ #define __NR_epoll_pwait 319 #define __NR_utimensat 320 #define __NR_signalfd 321 -#define __NR_timerfd 322 +#define __NR_timerfd_create 322 #define __NR_eventfd 323 #define __NR_fallocate 324 +#define __NR_timerfd_settime 315 +#define __NR_timerfd_gettime 316 #ifdef __KERNEL__ diff --git a/include/asm-frv/a.out.h b/include/asm-frv/a.out.h deleted file mode 100644 index dd3b7e5754c..00000000000 --- a/include/asm-frv/a.out.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * FRV doesn't do AOUT format. This header file should be removed as - * soon as fs/exec.c and fs/proc/kcore.c and the archs that require - * them to include linux/a.out.h are fixed. - */ diff --git a/include/asm-frv/atomic.h b/include/asm-frv/atomic.h index 6ec494a5bc5..46d696b331e 100644 --- a/include/asm-frv/atomic.h +++ b/include/asm-frv/atomic.h @@ -125,87 +125,6 @@ static inline void atomic_dec(atomic_t *v) #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) #define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0) -#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS -static inline -unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v) -{ - unsigned long old, tmp; - - asm volatile( - "0: \n" - " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */ - " ckeq icc3,cc7 \n" - " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */ - " orcr cc7,cc7,cc3 \n" /* set CC3 to true */ - " and%I3 %1,%3,%2 \n" - " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */ - " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */ - " beq icc3,#0,0b \n" - : "+U"(*v), "=&r"(old), "=r"(tmp) - : "NPr"(~mask) - : "memory", "cc7", "cc3", "icc3" - ); - - return old; -} - -static inline -unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v) -{ - unsigned long old, tmp; - - asm volatile( - "0: \n" - " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */ - " ckeq icc3,cc7 \n" - " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */ - " orcr cc7,cc7,cc3 \n" /* set CC3 to true */ - " or%I3 %1,%3,%2 \n" - " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */ - " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */ - " beq icc3,#0,0b \n" - : "+U"(*v), "=&r"(old), "=r"(tmp) - : "NPr"(mask) - : "memory", "cc7", "cc3", "icc3" - ); - - return old; -} - -static inline -unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v) -{ - unsigned long old, tmp; - - asm volatile( - "0: \n" - " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */ - " ckeq icc3,cc7 \n" - " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */ - " orcr cc7,cc7,cc3 \n" /* set CC3 to true */ - " xor%I3 %1,%3,%2 \n" - " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */ - " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */ - " beq icc3,#0,0b \n" - : "+U"(*v), "=&r"(old), "=r"(tmp) - : "NPr"(mask) - : "memory", "cc7", "cc3", "icc3" - ); - - return old; -} - -#else - -extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v); -extern unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v); -extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v); - -#endif - -#define atomic_clear_mask(mask, v) atomic_test_and_ANDNOT_mask((mask), (v)) -#define atomic_set_mask(mask, v) atomic_test_and_OR_mask((mask), (v)) - /*****************************************************************************/ /* * exchange value with memory diff --git a/include/asm-frv/bitops.h b/include/asm-frv/bitops.h index 5f86b876b29..39456ba0ec1 100644 --- a/include/asm-frv/bitops.h +++ b/include/asm-frv/bitops.h @@ -16,8 +16,6 @@ #include <linux/compiler.h> #include <asm/byteorder.h> -#include <asm/system.h> -#include <asm/atomic.h> #ifdef __KERNEL__ @@ -33,6 +31,87 @@ #define smp_mb__before_clear_bit() barrier() #define smp_mb__after_clear_bit() barrier() +#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS +static inline +unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v) +{ + unsigned long old, tmp; + + asm volatile( + "0: \n" + " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */ + " ckeq icc3,cc7 \n" + " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */ + " orcr cc7,cc7,cc3 \n" /* set CC3 to true */ + " and%I3 %1,%3,%2 \n" + " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */ + " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */ + " beq icc3,#0,0b \n" + : "+U"(*v), "=&r"(old), "=r"(tmp) + : "NPr"(~mask) + : "memory", "cc7", "cc3", "icc3" + ); + + return old; +} + +static inline +unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v) +{ + unsigned long old, tmp; + + asm volatile( + "0: \n" + " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */ + " ckeq icc3,cc7 \n" + " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */ + " orcr cc7,cc7,cc3 \n" /* set CC3 to true */ + " or%I3 %1,%3,%2 \n" + " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */ + " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */ + " beq icc3,#0,0b \n" + : "+U"(*v), "=&r"(old), "=r"(tmp) + : "NPr"(mask) + : "memory", "cc7", "cc3", "icc3" + ); + + return old; +} + +static inline +unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v) +{ + unsigned long old, tmp; + + asm volatile( + "0: \n" + " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */ + " ckeq icc3,cc7 \n" + " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */ + " orcr cc7,cc7,cc3 \n" /* set CC3 to true */ + " xor%I3 %1,%3,%2 \n" + " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */ + " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */ + " beq icc3,#0,0b \n" + : "+U"(*v), "=&r"(old), "=r"(tmp) + : "NPr"(mask) + : "memory", "cc7", "cc3", "icc3" + ); + + return old; +} + +#else + +extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v); +extern unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v); +extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v); + +#endif + +#define atomic_clear_mask(mask, v) atomic_test_and_ANDNOT_mask((mask), (v)) +#define atomic_set_mask(mask, v) atomic_test_and_OR_mask((mask), (v)) + static inline int test_and_clear_bit(int nr, volatile void *addr) { volatile unsigned long *ptr = addr; diff --git a/include/asm-frv/page.h b/include/asm-frv/page.h index cacc045700d..c2c1e89e747 100644 --- a/include/asm-frv/page.h +++ b/include/asm-frv/page.h @@ -25,6 +25,7 @@ typedef struct { unsigned long ste[64];} pmd_t; typedef struct { pmd_t pue[1]; } pud_t; typedef struct { pud_t pge[1]; } pgd_t; typedef struct { unsigned long pgprot; } pgprot_t; +typedef struct page *pgtable_t; #define pte_val(x) ((x).pte) #define pmd_val(x) ((x).ste[0]) diff --git a/include/asm-frv/param.h b/include/asm-frv/param.h index 365653b1726..6859dd503ed 100644 --- a/include/asm-frv/param.h +++ b/include/asm-frv/param.h @@ -2,7 +2,7 @@ #define _ASM_PARAM_H #ifdef __KERNEL__ -#define HZ 1000 /* Internal kernel timer frequency */ +#define HZ CONFIG_HZ /* Internal kernel timer frequency */ #define USER_HZ 100 /* .. some user interfaces are in "ticks" */ #define CLOCKS_PER_SEC (USER_HZ) /* like times() */ #endif diff --git a/include/asm-frv/pgalloc.h b/include/asm-frv/pgalloc.h index e89620ef08c..971e6addb00 100644 --- a/include/asm-frv/pgalloc.h +++ b/include/asm-frv/pgalloc.h @@ -25,6 +25,7 @@ do { \ __set_pmd((PMD), page_to_pfn(PAGE) << PAGE_SHIFT | _PAGE_TABLE); \ } while(0) +#define pmd_pgtable(pmd) pmd_page(pmd) /* * Allocate and free page tables. @@ -35,19 +36,24 @@ extern void pgd_free(struct mm_struct *mm, pgd_t *); extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long); -extern struct page *pte_alloc_one(struct mm_struct *, unsigned long); +extern pgtable_t pte_alloc_one(struct mm_struct *, unsigned long); static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) { free_page((unsigned long)pte); } -static inline void pte_free(struct mm_struct *mm, struct page *pte) +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) { + pgtable_page_dtor(pte); __free_page(pte); } -#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) +#define __pte_free_tlb(tlb,pte) \ +do { \ + pgtable_page_dtor(pte); \ + tlb_remove_page((tlb),(pte)); \ +} while (0) /* * allocating and freeing a pmd is trivial: the 1-entry pmd is diff --git a/include/asm-frv/posix_types.h b/include/asm-frv/posix_types.h index 73c2ba8d76b..a9f1f5be063 100644 --- a/include/asm-frv/posix_types.h +++ b/include/asm-frv/posix_types.h @@ -39,14 +39,10 @@ typedef long long __kernel_loff_t; #endif typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) +#if defined(__KERNEL__) #undef __FD_SET #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) @@ -60,7 +56,7 @@ typedef struct { #undef __FD_ZERO #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* defined(__KERNEL__) */ #endif diff --git a/include/asm-frv/system.h b/include/asm-frv/system.h index 59be5443a68..b400cea8148 100644 --- a/include/asm-frv/system.h +++ b/include/asm-frv/system.h @@ -14,6 +14,7 @@ #include <linux/types.h> #include <linux/linkage.h> +#include <linux/kernel.h> struct thread_struct; @@ -276,7 +277,7 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr, { switch (size) { case 4: - return cmpxchg(ptr, old, new); + return cmpxchg((unsigned long *)ptr, old, new); default: return __cmpxchg_local_generic(ptr, old, new, size); } diff --git a/include/asm-generic/Kbuild.asm b/include/asm-generic/Kbuild.asm index 57ba6063595..fd9dcfd91c3 100644 --- a/include/asm-generic/Kbuild.asm +++ b/include/asm-generic/Kbuild.asm @@ -1,4 +1,6 @@ +ifeq ($(wildcard include/asm-$(SRCARCH)/a.out.h),include/asm-$(SRCARCH)/a.out.h) unifdef-y += a.out.h +endif unifdef-y += auxvec.h unifdef-y += byteorder.h unifdef-y += errno.h diff --git a/include/asm-generic/iomap.h b/include/asm-generic/iomap.h index cde592fca44..67dc84cd134 100644 --- a/include/asm-generic/iomap.h +++ b/include/asm-generic/iomap.h @@ -25,17 +25,17 @@ * in the low address range. Architectures for which this is not * true can't use this generic implementation. */ -extern unsigned int fastcall ioread8(void __iomem *); -extern unsigned int fastcall ioread16(void __iomem *); -extern unsigned int fastcall ioread16be(void __iomem *); -extern unsigned int fastcall ioread32(void __iomem *); -extern unsigned int fastcall ioread32be(void __iomem *); +extern unsigned int ioread8(void __iomem *); +extern unsigned int ioread16(void __iomem *); +extern unsigned int ioread16be(void __iomem *); +extern unsigned int ioread32(void __iomem *); +extern unsigned int ioread32be(void __iomem *); -extern void fastcall iowrite8(u8, void __iomem *); -extern void fastcall iowrite16(u16, void __iomem *); -extern void fastcall iowrite16be(u16, void __iomem *); -extern void fastcall iowrite32(u32, void __iomem *); -extern void fastcall iowrite32be(u32, void __iomem *); +extern void iowrite8(u8, void __iomem *); +extern void iowrite16(u16, void __iomem *); +extern void iowrite16be(u16, void __iomem *); +extern void iowrite32(u32, void __iomem *); +extern void iowrite32be(u32, void __iomem *); /* * "string" versions of the above. Note that they @@ -48,13 +48,13 @@ extern void fastcall iowrite32be(u32, void __iomem *); * memory across multiple ports, use "memcpy_toio()" * and friends. */ -extern void fastcall ioread8_rep(void __iomem *port, void *buf, unsigned long count); -extern void fastcall ioread16_rep(void __iomem *port, void *buf, unsigned long count); -extern void fastcall ioread32_rep(void __iomem *port, void *buf, unsigned long count); +extern void ioread8_rep(void __iomem *port, void *buf, unsigned long count); +extern void ioread16_rep(void __iomem *port, void *buf, unsigned long count); +extern void ioread32_rep(void __iomem *port, void *buf, unsigned long count); -extern void fastcall iowrite8_rep(void __iomem *port, const void *buf, unsigned long count); -extern void fastcall iowrite16_rep(void __iomem *port, const void *buf, unsigned long count); -extern void fastcall iowrite32_rep(void __iomem *port, const void *buf, unsigned long count); +extern void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count); +extern void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count); +extern void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count); /* Create a virtual mapping cookie for an IO port range */ extern void __iomem *ioport_map(unsigned long port, unsigned int nr); diff --git a/include/asm-generic/mutex-dec.h b/include/asm-generic/mutex-dec.h index 0134151656a..ed108be6743 100644 --- a/include/asm-generic/mutex-dec.h +++ b/include/asm-generic/mutex-dec.h @@ -18,7 +18,7 @@ * 1 even when the "1" assertion wasn't true. */ static inline void -__mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) +__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *)) { if (unlikely(atomic_dec_return(count) < 0)) fail_fn(count); @@ -37,7 +37,7 @@ __mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) * or anything the slow path function returns. */ static inline int -__mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t *)) +__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *)) { if (unlikely(atomic_dec_return(count) < 0)) return fail_fn(count); @@ -61,7 +61,7 @@ __mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t * * to return 0 otherwise. */ static inline void -__mutex_fastpath_unlock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) +__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *)) { smp_mb(); if (unlikely(atomic_inc_return(count) <= 0)) diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h index 6a7e8c141b5..7b9cd2cbfeb 100644 --- a/include/asm-generic/mutex-xchg.h +++ b/include/asm-generic/mutex-xchg.h @@ -23,7 +23,7 @@ * even when the "1" assertion wasn't true. */ static inline void -__mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) +__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *)) { if (unlikely(atomic_xchg(count, 0) != 1)) fail_fn(count); @@ -42,7 +42,7 @@ __mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) * or anything the slow path function returns */ static inline int -__mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t *)) +__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *)) { if (unlikely(atomic_xchg(count, 0) != 1)) return fail_fn(count); @@ -65,7 +65,7 @@ __mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t * * to return 0 otherwise. */ static inline void -__mutex_fastpath_unlock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) +__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *)) { smp_mb(); if (unlikely(atomic_xchg(count, 1) != 0)) diff --git a/include/asm-generic/termios.h b/include/asm-generic/termios.h index 33dca30a3c4..7d39ecc92d9 100644 --- a/include/asm-generic/termios.h +++ b/include/asm-generic/termios.h @@ -61,8 +61,14 @@ static inline int kernel_termios_to_user_termio(struct termio __user *termio, return 0; } +#ifndef user_termios_to_kernel_termios #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) +#endif + +#ifndef kernel_termios_to_user_termios #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) +#endif + #define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) #define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) diff --git a/include/asm-h8300/a.out.h b/include/asm-h8300/a.out.h index aa5d2277823..ded780f0a49 100644 --- a/include/asm-h8300/a.out.h +++ b/include/asm-h8300/a.out.h @@ -17,11 +17,4 @@ struct exec #define N_DRSIZE(a) ((a).a_drsize) #define N_SYMSIZE(a) ((a).a_syms) -#ifdef __KERNEL__ - -#define STACK_TOP TASK_SIZE -#define STACK_TOP_MAX STACK_TOP - -#endif - #endif /* __H8300_A_OUT_H__ */ diff --git a/include/asm-h8300/param.h b/include/asm-h8300/param.h index c25806ed1fb..04f64f10037 100644 --- a/include/asm-h8300/param.h +++ b/include/asm-h8300/param.h @@ -3,7 +3,7 @@ #ifndef HZ -#define HZ 100 +#define HZ CONFIG_HZ #endif #ifdef __KERNEL__ diff --git a/include/asm-h8300/posix_types.h b/include/asm-h8300/posix_types.h index 7de94b1fd0e..5c553927fc5 100644 --- a/include/asm-h8300/posix_types.h +++ b/include/asm-h8300/posix_types.h @@ -38,14 +38,10 @@ typedef long long __kernel_loff_t; #endif typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) +#if defined(__KERNEL__) #undef __FD_SET #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) @@ -59,6 +55,6 @@ typedef struct { #undef __FD_ZERO #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* defined(__KERNEL__) */ #endif diff --git a/include/asm-h8300/processor.h b/include/asm-h8300/processor.h index 49fc886a623..69e8a34eb6d 100644 --- a/include/asm-h8300/processor.h +++ b/include/asm-h8300/processor.h @@ -39,6 +39,11 @@ static inline void wrusp(unsigned long usp) { */ #define TASK_SIZE (0xFFFFFFFFUL) +#ifdef __KERNEL__ +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP +#endif + /* * This decides where the kernel will search for a free chunk of vm * space during mmap's. We won't be using it diff --git a/include/asm-ia64/a.out.h b/include/asm-ia64/a.out.h index 7293ac1df3a..193dcfb6759 100644 --- a/include/asm-ia64/a.out.h +++ b/include/asm-ia64/a.out.h @@ -29,7 +29,4 @@ struct exec { #define N_SYMSIZE(x) 0 #define N_TXTOFF(x) 0 -#ifdef __KERNEL__ -#include <asm/ustack.h> -#endif #endif /* _ASM_IA64_A_OUT_H */ diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h index 8a8aa3fd7cd..4999a6c6377 100644 --- a/include/asm-ia64/page.h +++ b/include/asm-ia64/page.h @@ -185,6 +185,7 @@ get_order (unsigned long size) #endif typedef struct { unsigned long pgd; } pgd_t; typedef struct { unsigned long pgprot; } pgprot_t; + typedef struct page *pgtable_t; # define pte_val(x) ((x).pte) # define pmd_val(x) ((x).pmd) @@ -206,6 +207,7 @@ get_order (unsigned long size) typedef unsigned long pmd_t; typedef unsigned long pgd_t; typedef unsigned long pgprot_t; + typedef struct page *pgtable_t; # endif # define pte_val(x) (x) diff --git a/include/asm-ia64/pgalloc.h b/include/asm-ia64/pgalloc.h index 556d988123a..b9ac1a6fc21 100644 --- a/include/asm-ia64/pgalloc.h +++ b/include/asm-ia64/pgalloc.h @@ -70,10 +70,11 @@ static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd) #define __pmd_free_tlb(tlb, pmd) pmd_free((tlb)->mm, pmd) static inline void -pmd_populate(struct mm_struct *mm, pmd_t * pmd_entry, struct page *pte) +pmd_populate(struct mm_struct *mm, pmd_t * pmd_entry, pgtable_t pte) { pmd_val(*pmd_entry) = page_to_phys(pte); } +#define pmd_pgtable(pmd) pmd_page(pmd) static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmd_entry, pte_t * pte) @@ -81,11 +82,17 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmd_entry, pte_t * pte) pmd_val(*pmd_entry) = __pa(pte); } -static inline struct page *pte_alloc_one(struct mm_struct *mm, - unsigned long addr) +static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr) { - void *pg = quicklist_alloc(0, GFP_KERNEL, NULL); - return pg ? virt_to_page(pg) : NULL; + struct page *page; + void *pg; + + pg = quicklist_alloc(0, GFP_KERNEL, NULL); + if (!pg) + return NULL; + page = virt_to_page(pg); + pgtable_page_ctor(page); + return page; } static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, @@ -94,8 +101,9 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, return quicklist_alloc(0, GFP_KERNEL, NULL); } -static inline void pte_free(struct mm_struct *mm, struct page *pte) +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) { + pgtable_page_dtor(pte); quicklist_free_page(0, NULL, pte); } diff --git a/include/asm-m32r/a.out.h b/include/asm-m32r/a.out.h index 6a1b5d42f32..ab150f5c166 100644 --- a/include/asm-m32r/a.out.h +++ b/include/asm-m32r/a.out.h @@ -17,11 +17,4 @@ struct exec #define N_DRSIZE(a) ((a).a_drsize) #define N_SYMSIZE(a) ((a).a_syms) -#ifdef __KERNEL__ - -#define STACK_TOP TASK_SIZE -#define STACK_TOP_MAX STACK_TOP - -#endif - #endif /* _ASM_M32R_A_OUT_H */ diff --git a/include/asm-m32r/page.h b/include/asm-m32r/page.h index 05d43bbbf94..8a677f3fca6 100644 --- a/include/asm-m32r/page.h +++ b/include/asm-m32r/page.h @@ -28,6 +28,7 @@ typedef struct { unsigned long pgd; } pgd_t; #define PTE_MASK PAGE_MASK typedef struct { unsigned long pgprot; } pgprot_t; +typedef struct page *pgtable_t; #define pmd_val(x) ((x).pmd) #define pgd_val(x) ((x).pgd) diff --git a/include/asm-m32r/param.h b/include/asm-m32r/param.h index 3e14026e39c..94c77019604 100644 --- a/include/asm-m32r/param.h +++ b/include/asm-m32r/param.h @@ -2,7 +2,7 @@ #define _ASM_M32R_PARAM_H #ifdef __KERNEL__ -# define HZ 100 /* Internal kernel timer frequency */ +# define HZ CONFIG_HZ /* Internal kernel timer frequency */ # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ #endif diff --git a/include/asm-m32r/pgalloc.h b/include/asm-m32r/pgalloc.h index e5921adfad1..f11a2b909cd 100644 --- a/include/asm-m32r/pgalloc.h +++ b/include/asm-m32r/pgalloc.h @@ -9,10 +9,11 @@ set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte))) static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd, - struct page *pte) + pgtable_t pte) { set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte))); } +#define pmd_pgtable(pmd) pmd_page(pmd) /* * Allocate and free page tables. @@ -37,12 +38,12 @@ static __inline__ pte_t *pte_alloc_one_kernel(struct mm_struct *mm, return pte; } -static __inline__ struct page *pte_alloc_one(struct mm_struct *mm, +static __inline__ pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) { struct page *pte = alloc_page(GFP_KERNEL|__GFP_ZERO); - + pgtable_page_ctor(pte); return pte; } @@ -51,8 +52,9 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) free_page((unsigned long)pte); } -static inline void pte_free(struct mm_struct *mm, struct page *pte) +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) { + pgtable_page_dtor(pte); __free_page(pte); } diff --git a/include/asm-m32r/posix_types.h b/include/asm-m32r/posix_types.h index 1caac65d208..b309c585863 100644 --- a/include/asm-m32r/posix_types.h +++ b/include/asm-m32r/posix_types.h @@ -39,14 +39,10 @@ typedef long long __kernel_loff_t; #endif typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) +#if defined(__KERNEL__) #undef __FD_SET static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) @@ -117,6 +113,6 @@ static __inline__ void __FD_ZERO(__kernel_fd_set *__p) } } -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* defined(__KERNEL__) */ #endif /* _ASM_M32R_POSIX_TYPES_H */ diff --git a/include/asm-m32r/processor.h b/include/asm-m32r/processor.h index 32755bf136d..1a997fc148a 100644 --- a/include/asm-m32r/processor.h +++ b/include/asm-m32r/processor.h @@ -60,6 +60,11 @@ extern struct cpuinfo_m32r cpu_data[]; #define TASK_SIZE (0x00400000UL) #endif +#ifdef __KERNEL__ +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP +#endif + /* This decides where the kernel will search for a free chunk of vm * space during mmap's. */ diff --git a/include/asm-m68k/a.out-core.h b/include/asm-m68k/a.out-core.h new file mode 100644 index 00000000000..f6bfc1d63ff --- /dev/null +++ b/include/asm-m68k/a.out-core.h @@ -0,0 +1,67 @@ +/* a.out coredump register dumper + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_A_OUT_CORE_H +#define _ASM_A_OUT_CORE_H + +#ifdef __KERNEL__ + +#include <linux/user.h> +#include <linux/elfcore.h> + +/* + * fill in the user structure for an a.out core dump + */ +static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) +{ + struct switch_stack *sw; + +/* changed the size calculations - should hopefully work better. lbt */ + dump->magic = CMAGIC; + dump->start_code = 0; + dump->start_stack = rdusp() & ~(PAGE_SIZE - 1); + dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT; + dump->u_dsize = ((unsigned long) (current->mm->brk + + (PAGE_SIZE-1))) >> PAGE_SHIFT; + dump->u_dsize -= dump->u_tsize; + dump->u_ssize = 0; + + if (dump->start_stack < TASK_SIZE) + dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT; + + dump->u_ar0 = offsetof(struct user, regs); + sw = ((struct switch_stack *)regs) - 1; + dump->regs.d1 = regs->d1; + dump->regs.d2 = regs->d2; + dump->regs.d3 = regs->d3; + dump->regs.d4 = regs->d4; + dump->regs.d5 = regs->d5; + dump->regs.d6 = sw->d6; + dump->regs.d7 = sw->d7; + dump->regs.a0 = regs->a0; + dump->regs.a1 = regs->a1; + dump->regs.a2 = regs->a2; + dump->regs.a3 = sw->a3; + dump->regs.a4 = sw->a4; + dump->regs.a5 = sw->a5; + dump->regs.a6 = sw->a6; + dump->regs.d0 = regs->d0; + dump->regs.orig_d0 = regs->orig_d0; + dump->regs.stkadj = regs->stkadj; + dump->regs.sr = regs->sr; + dump->regs.pc = regs->pc; + dump->regs.fmtvec = (regs->format << 12) | regs->vector; + /* dump floating point stuff */ + dump->u_fpvalid = dump_fpu (regs, &dump->m68kfp); +} + +#endif /* __KERNEL__ */ +#endif /* _ASM_A_OUT_CORE_H */ diff --git a/include/asm-m68k/a.out.h b/include/asm-m68k/a.out.h index 6fc86a221a9..3885fe43432 100644 --- a/include/asm-m68k/a.out.h +++ b/include/asm-m68k/a.out.h @@ -17,11 +17,4 @@ struct exec #define N_DRSIZE(a) ((a).a_drsize) #define N_SYMSIZE(a) ((a).a_syms) -#ifdef __KERNEL__ - -#define STACK_TOP TASK_SIZE -#define STACK_TOP_MAX STACK_TOP - -#endif - #endif /* __M68K_A_OUT_H__ */ diff --git a/include/asm-m68k/motorola_pgalloc.h b/include/asm-m68k/motorola_pgalloc.h index 500ec9b8b18..d08bf6261df 100644 --- a/include/asm-m68k/motorola_pgalloc.h +++ b/include/asm-m68k/motorola_pgalloc.h @@ -7,7 +7,6 @@ extern pmd_t *get_pointer_table(void); extern int free_pointer_table(pmd_t *); - static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) { pte_t *pte; @@ -28,7 +27,7 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) free_page((unsigned long) pte); } -static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address) +static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) { struct page *page = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); pte_t *pte; @@ -43,19 +42,21 @@ static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long add nocache_page(pte); } kunmap(pte); - + pgtable_page_ctor(page); return page; } -static inline void pte_free(struct mm_struct *mm, struct page *page) +static inline void pte_free(struct mm_struct *mm, pgtable_t page) { + pgtable_page_dtor(page); cache_page(kmap(page)); kunmap(page); __free_page(page); } -static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *page) +static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t page) { + pgtable_page_dtor(page); cache_page(kmap(page)); kunmap(page); __free_page(page); @@ -94,10 +95,11 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t * pmd_set(pmd, pte); } -static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *page) +static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t page) { pmd_set(pmd, page_address(page)); } +#define pmd_pgtable(pmd) pmd_page(pmd) static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pmd_t *pmd) { diff --git a/include/asm-m68k/page.h b/include/asm-m68k/page.h index 3f29e2a03a4..880c2cbff8a 100644 --- a/include/asm-m68k/page.h +++ b/include/asm-m68k/page.h @@ -91,6 +91,7 @@ typedef struct { unsigned long pte; } pte_t; typedef struct { unsigned long pmd[16]; } pmd_t; typedef struct { unsigned long pgd; } pgd_t; typedef struct { unsigned long pgprot; } pgprot_t; +typedef struct page *pgtable_t; #define pte_val(x) ((x).pte) #define pmd_val(x) ((&x)->pmd[0]) diff --git a/include/asm-m68k/param.h b/include/asm-m68k/param.h index 60f409d8165..536a2788835 100644 --- a/include/asm-m68k/param.h +++ b/include/asm-m68k/param.h @@ -2,7 +2,7 @@ #define _M68K_PARAM_H #ifdef __KERNEL__ -# define HZ 100 /* Internal kernel timer frequency */ +# define HZ CONFIG_HZ /* Internal kernel timer frequency */ # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ #endif diff --git a/include/asm-m68k/posix_types.h b/include/asm-m68k/posix_types.h index fa166ee3028..63cdcc142d9 100644 --- a/include/asm-m68k/posix_types.h +++ b/include/asm-m68k/posix_types.h @@ -39,14 +39,10 @@ typedef long long __kernel_loff_t; #endif typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) +#if defined(__KERNEL__) #undef __FD_SET #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) @@ -60,6 +56,6 @@ typedef struct { #undef __FD_ZERO #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* defined(__KERNEL__) */ #endif diff --git a/include/asm-m68k/processor.h b/include/asm-m68k/processor.h index 4453ec379c5..1f61ef53f0e 100644 --- a/include/asm-m68k/processor.h +++ b/include/asm-m68k/processor.h @@ -41,6 +41,11 @@ static inline void wrusp(unsigned long usp) #define TASK_SIZE (0x0E000000UL) #endif +#ifdef __KERNEL__ +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP +#endif + /* This decides where the kernel will search for a free chunk of vm * space during mmap's. */ diff --git a/include/asm-m68k/sun3_pgalloc.h b/include/asm-m68k/sun3_pgalloc.h index a5a91e72714..d4c83f14381 100644 --- a/include/asm-m68k/sun3_pgalloc.h +++ b/include/asm-m68k/sun3_pgalloc.h @@ -26,12 +26,17 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) free_page((unsigned long) pte); } -static inline void pte_free(struct mm_struct *mm, struct page *page) +static inline void pte_free(struct mm_struct *mm, pgtable_t page) { + pgtable_page_dtor(page); __free_page(page); } -#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) +#define __pte_free_tlb(tlb,pte) \ +do { \ + pgtable_page_dtor(pte); \ + tlb_remove_page((tlb), pte); \ +} while (0) static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) @@ -45,8 +50,8 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, return (pte_t *) (page); } -static inline struct page *pte_alloc_one(struct mm_struct *mm, - unsigned long address) +static inline pgtable_t pte_alloc_one(struct mm_struct *mm, + unsigned long address) { struct page *page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, 0); @@ -54,6 +59,7 @@ static inline struct page *pte_alloc_one(struct mm_struct *mm, return NULL; clear_highpage(page); + pgtable_page_ctor(page); return page; } @@ -63,10 +69,11 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t * pmd_val(*pmd) = __pa((unsigned long)pte); } -static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *page) +static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t page) { pmd_val(*pmd) = __pa((unsigned long)page_address(page)); } +#define pmd_pgtable(pmd) pmd_page(pmd) /* * allocating and freeing a pmd is trivial: the 1-entry pmd is diff --git a/include/asm-m68knommu/param.h b/include/asm-m68knommu/param.h index 4c9904d6512..96c45101832 100644 --- a/include/asm-m68knommu/param.h +++ b/include/asm-m68knommu/param.h @@ -1,13 +1,7 @@ #ifndef _M68KNOMMU_PARAM_H #define _M68KNOMMU_PARAM_H - -#if defined(CONFIG_CLEOPATRA) -#define HZ 1000 -#endif -#ifndef HZ -#define HZ 100 -#endif +#define HZ CONFIG_HZ #ifdef __KERNEL__ #define USER_HZ HZ diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h index bf55a5b34be..cad8371422a 100644 --- a/include/asm-mips/a.out.h +++ b/include/asm-mips/a.out.h @@ -32,17 +32,4 @@ struct exec #define N_DRSIZE(a) ((a).a_drsize) #define N_SYMSIZE(a) ((a).a_syms) -#ifdef __KERNEL__ - -#ifdef CONFIG_32BIT -#define STACK_TOP TASK_SIZE -#endif -#ifdef CONFIG_64BIT -#define STACK_TOP \ - (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) -#endif -#define STACK_TOP_MAX TASK_SIZE - -#endif - #endif /* _ASM_A_OUT_H */ diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index 635aa44d229..8735aa0b896 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -90,6 +90,7 @@ typedef struct { unsigned long pte; } pte_t; #define pte_val(x) ((x).pte) #define __pte(x) ((pte_t) { (x) } ) #endif +typedef struct page *pgtable_t; /* * For 3-level pagetables we defines these ourselves, for 2-level the diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h index c4efeced839..1275831dda2 100644 --- a/include/asm-mips/pgalloc.h +++ b/include/asm-mips/pgalloc.h @@ -20,10 +20,11 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, } static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, - struct page *pte) + pgtable_t pte) { set_pmd(pmd, __pmd((unsigned long)page_address(pte))); } +#define pmd_pgtable(pmd) pmd_page(pmd) /* * Initialize a new pmd table with invalid pointers. @@ -79,9 +80,10 @@ static inline struct page *pte_alloc_one(struct mm_struct *mm, struct page *pte; pte = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER); - if (pte) + if (pte) { clear_highpage(pte); - + pgtable_page_ctor(pte); + } return pte; } @@ -90,12 +92,17 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) free_pages((unsigned long)pte, PTE_ORDER); } -static inline void pte_free(struct mm_struct *mm, struct page *pte) +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) { + pgtable_page_dtor(pte); __free_pages(pte, PTE_ORDER); } -#define __pte_free_tlb(tlb, pte) tlb_remove_page((tlb), (pte)) +#define __pte_free_tlb(tlb,pte) \ +do { \ + pgtable_page_dtor(pte); \ + tlb_remove_page((tlb), pte); \ +} while (0) #ifdef CONFIG_32BIT diff --git a/include/asm-mips/posix_types.h b/include/asm-mips/posix_types.h index c2e8a0070da..c200102c858 100644 --- a/include/asm-mips/posix_types.h +++ b/include/asm-mips/posix_types.h @@ -69,7 +69,7 @@ typedef struct { #endif } __kernel_fsid_t; -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) +#if defined(__KERNEL__) #undef __FD_SET static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) @@ -139,6 +139,6 @@ static __inline__ void __FD_ZERO(__kernel_fd_set *__p) } } -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* defined(__KERNEL__) */ #endif /* _ASM_POSIX_TYPES_H */ diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 36f42de5940..58cbac5a64e 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -39,6 +39,7 @@ extern unsigned int vced_count, vcei_count; * so don't change it unless you know what you are doing. */ #define TASK_SIZE 0x7fff8000UL +#define STACK_TOP TASK_SIZE /* * This decides where the kernel will search for a free chunk of vm @@ -57,6 +58,8 @@ extern unsigned int vced_count, vcei_count; */ #define TASK_SIZE32 0x7fff8000UL #define TASK_SIZE 0x10000000000UL +#define STACK_TOP \ + (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) /* * This decides where the kernel will search for a free chunk of vm @@ -69,6 +72,10 @@ extern unsigned int vced_count, vcei_count; (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) #endif +#ifdef __KERNEL__ +#define STACK_TOP_MAX TASK_SIZE +#endif + #define NUM_FPU_REGS 32 typedef __u64 fpureg_t; diff --git a/include/asm-mn10300/.gitignore b/include/asm-mn10300/.gitignore new file mode 100644 index 00000000000..0f87ba790e2 --- /dev/null +++ b/include/asm-mn10300/.gitignore @@ -0,0 +1,2 @@ +proc +unit diff --git a/include/asm-mn10300/Kbuild b/include/asm-mn10300/Kbuild new file mode 100644 index 00000000000..79384c537dc --- /dev/null +++ b/include/asm-mn10300/Kbuild @@ -0,0 +1,5 @@ +include include/asm-generic/Kbuild.asm + +unifdef-y += termios.h +unifdef-y += ptrace.h +unifdef-y += page.h diff --git a/include/asm-mn10300/atomic.h b/include/asm-mn10300/atomic.h new file mode 100644 index 00000000000..27c9690b957 --- /dev/null +++ b/include/asm-mn10300/atomic.h @@ -0,0 +1,166 @@ +/* MN10300 Atomic counter operations + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_ATOMIC_H +#define _ASM_ATOMIC_H + +#ifdef CONFIG_SMP +#error not SMP safe +#endif + +/* + * Atomic operations that C can't guarantee us. Useful for + * resource counting etc.. + */ + +/* + * Make sure gcc doesn't try to be clever and move things around + * on us. We need to use _exactly_ the address the user gave us, + * not some alias that contains the same information. + */ +typedef struct { + int counter; +} atomic_t; + +#define ATOMIC_INIT(i) { (i) } + +#ifdef __KERNEL__ + +/** + * atomic_read - read atomic variable + * @v: pointer of type atomic_t + * + * Atomically reads the value of @v. Note that the guaranteed + * useful range of an atomic_t is only 24 bits. + */ +#define atomic_read(v) ((v)->counter) + +/** + * atomic_set - set atomic variable + * @v: pointer of type atomic_t + * @i: required value + * + * Atomically sets the value of @v to @i. Note that the guaranteed + * useful range of an atomic_t is only 24 bits. + */ +#define atomic_set(v, i) (((v)->counter) = (i)) + +#include <asm/system.h> + +/** + * atomic_add_return - add integer to atomic variable + * @i: integer value to add + * @v: pointer of type atomic_t + * + * Atomically adds @i to @v and returns the result + * Note that the guaranteed useful range of an atomic_t is only 24 bits. + */ +static inline int atomic_add_return(int i, atomic_t *v) +{ + unsigned long flags; + int temp; + + local_irq_save(flags); + temp = v->counter; + temp += i; + v->counter = temp; + local_irq_restore(flags); + + return temp; +} + +/** + * atomic_sub_return - subtract integer from atomic variable + * @i: integer value to subtract + * @v: pointer of type atomic_t + * + * Atomically subtracts @i from @v and returns the result + * Note that the guaranteed useful range of an atomic_t is only 24 bits. + */ +static inline int atomic_sub_return(int i, atomic_t *v) +{ + unsigned long flags; + int temp; + + local_irq_save(flags); + temp = v->counter; + temp -= i; + v->counter = temp; + local_irq_restore(flags); + + return temp; +} + +static inline int atomic_add_negative(int i, atomic_t *v) +{ + return atomic_add_return(i, v) < 0; +} + +static inline void atomic_add(int i, atomic_t *v) +{ + atomic_add_return(i, v); +} + +static inline void atomic_sub(int i, atomic_t *v) +{ + atomic_sub_return(i, v); +} + +static inline void atomic_inc(atomic_t *v) +{ + atomic_add_return(1, v); +} + +static inline void atomic_dec(atomic_t *v) +{ + atomic_sub_return(1, v); +} + +#define atomic_dec_return(v) atomic_sub_return(1, (v)) +#define atomic_inc_return(v) atomic_add_return(1, (v)) + +#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0) +#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) +#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0) + +#define atomic_add_unless(v, a, u) \ +({ \ + int c, old; \ + c = atomic_read(v); \ + while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \ + c = old; \ + c != (u); \ +}) + +#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) + +static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) +{ + unsigned long flags; + + mask = ~mask; + local_irq_save(flags); + *addr &= mask; + local_irq_restore(flags); +} + +#define atomic_xchg(ptr, v) (xchg(&(ptr)->counter, (v))) +#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new))) + +/* Atomic operations are already serializing on MN10300??? */ +#define smp_mb__before_atomic_dec() barrier() +#define smp_mb__after_atomic_dec() barrier() +#define smp_mb__before_atomic_inc() barrier() +#define smp_mb__after_atomic_inc() barrier() + +#include <asm-generic/atomic.h> + +#endif /* __KERNEL__ */ +#endif /* _ASM_ATOMIC_H */ diff --git a/include/asm-mn10300/auxvec.h b/include/asm-mn10300/auxvec.h new file mode 100644 index 00000000000..4fdb60b2ae3 --- /dev/null +++ b/include/asm-mn10300/auxvec.h @@ -0,0 +1,4 @@ +#ifndef _ASM_AUXVEC_H +#define _ASM_AUXVEC_H + +#endif diff --git a/include/asm-mn10300/bitops.h b/include/asm-mn10300/bitops.h new file mode 100644 index 00000000000..cc6d40c05cf --- /dev/null +++ b/include/asm-mn10300/bitops.h @@ -0,0 +1,229 @@ +/* MN10300 bit operations + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + * + * These have to be done with inline assembly: that way the bit-setting + * is guaranteed to be atomic. All bit operations return 0 if the bit + * was cleared before the operation and != 0 if it was not. + * + * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). + */ +#ifndef __ASM_BITOPS_H +#define __ASM_BITOPS_H + +#include <asm/cpu-regs.h> + +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() + +/* + * set bit + */ +#define __set_bit(nr, addr) \ +({ \ + volatile unsigned char *_a = (unsigned char *)(addr); \ + const unsigned shift = (nr) & 7; \ + _a += (nr) >> 3; \ + \ + asm volatile("bset %2,(%1) # set_bit reg" \ + : "=m"(*_a) \ + : "a"(_a), "d"(1 << shift), "m"(*_a) \ + : "memory", "cc"); \ +}) + +#define set_bit(nr, addr) __set_bit((nr), (addr)) + +/* + * clear bit + */ +#define ___clear_bit(nr, addr) \ +({ \ + volatile unsigned char *_a = (unsigned char *)(addr); \ + const unsigned shift = (nr) & 7; \ + _a += (nr) >> 3; \ + \ + asm volatile("bclr %2,(%1) # clear_bit reg" \ + : "=m"(*_a) \ + : "a"(_a), "d"(1 << shift), "m"(*_a) \ + : "memory", "cc"); \ +}) + +#define clear_bit(nr, addr) ___clear_bit((nr), (addr)) + + +static inline void __clear_bit(int nr, volatile void *addr) +{ + unsigned int *a = (unsigned int *) addr; + int mask; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a &= ~mask; +} + +/* + * test bit + */ +static inline int test_bit(int nr, const volatile void *addr) +{ + return 1UL & (((const unsigned int *) addr)[nr >> 5] >> (nr & 31)); +} + +/* + * change bit + */ +static inline void __change_bit(int nr, volatile void *addr) +{ + int mask; + unsigned int *a = (unsigned int *) addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a ^= mask; +} + +extern void change_bit(int nr, volatile void *addr); + +/* + * test and set bit + */ +#define __test_and_set_bit(nr,addr) \ +({ \ + volatile unsigned char *_a = (unsigned char *)(addr); \ + const unsigned shift = (nr) & 7; \ + unsigned epsw; \ + _a += (nr) >> 3; \ + \ + asm volatile("bset %3,(%2) # test_set_bit reg\n" \ + "mov epsw,%1" \ + : "=m"(*_a), "=d"(epsw) \ + : "a"(_a), "d"(1 << shift), "m"(*_a) \ + : "memory", "cc"); \ + \ + !(epsw & EPSW_FLAG_Z); \ +}) + +#define test_and_set_bit(nr, addr) __test_and_set_bit((nr), (addr)) + +/* + * test and clear bit + */ +#define __test_and_clear_bit(nr, addr) \ +({ \ + volatile unsigned char *_a = (unsigned char *)(addr); \ + const unsigned shift = (nr) & 7; \ + unsigned epsw; \ + _a += (nr) >> 3; \ + \ + asm volatile("bclr %3,(%2) # test_clear_bit reg\n" \ + "mov epsw,%1" \ + : "=m"(*_a), "=d"(epsw) \ + : "a"(_a), "d"(1 << shift), "m"(*_a) \ + : "memory", "cc"); \ + \ + !(epsw & EPSW_FLAG_Z); \ +}) + +#define test_and_clear_bit(nr, addr) __test_and_clear_bit((nr), (addr)) + +/* + * test and change bit + */ +static inline int __test_and_change_bit(int nr, volatile void *addr) +{ + int mask, retval; + unsigned int *a = (unsigned int *)addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a ^= mask; + + return retval; +} + +extern int test_and_change_bit(int nr, volatile void *addr); + +#include <asm-generic/bitops/lock.h> + +#ifdef __KERNEL__ + +/** + * __ffs - find first bit set + * @x: the word to search + * + * - return 31..0 to indicate bit 31..0 most least significant bit set + * - if no bits are set in x, the result is undefined + */ +static inline __attribute__((const)) +unsigned long __ffs(unsigned long x) +{ + int bit; + asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(x & -x)); + return bit; +} + +/* + * special slimline version of fls() for calculating ilog2_u32() + * - note: no protection against n == 0 + */ +static inline __attribute__((const)) +int __ilog2_u32(u32 n) +{ + int bit; + asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(n)); + return bit; +} + +/** + * fls - find last bit set + * @x: the word to search + * + * This is defined the same way as ffs: + * - return 32..1 to indicate bit 31..0 most significant bit set + * - return 0 to indicate no bits set + */ +static inline __attribute__((const)) +int fls(int x) +{ + return (x != 0) ? __ilog2_u32(x) + 1 : 0; +} + +/** + * ffs - find first bit set + * @x: the word to search + * + * - return 32..1 to indicate bit 31..0 most least significant bit set + * - return 0 to indicate no bits set + */ +static inline __attribute__((const)) +int ffs(int x) +{ + /* Note: (x & -x) gives us a mask that is the least significant + * (rightmost) 1-bit of the value in x. + */ + return fls(x & -x); +} + +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/sched.h> +#include <asm-generic/bitops/hweight.h> + +#define ext2_set_bit_atomic(lock, nr, addr) \ + test_and_set_bit((nr) ^ 0x18, (addr)) +#define ext2_clear_bit_atomic(lock, nr, addr) \ + test_and_clear_bit((nr) ^ 0x18, (addr)) + +#include <asm-generic/bitops/ext2-non-atomic.h> +#include <asm-generic/bitops/minix-le.h> + +#endif /* __KERNEL__ */ +#endif /* __ASM_BITOPS_H */ diff --git a/include/asm-mn10300/bug.h b/include/asm-mn10300/bug.h new file mode 100644 index 00000000000..4fcf3384e25 --- /dev/null +++ b/include/asm-mn10300/bug.h @@ -0,0 +1,35 @@ +/* MN10300 Kernel bug reporting + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_BUG_H +#define _ASM_BUG_H + +/* + * Tell the user there is some problem. + */ +#define _debug_bug_trap() \ +do { \ + asm volatile( \ + " syscall 15 \n" \ + "0: \n" \ + " .section __bug_table,\"a\" \n" \ + " .long 0b,%0,%1 \n" \ + " .previous \n" \ + : \ + : "i"(__FILE__), "i"(__LINE__) \ + ); \ +} while (0) + +#define BUG() _debug_bug_trap() + +#define HAVE_ARCH_BUG +#include <asm-generic/bug.h> + +#endif /* _ASM_BUG_H */ diff --git a/include/asm-mn10300/bugs.h b/include/asm-mn10300/bugs.h new file mode 100644 index 00000000000..31c8bc592b4 --- /dev/null +++ b/include/asm-mn10300/bugs.h @@ -0,0 +1,20 @@ +/* MN10300 Checks for architecture-dependent bugs + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_BUGS_H +#define _ASM_BUGS_H + +#include <asm/processor.h> + +static inline void __init check_bugs(void) +{ +} + +#endif /* _ASM_BUGS_H */ diff --git a/include/asm-mn10300/busctl-regs.h b/include/asm-mn10300/busctl-regs.h new file mode 100644 index 00000000000..1632aef7340 --- /dev/null +++ b/include/asm-mn10300/busctl-regs.h @@ -0,0 +1,151 @@ +/* AM33v2 on-board bus controller registers + * + * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_BUSCTL_REGS_H +#define _ASM_BUSCTL_REGS_H + +#include <asm/cpu-regs.h> + +#ifdef __KERNEL__ + +/* bus controller registers */ +#define BCCR __SYSREG(0xc0002000, u32) /* bus controller control reg */ +#define BCCR_B0AD 0x00000003 /* block 0 (80000000-83ffffff) bus allocation */ +#define BCCR_B1AD 0x0000000c /* block 1 (84000000-87ffffff) bus allocation */ +#define BCCR_B2AD 0x00000030 /* block 2 (88000000-8bffffff) bus allocation */ +#define BCCR_B3AD 0x000000c0 /* block 3 (8c000000-8fffffff) bus allocation */ +#define BCCR_B4AD 0x00000300 /* block 4 (90000000-93ffffff) bus allocation */ +#define BCCR_B5AD 0x00000c00 /* block 5 (94000000-97ffffff) bus allocation */ +#define BCCR_B6AD 0x00003000 /* block 6 (98000000-9bffffff) bus allocation */ +#define BCCR_B7AD 0x0000c000 /* block 7 (9c000000-9fffffff) bus allocation */ +#define BCCR_BxAD_EXBUS 0x0 /* - direct to system bus controller */ +#define BCCR_BxAD_OPEXBUS 0x1 /* - direct to memory bus controller */ +#define BCCR_BxAD_OCMBUS 0x2 /* - direct to on chip memory */ +#define BCCR_API 0x00070000 /* bus arbitration priority */ +#define BCCR_API_DMACICD 0x00000000 /* - DMA > CI > CD */ +#define BCCR_API_DMACDCI 0x00010000 /* - DMA > CD > CI */ +#define BCCR_API_CICDDMA 0x00020000 /* - CI > CD > DMA */ +#define BCCR_API_CDCIDMA 0x00030000 /* - CD > CI > DMA */ +#define BCCR_API_ROUNDROBIN 0x00040000 /* - round robin */ +#define BCCR_BEPRI_DMACICD 0x00c00000 /* bus error address priority */ +#define BCCR_BEPRI_DMACDCI 0x00000000 /* - DMA > CI > CD */ +#define BCCR_BEPRI_CICDDMA 0x00400000 /* - DMA > CD > CI */ +#define BCCR_BEPRI_CDCIDMA 0x00800000 /* - CI > CD > DMA */ +#define BCCR_BEPRI 0x00c00000 /* - CD > CI > DMA */ +#define BCCR_TMON 0x03000000 /* timeout value settings */ +#define BCCR_TMON_16IOCLK 0x00000000 /* - 16 IOCLK cycles */ +#define BCCR_TMON_256IOCLK 0x01000000 /* - 256 IOCLK cycles */ +#define BCCR_TMON_4096IOCLK 0x02000000 /* - 4096 IOCLK cycles */ +#define BCCR_TMON_65536IOCLK 0x03000000 /* - 65536 IOCLK cycles */ +#define BCCR_TMOE 0x10000000 /* timeout detection enable */ + +#define BCBERR __SYSREG(0xc0002010, u32) /* bus error source reg */ +#define BCBERR_BESB 0x0000001f /* erroneous access destination space */ +#define BCBERR_BESB_MON 0x00000001 /* - monitor space */ +#define BCBERR_BESB_IO 0x00000002 /* - IO bus */ +#define BCBERR_BESB_EX 0x00000004 /* - EX bus */ +#define BCBERR_BESB_OPEX 0x00000008 /* - OpEX bus */ +#define BCBERR_BESB_OCM 0x00000010 /* - on chip memory */ +#define BCBERR_BERW 0x00000100 /* type of access */ +#define BCBERR_BERW_WRITE 0x00000000 /* - write */ +#define BCBERR_BERW_READ 0x00000100 /* - read */ +#define BCBERR_BESD 0x00000200 /* error detector */ +#define BCBERR_BESD_BCU 0x00000000 /* - BCU detected error */ +#define BCBERR_BESD_SLAVE_BUS 0x00000200 /* - slave bus detected error */ +#define BCBERR_BEBST 0x00000400 /* type of access */ +#define BCBERR_BEBST_SINGLE 0x00000000 /* - single */ +#define BCBERR_BEBST_BURST 0x00000400 /* - burst */ +#define BCBERR_BEME 0x00000800 /* multiple bus error flag */ +#define BCBERR_BEMR 0x00007000 /* master bus that caused the error */ +#define BCBERR_BEMR_NOERROR 0x00000000 /* - no error */ +#define BCBERR_BEMR_CI 0x00001000 /* - CPU instruction fetch bus caused error */ +#define BCBERR_BEMR_CD 0x00002000 /* - CPU data bus caused error */ +#define BCBERR_BEMR_DMA 0x00004000 /* - DMA bus caused error */ + +#define BCBEAR __SYSREGC(0xc0002020, u32) /* bus error address reg */ + +/* system bus controller registers */ +#define SBBASE(X) __SYSREG(0xd8c00100 + (X) * 0x10, u32) /* SBC base addr regs */ +#define SBBASE_BE 0x00000001 /* bank enable */ +#define SBBASE_BAM 0x0000fffe /* bank address mask [31:17] */ +#define SBBASE_BBA 0xfffe0000 /* bank base address [31:17] */ + +#define SBCNTRL0(X) __SYSREG(0xd8c00200 + (X) * 0x10, u32) /* SBC bank ctrl0 regs */ +#define SBCNTRL0_WEH 0x00000f00 /* write enable hold */ +#define SBCNTRL0_REH 0x0000f000 /* read enable hold */ +#define SBCNTRL0_RWH 0x000f0000 /* SRW signal hold */ +#define SBCNTRL0_CSH 0x00f00000 /* chip select hold */ +#define SBCNTRL0_DAH 0x0f000000 /* data hold */ +#define SBCNTRL0_ADH 0xf0000000 /* address hold */ + +#define SBCNTRL1(X) __SYSREG(0xd8c00204 + (X) * 0x10, u32) /* SBC bank ctrl1 regs */ +#define SBCNTRL1_WED 0x00000f00 /* write enable delay */ +#define SBCNTRL1_RED 0x0000f000 /* read enable delay */ +#define SBCNTRL1_RWD 0x000f0000 /* SRW signal delay */ +#define SBCNTRL1_ASW 0x00f00000 /* address strobe width */ +#define SBCNTRL1_CSD 0x0f000000 /* chip select delay */ +#define SBCNTRL1_ASD 0xf0000000 /* address strobe delay */ + +#define SBCNTRL2(X) __SYSREG(0xd8c00208 + (X) * 0x10, u32) /* SBC bank ctrl2 regs */ +#define SBCNTRL2_WC 0x000000ff /* wait count */ +#define SBCNTRL2_BWC 0x00000f00 /* burst wait count */ +#define SBCNTRL2_WM 0x01000000 /* wait mode setting */ +#define SBCNTRL2_WM_FIXEDWAIT 0x00000000 /* - fixed wait access */ +#define SBCNTRL2_WM_HANDSHAKE 0x01000000 /* - handshake access */ +#define SBCNTRL2_BM 0x02000000 /* bus synchronisation mode */ +#define SBCNTRL2_BM_SYNC 0x00000000 /* - synchronous mode */ +#define SBCNTRL2_BM_ASYNC 0x02000000 /* - asynchronous mode */ +#define SBCNTRL2_BW 0x04000000 /* bus width */ +#define SBCNTRL2_BW_32 0x00000000 /* - 32 bits */ +#define SBCNTRL2_BW_16 0x04000000 /* - 16 bits */ +#define SBCNTRL2_RWINV 0x08000000 /* R/W signal invert polarity */ +#define SBCNTRL2_RWINV_NORM 0x00000000 /* - normal (read high) */ +#define SBCNTRL2_RWINV_INV 0x08000000 /* - inverted (read low) */ +#define SBCNTRL2_BT 0x70000000 /* bus type setting */ +#define SBCNTRL2_BT_SRAM 0x00000000 /* - SRAM interface */ +#define SBCNTRL2_BT_ADMUX 0x00000000 /* - addr/data multiplexed interface */ +#define SBCNTRL2_BT_BROM 0x00000000 /* - burst ROM interface */ +#define SBCNTRL2_BTSE 0x80000000 /* burst enable */ + +/* memory bus controller */ +#define SDBASE(X) __SYSREG(0xda000008 + (X) * 0x4, u32) /* MBC base addr regs */ +#define SDBASE_CE 0x00000001 /* chip enable */ +#define SDBASE_CBAM 0x0000fff0 /* chip base address mask [31:20] */ +#define SDBASE_CBAM_SHIFT 16 +#define SDBASE_CBA 0xfff00000 /* chip base address [31:20] */ + +#define SDRAMBUS __SYSREG(0xda000000, u32) /* bus mode control reg */ +#define SDRAMBUS_REFEN 0x00000004 /* refresh enable */ +#define SDRAMBUS_TRC 0x00000018 /* refresh command delay time */ +#define SDRAMBUS_BSTPT 0x00000020 /* burst stop command enable */ +#define SDRAMBUS_PONSEQ 0x00000040 /* power on sequence */ +#define SDRAMBUS_SELFREQ 0x00000080 /* self-refresh mode request */ +#define SDRAMBUS_SELFON 0x00000100 /* self-refresh mode on */ +#define SDRAMBUS_SIZE 0x00030000 /* SDRAM size */ +#define SDRAMBUS_SIZE_64Mbit 0x00010000 /* 64Mbit SDRAM (x16) */ +#define SDRAMBUS_SIZE_128Mbit 0x00020000 /* 128Mbit SDRAM (x16) */ +#define SDRAMBUS_SIZE_256Mbit 0x00030000 /* 256Mbit SDRAM (x16) */ +#define SDRAMBUS_TRASWAIT 0x000c0000 /* row address precharge command cycle number */ +#define SDRAMBUS_REFNUM 0x00300000 /* refresh command number */ +#define SDRAMBUS_BSTWAIT 0x00c00000 /* burst stop command cycle */ +#define SDRAMBUS_SETWAIT 0x03000000 /* mode register setting command cycle */ +#define SDRAMBUS_PREWAIT 0x0c000000 /* precharge command cycle */ +#define SDRAMBUS_RASLATE 0x30000000 /* RAS latency */ +#define SDRAMBUS_CASLATE 0xc0000000 /* CAS latency */ + +#define SDREFCNT __SYSREG(0xda000004, u32) /* refresh period reg */ +#define SDREFCNT_PERI 0x00000fff /* refresh period */ + +#define SDSHDW __SYSREG(0xda000010, u32) /* test reg */ + +#endif /* __KERNEL__ */ + +#endif /* _ASM_BUSCTL_REGS_H */ diff --git a/include/asm-mn10300/byteorder.h b/include/asm-mn10300/byteorder.h new file mode 100644 index 00000000000..3c993cc625f --- /dev/null +++ b/include/asm-mn10300/byteorder.h @@ -0,0 +1,46 @@ +/* MN10300 Byte-order primitive construction + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_BYTEORDER_H +#define _ASM_BYTEORDER_H + +#include <asm/types.h> + +#ifdef __GNUC__ + +static inline __attribute__((const)) +__u32 ___arch__swab32(__u32 x) +{ + __u32 ret; + asm("swap %1,%0" : "=r" (ret) : "r" (x)); + return ret; +} + +static inline __attribute__((const)) +__u16 ___arch__swab16(__u16 x) +{ + __u16 ret; + asm("swaph %1,%0" : "=r" (ret) : "r" (x)); + return ret; +} + +#define __arch__swab32(x) ___arch__swab32(x) +#define __arch__swab16(x) ___arch__swab16(x) + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#endif /* __GNUC__ */ + +#include <linux/byteorder/little_endian.h> + +#endif /* _ASM_BYTEORDER_H */ diff --git a/include/asm-mn10300/cache.h b/include/asm-mn10300/cache.h new file mode 100644 index 00000000000..9e01122208a --- /dev/null +++ b/include/asm-mn10300/cache.h @@ -0,0 +1,54 @@ +/* MN10300 cache management registers + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_CACHE_H +#define _ASM_CACHE_H + +#include <asm/cpu-regs.h> +#include <asm/proc/cache.h> + +#ifndef __ASSEMBLY__ +#define L1_CACHE_DISPARITY (L1_CACHE_NENTRIES * L1_CACHE_BYTES) +#else +#define L1_CACHE_DISPARITY L1_CACHE_NENTRIES * L1_CACHE_BYTES +#endif + +/* data cache purge registers + * - read from the register to unconditionally purge that cache line + * - write address & 0xffffff00 to conditionally purge that cache line + * - clear LSB to request invalidation as well + */ +#define DCACHE_PURGE(WAY, ENTRY) \ + __SYSREG(0xc8400000 + (WAY) * L1_CACHE_WAYDISP + \ + (ENTRY) * L1_CACHE_BYTES, u32) + +#define DCACHE_PURGE_WAY0(ENTRY) \ + __SYSREG(0xc8400000 + 0 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) +#define DCACHE_PURGE_WAY1(ENTRY) \ + __SYSREG(0xc8400000 + 1 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) +#define DCACHE_PURGE_WAY2(ENTRY) \ + __SYSREG(0xc8400000 + 2 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) +#define DCACHE_PURGE_WAY3(ENTRY) \ + __SYSREG(0xc8400000 + 3 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) + +/* instruction cache access registers */ +#define ICACHE_DATA(WAY, ENTRY, OFF) \ + __SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32) +#define ICACHE_TAG(WAY, ENTRY) \ + __SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32) + +/* instruction cache access registers */ +#define DCACHE_DATA(WAY, ENTRY, OFF) \ + __SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32) +#define DCACHE_TAG(WAY, ENTRY) \ + __SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32) + +#endif /* _ASM_CACHE_H */ diff --git a/include/asm-mn10300/cacheflush.h b/include/asm-mn10300/cacheflush.h new file mode 100644 index 00000000000..2db746a251f --- /dev/null +++ b/include/asm-mn10300/cacheflush.h @@ -0,0 +1,116 @@ +/* MN10300 Cache flushing + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_CACHEFLUSH_H +#define _ASM_CACHEFLUSH_H + +#ifndef __ASSEMBLY__ + +/* Keep includes the same across arches. */ +#include <linux/mm.h> + +/* + * virtually-indexed cache managment (our cache is physically indexed) + */ +#define flush_cache_all() do {} while (0) +#define flush_cache_mm(mm) do {} while (0) +#define flush_cache_dup_mm(mm) do {} while (0) +#define flush_cache_range(mm, start, end) do {} while (0) +#define flush_cache_page(vma, vmaddr, pfn) do {} while (0) +#define flush_cache_vmap(start, end) do {} while (0) +#define flush_cache_vunmap(start, end) do {} while (0) +#define flush_dcache_page(page) do {} while (0) +#define flush_dcache_mmap_lock(mapping) do {} while (0) +#define flush_dcache_mmap_unlock(mapping) do {} while (0) + +/* + * physically-indexed cache managment + */ +#ifndef CONFIG_MN10300_CACHE_DISABLED + +extern void flush_icache_range(unsigned long start, unsigned long end); +extern void flush_icache_page(struct vm_area_struct *vma, struct page *pg); + +#else + +#define flush_icache_range(start, end) do {} while (0) +#define flush_icache_page(vma, pg) do {} while (0) + +#endif + +#define flush_icache_user_range(vma, pg, adr, len) \ + flush_icache_range(adr, adr + len) + +#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ + do { \ + memcpy(dst, src, len); \ + flush_icache_page(vma, page); \ + } while (0) + +#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ + memcpy(dst, src, len) + +/* + * primitive routines + */ +#ifndef CONFIG_MN10300_CACHE_DISABLED +extern void mn10300_icache_inv(void); +extern void mn10300_dcache_inv(void); +extern void mn10300_dcache_inv_page(unsigned start); +extern void mn10300_dcache_inv_range(unsigned start, unsigned end); +extern void mn10300_dcache_inv_range2(unsigned start, unsigned size); +#ifdef CONFIG_MN10300_CACHE_WBACK +extern void mn10300_dcache_flush(void); +extern void mn10300_dcache_flush_page(unsigned start); +extern void mn10300_dcache_flush_range(unsigned start, unsigned end); +extern void mn10300_dcache_flush_range2(unsigned start, unsigned size); +extern void mn10300_dcache_flush_inv(void); +extern void mn10300_dcache_flush_inv_page(unsigned start); +extern void mn10300_dcache_flush_inv_range(unsigned start, unsigned end); +extern void mn10300_dcache_flush_inv_range2(unsigned start, unsigned size); +#else +#define mn10300_dcache_flush() do {} while (0) +#define mn10300_dcache_flush_page(start) do {} while (0) +#define mn10300_dcache_flush_range(start, end) do {} while (0) +#define mn10300_dcache_flush_range2(start, size) do {} while (0) +#define mn10300_dcache_flush_inv() mn10300_dcache_inv() +#define mn10300_dcache_flush_inv_page(start) \ + mn10300_dcache_inv_page((start)) +#define mn10300_dcache_flush_inv_range(start, end) \ + mn10300_dcache_inv_range((start), (end)) +#define mn10300_dcache_flush_inv_range2(start, size) \ + mn10300_dcache_inv_range2((start), (size)) +#endif /* CONFIG_MN10300_CACHE_WBACK */ +#else +#define mn10300_icache_inv() do {} while (0) +#define mn10300_dcache_inv() do {} while (0) +#define mn10300_dcache_inv_page(start) do {} while (0) +#define mn10300_dcache_inv_range(start, end) do {} while (0) +#define mn10300_dcache_inv_range2(start, size) do {} while (0) +#define mn10300_dcache_flush() do {} while (0) +#define mn10300_dcache_flush_inv_page(start) do {} while (0) +#define mn10300_dcache_flush_inv() do {} while (0) +#define mn10300_dcache_flush_inv_range(start, end) do {} while (0) +#define mn10300_dcache_flush_inv_range2(start, size) do {} while (0) +#define mn10300_dcache_flush_page(start) do {} while (0) +#define mn10300_dcache_flush_range(start, end) do {} while (0) +#define mn10300_dcache_flush_range2(start, size) do {} while (0) +#endif /* CONFIG_MN10300_CACHE_DISABLED */ + +/* + * internal debugging function + */ +#ifdef CONFIG_DEBUG_PAGEALLOC +extern void kernel_map_pages(struct page *page, int numpages, int enable); +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_CACHEFLUSH_H */ diff --git a/include/asm-mn10300/checksum.h b/include/asm-mn10300/checksum.h new file mode 100644 index 00000000000..9fb2a8d8826 --- /dev/null +++ b/include/asm-mn10300/checksum.h @@ -0,0 +1,86 @@ +/* MN10300 Optimised checksumming code + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_CHECKSUM_H +#define _ASM_CHECKSUM_H + +extern __wsum csum_partial(const void *buff, int len, __wsum sum); +extern __wsum csum_partial_copy_nocheck(const void *src, void *dst, + int len, __wsum sum); +extern __wsum csum_partial_copy_from_user(const void *src, void *dst, + int len, __wsum sum, + int *err_ptr); +extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl); +extern __wsum csum_partial(const void *buff, int len, __wsum sum); +extern __sum16 ip_compute_csum(const void *buff, int len); + +#define csum_partial_copy_fromuser csum_partial_copy +extern __wsum csum_partial_copy(const void *src, void *dst, int len, + __wsum sum); + +static inline __sum16 csum_fold(__wsum sum) +{ + asm( + " add %1,%0 \n" + " addc 0xffff,%0 \n" + : "=r" (sum) + : "r" (sum << 16), "0" (sum & 0xffff0000) + : "cc" + ); + return (~sum) >> 16; +} + +static inline __wsum csum_tcpudp_nofold(unsigned long saddr, + unsigned long daddr, + unsigned short len, + unsigned short proto, + __wsum sum) +{ + __wsum tmp; + + tmp = (__wsum) ntohs(len) << 16; + tmp += (__wsum) proto << 8; + + asm( + " add %1,%0 \n" + " addc %2,%0 \n" + " addc %3,%0 \n" + " addc 0,%0 \n" + : "=r" (sum) + : "r" (daddr), "r"(saddr), "r"(tmp), "0"(sum) + : "cc" + ); + return sum; +} + +/* + * computes the checksum of the TCP/UDP pseudo-header + * returns a 16-bit checksum, already complemented + */ +static inline __sum16 csum_tcpudp_magic(unsigned long saddr, + unsigned long daddr, + unsigned short len, + unsigned short proto, + __wsum sum) +{ + return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum)); +} + +#undef _HAVE_ARCH_IPV6_CSUM + +/* + * Copy and checksum to user + */ +#define HAVE_CSUM_COPY_USER +extern __wsum csum_and_copy_to_user(const void *src, void *dst, int len, + __wsum sum, int *err_ptr); + + +#endif /* _ASM_CHECKSUM_H */ diff --git a/include/asm-mn10300/cpu-regs.h b/include/asm-mn10300/cpu-regs.h new file mode 100644 index 00000000000..757e9b5388e --- /dev/null +++ b/include/asm-mn10300/cpu-regs.h @@ -0,0 +1,290 @@ +/* MN10300 Core system registers + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_CPU_REGS_H +#define _ASM_CPU_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/types.h> +#endif + +#ifdef CONFIG_MN10300_CPU_AM33V2 +/* we tell the compiler to pretend to be AM33 so that it doesn't try and use + * the FP regs, but tell the assembler that we're actually allowed AM33v2 + * instructions */ +#ifndef __ASSEMBLY__ +asm(" .am33_2\n"); +#else +.am33_2 +#endif +#endif + +#ifdef __KERNEL__ + +#ifndef __ASSEMBLY__ +#define __SYSREG(ADDR, TYPE) (*(volatile TYPE *)(ADDR)) +#define __SYSREGC(ADDR, TYPE) (*(const volatile TYPE *)(ADDR)) +#else +#define __SYSREG(ADDR, TYPE) ADDR +#define __SYSREGC(ADDR, TYPE) ADDR +#endif + +/* CPU registers */ +#define EPSW_FLAG_Z 0x00000001 /* zero flag */ +#define EPSW_FLAG_N 0x00000002 /* negative flag */ +#define EPSW_FLAG_C 0x00000004 /* carry flag */ +#define EPSW_FLAG_V 0x00000008 /* overflow flag */ +#define EPSW_IM 0x00000700 /* interrupt mode */ +#define EPSW_IM_0 0x00000000 /* interrupt mode 0 */ +#define EPSW_IM_1 0x00000100 /* interrupt mode 1 */ +#define EPSW_IM_2 0x00000200 /* interrupt mode 2 */ +#define EPSW_IM_3 0x00000300 /* interrupt mode 3 */ +#define EPSW_IM_4 0x00000400 /* interrupt mode 4 */ +#define EPSW_IM_5 0x00000500 /* interrupt mode 5 */ +#define EPSW_IM_6 0x00000600 /* interrupt mode 6 */ +#define EPSW_IM_7 0x00000700 /* interrupt mode 7 */ +#define EPSW_IE 0x00000800 /* interrupt enable */ +#define EPSW_S 0x00003000 /* software auxilliary bits */ +#define EPSW_T 0x00008000 /* trace enable */ +#define EPSW_nSL 0x00010000 /* not supervisor level */ +#define EPSW_NMID 0x00020000 /* nonmaskable interrupt disable */ +#define EPSW_nAR 0x00040000 /* register bank control */ +#define EPSW_ML 0x00080000 /* monitor level */ +#define EPSW_FE 0x00100000 /* FPU enable */ + +/* FPU registers */ +#define FPCR_EF_I 0x00000001 /* inexact result FPU exception flag */ +#define FPCR_EF_U 0x00000002 /* underflow FPU exception flag */ +#define FPCR_EF_O 0x00000004 /* overflow FPU exception flag */ +#define FPCR_EF_Z 0x00000008 /* zero divide FPU exception flag */ +#define FPCR_EF_V 0x00000010 /* invalid operand FPU exception flag */ +#define FPCR_EE_I 0x00000020 /* inexact result FPU exception enable */ +#define FPCR_EE_U 0x00000040 /* underflow FPU exception enable */ +#define FPCR_EE_O 0x00000080 /* overflow FPU exception enable */ +#define FPCR_EE_Z 0x00000100 /* zero divide FPU exception enable */ +#define FPCR_EE_V 0x00000200 /* invalid operand FPU exception enable */ +#define FPCR_EC_I 0x00000400 /* inexact result FPU exception cause */ +#define FPCR_EC_U 0x00000800 /* underflow FPU exception cause */ +#define FPCR_EC_O 0x00001000 /* overflow FPU exception cause */ +#define FPCR_EC_Z 0x00002000 /* zero divide FPU exception cause */ +#define FPCR_EC_V 0x00004000 /* invalid operand FPU exception cause */ +#define FPCR_RM 0x00030000 /* rounding mode */ +#define FPCR_RM_NEAREST 0x00000000 /* - round to nearest value */ +#define FPCR_FCC_U 0x00040000 /* FPU unordered condition code */ +#define FPCR_FCC_E 0x00080000 /* FPU equal condition code */ +#define FPCR_FCC_G 0x00100000 /* FPU greater than condition code */ +#define FPCR_FCC_L 0x00200000 /* FPU less than condition code */ +#define FPCR_INIT 0x00000000 /* no exceptions, rounding to nearest */ + +/* CPU control registers */ +#define CPUP __SYSREG(0xc0000020, u16) /* CPU pipeline register */ +#define CPUP_DWBD 0x0020 /* write buffer disable flag */ +#define CPUP_IPFD 0x0040 /* instruction prefetch disable flag */ +#define CPUP_EXM 0x0080 /* exception operation mode */ +#define CPUP_EXM_AM33V1 0x0000 /* - AM33 v1 exception mode */ +#define CPUP_EXM_AM33V2 0x0080 /* - AM33 v2 exception mode */ + +#define CPUM __SYSREG(0xc0000040, u16) /* CPU mode register */ +#define CPUM_SLEEP 0x0004 /* set to enter sleep state */ +#define CPUM_HALT 0x0008 /* set to enter halt state */ +#define CPUM_STOP 0x0010 /* set to enter stop state */ + +#define CPUREV __SYSREGC(0xc0000050, u32) /* CPU revision register */ +#define CPUREV_TYPE 0x0000000f /* CPU type */ +#define CPUREV_TYPE_S 0 +#define CPUREV_TYPE_AM33V1 0x00000000 /* - AM33 V1 core, AM33/1.00 arch */ +#define CPUREV_TYPE_AM33V2 0x00000001 /* - AM33 V2 core, AM33/2.00 arch */ +#define CPUREV_TYPE_AM34V1 0x00000002 /* - AM34 V1 core, AM33/2.00 arch */ +#define CPUREV_REVISION 0x000000f0 /* CPU revision */ +#define CPUREV_REVISION_S 4 +#define CPUREV_ICWAY 0x00000f00 /* number of instruction cache ways */ +#define CPUREV_ICWAY_S 8 +#define CPUREV_ICSIZE 0x0000f000 /* instruction cache way size */ +#define CPUREV_ICSIZE_S 12 +#define CPUREV_DCWAY 0x000f0000 /* number of data cache ways */ +#define CPUREV_DCWAY_S 16 +#define CPUREV_DCSIZE 0x00f00000 /* data cache way size */ +#define CPUREV_DCSIZE_S 20 +#define CPUREV_FPUTYPE 0x0f000000 /* FPU core type */ +#define CPUREV_FPUTYPE_NONE 0x00000000 /* - no FPU core implemented */ +#define CPUREV_OCDCTG 0xf0000000 /* on-chip debug function category */ + +#define DCR __SYSREG(0xc0000030, u16) /* Debug control register */ + +/* interrupt/exception control registers */ +#define IVAR0 __SYSREG(0xc0000000, u16) /* interrupt vector 0 */ +#define IVAR1 __SYSREG(0xc0000004, u16) /* interrupt vector 1 */ +#define IVAR2 __SYSREG(0xc0000008, u16) /* interrupt vector 2 */ +#define IVAR3 __SYSREG(0xc000000c, u16) /* interrupt vector 3 */ +#define IVAR4 __SYSREG(0xc0000010, u16) /* interrupt vector 4 */ +#define IVAR5 __SYSREG(0xc0000014, u16) /* interrupt vector 5 */ +#define IVAR6 __SYSREG(0xc0000018, u16) /* interrupt vector 6 */ + +#define TBR __SYSREG(0xc0000024, u32) /* Trap table base */ +#define TBR_TB 0xff000000 /* table base address bits 31-24 */ +#define TBR_INT_CODE 0x00ffffff /* interrupt code */ + +#define DEAR __SYSREG(0xc0000038, u32) /* Data access exception address */ + +#define sISR __SYSREG(0xc0000044, u32) /* Supervisor interrupt status */ +#define sISR_IRQICE 0x00000001 /* ICE interrupt */ +#define sISR_ISTEP 0x00000002 /* single step interrupt */ +#define sISR_MISSA 0x00000004 /* memory access address misalignment fault */ +#define sISR_UNIMP 0x00000008 /* unimplemented instruction execution fault */ +#define sISR_PIEXE 0x00000010 /* program interrupt */ +#define sISR_MEMERR 0x00000020 /* illegal memory access fault */ +#define sISR_IBREAK 0x00000040 /* instraction break interrupt */ +#define sISR_DBSRL 0x00000080 /* debug serial interrupt */ +#define sISR_PERIDB 0x00000100 /* peripheral debug interrupt */ +#define sISR_EXUNIMP 0x00000200 /* unimplemented ex-instruction execution fault */ +#define sISR_OBREAK 0x00000400 /* operand break interrupt */ +#define sISR_PRIV 0x00000800 /* privileged instruction execution fault */ +#define sISR_BUSERR 0x00001000 /* bus error fault */ +#define sISR_DBLFT 0x00002000 /* double fault */ +#define sISR_DBG 0x00008000 /* debug reserved interrupt */ +#define sISR_ITMISS 0x00010000 /* instruction TLB miss */ +#define sISR_DTMISS 0x00020000 /* data TLB miss */ +#define sISR_ITEX 0x00040000 /* instruction TLB access exception */ +#define sISR_DTEX 0x00080000 /* data TLB access exception */ +#define sISR_ILGIA 0x00100000 /* illegal instruction access exception */ +#define sISR_ILGDA 0x00200000 /* illegal data access exception */ +#define sISR_IOIA 0x00400000 /* internal I/O space instruction access excep */ +#define sISR_PRIVA 0x00800000 /* privileged space instruction access excep */ +#define sISR_PRIDA 0x01000000 /* privileged space data access excep */ +#define sISR_DISA 0x02000000 /* data space instruction access excep */ +#define sISR_SYSC 0x04000000 /* system call instruction excep */ +#define sISR_FPUD 0x08000000 /* FPU disabled excep */ +#define sISR_FPUUI 0x10000000 /* FPU unimplemented instruction excep */ +#define sISR_FPUOP 0x20000000 /* FPU operation excep */ +#define sISR_NE 0x80000000 /* multiple synchronous exceptions excep */ + +/* cache control registers */ +#define CHCTR __SYSREG(0xc0000070, u16) /* cache control */ +#define CHCTR_ICEN 0x0001 /* instruction cache enable */ +#define CHCTR_DCEN 0x0002 /* data cache enable */ +#define CHCTR_ICBUSY 0x0004 /* instruction cache busy */ +#define CHCTR_DCBUSY 0x0008 /* data cache busy */ +#define CHCTR_ICINV 0x0010 /* instruction cache invalidate */ +#define CHCTR_DCINV 0x0020 /* data cache invalidate */ +#define CHCTR_DCWTMD 0x0040 /* data cache writing mode */ +#define CHCTR_DCWTMD_WRBACK 0x0000 /* - write back mode */ +#define CHCTR_DCWTMD_WRTHROUGH 0x0040 /* - write through mode */ +#define CHCTR_DCALMD 0x0080 /* data cache allocation mode */ +#define CHCTR_ICWMD 0x0f00 /* instruction cache way mode */ +#define CHCTR_DCWMD 0xf000 /* data cache way mode */ + +/* MMU control registers */ +#define MMUCTR __SYSREG(0xc0000090, u32) /* MMU control register */ +#define MMUCTR_IRP 0x0000003f /* instruction TLB replace pointer */ +#define MMUCTR_ITE 0x00000040 /* instruction TLB enable */ +#define MMUCTR_IIV 0x00000080 /* instruction TLB invalidate */ +#define MMUCTR_ITL 0x00000700 /* instruction TLB lock pointer */ +#define MMUCTR_ITL_NOLOCK 0x00000000 /* - no lock */ +#define MMUCTR_ITL_LOCK0 0x00000100 /* - entry 0 locked */ +#define MMUCTR_ITL_LOCK0_1 0x00000200 /* - entry 0-1 locked */ +#define MMUCTR_ITL_LOCK0_3 0x00000300 /* - entry 0-3 locked */ +#define MMUCTR_ITL_LOCK0_7 0x00000400 /* - entry 0-7 locked */ +#define MMUCTR_ITL_LOCK0_15 0x00000500 /* - entry 0-15 locked */ +#define MMUCTR_CE 0x00008000 /* cacheable bit enable */ +#define MMUCTR_DRP 0x003f0000 /* data TLB replace pointer */ +#define MMUCTR_DTE 0x00400000 /* data TLB enable */ +#define MMUCTR_DIV 0x00800000 /* data TLB invalidate */ +#define MMUCTR_DTL 0x07000000 /* data TLB lock pointer */ +#define MMUCTR_DTL_NOLOCK 0x00000000 /* - no lock */ +#define MMUCTR_DTL_LOCK0 0x01000000 /* - entry 0 locked */ +#define MMUCTR_DTL_LOCK0_1 0x02000000 /* - entry 0-1 locked */ +#define MMUCTR_DTL_LOCK0_3 0x03000000 /* - entry 0-3 locked */ +#define MMUCTR_DTL_LOCK0_7 0x04000000 /* - entry 0-7 locked */ +#define MMUCTR_DTL_LOCK0_15 0x05000000 /* - entry 0-15 locked */ + +#define PIDR __SYSREG(0xc0000094, u16) /* PID register */ +#define PIDR_PID 0x00ff /* process identifier */ + +#define PTBR __SYSREG(0xc0000098, unsigned long) /* Page table base register */ + +#define IPTEL __SYSREG(0xc00000a0, u32) /* instruction TLB entry */ +#define DPTEL __SYSREG(0xc00000b0, u32) /* data TLB entry */ +#define xPTEL_V 0x00000001 /* TLB entry valid */ +#define xPTEL_UNUSED1 0x00000002 /* unused bit */ +#define xPTEL_UNUSED2 0x00000004 /* unused bit */ +#define xPTEL_C 0x00000008 /* cached if set */ +#define xPTEL_PV 0x00000010 /* page valid */ +#define xPTEL_D 0x00000020 /* dirty */ +#define xPTEL_PR 0x000001c0 /* page protection */ +#define xPTEL_PR_ROK 0x00000000 /* - R/O kernel */ +#define xPTEL_PR_RWK 0x00000100 /* - R/W kernel */ +#define xPTEL_PR_ROK_ROU 0x00000080 /* - R/O kernel and R/O user */ +#define xPTEL_PR_RWK_ROU 0x00000180 /* - R/W kernel and R/O user */ +#define xPTEL_PR_RWK_RWU 0x000001c0 /* - R/W kernel and R/W user */ +#define xPTEL_G 0x00000200 /* global (use PID if 0) */ +#define xPTEL_PS 0x00000c00 /* page size */ +#define xPTEL_PS_4Kb 0x00000000 /* - 4Kb page */ +#define xPTEL_PS_128Kb 0x00000400 /* - 128Kb page */ +#define xPTEL_PS_1Kb 0x00000800 /* - 1Kb page */ +#define xPTEL_PS_4Mb 0x00000c00 /* - 4Mb page */ +#define xPTEL_PPN 0xfffff006 /* physical page number */ + +#define xPTEL_V_BIT 0 /* bit numbers corresponding to above masks */ +#define xPTEL_UNUSED1_BIT 1 +#define xPTEL_UNUSED2_BIT 2 +#define xPTEL_C_BIT 3 +#define xPTEL_PV_BIT 4 +#define xPTEL_D_BIT 5 +#define xPTEL_G_BIT 9 + +#define IPTEU __SYSREG(0xc00000a4, u32) /* instruction TLB virtual addr */ +#define DPTEU __SYSREG(0xc00000b4, u32) /* data TLB virtual addr */ +#define xPTEU_VPN 0xfffffc00 /* virtual page number */ +#define xPTEU_PID 0x000000ff /* process identifier to which applicable */ + +#define IPTEL2 __SYSREG(0xc00000a8, u32) /* instruction TLB entry */ +#define DPTEL2 __SYSREG(0xc00000b8, u32) /* data TLB entry */ +#define xPTEL2_V 0x00000001 /* TLB entry valid */ +#define xPTEL2_C 0x00000002 /* cacheable */ +#define xPTEL2_PV 0x00000004 /* page valid */ +#define xPTEL2_D 0x00000008 /* dirty */ +#define xPTEL2_PR 0x00000070 /* page protection */ +#define xPTEL2_PR_ROK 0x00000000 /* - R/O kernel */ +#define xPTEL2_PR_RWK 0x00000040 /* - R/W kernel */ +#define xPTEL2_PR_ROK_ROU 0x00000020 /* - R/O kernel and R/O user */ +#define xPTEL2_PR_RWK_ROU 0x00000060 /* - R/W kernel and R/O user */ +#define xPTEL2_PR_RWK_RWU 0x00000070 /* - R/W kernel and R/W user */ +#define xPTEL2_G 0x00000080 /* global (use PID if 0) */ +#define xPTEL2_PS 0x00000300 /* page size */ +#define xPTEL2_PS_4Kb 0x00000000 /* - 4Kb page */ +#define xPTEL2_PS_128Kb 0x00000100 /* - 128Kb page */ +#define xPTEL2_PS_1Kb 0x00000200 /* - 1Kb page */ +#define xPTEL2_PS_4Mb 0x00000300 /* - 4Mb page */ +#define xPTEL2_PPN 0xfffffc00 /* physical page number */ + +#define MMUFCR __SYSREGC(0xc000009c, u32) /* MMU exception cause */ +#define MMUFCR_IFC __SYSREGC(0xc000009c, u16) /* MMU instruction excep cause */ +#define MMUFCR_DFC __SYSREGC(0xc000009e, u16) /* MMU data exception cause */ +#define MMUFCR_xFC_TLBMISS 0x0001 /* TLB miss flag */ +#define MMUFCR_xFC_INITWR 0x0002 /* initial write excep flag */ +#define MMUFCR_xFC_PGINVAL 0x0004 /* page invalid excep flag */ +#define MMUFCR_xFC_PROTVIOL 0x0008 /* protection violation excep flag */ +#define MMUFCR_xFC_ACCESS 0x0010 /* access level flag */ +#define MMUFCR_xFC_ACCESS_USR 0x0000 /* - user mode */ +#define MMUFCR_xFC_ACCESS_SR 0x0010 /* - supervisor mode */ +#define MMUFCR_xFC_TYPE 0x0020 /* access type flag */ +#define MMUFCR_xFC_TYPE_READ 0x0000 /* - read */ +#define MMUFCR_xFC_TYPE_WRITE 0x0020 /* - write */ +#define MMUFCR_xFC_PR 0x01c0 /* page protection flag */ +#define MMUFCR_xFC_PR_ROK 0x0000 /* - R/O kernel */ +#define MMUFCR_xFC_PR_RWK 0x0100 /* - R/W kernel */ +#define MMUFCR_xFC_PR_ROK_ROU 0x0080 /* - R/O kernel and R/O user */ +#define MMUFCR_xFC_PR_RWK_ROU 0x0180 /* - R/W kernel and R/O user */ +#define MMUFCR_xFC_PR_RWK_RWU 0x01c0 /* - R/W kernel and R/W user */ +#define MMUFCR_xFC_ILLADDR 0x0200 /* illegal address excep flag */ + +#endif /* __KERNEL__ */ + +#endif /* _ASM_CPU_REGS_H */ diff --git a/include/asm-mn10300/cputime.h b/include/asm-mn10300/cputime.h new file mode 100644 index 00000000000..6d68ad7e0ea --- /dev/null +++ b/include/asm-mn10300/cputime.h @@ -0,0 +1 @@ +#include <asm-generic/cputime.h> diff --git a/include/asm-mn10300/current.h b/include/asm-mn10300/current.h new file mode 100644 index 00000000000..ca6027d8374 --- /dev/null +++ b/include/asm-mn10300/current.h @@ -0,0 +1,37 @@ +/* MN10300 Current task structure accessor + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_CURRENT_H +#define _ASM_CURRENT_H + +#include <linux/thread_info.h> + +/* + * dedicate E2 to keeping the current task pointer + */ +#ifdef CONFIG_MN10300_CURRENT_IN_E2 + +register struct task_struct *const current asm("e2") __attribute__((used)); + +#define get_current() current + +extern struct task_struct *__current; + +#else +static inline __attribute__((const)) +struct task_struct *get_current(void) +{ + return current_thread_info()->task; +} + +#define current get_current() +#endif + +#endif /* _ASM_CURRENT_H */ diff --git a/include/asm-mn10300/delay.h b/include/asm-mn10300/delay.h new file mode 100644 index 00000000000..34517b35939 --- /dev/null +++ b/include/asm-mn10300/delay.h @@ -0,0 +1,19 @@ +/* MN10300 Uninterruptible delay routines + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_DELAY_H +#define _ASM_DELAY_H + +extern void __udelay(unsigned long usecs); +extern void __delay(unsigned long loops); + +#define udelay(n) __udelay(n) + +#endif /* _ASM_DELAY_H */ diff --git a/include/asm-mn10300/device.h b/include/asm-mn10300/device.h new file mode 100644 index 00000000000..f0a4c256403 --- /dev/null +++ b/include/asm-mn10300/device.h @@ -0,0 +1 @@ +#include <asm-generic/device.h> diff --git a/include/asm-mn10300/div64.h b/include/asm-mn10300/div64.h new file mode 100644 index 00000000000..bf9c515a998 --- /dev/null +++ b/include/asm-mn10300/div64.h @@ -0,0 +1,103 @@ +/* MN10300 64-bit division + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_DIV64 +#define _ASM_DIV64 + +#include <linux/types.h> + +extern void ____unhandled_size_in_do_div___(void); + +/* + * divide n by base, leaving the result in n and returning the remainder + * - we can do this quite efficiently on the MN10300 by cascading the divides + * through the MDR register + */ +#define do_div(n, base) \ +({ \ + unsigned __rem = 0; \ + if (sizeof(n) <= 4) { \ + asm("mov %1,mdr \n" \ + "divu %2,%0 \n" \ + "mov mdr,%1 \n" \ + : "+r"(n), "=d"(__rem) \ + : "r"(base), "1"(__rem) \ + : "cc" \ + ); \ + } else if (sizeof(n) <= 8) { \ + union { \ + unsigned long long l; \ + u32 w[2]; \ + } __quot; \ + __quot.l = n; \ + asm("mov %0,mdr \n" /* MDR = 0 */ \ + "divu %3,%1 \n" \ + /* __quot.MSL = __div.MSL / base, */ \ + /* MDR = MDR:__div.MSL % base */ \ + "divu %3,%2 \n" \ + /* __quot.LSL = MDR:__div.LSL / base, */ \ + /* MDR = MDR:__div.LSL % base */ \ + "mov mdr,%0 \n" \ + : "=d"(__rem), "=r"(__quot.w[1]), "=r"(__quot.w[0]) \ + : "r"(base), "0"(__rem), "1"(__quot.w[1]), \ + "2"(__quot.w[0]) \ + : "cc" \ + ); \ + n = __quot.l; \ + } else { \ + ____unhandled_size_in_do_div___(); \ + } \ + __rem; \ +}) + +/* + * do an unsigned 32-bit multiply and divide with intermediate 64-bit product + * so as not to lose accuracy + * - we use the MDR register to hold the MSW of the product + */ +static inline __attribute__((const)) +unsigned __muldiv64u(unsigned val, unsigned mult, unsigned div) +{ + unsigned result; + + asm("mulu %2,%0 \n" /* MDR:val = val*mult */ + "divu %3,%0 \n" /* val = MDR:val/div; + * MDR = MDR:val%div */ + : "=r"(result) + : "0"(val), "ir"(mult), "r"(div) + ); + + return result; +} + +/* + * do a signed 32-bit multiply and divide with intermediate 64-bit product so + * as not to lose accuracy + * - we use the MDR register to hold the MSW of the product + */ +static inline __attribute__((const)) +signed __muldiv64s(signed val, signed mult, signed div) +{ + signed result; + + asm("mul %2,%0 \n" /* MDR:val = val*mult */ + "div %3,%0 \n" /* val = MDR:val/div; + * MDR = MDR:val%div */ + : "=r"(result) + : "0"(val), "ir"(mult), "r"(div) + ); + + return result; +} + +extern __attribute__((const)) +uint64_t div64_64(uint64_t dividend, uint64_t divisor); + +#endif /* _ASM_DIV64 */ diff --git a/include/asm-mn10300/dma-mapping.h b/include/asm-mn10300/dma-mapping.h new file mode 100644 index 00000000000..7c882fca9ec --- /dev/null +++ b/include/asm-mn10300/dma-mapping.h @@ -0,0 +1,234 @@ +/* DMA mapping routines for the MN10300 arch + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_DMA_MAPPING_H +#define _ASM_DMA_MAPPING_H + +#include <linux/mm.h> +#include <linux/scatterlist.h> + +#include <asm/cache.h> +#include <asm/io.h> + +extern void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, int flag); + +extern void dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle); + +#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent((d), (s), (h), (f)) +#define dma_free_noncoherent(d, s, v, h) dma_free_coherent((d), (s), (v), (h)) + +/* + * Map a single buffer of the indicated size for DMA in streaming mode. The + * 32-bit bus address to use is returned. + * + * Once the device is given the dma address, the device owns this memory until + * either pci_unmap_single or pci_dma_sync_single is performed. + */ +static inline +dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); + mn10300_dcache_flush_inv(); + return virt_to_bus(ptr); +} + +/* + * Unmap a single streaming mode DMA translation. The dma_addr and size must + * match what was provided for in a previous pci_map_single call. All other + * usages are undefined. + * + * After this call, reads by the cpu to the buffer are guarenteed to see + * whatever the device wrote there. + */ +static inline +void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); +} + +/* + * Map a set of buffers described by scatterlist in streaming mode for DMA. + * This is the scather-gather version of the above pci_map_single interface. + * Here the scatter gather list elements are each tagged with the appropriate + * dma address and length. They are obtained via sg_dma_{address,length}(SG). + * + * NOTE: An implementation may be able to use a smaller number of DMA + * address/length pairs than there are SG table elements. (for example + * via virtual mapping capabilities) The routine returns the number of + * addr/length pairs actually used, at most nents. + * + * Device ownership issues as mentioned above for pci_map_single are the same + * here. + */ +static inline +int dma_map_sg(struct device *dev, struct scatterlist *sglist, int nents, + enum dma_data_direction direction) +{ + struct scatterlist *sg; + int i; + + BUG_ON(!valid_dma_direction(direction)); + WARN_ON(nents == 0 || sglist[0].length == 0); + + for_each_sg(sglist, sg, nents, i) { + BUG_ON(!sg_page(sg)); + + sg->dma_address = sg_phys(sg); + } + + mn10300_dcache_flush_inv(); + return nents; +} + +/* + * Unmap a set of streaming mode DMA translations. + * Again, cpu read rules concerning calls here are the same as for + * pci_unmap_single() above. + */ +static inline +void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, + enum dma_data_direction direction) +{ + BUG_ON(!valid_dma_direction(direction)); +} + +/* + * pci_{map,unmap}_single_page maps a kernel page to a dma_addr_t. identical + * to pci_map_single, but takes a struct page instead of a virtual address + */ +static inline +dma_addr_t dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); + return page_to_bus(page) + offset; +} + +static inline +void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); +} + +/* + * Make physical memory consistent for a single streaming mode DMA translation + * after a transfer. + * + * If you perform a pci_map_single() but wish to interrogate the buffer using + * the cpu, yet do not wish to teardown the PCI dma mapping, you must call this + * function before doing so. At the next point you give the PCI dma address + * back to the card, the device again owns the buffer. + */ +static inline +void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, + size_t size, enum dma_data_direction direction) +{ +} + +static inline +void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, + size_t size, enum dma_data_direction direction) +{ + mn10300_dcache_flush_inv(); +} + +static inline +void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, + unsigned long offset, size_t size, + enum dma_data_direction direction) +{ +} + +static inline void +dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, + unsigned long offset, size_t size, + enum dma_data_direction direction) +{ + mn10300_dcache_flush_inv(); +} + + +/* + * Make physical memory consistent for a set of streaming mode DMA translations + * after a transfer. + * + * The same as pci_dma_sync_single but for a scatter-gather list, same rules + * and usage. + */ +static inline +void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, + int nelems, enum dma_data_direction direction) +{ +} + +static inline +void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, + int nelems, enum dma_data_direction direction) +{ + mn10300_dcache_flush_inv(); +} + +static inline +int dma_mapping_error(dma_addr_t dma_addr) +{ + return 0; +} + +/* + * Return whether the given PCI device DMA address mask can be supported + * properly. For example, if your device can only drive the low 24-bits during + * PCI bus mastering, then you would pass 0x00ffffff as the mask to this + * function. + */ +static inline +int dma_supported(struct device *dev, u64 mask) +{ + /* + * we fall back to GFP_DMA when the mask isn't all 1s, so we can't + * guarantee allocations that must be within a tighter range than + * GFP_DMA + */ + if (mask < 0x00ffffff) + return 0; + return 1; +} + +static inline +int dma_set_mask(struct device *dev, u64 mask) +{ + if (!dev->dma_mask || !dma_supported(dev, mask)) + return -EIO; + + *dev->dma_mask = mask; + return 0; +} + +static inline +int dma_get_cache_alignment(void) +{ + return 1 << L1_CACHE_SHIFT; +} + +#define dma_is_consistent(d) (1) + +static inline +void dma_cache_sync(void *vaddr, size_t size, + enum dma_data_direction direction) +{ + mn10300_dcache_flush_inv(); +} + +#endif diff --git a/include/asm-mn10300/dma.h b/include/asm-mn10300/dma.h new file mode 100644 index 00000000000..098df2e617a --- /dev/null +++ b/include/asm-mn10300/dma.h @@ -0,0 +1,118 @@ +/* MN10300 ISA DMA handlers and definitions + * + * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_DMA_H +#define _ASM_DMA_H + +#include <asm/system.h> +#include <linux/spinlock.h> +#include <asm/io.h> +#include <linux/delay.h> + +#undef MAX_DMA_CHANNELS /* switch off linux/kernel/dma.c */ +#define MAX_DMA_ADDRESS 0xbfffffff + +extern spinlock_t dma_spin_lock; + +static inline unsigned long claim_dma_lock(void) +{ + unsigned long flags; + spin_lock_irqsave(&dma_spin_lock, flags); + return flags; +} + +static inline void release_dma_lock(unsigned long flags) +{ + spin_unlock_irqrestore(&dma_spin_lock, flags); +} + +/* enable/disable a specific DMA channel */ +static inline void enable_dma(unsigned int dmanr) +{ +} + +static inline void disable_dma(unsigned int dmanr) +{ +} + +/* Clear the 'DMA Pointer Flip Flop'. + * Write 0 for LSB/MSB, 1 for MSB/LSB access. + * Use this once to initialize the FF to a known state. + * After that, keep track of it. :-) + * --- In order to do that, the DMA routines below should --- + * --- only be used while holding the DMA lock ! --- + */ +static inline void clear_dma_ff(unsigned int dmanr) +{ +} + +/* set mode (above) for a specific DMA channel */ +static inline void set_dma_mode(unsigned int dmanr, char mode) +{ +} + +/* Set only the page register bits of the transfer address. + * This is used for successive transfers when we know the contents of + * the lower 16 bits of the DMA current address register, but a 64k boundary + * may have been crossed. + */ +static inline void set_dma_page(unsigned int dmanr, char pagenr) +{ +} + + +/* Set transfer address & page bits for specific DMA channel. + * Assumes dma flipflop is clear. + */ +static inline void set_dma_addr(unsigned int dmanr, unsigned int a) +{ +} + + +/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for + * a specific DMA channel. + * You must ensure the parameters are valid. + * NOTE: from a manual: "the number of transfers is one more + * than the initial word count"! This is taken into account. + * Assumes dma flip-flop is clear. + * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. + */ +static inline void set_dma_count(unsigned int dmanr, unsigned int count) +{ +} + + +/* Get DMA residue count. After a DMA transfer, this + * should return zero. Reading this while a DMA transfer is + * still in progress will return unpredictable results. + * If called before the channel has been used, it may return 1. + * Otherwise, it returns the number of _bytes_ left to transfer. + * + * Assumes DMA flip-flop is clear. + */ +static inline int get_dma_residue(unsigned int dmanr) +{ + return 0; +} + + +/* These are in kernel/dma.c: */ +extern int request_dma(unsigned int dmanr, const char *device_id); +extern void free_dma(unsigned int dmanr); + +/* From PCI */ + +#ifdef CONFIG_PCI +extern int isa_dma_bridge_buggy; +#else +#define isa_dma_bridge_buggy (0) +#endif + +#endif /* _ASM_DMA_H */ diff --git a/include/asm-mn10300/dmactl-regs.h b/include/asm-mn10300/dmactl-regs.h new file mode 100644 index 00000000000..58a199da0f4 --- /dev/null +++ b/include/asm-mn10300/dmactl-regs.h @@ -0,0 +1,101 @@ +/* MN10300 on-board DMA controller registers + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_DMACTL_REGS_H +#define _ASM_DMACTL_REGS_H + +#include <asm/cpu-regs.h> + +#ifdef __KERNEL__ + +/* DMA registers */ +#define DMxCTR(N) __SYSREG(0xd2000000 + ((N) * 0x100), u32) /* control reg */ +#define DMxCTR_BG 0x0000001f /* transfer request source */ +#define DMxCTR_BG_SOFT 0x00000000 /* - software source */ +#define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */ +#define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */ +#define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */ +#define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */ +#define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */ +#define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */ +#define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */ +#define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */ +#define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */ +#define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */ +#define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */ +#define DMxCTR_BG_AFE 0x0000000d /* - analogue front-end interrupt source */ +#define DMxCTR_BG_ADC 0x0000000e /* - A/D conversion end interrupt source */ +#define DMxCTR_BG_IRDA 0x0000000f /* - IrDA interrupt source */ +#define DMxCTR_BG_RTC 0x00000010 /* - RTC interrupt source */ +#define DMxCTR_BG_XIRQ0 0x00000011 /* - XIRQ0 pin interrupt source */ +#define DMxCTR_BG_XIRQ1 0x00000012 /* - XIRQ1 pin interrupt source */ +#define DMxCTR_BG_XDMR0 0x00000013 /* - external request 0 source (XDMR0 pin) */ +#define DMxCTR_BG_XDMR1 0x00000014 /* - external request 1 source (XDMR1 pin) */ +#define DMxCTR_SAM 0x000000e0 /* DMA transfer src addr mode */ +#define DMxCTR_SAM_INCR 0x00000000 /* - increment */ +#define DMxCTR_SAM_DECR 0x00000020 /* - decrement */ +#define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */ +#define DMxCTR_DAM 0x00000000 /* DMA transfer dest addr mode */ +#define DMxCTR_DAM_INCR 0x00000000 /* - increment */ +#define DMxCTR_DAM_DECR 0x00000100 /* - decrement */ +#define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */ +#define DMxCTR_TM 0x00001800 /* DMA transfer mode */ +#define DMxCTR_TM_BATCH 0x00000000 /* - batch transfer */ +#define DMxCTR_TM_INTERM 0x00001000 /* - intermittent transfer */ +#define DMxCTR_UT 0x00006000 /* DMA transfer unit */ +#define DMxCTR_UT_1 0x00000000 /* - 1 byte */ +#define DMxCTR_UT_2 0x00002000 /* - 2 byte */ +#define DMxCTR_UT_4 0x00004000 /* - 4 byte */ +#define DMxCTR_UT_16 0x00006000 /* - 16 byte */ +#define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */ +#define DMxCTR_RQM 0x00060000 /* external request input source mode */ +#define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */ +#define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */ +#define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */ +#define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */ +#define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */ +#define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */ + +#define DMxSRC(N) __SYSREG(0xd2000004 + ((N) * 0x100), u32) /* control reg */ + +#define DMxDST(N) __SYSREG(0xd2000008 + ((N) * 0x100), u32) /* src addr reg */ + +#define DMxSIZ(N) __SYSREG(0xd200000c + ((N) * 0x100), u32) /* dest addr reg */ +#define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */ + +#define DMxCYC(N) __SYSREG(0xd2000010 + ((N) * 0x100), u32) /* intermittent + * size reg */ +#define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */ + +#define DM0IRQ 16 /* DMA channel 0 complete IRQ */ +#define DM1IRQ 17 /* DMA channel 1 complete IRQ */ +#define DM2IRQ 18 /* DMA channel 2 complete IRQ */ +#define DM3IRQ 19 /* DMA channel 3 complete IRQ */ + +#define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */ +#define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */ +#define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */ +#define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */ + +#ifndef __ASSEMBLY__ + +struct mn10300_dmactl_regs { + u32 ctr; + const void *src; + void *dst; + u32 siz; + u32 cyc; +} __attribute__((aligned(0x100))); + +#endif /* __ASSEMBLY__ */ + +#endif /* __KERNEL__ */ + +#endif /* _ASM_DMACTL_REGS_H */ diff --git a/include/asm-mn10300/elf.h b/include/asm-mn10300/elf.h new file mode 100644 index 00000000000..256a70466ca --- /dev/null +++ b/include/asm-mn10300/elf.h @@ -0,0 +1,147 @@ +/* MN10300 ELF constant and register definitions + * + * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_ELF_H +#define _ASM_ELF_H + +#include <linux/utsname.h> +#include <asm/ptrace.h> +#include <asm/user.h> + +/* + * AM33 relocations + */ +#define R_MN10300_NONE 0 /* No reloc. */ +#define R_MN10300_32 1 /* Direct 32 bit. */ +#define R_MN10300_16 2 /* Direct 16 bit. */ +#define R_MN10300_8 3 /* Direct 8 bit. */ +#define R_MN10300_PCREL32 4 /* PC-relative 32-bit. */ +#define R_MN10300_PCREL16 5 /* PC-relative 16-bit signed. */ +#define R_MN10300_PCREL8 6 /* PC-relative 8-bit signed. */ +#define R_MN10300_24 9 /* Direct 24 bit. */ +#define R_MN10300_RELATIVE 23 /* Adjust by program base. */ + +/* + * ELF register definitions.. + */ +typedef unsigned long elf_greg_t; + +#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +#define ELF_NFPREG 32 +typedef float elf_fpreg_t; + +typedef struct { + elf_fpreg_t fpregs[ELF_NFPREG]; + u_int32_t fpcr; +} elf_fpregset_t; + +extern int dump_fpu(struct pt_regs *, elf_fpregset_t *); + +/* + * This is used to ensure we don't load something for the wrong architecture + */ +#define elf_check_arch(x) \ + (((x)->e_machine == EM_CYGNUS_MN10300) || \ + ((x)->e_machine == EM_MN10300)) + +/* + * These are used to set parameters in the core dumps. + */ +#define ELF_CLASS ELFCLASS32 +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_MN10300 + +/* + * ELF process initialiser + */ +#define ELF_PLAT_INIT(_r, load_addr) \ +do { \ + struct pt_regs *_ur = current->thread.uregs; \ + _ur->a3 = 0; _ur->a2 = 0; _ur->d3 = 0; _ur->d2 = 0; \ + _ur->mcvf = 0; _ur->mcrl = 0; _ur->mcrh = 0; _ur->mdrq = 0; \ + _ur->e1 = 0; _ur->e0 = 0; _ur->e7 = 0; _ur->e6 = 0; \ + _ur->e5 = 0; _ur->e4 = 0; _ur->e3 = 0; _ur->e2 = 0; \ + _ur->lar = 0; _ur->lir = 0; _ur->mdr = 0; \ + _ur->a1 = 0; _ur->a0 = 0; _ur->d1 = 0; _ur->d0 = 0; \ +} while (0) + +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 + +/* + * This is the location that an ET_DYN program is loaded if exec'ed. Typical + * use of this is to invoke "./ld.so someprog" to test out a new version of + * the loader. We need to make sure that it is out of the way of the program + * that it will "exec", and that there is sufficient room for the brk. + * - must clear the VMALLOC area + */ +#define ELF_ET_DYN_BASE 0x04000000 + +/* + * regs is struct pt_regs, pr_reg is elf_gregset_t (which is + * now struct user_regs, they are different) + * - ELF_CORE_COPY_REGS has been guessed, and may be wrong + */ +#define ELF_CORE_COPY_REGS(pr_reg, regs) \ +do { \ + pr_reg[0] = regs->a3; \ + pr_reg[1] = regs->a2; \ + pr_reg[2] = regs->d3; \ + pr_reg[3] = regs->d2; \ + pr_reg[4] = regs->mcvf; \ + pr_reg[5] = regs->mcrl; \ + pr_reg[6] = regs->mcrh; \ + pr_reg[7] = regs->mdrq; \ + pr_reg[8] = regs->e1; \ + pr_reg[9] = regs->e0; \ + pr_reg[10] = regs->e7; \ + pr_reg[11] = regs->e6; \ + pr_reg[12] = regs->e5; \ + pr_reg[13] = regs->e4; \ + pr_reg[14] = regs->e3; \ + pr_reg[15] = regs->e2; \ + pr_reg[16] = regs->sp; \ + pr_reg[17] = regs->lar; \ + pr_reg[18] = regs->lir; \ + pr_reg[19] = regs->mdr; \ + pr_reg[20] = regs->a1; \ + pr_reg[21] = regs->a0; \ + pr_reg[22] = regs->d1; \ + pr_reg[23] = regs->d0; \ + pr_reg[24] = regs->orig_d0; \ + pr_reg[25] = regs->epsw; \ + pr_reg[26] = regs->pc; \ +} while (0); + +/* + * This yields a mask that user programs can use to figure out what + * instruction set this CPU supports. This could be done in user space, + * but it's not easy, and we've already done it here. + */ +#define ELF_HWCAP (0) + +/* + * This yields a string that ld.so will use to load implementation + * specific libraries for optimization. This is more specific in + * intent than poking at uname or /proc/cpuinfo. + * + * For the moment, we have only optimizations for the Intel generations, + * but that could change... + */ +#define ELF_PLATFORM (NULL) + +#ifdef __KERNEL__ +#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX) +#endif + +#endif /* _ASM_ELF_H */ diff --git a/include/asm-mn10300/emergency-restart.h b/include/asm-mn10300/emergency-restart.h new file mode 100644 index 00000000000..3711bd9d50b --- /dev/null +++ b/include/asm-mn10300/emergency-restart.h @@ -0,0 +1 @@ +#include <asm-generic/emergency-restart.h> diff --git a/include/asm-mn10300/errno.h b/include/asm-mn10300/errno.h new file mode 100644 index 00000000000..4c82b503d92 --- /dev/null +++ b/include/asm-mn10300/errno.h @@ -0,0 +1 @@ +#include <asm-generic/errno.h> diff --git a/include/asm-mn10300/exceptions.h b/include/asm-mn10300/exceptions.h new file mode 100644 index 00000000000..fa16466ef3f --- /dev/null +++ b/include/asm-mn10300/exceptions.h @@ -0,0 +1,121 @@ +/* MN10300 Microcontroller core exceptions + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_EXCEPTIONS_H +#define _ASM_EXCEPTIONS_H + +#include <linux/linkage.h> + +/* + * define the breakpoint instruction opcode to use + * - note that the JTAG unit steals 0xFF, so we want to avoid that if we can + * (can use 0xF7) + */ +#define GDBSTUB_BKPT 0xFF + +#ifndef __ASSEMBLY__ + +/* + * enumeration of exception codes (as extracted from TBR MSW) + */ +enum exception_code { + EXCEP_RESET = 0x000000, /* reset */ + + /* MMU exceptions */ + EXCEP_ITLBMISS = 0x000100, /* instruction TLB miss */ + EXCEP_DTLBMISS = 0x000108, /* data TLB miss */ + EXCEP_IAERROR = 0x000110, /* instruction address */ + EXCEP_DAERROR = 0x000118, /* data address */ + + /* system exceptions */ + EXCEP_TRAP = 0x000128, /* program interrupt (PI instruction) */ + EXCEP_ISTEP = 0x000130, /* single step */ + EXCEP_IBREAK = 0x000150, /* instruction breakpoint */ + EXCEP_OBREAK = 0x000158, /* operand breakpoint */ + EXCEP_PRIVINS = 0x000160, /* privileged instruction execution */ + EXCEP_UNIMPINS = 0x000168, /* unimplemented instruction execution */ + EXCEP_UNIMPEXINS = 0x000170, /* unimplemented extended instruction execution */ + EXCEP_MEMERR = 0x000178, /* illegal memory access */ + EXCEP_MISALIGN = 0x000180, /* misalignment */ + EXCEP_BUSERROR = 0x000188, /* bus error */ + EXCEP_ILLINSACC = 0x000190, /* illegal instruction access */ + EXCEP_ILLDATACC = 0x000198, /* illegal data access */ + EXCEP_IOINSACC = 0x0001a0, /* I/O space instruction access */ + EXCEP_PRIVINSACC = 0x0001a8, /* privileged space instruction access */ + EXCEP_PRIVDATACC = 0x0001b0, /* privileged space data access */ + EXCEP_DATINSACC = 0x0001b8, /* data space instruction access */ + EXCEP_DOUBLE_FAULT = 0x000200, /* double fault */ + + /* FPU exceptions */ + EXCEP_FPU_DISABLED = 0x0001c0, /* FPU disabled */ + EXCEP_FPU_UNIMPINS = 0x0001c8, /* FPU unimplemented operation */ + EXCEP_FPU_OPERATION = 0x0001d0, /* FPU operation */ + + /* interrupts */ + EXCEP_WDT = 0x000240, /* watchdog timer overflow */ + EXCEP_NMI = 0x000248, /* non-maskable interrupt */ + EXCEP_IRQ_LEVEL0 = 0x000280, /* level 0 maskable interrupt */ + EXCEP_IRQ_LEVEL1 = 0x000288, /* level 1 maskable interrupt */ + EXCEP_IRQ_LEVEL2 = 0x000290, /* level 2 maskable interrupt */ + EXCEP_IRQ_LEVEL3 = 0x000298, /* level 3 maskable interrupt */ + EXCEP_IRQ_LEVEL4 = 0x0002a0, /* level 4 maskable interrupt */ + EXCEP_IRQ_LEVEL5 = 0x0002a8, /* level 5 maskable interrupt */ + EXCEP_IRQ_LEVEL6 = 0x0002b0, /* level 6 maskable interrupt */ + + /* system calls */ + EXCEP_SYSCALL0 = 0x000300, /* system call 0 */ + EXCEP_SYSCALL1 = 0x000308, /* system call 1 */ + EXCEP_SYSCALL2 = 0x000310, /* system call 2 */ + EXCEP_SYSCALL3 = 0x000318, /* system call 3 */ + EXCEP_SYSCALL4 = 0x000320, /* system call 4 */ + EXCEP_SYSCALL5 = 0x000328, /* system call 5 */ + EXCEP_SYSCALL6 = 0x000330, /* system call 6 */ + EXCEP_SYSCALL7 = 0x000338, /* system call 7 */ + EXCEP_SYSCALL8 = 0x000340, /* system call 8 */ + EXCEP_SYSCALL9 = 0x000348, /* system call 9 */ + EXCEP_SYSCALL10 = 0x000350, /* system call 10 */ + EXCEP_SYSCALL11 = 0x000358, /* system call 11 */ + EXCEP_SYSCALL12 = 0x000360, /* system call 12 */ + EXCEP_SYSCALL13 = 0x000368, /* system call 13 */ + EXCEP_SYSCALL14 = 0x000370, /* system call 14 */ + EXCEP_SYSCALL15 = 0x000378, /* system call 15 */ +}; + +extern void __set_intr_stub(enum exception_code code, void *handler); +extern void set_intr_stub(enum exception_code code, void *handler); +extern void set_jtag_stub(enum exception_code code, void *handler); + +struct pt_regs; + +extern asmlinkage void __common_exception(void); +extern asmlinkage void itlb_miss(void); +extern asmlinkage void dtlb_miss(void); +extern asmlinkage void itlb_aerror(void); +extern asmlinkage void dtlb_aerror(void); +extern asmlinkage void raw_bus_error(void); +extern asmlinkage void double_fault(void); +extern asmlinkage int system_call(struct pt_regs *); +extern asmlinkage void fpu_exception(struct pt_regs *, enum exception_code); +extern asmlinkage void nmi(struct pt_regs *, enum exception_code); +extern asmlinkage void uninitialised_exception(struct pt_regs *, + enum exception_code); +extern asmlinkage void irq_handler(void); +extern asmlinkage void profile_handler(void); +extern asmlinkage void nmi_handler(void); +extern asmlinkage void misalignment(struct pt_regs *, enum exception_code); + +extern void die(const char *, struct pt_regs *, enum exception_code) + ATTRIB_NORET; + +extern int die_if_no_fixup(const char *, struct pt_regs *, enum exception_code); + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_EXCEPTIONS_H */ diff --git a/include/asm-mn10300/fb.h b/include/asm-mn10300/fb.h new file mode 100644 index 00000000000..697b24a91e1 --- /dev/null +++ b/include/asm-mn10300/fb.h @@ -0,0 +1,23 @@ +/* MN10300 Frame buffer stuff + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_FB_H +#define _ASM_FB_H + +#include <linux/fb.h> + +#define fb_pgprotect(...) do {} while (0) + +static inline int fb_is_primary_device(struct fb_info *info) +{ + return 0; +} + +#endif /* _ASM_FB_H */ diff --git a/include/asm-mn10300/fcntl.h b/include/asm-mn10300/fcntl.h new file mode 100644 index 00000000000..46ab12db573 --- /dev/null +++ b/include/asm-mn10300/fcntl.h @@ -0,0 +1 @@ +#include <asm-generic/fcntl.h> diff --git a/include/asm-mn10300/fpu.h b/include/asm-mn10300/fpu.h new file mode 100644 index 00000000000..64a2b83a7a6 --- /dev/null +++ b/include/asm-mn10300/fpu.h @@ -0,0 +1,85 @@ +/* MN10300 FPU definitions + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * Derived from include/asm-i386/i387.h: Copyright (C) 1994 Linus Torvalds + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_FPU_H +#define _ASM_FPU_H + +#include <asm/processor.h> +#include <asm/sigcontext.h> +#include <asm/user.h> + +#ifdef __KERNEL__ + +/* the task that owns the FPU state */ +extern struct task_struct *fpu_state_owner; + +#define set_using_fpu(tsk) \ +do { \ + (tsk)->thread.fpu_flags |= THREAD_USING_FPU; \ +} while (0) + +#define clear_using_fpu(tsk) \ +do { \ + (tsk)->thread.fpu_flags &= ~THREAD_USING_FPU; \ +} while (0) + +#define is_using_fpu(tsk) ((tsk)->thread.fpu_flags & THREAD_USING_FPU) + +#define unlazy_fpu(tsk) \ +do { \ + preempt_disable(); \ + if (fpu_state_owner == (tsk)) \ + fpu_save(&tsk->thread.fpu_state); \ + preempt_enable(); \ +} while (0) + +#define exit_fpu() \ +do { \ + struct task_struct *__tsk = current; \ + preempt_disable(); \ + if (fpu_state_owner == __tsk) \ + fpu_state_owner = NULL; \ + preempt_enable(); \ +} while (0) + +#define flush_fpu() \ +do { \ + struct task_struct *__tsk = current; \ + preempt_disable(); \ + if (fpu_state_owner == __tsk) { \ + fpu_state_owner = NULL; \ + __tsk->thread.uregs->epsw &= ~EPSW_FE; \ + } \ + preempt_enable(); \ + clear_using_fpu(__tsk); \ +} while (0) + +extern asmlinkage void fpu_init_state(void); +extern asmlinkage void fpu_kill_state(struct task_struct *); +extern asmlinkage void fpu_disabled(struct pt_regs *, enum exception_code); +extern asmlinkage void fpu_exception(struct pt_regs *, enum exception_code); + +#ifdef CONFIG_FPU +extern asmlinkage void fpu_save(struct fpu_state_struct *); +extern asmlinkage void fpu_restore(struct fpu_state_struct *); +#else +#define fpu_save(a) +#define fpu_restore(a) +#endif /* CONFIG_FPU */ + +/* + * signal frame handlers + */ +extern int fpu_setup_sigcontext(struct fpucontext *buf); +extern int fpu_restore_sigcontext(struct fpucontext *buf); + +#endif /* __KERNEL__ */ +#endif /* _ASM_FPU_H */ diff --git a/include/asm-mn10300/frame.inc b/include/asm-mn10300/frame.inc new file mode 100644 index 00000000000..5b1949bdf03 --- /dev/null +++ b/include/asm-mn10300/frame.inc @@ -0,0 +1,91 @@ +/* MN10300 Microcontroller core system register definitions -*- asm -*- + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_FRAME_INC +#define _ASM_FRAME_INC + +#ifndef __ASSEMBLY__ +#error not for use in C files +#endif + +#ifndef __ASM_OFFSETS_H__ +#include <asm/asm-offsets.h> +#endif + +#define pi break + +#define fp a3 + +############################################################################### +# +# build a stack frame from the registers +# - the caller has subtracted 4 from SP before coming here +# +############################################################################### +.macro SAVE_ALL + add -4,sp # next exception frame ptr save area + movm [other],(sp) + mov usp,a1 + mov a1,(sp) # USP in MOVM[other] dummy slot + movm [d2,d3,a2,a3,exreg0,exreg1,exother],(sp) + mov sp,fp # FRAME pointer in A3 + add -12,sp # allow for calls to be made + mov (__frame),a1 + mov a1,(REG_NEXT,fp) + mov fp,(__frame) + + and ~EPSW_FE,epsw # disable the FPU inside the kernel + + # we may be holding current in E2 +#ifdef CONFIG_MN10300_CURRENT_IN_E2 + mov (__current),e2 +#endif +.endm + +############################################################################### +# +# restore the registers from a stack frame +# +############################################################################### +.macro RESTORE_ALL + # peel back the stack to the calling frame + # - this permits execve() to discard extra frames due to kernel syscalls + mov (__frame),fp + mov fp,sp + mov (REG_NEXT,fp),d0 # userspace has regs->next == 0 + mov d0,(__frame) + +#ifndef CONFIG_MN10300_USING_JTAG + mov (REG_EPSW,fp),d0 + btst EPSW_T,d0 + beq 99f + + or EPSW_NMID,epsw + movhu (DCR),d1 + or 0x0001, d1 + movhu d1,(DCR) + +99: +#endif + movm (sp),[d2,d3,a2,a3,exreg0,exreg1,exother] + + # must restore usp even if returning to kernel space, + # when CONFIG_PREEMPT is enabled. + mov (sp),a1 # USP in MOVM[other] dummy slot + mov a1,usp + + movm (sp),[other] + add 8,sp + rti + +.endm + + +#endif /* _ASM_FRAME_INC */ diff --git a/include/asm-mn10300/futex.h b/include/asm-mn10300/futex.h new file mode 100644 index 00000000000..0b745828f42 --- /dev/null +++ b/include/asm-mn10300/futex.h @@ -0,0 +1 @@ +#include <asm-generic/futex.h> diff --git a/include/asm-mn10300/gdb-stub.h b/include/asm-mn10300/gdb-stub.h new file mode 100644 index 00000000000..e5a6368559a --- /dev/null +++ b/include/asm-mn10300/gdb-stub.h @@ -0,0 +1,183 @@ +/* MN10300 Kernel GDB stub definitions + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * - Derived from asm-mips/gdb-stub.h (c) 1995 Andreas Busse + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_GDB_STUB_H +#define _ASM_GDB_STUB_H + +#include <asm/exceptions.h> + +/* + * register ID numbers in GDB remote protocol + */ + +#define GDB_REGID_PC 9 +#define GDB_REGID_FP 7 +#define GDB_REGID_SP 8 + +/* + * virtual stack layout for the GDB exception handler + */ +#define NUMREGS 64 + +#define GDB_FR_D0 (0 * 4) +#define GDB_FR_D1 (1 * 4) +#define GDB_FR_D2 (2 * 4) +#define GDB_FR_D3 (3 * 4) +#define GDB_FR_A0 (4 * 4) +#define GDB_FR_A1 (5 * 4) +#define GDB_FR_A2 (6 * 4) +#define GDB_FR_A3 (7 * 4) + +#define GDB_FR_SP (8 * 4) +#define GDB_FR_PC (9 * 4) +#define GDB_FR_MDR (10 * 4) +#define GDB_FR_EPSW (11 * 4) +#define GDB_FR_LIR (12 * 4) +#define GDB_FR_LAR (13 * 4) +#define GDB_FR_MDRQ (14 * 4) + +#define GDB_FR_E0 (15 * 4) +#define GDB_FR_E1 (16 * 4) +#define GDB_FR_E2 (17 * 4) +#define GDB_FR_E3 (18 * 4) +#define GDB_FR_E4 (19 * 4) +#define GDB_FR_E5 (20 * 4) +#define GDB_FR_E6 (21 * 4) +#define GDB_FR_E7 (22 * 4) + +#define GDB_FR_SSP (23 * 4) +#define GDB_FR_MSP (24 * 4) +#define GDB_FR_USP (25 * 4) +#define GDB_FR_MCRH (26 * 4) +#define GDB_FR_MCRL (27 * 4) +#define GDB_FR_MCVF (28 * 4) + +#define GDB_FR_FPCR (29 * 4) +#define GDB_FR_DUMMY0 (30 * 4) +#define GDB_FR_DUMMY1 (31 * 4) + +#define GDB_FR_FS0 (32 * 4) + +#define GDB_FR_SIZE (NUMREGS * 4) + +#ifndef __ASSEMBLY__ + +/* + * This is the same as above, but for the high-level + * part of the GDB stub. + */ + +struct gdb_regs { + /* saved main processor registers */ + u32 d0, d1, d2, d3, a0, a1, a2, a3; + u32 sp, pc, mdr, epsw, lir, lar, mdrq; + u32 e0, e1, e2, e3, e4, e5, e6, e7; + u32 ssp, msp, usp, mcrh, mcrl, mcvf; + + /* saved floating point registers */ + u32 fpcr, _dummy0, _dummy1; + u32 fs0, fs1, fs2, fs3, fs4, fs5, fs6, fs7; + u32 fs8, fs9, fs10, fs11, fs12, fs13, fs14, fs15; + u32 fs16, fs17, fs18, fs19, fs20, fs21, fs22, fs23; + u32 fs24, fs25, fs26, fs27, fs28, fs29, fs30, fs31; +}; + +/* + * Prototypes + */ +extern void show_registers_only(struct pt_regs *regs); + +extern asmlinkage void gdbstub_init(void); +extern asmlinkage void gdbstub_exit(int status); +extern asmlinkage void gdbstub_io_init(void); +extern asmlinkage void gdbstub_io_set_baud(unsigned baud); +extern asmlinkage int gdbstub_io_rx_char(unsigned char *_ch, int nonblock); +extern asmlinkage void gdbstub_io_tx_char(unsigned char ch); +extern asmlinkage void gdbstub_io_tx_flush(void); + +extern asmlinkage void gdbstub_io_rx_handler(void); +extern asmlinkage void gdbstub_rx_irq(struct pt_regs *, enum exception_code); +extern asmlinkage int gdbstub_intercept(struct pt_regs *, enum exception_code); +extern asmlinkage void gdbstub_exception(struct pt_regs *, enum exception_code); +extern asmlinkage void __gdbstub_bug_trap(void); +extern asmlinkage void __gdbstub_pause(void); +extern asmlinkage void start_kernel(void); + +#ifndef CONFIG_MN10300_CACHE_DISABLED +extern asmlinkage void gdbstub_purge_cache(void); +#else +#define gdbstub_purge_cache() do {} while (0) +#endif + +/* Used to prevent crashes in memory access */ +extern asmlinkage int gdbstub_read_byte(const u8 *, u8 *); +extern asmlinkage int gdbstub_read_word(const u8 *, u8 *); +extern asmlinkage int gdbstub_read_dword(const u8 *, u8 *); +extern asmlinkage int gdbstub_write_byte(u32, u8 *); +extern asmlinkage int gdbstub_write_word(u32, u8 *); +extern asmlinkage int gdbstub_write_dword(u32, u8 *); + +extern asmlinkage void gdbstub_read_byte_guard(void); +extern asmlinkage void gdbstub_read_byte_cont(void); +extern asmlinkage void gdbstub_read_word_guard(void); +extern asmlinkage void gdbstub_read_word_cont(void); +extern asmlinkage void gdbstub_read_dword_guard(void); +extern asmlinkage void gdbstub_read_dword_cont(void); +extern asmlinkage void gdbstub_write_byte_guard(void); +extern asmlinkage void gdbstub_write_byte_cont(void); +extern asmlinkage void gdbstub_write_word_guard(void); +extern asmlinkage void gdbstub_write_word_cont(void); +extern asmlinkage void gdbstub_write_dword_guard(void); +extern asmlinkage void gdbstub_write_dword_cont(void); + +extern u8 gdbstub_rx_buffer[PAGE_SIZE]; +extern u32 gdbstub_rx_inp; +extern u32 gdbstub_rx_outp; +extern u8 gdbstub_rx_overflow; +extern u8 gdbstub_busy; +extern u8 gdbstub_rx_unget; + +#ifdef CONFIG_GDBSTUB_DEBUGGING +extern void gdbstub_printk(const char *fmt, ...) + __attribute__((format(printf, 1, 2))); +#else +static inline __attribute__((format(printf, 1, 2))) +void gdbstub_printk(const char *fmt, ...) +{ +} +#endif + +#ifdef CONFIG_GDBSTUB_DEBUG_ENTRY +#define gdbstub_entry(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__) +#else +#define gdbstub_entry(FMT, ...) ({ 0; }) +#endif + +#ifdef CONFIG_GDBSTUB_DEBUG_PROTOCOL +#define gdbstub_proto(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__) +#else +#define gdbstub_proto(FMT, ...) ({ 0; }) +#endif + +#ifdef CONFIG_GDBSTUB_DEBUG_IO +#define gdbstub_io(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__) +#else +#define gdbstub_io(FMT, ...) ({ 0; }) +#endif + +#ifdef CONFIG_GDBSTUB_DEBUG_BREAKPOINT +#define gdbstub_bkpt(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__) +#else +#define gdbstub_bkpt(FMT, ...) ({ 0; }) +#endif + +#endif /* !__ASSEMBLY__ */ +#endif /* _ASM_GDB_STUB_H */ diff --git a/include/asm-mn10300/hardirq.h b/include/asm-mn10300/hardirq.h new file mode 100644 index 00000000000..54d95011767 --- /dev/null +++ b/include/asm-mn10300/hardirq.h @@ -0,0 +1,48 @@ +/* MN10300 Hardware IRQ statistics and management + * + * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Modified by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_HARDIRQ_H +#define _ASM_HARDIRQ_H + +#include <linux/threads.h> +#include <linux/irq.h> +#include <asm/exceptions.h> + +/* assembly code in softirq.h is sensitive to the offsets of these fields */ +typedef struct { + unsigned int __softirq_pending; + unsigned long idle_timestamp; + unsigned int __nmi_count; /* arch dependent */ + unsigned int __irq_count; /* arch dependent */ +} ____cacheline_aligned irq_cpustat_t; + +#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ + +extern void ack_bad_irq(int irq); + +/* + * manipulate stubs in the MN10300 CPU Trap/Interrupt Vector table + * - these should jump to __common_exception in entry.S unless there's a good + * reason to do otherwise (see trap_preinit() in traps.c) + */ +typedef void (*intr_stub_fnx)(struct pt_regs *regs, + enum exception_code intcode); + +/* + * manipulate pointers in the Exception table (see entry.S) + * - these are indexed by decoding the lower 24 bits of the TBR register + * - note that the MN103E010 doesn't always trap through the correct vector, + * but does always set the TBR correctly + */ +extern asmlinkage void set_excp_vector(enum exception_code code, + intr_stub_fnx handler); + +#endif /* _ASM_HARDIRQ_H */ diff --git a/include/asm-mn10300/highmem.h b/include/asm-mn10300/highmem.h new file mode 100644 index 00000000000..383c0c42982 --- /dev/null +++ b/include/asm-mn10300/highmem.h @@ -0,0 +1,114 @@ +/* MN10300 Virtual kernel memory mappings for high memory + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * - Derived from include/asm-i386/highmem.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_HIGHMEM_H +#define _ASM_HIGHMEM_H + +#ifdef __KERNEL__ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <asm/kmap_types.h> +#include <asm/pgtable.h> + +/* undef for production */ +#undef HIGHMEM_DEBUG + +/* declarations for highmem.c */ +extern unsigned long highstart_pfn, highend_pfn; + +extern pte_t *kmap_pte; +extern pgprot_t kmap_prot; +extern pte_t *pkmap_page_table; + +extern void __init kmap_init(void); + +/* + * Right now we initialize only a single pte table. It can be extended + * easily, subsequent pte tables have to be allocated in one physical + * chunk of RAM. + */ +#define PKMAP_BASE 0xfe000000UL +#define LAST_PKMAP 1024 +#define LAST_PKMAP_MASK (LAST_PKMAP - 1) +#define PKMAP_NR(virt) ((virt - PKMAP_BASE) >> PAGE_SHIFT) +#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) + +extern unsigned long __fastcall kmap_high(struct page *page); +extern void __fastcall kunmap_high(struct page *page); + +static inline unsigned long kmap(struct page *page) +{ + if (in_interrupt()) + BUG(); + if (page < highmem_start_page) + return page_address(page); + return kmap_high(page); +} + +static inline void kunmap(struct page *page) +{ + if (in_interrupt()) + BUG(); + if (page < highmem_start_page) + return; + kunmap_high(page); +} + +/* + * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap + * gives a more generic (and caching) interface. But kmap_atomic can + * be used in IRQ contexts, so in some (very limited) cases we need + * it. + */ +static inline unsigned long kmap_atomic(struct page *page, enum km_type type) +{ + enum fixed_addresses idx; + unsigned long vaddr; + + if (page < highmem_start_page) + return page_address(page); + + idx = type + KM_TYPE_NR * smp_processor_id(); + vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); +#if HIGHMEM_DEBUG + if (!pte_none(*(kmap_pte - idx))) + BUG(); +#endif + set_pte(kmap_pte - idx, mk_pte(page, kmap_prot)); + __flush_tlb_one(vaddr); + + return vaddr; +} + +static inline void kunmap_atomic(unsigned long vaddr, enum km_type type) +{ +#if HIGHMEM_DEBUG + enum fixed_addresses idx = type + KM_TYPE_NR * smp_processor_id(); + + if (vaddr < FIXADDR_START) /* FIXME */ + return; + + if (vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)) + BUG(); + + /* + * force other mappings to Oops if they'll try to access + * this pte without first remap it + */ + pte_clear(kmap_pte - idx); + __flush_tlb_one(vaddr); +#endif +} + +#endif /* __KERNEL__ */ + +#endif /* _ASM_HIGHMEM_H */ diff --git a/include/asm-mn10300/hw_irq.h b/include/asm-mn10300/hw_irq.h new file mode 100644 index 00000000000..70619901098 --- /dev/null +++ b/include/asm-mn10300/hw_irq.h @@ -0,0 +1,14 @@ +/* MN10300 Hardware interrupt definitions + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_HW_IRQ_H +#define _ASM_HW_IRQ_H + +#endif /* _ASM_HW_IRQ_H */ diff --git a/include/asm-mn10300/ide.h b/include/asm-mn10300/ide.h new file mode 100644 index 00000000000..dc235121ec4 --- /dev/null +++ b/include/asm-mn10300/ide.h @@ -0,0 +1,43 @@ +/* MN10300 Arch-specific IDE code + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * - Derived from include/asm-i386/ide.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_IDE_H +#define _ASM_IDE_H + +#ifdef __KERNEL__ + +#include <asm/intctl-regs.h> + +#undef SUPPORT_SLOW_DATA_PORTS +#define SUPPORT_SLOW_DATA_PORTS 0 + +#undef SUPPORT_VLB_SYNC +#define SUPPORT_VLB_SYNC 0 + +#ifndef MAX_HWIFS +#define MAX_HWIFS 8 +#endif + +/* + * some bits needed for parts of the IDE subsystem to compile + */ +#define __ide_mm_insw(port, addr, n) \ + insw((unsigned long) (port), (addr), (n)) +#define __ide_mm_insl(port, addr, n) \ + insl((unsigned long) (port), (addr), (n)) +#define __ide_mm_outsw(port, addr, n) \ + outsw((unsigned long) (port), (addr), (n)) +#define __ide_mm_outsl(port, addr, n) \ + outsl((unsigned long) (port), (addr), (n)) + +#endif /* __KERNEL__ */ +#endif /* _ASM_IDE_H */ diff --git a/include/asm-mn10300/intctl-regs.h b/include/asm-mn10300/intctl-regs.h new file mode 100644 index 00000000000..ba544c796c5 --- /dev/null +++ b/include/asm-mn10300/intctl-regs.h @@ -0,0 +1,73 @@ +/* MN10300 On-board interrupt controller registers + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_INTCTL_REGS_H +#define _ASM_INTCTL_REGS_H + +#include <asm/cpu-regs.h> + +#ifdef __KERNEL__ + +/* interrupt controller registers */ +#define GxICR(X) __SYSREG(0xd4000000 + (X) * 4, u16) /* group irq ctrl regs */ + +#define IAGR __SYSREG(0xd4000100, u16) /* intr acceptance group reg */ +#define IAGR_GN 0x00fc /* group number register + * (documentation _has_ to be wrong) + */ + +#define EXTMD __SYSREG(0xd4000200, u16) /* external pin intr spec reg */ +#define GET_XIRQ_TRIGGER(X) ((EXTMD >> ((X) * 2)) & 3) + +#define SET_XIRQ_TRIGGER(X,Y) \ +do { \ + u16 x = EXTMD; \ + x &= ~(3 << ((X) * 2)); \ + x |= ((Y) & 3) << ((X) * 2); \ + EXTMD = x; \ +} while (0) + +#define XIRQ_TRIGGER_LOWLEVEL 0 +#define XIRQ_TRIGGER_HILEVEL 1 +#define XIRQ_TRIGGER_NEGEDGE 2 +#define XIRQ_TRIGGER_POSEDGE 3 + +/* non-maskable interrupt control */ +#define NMIIRQ 0 +#define NMICR GxICR(NMIIRQ) /* NMI control register */ +#define NMICR_NMIF 0x0001 /* NMI pin interrupt flag */ +#define NMICR_WDIF 0x0002 /* watchdog timer overflow flag */ +#define NMICR_ABUSERR 0x0008 /* async bus error flag */ + +/* maskable interrupt control */ +#define GxICR_DETECT 0x0001 /* interrupt detect flag */ +#define GxICR_REQUEST 0x0010 /* interrupt request flag */ +#define GxICR_ENABLE 0x0100 /* interrupt enable flag */ +#define GxICR_LEVEL 0x7000 /* interrupt priority level */ +#define GxICR_LEVEL_0 0x0000 /* - level 0 */ +#define GxICR_LEVEL_1 0x1000 /* - level 1 */ +#define GxICR_LEVEL_2 0x2000 /* - level 2 */ +#define GxICR_LEVEL_3 0x3000 /* - level 3 */ +#define GxICR_LEVEL_4 0x4000 /* - level 4 */ +#define GxICR_LEVEL_5 0x5000 /* - level 5 */ +#define GxICR_LEVEL_6 0x6000 /* - level 6 */ +#define GxICR_LEVEL_SHIFT 12 + +#ifndef __ASSEMBLY__ +extern void set_intr_level(int irq, u16 level); +extern void set_intr_postackable(int irq); +#endif + +/* external interrupts */ +#define XIRQxICR(X) GxICR((X)) /* external interrupt control regs */ + +#endif /* __KERNEL__ */ + +#endif /* _ASM_INTCTL_REGS_H */ diff --git a/include/asm-mn10300/io.h b/include/asm-mn10300/io.h new file mode 100644 index 00000000000..b8b6dc87825 --- /dev/null +++ b/include/asm-mn10300/io.h @@ -0,0 +1,299 @@ +/* MN10300 I/O port emulation and memory-mapped I/O + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_IO_H +#define _ASM_IO_H + +#include <asm/page.h> /* I/O is all done through memory accesses */ +#include <asm/cpu-regs.h> +#include <asm/cacheflush.h> + +#define mmiowb() do {} while (0) + +/*****************************************************************************/ +/* + * readX/writeX() are used to access memory mapped devices. On some + * architectures the memory mapped IO stuff needs to be accessed + * differently. On the x86 architecture, we just read/write the + * memory location directly. + */ +static inline u8 readb(const volatile void __iomem *addr) +{ + return *(const volatile u8 *) addr; +} + +static inline u16 readw(const volatile void __iomem *addr) +{ + return *(const volatile u16 *) addr; +} + +static inline u32 readl(const volatile void __iomem *addr) +{ + return *(const volatile u32 *) addr; +} + +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl + +#define readb_relaxed readb +#define readw_relaxed readw +#define readl_relaxed readl + +static inline void writeb(u8 b, volatile void __iomem *addr) +{ + *(volatile u8 *) addr = b; +} + +static inline void writew(u16 b, volatile void __iomem *addr) +{ + *(volatile u16 *) addr = b; +} + +static inline void writel(u32 b, volatile void __iomem *addr) +{ + *(volatile u32 *) addr = b; +} + +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel + +/*****************************************************************************/ +/* + * traditional input/output functions + */ +static inline u8 inb_local(unsigned long addr) +{ + return readb((volatile void __iomem *) addr); +} + +static inline void outb_local(u8 b, unsigned long addr) +{ + return writeb(b, (volatile void __iomem *) addr); +} + +static inline u8 inb(unsigned long addr) +{ + return readb((volatile void __iomem *) addr); +} + +static inline u16 inw(unsigned long addr) +{ + return readw((volatile void __iomem *) addr); +} + +static inline u32 inl(unsigned long addr) +{ + return readl((volatile void __iomem *) addr); +} + +static inline void outb(u8 b, unsigned long addr) +{ + return writeb(b, (volatile void __iomem *) addr); +} + +static inline void outw(u16 b, unsigned long addr) +{ + return writew(b, (volatile void __iomem *) addr); +} + +static inline void outl(u32 b, unsigned long addr) +{ + return writel(b, (volatile void __iomem *) addr); +} + +#define inb_p(addr) inb(addr) +#define inw_p(addr) inw(addr) +#define inl_p(addr) inl(addr) +#define outb_p(x, addr) outb((x), (addr)) +#define outw_p(x, addr) outw((x), (addr)) +#define outl_p(x, addr) outl((x), (addr)) + +static inline void insb(unsigned long addr, void *buffer, int count) +{ + if (count) { + u8 *buf = buffer; + do { + u8 x = inb(addr); + *buf++ = x; + } while (--count); + } +} + +static inline void insw(unsigned long addr, void *buffer, int count) +{ + if (count) { + u16 *buf = buffer; + do { + u16 x = inw(addr); + *buf++ = x; + } while (--count); + } +} + +static inline void insl(unsigned long addr, void *buffer, int count) +{ + if (count) { + u32 *buf = buffer; + do { + u32 x = inl(addr); + *buf++ = x; + } while (--count); + } +} + +static inline void outsb(unsigned long addr, const void *buffer, int count) +{ + if (count) { + const u8 *buf = buffer; + do { + outb(*buf++, addr); + } while (--count); + } +} + +static inline void outsw(unsigned long addr, const void *buffer, int count) +{ + if (count) { + const u16 *buf = buffer; + do { + outw(*buf++, addr); + } while (--count); + } +} + +extern void __outsl(unsigned long addr, const void *buffer, int count); +static inline void outsl(unsigned long addr, const void *buffer, int count) +{ + if ((unsigned long) buffer & 0x3) + return __outsl(addr, buffer, count); + + if (count) { + const u32 *buf = buffer; + do { + outl(*buf++, addr); + } while (--count); + } +} + +#define ioread8(addr) readb(addr) +#define ioread16(addr) readw(addr) +#define ioread32(addr) readl(addr) + +#define iowrite8(v, addr) writeb((v), (addr)) +#define iowrite16(v, addr) writew((v), (addr)) +#define iowrite32(v, addr) writel((v), (addr)) + +#define ioread8_rep(p, dst, count) \ + insb((unsigned long) (p), (dst), (count)) +#define ioread16_rep(p, dst, count) \ + insw((unsigned long) (p), (dst), (count)) +#define ioread32_rep(p, dst, count) \ + insl((unsigned long) (p), (dst), (count)) + +#define iowrite8_rep(p, src, count) \ + outsb((unsigned long) (p), (src), (count)) +#define iowrite16_rep(p, src, count) \ + outsw((unsigned long) (p), (src), (count)) +#define iowrite32_rep(p, src, count) \ + outsl((unsigned long) (p), (src), (count)) + + +#define IO_SPACE_LIMIT 0xffffffff + +#ifdef __KERNEL__ + +#include <linux/vmalloc.h> +#define __io_virt(x) ((void *) (x)) + +/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ +struct pci_dev; +extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); +static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p) +{ +} + +/* + * Change virtual addresses to physical addresses and vv. + * These are pretty trivial + */ +static inline unsigned long virt_to_phys(volatile void *address) +{ + return __pa(address); +} + +static inline void *phys_to_virt(unsigned long address) +{ + return __va(address); +} + +/* + * Change "struct page" to physical address. + */ +static inline void *__ioremap(unsigned long offset, unsigned long size, + unsigned long flags) +{ + return (void *) offset; +} + +static inline void *ioremap(unsigned long offset, unsigned long size) +{ + return (void *) offset; +} + +/* + * This one maps high address device memory and turns off caching for that + * area. it's useful if some control registers are in such an area and write + * combining or read caching is not desirable: + */ +static inline void *ioremap_nocache(unsigned long offset, unsigned long size) +{ + return (void *) (offset | 0x20000000); +} + +static inline void iounmap(void *addr) +{ +} + +static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) +{ + return (void __iomem *) port; +} + +static inline void ioport_unmap(void __iomem *p) +{ +} + +#define xlate_dev_kmem_ptr(p) ((void *) (p)) +#define xlate_dev_mem_ptr(p) ((void *) (p)) + +/* + * PCI bus iomem addresses must be in the region 0x80000000-0x9fffffff + */ +static inline unsigned long virt_to_bus(volatile void *address) +{ + return ((unsigned long) address) & ~0x20000000; +} + +static inline void *bus_to_virt(unsigned long address) +{ + return (void *) address; +} + +#define page_to_bus page_to_phys + +#define memset_io(a, b, c) memset(__io_virt(a), (b), (c)) +#define memcpy_fromio(a, b, c) memcpy((a), __io_virt(b), (c)) +#define memcpy_toio(a, b, c) memcpy(__io_virt(a), (b), (c)) + +#endif /* __KERNEL__ */ + +#endif /* _ASM_IO_H */ diff --git a/include/asm-mn10300/ioctl.h b/include/asm-mn10300/ioctl.h new file mode 100644 index 00000000000..b279fe06dfe --- /dev/null +++ b/include/asm-mn10300/ioctl.h @@ -0,0 +1 @@ +#include <asm-generic/ioctl.h> diff --git a/include/asm-mn10300/ioctls.h b/include/asm-mn10300/ioctls.h new file mode 100644 index 00000000000..dcbfb452974 --- /dev/null +++ b/include/asm-mn10300/ioctls.h @@ -0,0 +1,88 @@ +#ifndef _ASM_IOCTLS_H +#define _ASM_IOCTLS_H + +#include <asm/ioctl.h> + +/* 0x54 is just a magic number to make these relatively unique ('T') */ + +#define TCGETS 0x5401 +#define TCSETS 0x5402 +#define TCSETSW 0x5403 +#define TCSETSF 0x5404 +#define TCGETA 0x5405 +#define TCSETA 0x5406 +#define TCSETAW 0x5407 +#define TCSETAF 0x5408 +#define TCSBRK 0x5409 +#define TCXONC 0x540A +#define TCFLSH 0x540B +#define TIOCEXCL 0x540C +#define TIOCNXCL 0x540D +#define TIOCSCTTY 0x540E +#define TIOCGPGRP 0x540F +#define TIOCSPGRP 0x5410 +#define TIOCOUTQ 0x5411 +#define TIOCSTI 0x5412 +#define TIOCGWINSZ 0x5413 +#define TIOCSWINSZ 0x5414 +#define TIOCMGET 0x5415 +#define TIOCMBIS 0x5416 +#define TIOCMBIC 0x5417 +#define TIOCMSET 0x5418 +#define TIOCGSOFTCAR 0x5419 +#define TIOCSSOFTCAR 0x541A +#define FIONREAD 0x541B +#define TIOCINQ FIONREAD +#define TIOCLINUX 0x541C +#define TIOCCONS 0x541D +#define TIOCGSERIAL 0x541E +#define TIOCSSERIAL 0x541F +#define TIOCPKT 0x5420 +#define FIONBIO 0x5421 +#define TIOCNOTTY 0x5422 +#define TIOCSETD 0x5423 +#define TIOCGETD 0x5424 +#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ +/* #define TIOCTTYGSTRUCT 0x5426 - Former debugging-only ioctl */ +#define TIOCSBRK 0x5427 /* BSD compatibility */ +#define TIOCCBRK 0x5428 /* BSD compatibility */ +#define TIOCGSID 0x5429 /* Return the session ID of FD */ +#define TCGETS2 _IOR('T', 0x2A, struct termios2) +#define TCSETS2 _IOW('T', 0x2B, struct termios2) +#define TCSETSW2 _IOW('T', 0x2C, struct termios2) +#define TCSETSF2 _IOW('T', 0x2D, struct termios2) +#define TIOCGPTN _IOR('T', 0x30, unsigned int) /* Get Pty Number + * (of pty-mux device) */ +#define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */ + +#define FIONCLEX 0x5450 +#define FIOCLEX 0x5451 +#define FIOASYNC 0x5452 +#define TIOCSERCONFIG 0x5453 +#define TIOCSERGWILD 0x5454 +#define TIOCSERSWILD 0x5455 +#define TIOCGLCKTRMIOS 0x5456 +#define TIOCSLCKTRMIOS 0x5457 +#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ +#define TIOCSERGETLSR 0x5459 /* Get line status register */ +#define TIOCSERGETMULTI 0x545A /* Get multiport config */ +#define TIOCSERSETMULTI 0x545B /* Set multiport config */ + +#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ +#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ +#define TIOCGHAYESESP 0x545E /* Get Hayes ESP configuration */ +#define TIOCSHAYESESP 0x545F /* Set Hayes ESP configuration */ +#define FIOQSIZE 0x5460 + +/* Used for packet mode */ +#define TIOCPKT_DATA 0 +#define TIOCPKT_FLUSHREAD 1 +#define TIOCPKT_FLUSHWRITE 2 +#define TIOCPKT_STOP 4 +#define TIOCPKT_START 8 +#define TIOCPKT_NOSTOP 16 +#define TIOCPKT_DOSTOP 32 + +#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ + +#endif /* _ASM_IOCTLS_H */ diff --git a/include/asm-mn10300/ipc.h b/include/asm-mn10300/ipc.h new file mode 100644 index 00000000000..a46e3d9c2a3 --- /dev/null +++ b/include/asm-mn10300/ipc.h @@ -0,0 +1 @@ +#include <asm-generic/ipc.h> diff --git a/include/asm-mn10300/ipcbuf.h b/include/asm-mn10300/ipcbuf.h new file mode 100644 index 00000000000..efbbef8d1c6 --- /dev/null +++ b/include/asm-mn10300/ipcbuf.h @@ -0,0 +1,29 @@ +#ifndef _ASM_IPCBUF_H_ +#define _ASM_IPCBUF_H + +/* + * The ipc64_perm structure for MN10300 architecture. + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 32-bit mode_t and seq + * - 2 miscellaneous 32-bit values + */ + +struct ipc64_perm +{ + __kernel_key_t key; + __kernel_uid32_t uid; + __kernel_gid32_t gid; + __kernel_uid32_t cuid; + __kernel_gid32_t cgid; + __kernel_mode_t mode; + unsigned short __pad1; + unsigned short seq; + unsigned short __pad2; + unsigned long __unused1; + unsigned long __unused2; +}; + +#endif /* _ASM_IPCBUF_H */ diff --git a/include/asm-mn10300/irq.h b/include/asm-mn10300/irq.h new file mode 100644 index 00000000000..53b38011690 --- /dev/null +++ b/include/asm-mn10300/irq.h @@ -0,0 +1,32 @@ +/* MN10300 Hardware interrupt definitions + * + * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Modified by David Howells (dhowells@redhat.com) + * - Derived from include/asm-i386/irq.h: + * - (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_IRQ_H +#define _ASM_IRQ_H + +#include <asm/intctl-regs.h> +#include <asm/reset-regs.h> +#include <asm/proc/irq.h> + +/* this number is used when no interrupt has been assigned */ +#define NO_IRQ INT_MAX + +/* hardware irq numbers */ +#define NR_IRQS GxICR_NUM_IRQS + +/* external hardware irq numbers */ +#define NR_XIRQS GxICR_NUM_XIRQS + +#define irq_canonicalize(IRQ) (IRQ) + +#endif /* _ASM_IRQ_H */ diff --git a/include/asm-mn10300/irq_regs.h b/include/asm-mn10300/irq_regs.h new file mode 100644 index 00000000000..a848cd232eb --- /dev/null +++ b/include/asm-mn10300/irq_regs.h @@ -0,0 +1,24 @@ +/* MN10300 IRQ registers pointer definition + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_IRQ_REGS_H +#define _ASM_IRQ_REGS_H + +/* + * Per-cpu current frame pointer - the location of the last exception frame on + * the stack + */ +#define ARCH_HAS_OWN_IRQ_REGS + +#ifndef __ASSEMBLY__ +#define get_irq_regs() (__frame) +#endif + +#endif /* _ASM_IRQ_REGS_H */ diff --git a/include/asm-mn10300/kdebug.h b/include/asm-mn10300/kdebug.h new file mode 100644 index 00000000000..0f47e112190 --- /dev/null +++ b/include/asm-mn10300/kdebug.h @@ -0,0 +1,22 @@ +/* MN10300 In-kernel death knells + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_KDEBUG_H +#define _ASM_KDEBUG_H + +/* Grossly misnamed. */ +enum die_val { + DIE_OOPS = 1, + DIE_BREAKPOINT, + DIE_GPF, +}; + +#endif /* _ASM_KDEBUG_H */ diff --git a/include/asm-mn10300/kmap_types.h b/include/asm-mn10300/kmap_types.h new file mode 100644 index 00000000000..3398f9f3560 --- /dev/null +++ b/include/asm-mn10300/kmap_types.h @@ -0,0 +1,31 @@ +/* MN10300 kmap_atomic() slot IDs + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_KMAP_TYPES_H +#define _ASM_KMAP_TYPES_H + +enum km_type { + KM_BOUNCE_READ, + KM_SKB_SUNRPC_DATA, + KM_SKB_DATA_SOFTIRQ, + KM_USER0, + KM_USER1, + KM_BIO_SRC_IRQ, + KM_BIO_DST_IRQ, + KM_PTE0, + KM_PTE1, + KM_IRQ0, + KM_IRQ1, + KM_SOFTIRQ0, + KM_SOFTIRQ1, + KM_TYPE_NR +}; + +#endif /* _ASM_KMAP_TYPES_H */ diff --git a/include/asm-mn10300/kprobes.h b/include/asm-mn10300/kprobes.h new file mode 100644 index 00000000000..c800b590183 --- /dev/null +++ b/include/asm-mn10300/kprobes.h @@ -0,0 +1,50 @@ +/* MN10300 Kernel Probes support + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by Mark Salter (msalter@redhat.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public Licence as published by + * the Free Software Foundation; either version 2 of the Licence, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public Licence for more details. + * + * You should have received a copy of the GNU General Public Licence + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ +#ifndef _ASM_KPROBES_H +#define _ASM_KPROBES_H + +#include <linux/types.h> +#include <linux/ptrace.h> + +struct kprobe; + +typedef unsigned char kprobe_opcode_t; +#define BREAKPOINT_INSTRUCTION 0xff +#define MAX_INSN_SIZE 8 +#define MAX_STACK_SIZE 128 + +/* Architecture specific copy of original instruction */ +struct arch_specific_insn { + /* copy of original instruction + */ + kprobe_opcode_t insn[MAX_INSN_SIZE]; +}; + +extern const int kretprobe_blacklist_size; + +extern int kprobe_exceptions_notify(struct notifier_block *self, + unsigned long val, void *data); + +#define flush_insn_slot(p) do {} while (0) + +extern void arch_remove_kprobe(struct kprobe *p); + +#endif /* _ASM_KPROBES_H */ diff --git a/include/asm-mn10300/linkage.h b/include/asm-mn10300/linkage.h new file mode 100644 index 00000000000..29a32e46752 --- /dev/null +++ b/include/asm-mn10300/linkage.h @@ -0,0 +1,22 @@ +/* MN10300 Linkage and calling-convention overrides + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_LINKAGE_H +#define _ASM_LINKAGE_H + +/* don't override anything */ +#define asmlinkage +#define FASTCALL(x) x +#define fastcall + +#define __ALIGN .align 4,0xcb +#define __ALIGN_STR ".align 4,0xcb" + +#endif diff --git a/include/asm-mn10300/local.h b/include/asm-mn10300/local.h new file mode 100644 index 00000000000..c11c530f74d --- /dev/null +++ b/include/asm-mn10300/local.h @@ -0,0 +1 @@ +#include <asm-generic/local.h> diff --git a/include/asm-mn10300/mc146818rtc.h b/include/asm-mn10300/mc146818rtc.h new file mode 100644 index 00000000000..df6bc6e0e8c --- /dev/null +++ b/include/asm-mn10300/mc146818rtc.h @@ -0,0 +1 @@ +#include <asm/rtc-regs.h> diff --git a/include/asm-mn10300/mman.h b/include/asm-mn10300/mman.h new file mode 100644 index 00000000000..b7986b65add --- /dev/null +++ b/include/asm-mn10300/mman.h @@ -0,0 +1,28 @@ +/* MN10300 Constants for mmap and co. + * + * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * - Derived from asm-x86/mman.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_MMAN_H +#define _ASM_MMAN_H + +#include <asm-generic/mman.h> + +#define MAP_GROWSDOWN 0x0100 /* stack-like segment */ +#define MAP_DENYWRITE 0x0800 /* ETXTBSY */ +#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ +#define MAP_LOCKED 0x2000 /* pages are locked */ +#define MAP_NORESERVE 0x4000 /* don't check for reservations */ +#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ +#define MAP_NONBLOCK 0x10000 /* do not block on IO */ + +#define MCL_CURRENT 1 /* lock all current mappings */ +#define MCL_FUTURE 2 /* lock all future mappings */ + +#endif /* _ASM_MMAN_H */ diff --git a/include/asm-mn10300/mmu.h b/include/asm-mn10300/mmu.h new file mode 100644 index 00000000000..2d2d097e730 --- /dev/null +++ b/include/asm-mn10300/mmu.h @@ -0,0 +1,19 @@ +/* MN10300 Memory management context + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * - Derived from include/asm-frv/mmu.h + */ + +#ifndef _ASM_MMU_H +#define _ASM_MMU_H + +/* + * MMU context + */ +typedef struct { + unsigned long tlbpid[NR_CPUS]; /* TLB PID for this process on + * each CPU */ +} mm_context_t; + +#endif /* _ASM_MMU_H */ diff --git a/include/asm-mn10300/mmu_context.h b/include/asm-mn10300/mmu_context.h new file mode 100644 index 00000000000..a9e2e34f69b --- /dev/null +++ b/include/asm-mn10300/mmu_context.h @@ -0,0 +1,138 @@ +/* MN10300 MMU context management + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Modified by David Howells (dhowells@redhat.com) + * - Derived from include/asm-m32r/mmu_context.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + * + * + * This implements an algorithm to provide TLB PID mappings to provide + * selective access to the TLB for processes, thus reducing the number of TLB + * flushes required. + * + * Note, however, that the M32R algorithm is technically broken as it does not + * handle version wrap-around, and could, theoretically, have a problem with a + * very long lived program that sleeps long enough for the version number to + * wrap all the way around so that its TLB mappings appear valid once again. + */ +#ifndef _ASM_MMU_CONTEXT_H +#define _ASM_MMU_CONTEXT_H + +#include <asm/atomic.h> +#include <asm/pgalloc.h> +#include <asm/tlbflush.h> +#include <asm-generic/mm_hooks.h> + +#define MMU_CONTEXT_TLBPID_MASK 0x000000ffUL +#define MMU_CONTEXT_VERSION_MASK 0xffffff00UL +#define MMU_CONTEXT_FIRST_VERSION 0x00000100UL +#define MMU_NO_CONTEXT 0x00000000UL + +extern unsigned long mmu_context_cache[NR_CPUS]; +#define mm_context(mm) (mm->context.tlbpid[smp_processor_id()]) + +#define enter_lazy_tlb(mm, tsk) do {} while (0) + +#ifdef CONFIG_SMP +#define cpu_ran_vm(cpu, task) \ + cpu_set((cpu), (task)->cpu_vm_mask) +#define cpu_maybe_ran_vm(cpu, task) \ + cpu_test_and_set((cpu), (task)->cpu_vm_mask) +#else +#define cpu_ran_vm(cpu, task) do {} while (0) +#define cpu_maybe_ran_vm(cpu, task) true +#endif /* CONFIG_SMP */ + +/* + * allocate an MMU context + */ +static inline unsigned long allocate_mmu_context(struct mm_struct *mm) +{ + unsigned long *pmc = &mmu_context_cache[smp_processor_id()]; + unsigned long mc = ++(*pmc); + + if (!(mc & MMU_CONTEXT_TLBPID_MASK)) { + /* we exhausted the TLB PIDs of this version on this CPU, so we + * flush this CPU's TLB in its entirety and start new cycle */ + flush_tlb_all(); + + /* fix the TLB version if needed (we avoid version #0 so as to + * distingush MMU_NO_CONTEXT) */ + if (!mc) + *pmc = mc = MMU_CONTEXT_FIRST_VERSION; + } + mm_context(mm) = mc; + return mc; +} + +/* + * get an MMU context if one is needed + */ +static inline unsigned long get_mmu_context(struct mm_struct *mm) +{ + unsigned long mc = MMU_NO_CONTEXT, cache; + + if (mm) { + cache = mmu_context_cache[smp_processor_id()]; + mc = mm_context(mm); + + /* if we have an old version of the context, replace it */ + if ((mc ^ cache) & MMU_CONTEXT_VERSION_MASK) + mc = allocate_mmu_context(mm); + } + return mc; +} + +/* + * initialise the context related info for a new mm_struct instance + */ +static inline int init_new_context(struct task_struct *tsk, + struct mm_struct *mm) +{ + int num_cpus = NR_CPUS, i; + + for (i = 0; i < num_cpus; i++) + mm->context.tlbpid[i] = MMU_NO_CONTEXT; + return 0; +} + +/* + * destroy context related info for an mm_struct that is about to be put to + * rest + */ +#define destroy_context(mm) do { } while (0) + +/* + * after we have set current->mm to a new value, this activates the context for + * the new mm so we see the new mappings. + */ +static inline void activate_context(struct mm_struct *mm, int cpu) +{ + PIDR = get_mmu_context(mm) & MMU_CONTEXT_TLBPID_MASK; +} + +/* + * change between virtual memory sets + */ +static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk) +{ + int cpu = smp_processor_id(); + + if (prev != next) { + cpu_ran_vm(cpu, next); + activate_context(next, cpu); + PTBR = (unsigned long) next->pgd; + } else if (!cpu_maybe_ran_vm(cpu, next)) { + activate_context(next, cpu); + } +} + +#define deactivate_mm(tsk, mm) do {} while (0) +#define activate_mm(prev, next) switch_mm((prev), (next), NULL) + +#endif /* _ASM_MMU_CONTEXT_H */ diff --git a/include/asm-mn10300/module.h b/include/asm-mn10300/module.h new file mode 100644 index 00000000000..5d7057d0149 --- /dev/null +++ b/include/asm-mn10300/module.h @@ -0,0 +1,27 @@ +/* MN10300 Arch-specific module definitions + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by Mark Salter (msalter@redhat.com) + * Derived from include/asm-i386/module.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_MODULE_H +#define _ASM_MODULE_H + +struct mod_arch_specific { +}; + +#define Elf_Shdr Elf32_Shdr +#define Elf_Sym Elf32_Sym +#define Elf_Ehdr Elf32_Ehdr + +/* + * Include the MN10300 architecture version. + */ +#define MODULE_ARCH_VERMAGIC __stringify(PROCESSOR_MODEL_NAME) " " + +#endif /* _ASM_MODULE_H */ diff --git a/include/asm-mn10300/msgbuf.h b/include/asm-mn10300/msgbuf.h new file mode 100644 index 00000000000..8b602450cc4 --- /dev/null +++ b/include/asm-mn10300/msgbuf.h @@ -0,0 +1,31 @@ +#ifndef _ASM_MSGBUF_H +#define _ASM_MSGBUF_H + +/* + * The msqid64_ds structure for MN10300 architecture. + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 64-bit time_t to solve y2038 problem + * - 2 miscellaneous 32-bit values + */ + +struct msqid64_ds { + struct ipc64_perm msg_perm; + __kernel_time_t msg_stime; /* last msgsnd time */ + unsigned long __unused1; + __kernel_time_t msg_rtime; /* last msgrcv time */ + unsigned long __unused2; + __kernel_time_t msg_ctime; /* last change time */ + unsigned long __unused3; + unsigned long msg_cbytes; /* current number of bytes on queue */ + unsigned long msg_qnum; /* number of messages in queue */ + unsigned long msg_qbytes; /* max number of bytes on queue */ + __kernel_pid_t msg_lspid; /* pid of last msgsnd */ + __kernel_pid_t msg_lrpid; /* last receive pid */ + unsigned long __unused4; + unsigned long __unused5; +}; + +#endif /* _ASM_MSGBUF_H */ diff --git a/include/asm-mn10300/mutex.h b/include/asm-mn10300/mutex.h new file mode 100644 index 00000000000..84f5490c6fb --- /dev/null +++ b/include/asm-mn10300/mutex.h @@ -0,0 +1,16 @@ +/* MN10300 Mutex fastpath + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + * + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ +#include <asm-generic/mutex-null.h> diff --git a/include/asm-mn10300/namei.h b/include/asm-mn10300/namei.h new file mode 100644 index 00000000000..bd9ce94aeb6 --- /dev/null +++ b/include/asm-mn10300/namei.h @@ -0,0 +1,22 @@ +/* Emulation stuff + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_NAMEI_H +#define _ASM_NAMEI_H + +/* This dummy routine maybe changed to something useful + * for /usr/gnemul/ emulation stuff. + * Look at asm-sparc/namei.h for details. + */ + +#define __emul_prefix() NULL + +#endif /* _ASM_NAMEI_H */ diff --git a/include/asm-mn10300/nmi.h b/include/asm-mn10300/nmi.h new file mode 100644 index 00000000000..f3671cbbc11 --- /dev/null +++ b/include/asm-mn10300/nmi.h @@ -0,0 +1,14 @@ +/* MN10300 NMI handling + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_NMI_H +#define _ASM_NMI_H + +#endif /* _ASM_NMI_H */ diff --git a/include/asm-mn10300/page.h b/include/asm-mn10300/page.h new file mode 100644 index 00000000000..124971b9fb9 --- /dev/null +++ b/include/asm-mn10300/page.h @@ -0,0 +1,131 @@ +/* MN10300 Page table definitions + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_PAGE_H +#define _ASM_PAGE_H + +/* PAGE_SHIFT determines the page size */ +#define PAGE_SHIFT 12 + +#ifndef __ASSEMBLY__ +#define PAGE_SIZE (1UL << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE - 1)) +#else +#define PAGE_SIZE +(1 << PAGE_SHIFT) /* unary plus marks an + * immediate val not an addr */ +#define PAGE_MASK +(~(PAGE_SIZE - 1)) +#endif + +#ifdef __KERNEL__ +#ifndef __ASSEMBLY__ + +#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) +#define copy_page(to, from) memcpy((void *)(to), (void *)(from), PAGE_SIZE) + +#define clear_user_page(addr, vaddr, page) clear_page(addr) +#define copy_user_page(vto, vfrom, vaddr, to) copy_page(vto, vfrom) + +/* + * These are used to make use of C type-checking.. + */ +typedef struct { unsigned long pte; } pte_t; +typedef struct { unsigned long pgd; } pgd_t; +typedef struct { unsigned long pgprot; } pgprot_t; +typedef struct page *pgtable_t; + +#define PTE_MASK PAGE_MASK +#define HPAGE_SHIFT 22 + +#ifdef CONFIG_HUGETLB_PAGE +#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT) +#define HPAGE_MASK (~(HPAGE_SIZE - 1)) +#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) +#endif + +#define pte_val(x) ((x).pte) +#define pgd_val(x) ((x).pgd) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) }) +#define __pgd(x) ((pgd_t) { (x) }) +#define __pgprot(x) ((pgprot_t) { (x) }) + +#include <asm-generic/pgtable-nopmd.h> + +#endif /* !__ASSEMBLY__ */ + +/* to align the pointer to the (next) page boundary */ +#define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) + +/* + * This handles the memory map.. We could make this a config + * option, but too many people screw it up, and too few need + * it. + * + * A __PAGE_OFFSET of 0xC0000000 means that the kernel has + * a virtual address space of one gigabyte, which limits the + * amount of physical memory you can use to about 950MB. + */ + +#ifndef __ASSEMBLY__ + +/* Pure 2^n version of get_order */ +static inline int get_order(unsigned long size) __attribute__((const)); +static inline int get_order(unsigned long size) +{ + int order; + + size = (size - 1) >> (PAGE_SHIFT - 1); + order = -1; + do { + size >>= 1; + order++; + } while (size); + return order; +} + +#endif /* __ASSEMBLY__ */ + +#include <asm/page_offset.h> + +#define __PAGE_OFFSET (PAGE_OFFSET_RAW) +#define PAGE_OFFSET ((unsigned long) __PAGE_OFFSET) + +/* + * main RAM and kernel working space are coincident at 0x90000000, but to make + * life more interesting, there's also an uncached virtual shadow at 0xb0000000 + * - these mappings are fixed in the MMU + */ +#define __pfn_disp (CONFIG_KERNEL_RAM_BASE_ADDRESS >> PAGE_SHIFT) + +#define __pa(x) ((unsigned long)(x)) +#define __va(x) ((void *)(unsigned long)(x)) +#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) +#define pfn_to_page(pfn) (mem_map + ((pfn) - __pfn_disp)) +#define page_to_pfn(page) ((unsigned long)((page) - mem_map) + __pfn_disp) + +#define pfn_valid(pfn) \ +({ \ + unsigned long __pfn = (pfn) - __pfn_disp; \ + __pfn < max_mapnr; \ +}) + +#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) +#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) +#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) + +#define VM_DATA_DEFAULT_FLAGS \ + (VM_READ | VM_WRITE | \ + ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \ + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) + +#endif /* __KERNEL__ */ + +#endif /* _ASM_PAGE_H */ diff --git a/include/asm-mn10300/page_offset.h b/include/asm-mn10300/page_offset.h new file mode 100644 index 00000000000..8eb5b16ad86 --- /dev/null +++ b/include/asm-mn10300/page_offset.h @@ -0,0 +1,11 @@ +/* MN10300 Kernel base address + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + */ +#ifndef _ASM_PAGE_OFFSET_H +#define _ASM_PAGE_OFFSET_H + +#define PAGE_OFFSET_RAW CONFIG_KERNEL_RAM_BASE_ADDRESS + +#endif diff --git a/include/asm-mn10300/param.h b/include/asm-mn10300/param.h new file mode 100644 index 00000000000..54b883ec390 --- /dev/null +++ b/include/asm-mn10300/param.h @@ -0,0 +1,34 @@ +/* MN10300 Kernel parameters + * + * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_PARAM_H +#define _ASM_PARAM_H + +#ifdef __KERNEL__ +#define HZ 1000 /* Internal kernel timer frequency */ +#define USER_HZ 100 /* .. some user interfaces are in + * "ticks" */ +#define CLOCKS_PER_SEC (USER_HZ) /* like times() */ +#endif + +#ifndef HZ +#define HZ 100 +#endif + +#define EXEC_PAGESIZE 4096 + +#ifndef NOGROUP +#define NOGROUP (-1) +#endif + +#define MAXHOSTNAMELEN 64 /* max length of hostname */ +#define COMMAND_LINE_SIZE 256 + +#endif /* _ASM_PARAM_H */ diff --git a/include/asm-mn10300/pci.h b/include/asm-mn10300/pci.h new file mode 100644 index 00000000000..205192c52bb --- /dev/null +++ b/include/asm-mn10300/pci.h @@ -0,0 +1,133 @@ +/* MN10300 PCI definitions + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_PCI_H +#define _ASM_PCI_H + +#ifdef __KERNEL__ +#include <linux/mm.h> /* for struct page */ + +#if 0 +#define __pcbdebug(FMT, ADDR, ...) \ + printk(KERN_DEBUG "PCIBRIDGE[%08x]: "FMT"\n", \ + (u32)(ADDR), ##__VA_ARGS__) + +#define __pcidebug(FMT, BUS, DEVFN, WHERE,...) \ +do { \ + printk(KERN_DEBUG "PCI[%02x:%02x.%x + %02x]: "FMT"\n", \ + (BUS)->number, \ + PCI_SLOT(DEVFN), \ + PCI_FUNC(DEVFN), \ + (u32)(WHERE), ##__VA_ARGS__); \ +} while (0) + +#else +#define __pcbdebug(FMT, ADDR, ...) do {} while (0) +#define __pcidebug(FMT, BUS, DEVFN, WHERE, ...) do {} while (0) +#endif + +/* Can be used to override the logic in pci_scan_bus for skipping + * already-configured bus numbers - to be used for buggy BIOSes or + * architectures with incomplete PCI setup by the loader */ + +#ifdef CONFIG_PCI +#define pcibios_assign_all_busses() 1 +extern void unit_pci_init(void); +#else +#define pcibios_assign_all_busses() 0 +#endif + +extern unsigned long pci_mem_start; +#define PCIBIOS_MIN_IO 0xBE000004 +#define PCIBIOS_MIN_MEM 0xB8000000 + +void pcibios_set_master(struct pci_dev *dev); +void pcibios_penalize_isa_irq(int irq); + +/* Dynamic DMA mapping stuff. + * i386 has everything mapped statically. + */ + +#include <linux/types.h> +#include <linux/slab.h> +#include <asm/scatterlist.h> +#include <linux/string.h> +#include <linux/mm.h> +#include <asm/io.h> + +struct pci_dev; + +/* The PCI address space does equal the physical memory + * address space. The networking and block device layers use + * this boolean for bounce buffer decisions. + */ +#define PCI_DMA_BUS_IS_PHYS (1) + + +/* This is always fine. */ +#define pci_dac_dma_supported(pci_dev, mask) (0) + +/* + * These macros should be used after a pci_map_sg call has been done + * to get bus addresses of each of the SG entries and their lengths. + * You should only work with the number of sg entries pci_map_sg + * returns. + */ +#define sg_dma_address(sg) ((sg)->dma_address) +#define sg_dma_len(sg) ((sg)->length) + +/* Return the index of the PCI controller for device. */ +static inline int pci_controller_num(struct pci_dev *dev) +{ + return 0; +} + +#define HAVE_PCI_MMAP +extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, + enum pci_mmap_state mmap_state, + int write_combine); + +#endif /* __KERNEL__ */ + +/* implement the pci_ DMA API in terms of the generic device dma_ one */ +#include <asm-generic/pci-dma-compat.h> + +/** + * pcibios_resource_to_bus - convert resource to PCI bus address + * @dev: device which owns this resource + * @region: converted bus-centric region (start,end) + * @res: resource to convert + * + * Convert a resource to a PCI device bus address or bus window. + */ +extern void pcibios_resource_to_bus(struct pci_dev *dev, + struct pci_bus_region *region, + struct resource *res); + +extern void pcibios_bus_to_resource(struct pci_dev *dev, + struct resource *res, + struct pci_bus_region *region); + +static inline struct resource * +pcibios_select_root(struct pci_dev *pdev, struct resource *res) +{ + struct resource *root = NULL; + + if (res->flags & IORESOURCE_IO) + root = &ioport_resource; + if (res->flags & IORESOURCE_MEM) + root = &iomem_resource; + + return root; +} + +#define pcibios_scan_all_fns(a, b) 0 + +#endif /* _ASM_PCI_H */ diff --git a/include/asm-mn10300/percpu.h b/include/asm-mn10300/percpu.h new file mode 100644 index 00000000000..06a959d6723 --- /dev/null +++ b/include/asm-mn10300/percpu.h @@ -0,0 +1 @@ +#include <asm-generic/percpu.h> diff --git a/include/asm-mn10300/pgalloc.h b/include/asm-mn10300/pgalloc.h new file mode 100644 index 00000000000..ec057e1bd4c --- /dev/null +++ b/include/asm-mn10300/pgalloc.h @@ -0,0 +1,56 @@ +/* MN10300 Page and page table/directory allocation + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_PGALLOC_H +#define _ASM_PGALLOC_H + +#include <asm/processor.h> +#include <asm/page.h> +#include <linux/threads.h> +#include <linux/mm.h> /* for struct page */ + +struct mm_struct; +struct page; + +/* attach a page table to a PMD entry */ +#define pmd_populate_kernel(mm, pmd, pte) \ + set_pmd(pmd, __pmd(__pa(pte) | _PAGE_TABLE)) + +static inline +void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *pte) +{ + set_pmd(pmd, __pmd((page_to_pfn(pte) << PAGE_SHIFT) | _PAGE_TABLE)); +} +#define pmd_pgtable(pmd) pmd_page(pmd) + +/* + * Allocate and free page tables. + */ + +extern pgd_t *pgd_alloc(struct mm_struct *); +extern void pgd_free(struct mm_struct *, pgd_t *); + +extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long); +extern struct page *pte_alloc_one(struct mm_struct *, unsigned long); + +static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) +{ + free_page((unsigned long) pte); +} + +static inline void pte_free(struct mm_struct *mm, struct page *pte) +{ + __free_page(pte); +} + + +#define __pte_free_tlb(tlb, pte) tlb_remove_page((tlb), (pte)) + +#endif /* _ASM_PGALLOC_H */ diff --git a/include/asm-mn10300/pgtable.h b/include/asm-mn10300/pgtable.h new file mode 100644 index 00000000000..375c4941ded --- /dev/null +++ b/include/asm-mn10300/pgtable.h @@ -0,0 +1,489 @@ +/* MN10300 Page table manipulators and constants + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + * + * + * The Linux memory management assumes a three-level page table setup. On + * the i386, we use that, but "fold" the mid level into the top-level page + * table, so that we physically have the same two-level page table as the + * i386 mmu expects. + * + * This file contains the functions and defines necessary to modify and use + * the i386 page table tree for the purposes of the MN10300 TLB handler + * functions. + */ +#ifndef _ASM_PGTABLE_H +#define _ASM_PGTABLE_H + +#include <asm/cpu-regs.h> + +#ifndef __ASSEMBLY__ +#include <asm/processor.h> +#include <asm/cache.h> +#include <linux/threads.h> + +#include <asm/bitops.h> + +#include <linux/slab.h> +#include <linux/list.h> +#include <linux/spinlock.h> + +/* + * ZERO_PAGE is a global shared page that is always zero: used + * for zero-mapped memory areas etc.. + */ +#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) +extern unsigned long empty_zero_page[1024]; +extern spinlock_t pgd_lock; +extern struct page *pgd_list; + +extern void pmd_ctor(void *, struct kmem_cache *, unsigned long); +extern void pgtable_cache_init(void); +extern void paging_init(void); + +#endif /* !__ASSEMBLY__ */ + +/* + * The Linux mn10300 paging architecture only implements both the traditional + * 2-level page tables + */ +#define PGDIR_SHIFT 22 +#define PTRS_PER_PGD 1024 +#define PTRS_PER_PUD 1 /* we don't really have any PUD physically */ +#define PTRS_PER_PMD 1 /* we don't really have any PMD physically */ +#define PTRS_PER_PTE 1024 + +#define PGD_SIZE PAGE_SIZE +#define PMD_SIZE (1UL << PMD_SHIFT) +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE - 1)) + +#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) +#define FIRST_USER_ADDRESS 0 + +#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) +#define KERNEL_PGD_PTRS (PTRS_PER_PGD - USER_PGD_PTRS) + +#define TWOLEVEL_PGDIR_SHIFT 22 +#define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT) +#define BOOT_KERNEL_PGD_PTRS (1024 - BOOT_USER_PGD_PTRS) + +#ifndef __ASSEMBLY__ +extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; +#endif + +/* + * Unfortunately, due to the way the MMU works on the MN10300, the vmalloc VM + * area has to be in the lower half of the virtual address range (the upper + * half is not translated through the TLB). + * + * So in this case, the vmalloc area goes at the bottom of the address map + * (leaving a hole at the very bottom to catch addressing errors), and + * userspace starts immediately above. + * + * The vmalloc() routines also leaves a hole of 4kB between each vmalloced + * area to catch addressing errors. + */ +#define VMALLOC_OFFSET (8 * 1024 * 1024) +#define VMALLOC_START (0x70000000) +#define VMALLOC_END (0x7C000000) + +#ifndef __ASSEMBLY__ +extern pte_t kernel_vmalloc_ptes[(VMALLOC_END - VMALLOC_START) / PAGE_SIZE]; +#endif + +/* IPTEL/DPTEL bit assignments */ +#define _PAGE_BIT_VALID xPTEL_V_BIT +#define _PAGE_BIT_ACCESSED xPTEL_UNUSED1_BIT /* mustn't be loaded into IPTEL/DPTEL */ +#define _PAGE_BIT_NX xPTEL_UNUSED2_BIT /* mustn't be loaded into IPTEL/DPTEL */ +#define _PAGE_BIT_CACHE xPTEL_C_BIT +#define _PAGE_BIT_PRESENT xPTEL_PV_BIT +#define _PAGE_BIT_DIRTY xPTEL_D_BIT +#define _PAGE_BIT_GLOBAL xPTEL_G_BIT + +#define _PAGE_VALID xPTEL_V +#define _PAGE_ACCESSED xPTEL_UNUSED1 +#define _PAGE_NX xPTEL_UNUSED2 /* no-execute bit */ +#define _PAGE_CACHE xPTEL_C +#define _PAGE_PRESENT xPTEL_PV +#define _PAGE_DIRTY xPTEL_D +#define _PAGE_PROT xPTEL_PR +#define _PAGE_PROT_RKNU xPTEL_PR_ROK +#define _PAGE_PROT_WKNU xPTEL_PR_RWK +#define _PAGE_PROT_RKRU xPTEL_PR_ROK_ROU +#define _PAGE_PROT_WKRU xPTEL_PR_RWK_ROU +#define _PAGE_PROT_WKWU xPTEL_PR_RWK_RWU +#define _PAGE_GLOBAL xPTEL_G +#define _PAGE_PSE xPTEL_PS_4Mb /* 4MB page */ + +#define _PAGE_FILE xPTEL_UNUSED1_BIT /* set:pagecache unset:swap */ + +#define __PAGE_PROT_UWAUX 0x040 +#define __PAGE_PROT_USER 0x080 +#define __PAGE_PROT_WRITE 0x100 + +#define _PAGE_PRESENTV (_PAGE_PRESENT|_PAGE_VALID) +#define _PAGE_PROTNONE 0x000 /* If not present */ + +#ifndef __ASSEMBLY__ + +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) + +#define _PAGE_TABLE (_PAGE_PRESENTV | _PAGE_PROT_WKNU | _PAGE_ACCESSED | _PAGE_DIRTY) +#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) + +#define __PAGE_NONE (_PAGE_PRESENTV | _PAGE_PROT_RKNU | _PAGE_ACCESSED | _PAGE_CACHE) +#define __PAGE_SHARED (_PAGE_PRESENTV | _PAGE_PROT_WKWU | _PAGE_ACCESSED | _PAGE_CACHE) +#define __PAGE_COPY (_PAGE_PRESENTV | _PAGE_PROT_RKRU | _PAGE_ACCESSED | _PAGE_CACHE) +#define __PAGE_READONLY (_PAGE_PRESENTV | _PAGE_PROT_RKRU | _PAGE_ACCESSED | _PAGE_CACHE) + +#define PAGE_NONE __pgprot(__PAGE_NONE | _PAGE_NX) +#define PAGE_SHARED_NOEXEC __pgprot(__PAGE_SHARED | _PAGE_NX) +#define PAGE_COPY_NOEXEC __pgprot(__PAGE_COPY | _PAGE_NX) +#define PAGE_READONLY_NOEXEC __pgprot(__PAGE_READONLY | _PAGE_NX) +#define PAGE_SHARED_EXEC __pgprot(__PAGE_SHARED) +#define PAGE_COPY_EXEC __pgprot(__PAGE_COPY) +#define PAGE_READONLY_EXEC __pgprot(__PAGE_READONLY) +#define PAGE_COPY PAGE_COPY_NOEXEC +#define PAGE_READONLY PAGE_READONLY_NOEXEC +#define PAGE_SHARED PAGE_SHARED_EXEC + +#define __PAGE_KERNEL_BASE (_PAGE_PRESENTV | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_GLOBAL) + +#define __PAGE_KERNEL (__PAGE_KERNEL_BASE | _PAGE_PROT_WKNU | _PAGE_CACHE | _PAGE_NX) +#define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL_BASE | _PAGE_PROT_WKNU | _PAGE_NX) +#define __PAGE_KERNEL_EXEC (__PAGE_KERNEL & ~_PAGE_NX) +#define __PAGE_KERNEL_RO (__PAGE_KERNEL_BASE | _PAGE_PROT_RKNU | _PAGE_CACHE | _PAGE_NX) +#define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE) +#define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE) + +#define PAGE_KERNEL __pgprot(__PAGE_KERNEL) +#define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO) +#define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC) +#define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE) +#define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE) +#define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC) + +/* + * Whilst the MN10300 can do page protection for execute (given separate data + * and insn TLBs), we are not supporting it at the moment. Write permission, + * however, always implies read permission (but not execute permission). + */ +#define __P000 PAGE_NONE +#define __P001 PAGE_READONLY_NOEXEC +#define __P010 PAGE_COPY_NOEXEC +#define __P011 PAGE_COPY_NOEXEC +#define __P100 PAGE_READONLY_EXEC +#define __P101 PAGE_READONLY_EXEC +#define __P110 PAGE_COPY_EXEC +#define __P111 PAGE_COPY_EXEC + +#define __S000 PAGE_NONE +#define __S001 PAGE_READONLY_NOEXEC +#define __S010 PAGE_SHARED_NOEXEC +#define __S011 PAGE_SHARED_NOEXEC +#define __S100 PAGE_READONLY_EXEC +#define __S101 PAGE_READONLY_EXEC +#define __S110 PAGE_SHARED_EXEC +#define __S111 PAGE_SHARED_EXEC + +/* + * Define this to warn about kernel memory accesses that are + * done without a 'verify_area(VERIFY_WRITE,..)' + */ +#undef TEST_VERIFY_AREA + +#define pte_present(x) (pte_val(x) & _PAGE_VALID) +#define pte_clear(mm, addr, xp) \ +do { \ + set_pte_at((mm), (addr), (xp), __pte(0)); \ +} while (0) + +#define pmd_none(x) (!pmd_val(x)) +#define pmd_present(x) (!pmd_none(x)) +#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0) +#define pmd_bad(x) 0 + + +#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT)) + +#ifndef __ASSEMBLY__ + +/* + * The following only work if pte_present() is true. + * Undefined behaviour if not.. + */ +static inline int pte_user(pte_t pte) { return pte_val(pte) & __PAGE_PROT_USER; } +static inline int pte_read(pte_t pte) { return pte_val(pte) & __PAGE_PROT_USER; } +static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } +static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } +static inline int pte_write(pte_t pte) { return pte_val(pte) & __PAGE_PROT_WRITE; } + +/* + * The following only works if pte_present() is not true. + */ +static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } + +static inline pte_t pte_rdprotect(pte_t pte) +{ + pte_val(pte) &= ~(__PAGE_PROT_USER|__PAGE_PROT_UWAUX); return pte; +} +static inline pte_t pte_exprotect(pte_t pte) +{ + pte_val(pte) |= _PAGE_NX; return pte; +} + +static inline pte_t pte_wrprotect(pte_t pte) +{ + pte_val(pte) &= ~(__PAGE_PROT_WRITE|__PAGE_PROT_UWAUX); return pte; +} + +static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } +static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } +static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; } +static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; } +static inline pte_t pte_mkexec(pte_t pte) { pte_val(pte) &= ~_PAGE_NX; return pte; } + +static inline pte_t pte_mkread(pte_t pte) +{ + pte_val(pte) |= __PAGE_PROT_USER; + if (pte_write(pte)) + pte_val(pte) |= __PAGE_PROT_UWAUX; + return pte; +} +static inline pte_t pte_mkwrite(pte_t pte) +{ + pte_val(pte) |= __PAGE_PROT_WRITE; + if (pte_val(pte) & __PAGE_PROT_USER) + pte_val(pte) |= __PAGE_PROT_UWAUX; + return pte; +} + +#define pte_ERROR(e) \ + printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \ + __FILE__, __LINE__, pte_val(e)) +#define pgd_ERROR(e) \ + printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \ + __FILE__, __LINE__, pgd_val(e)) + +/* + * The "pgd_xxx()" functions here are trivial for a folded two-level + * setup: the pgd is never bad, and a pmd always exists (as it's folded + * into the pgd entry) + */ +#define pgd_clear(xp) do { } while (0) + +/* + * Certain architectures need to do special things when PTEs + * within a page table are directly modified. Thus, the following + * hook is made available. + */ +#define set_pte(pteptr, pteval) (*(pteptr) = pteval) +#define set_pte_at(mm, addr, ptep, pteval) set_pte((ptep), (pteval)) +#define set_pte_atomic(pteptr, pteval) set_pte((pteptr), (pteval)) + +/* + * (pmds are folded into pgds so this doesn't get actually called, + * but the define is needed for a generic inline function.) + */ +#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) + +#define ptep_get_and_clear(mm, addr, ptep) \ + __pte(xchg(&(ptep)->pte, 0)) +#define pte_same(a, b) (pte_val(a) == pte_val(b)) +#define pte_page(x) pfn_to_page(pte_pfn(x)) +#define pte_none(x) (!pte_val(x)) +#define pte_pfn(x) ((unsigned long) (pte_val(x) >> PAGE_SHIFT)) +#define __pfn_addr(pfn) ((pfn) << PAGE_SHIFT) +#define pfn_pte(pfn, prot) __pte(__pfn_addr(pfn) | pgprot_val(prot)) +#define pfn_pmd(pfn, prot) __pmd(__pfn_addr(pfn) | pgprot_val(prot)) + +/* + * All present user pages are user-executable: + */ +static inline int pte_exec(pte_t pte) +{ + return pte_user(pte); +} + +/* + * All present pages are kernel-executable: + */ +static inline int pte_exec_kernel(pte_t pte) +{ + return 1; +} + +/* + * Bits 0 and 1 are taken, split up the 29 bits of offset + * into this range: + */ +#define PTE_FILE_MAX_BITS 29 + +#define pte_to_pgoff(pte) (pte_val(pte) >> 2) +#define pgoff_to_pte(off) __pte((off) << 2 | _PAGE_FILE) + +/* Encode and de-code a swap entry */ +#define __swp_type(x) (((x).val >> 2) & 0x3f) +#define __swp_offset(x) ((x).val >> 8) +#define __swp_entry(type, offset) \ + ((swp_entry_t) { ((type) << 2) | ((offset) << 8) }) +#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) +#define __swp_entry_to_pte(x) __pte((x).val) + +static inline +int ptep_test_and_clear_dirty(struct vm_area_struct *vma, unsigned long addr, + pte_t *ptep) +{ + if (!pte_dirty(*ptep)) + return 0; + return test_and_clear_bit(_PAGE_BIT_DIRTY, &ptep->pte); +} + +static inline +int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, + pte_t *ptep) +{ + if (!pte_young(*ptep)) + return 0; + return test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte); +} + +static inline +void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) +{ + pte_val(*ptep) &= ~(__PAGE_PROT_WRITE|__PAGE_PROT_UWAUX); +} + +static inline void ptep_mkdirty(pte_t *ptep) +{ + set_bit(_PAGE_BIT_DIRTY, &ptep->pte); +} + +/* + * Macro to mark a page protection value as "uncacheable". On processors which + * do not support it, this is a no-op. + */ +#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_CACHE) + + +/* + * Conversion functions: convert a page and protection to a page entry, + * and a page entry and page directory to the page they refer to. + */ + +#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) +#define mk_pte_huge(entry) \ + ((entry).pte |= _PAGE_PRESENT | _PAGE_PSE | _PAGE_VALID) + +static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +{ + pte_val(pte) &= _PAGE_CHG_MASK; + pte_val(pte) |= pgprot_val(newprot); + return pte; +} + +#define page_pte(page) page_pte_prot((page), __pgprot(0)) + +#define pmd_page_kernel(pmd) \ + ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) + +#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) + +#define pmd_large(pmd) \ + ((pmd_val(pmd) & (_PAGE_PSE | _PAGE_PRESENT)) == \ + (_PAGE_PSE | _PAGE_PRESENT)) + +/* + * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD] + * + * this macro returns the index of the entry in the pgd page which would + * control the given virtual address + */ +#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) + +/* + * pgd_offset() returns a (pgd_t *) + * pgd_index() is used get the offset into the pgd page's array of pgd_t's; + */ +#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) + +/* + * a shortcut which implies the use of the kernel's pgd, instead + * of a process's + */ +#define pgd_offset_k(address) pgd_offset(&init_mm, address) + +/* + * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD] + * + * this macro returns the index of the entry in the pmd page which would + * control the given virtual address + */ +#define pmd_index(address) \ + (((address) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) + +/* + * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE] + * + * this macro returns the index of the entry in the pte page which would + * control the given virtual address + */ +#define pte_index(address) \ + (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) + +#define pte_offset_kernel(dir, address) \ + ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(address)) + +/* + * Make a given kernel text page executable/non-executable. + * Returns the previous executability setting of that page (which + * is used to restore the previous state). Used by the SMP bootup code. + * NOTE: this is an __init function for security reasons. + */ +static inline int set_kernel_exec(unsigned long vaddr, int enable) +{ + return 0; +} + +#define pte_offset_map(dir, address) \ + ((pte_t *) page_address(pmd_page(*(dir))) + pte_index(address)) +#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address) +#define pte_unmap(pte) do {} while (0) +#define pte_unmap_nested(pte) do {} while (0) + +/* + * The MN10300 has external MMU info in the form of a TLB: this is adapted from + * the kernel page tables containing the necessary information by tlb-mn10300.S + */ +extern void update_mmu_cache(struct vm_area_struct *vma, + unsigned long address, pte_t pte); + +#endif /* !__ASSEMBLY__ */ + +#define kern_addr_valid(addr) (1) + +#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ + remap_pfn_range((vma), (vaddr), (pfn), (size), (prot)) + +#define MK_IOSPACE_PFN(space, pfn) (pfn) +#define GET_IOSPACE(pfn) 0 +#define GET_PFN(pfn) (pfn) + +#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG +#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY +#define __HAVE_ARCH_PTEP_GET_AND_CLEAR +#define __HAVE_ARCH_PTEP_SET_WRPROTECT +#define __HAVE_ARCH_PTEP_MKDIRTY +#define __HAVE_ARCH_PTE_SAME +#include <asm-generic/pgtable.h> + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_PGTABLE_H */ diff --git a/include/asm-mn10300/pio-regs.h b/include/asm-mn10300/pio-regs.h new file mode 100644 index 00000000000..96bc8182d0b --- /dev/null +++ b/include/asm-mn10300/pio-regs.h @@ -0,0 +1,233 @@ +/* MN10300 On-board I/O port module registers + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_PIO_REGS_H +#define _ASM_PIO_REGS_H + +#include <asm/cpu-regs.h> +#include <asm/intctl-regs.h> + +#ifdef __KERNEL__ + +/* I/O port 0 */ +#define P0MD __SYSREG(0xdb000000, u16) /* mode reg */ +#define P0MD_0 0x0003 /* mask */ +#define P0MD_0_IN 0x0000 /* input mode */ +#define P0MD_0_OUT 0x0001 /* output mode */ +#define P0MD_0_TM0IO 0x0002 /* timer 0 I/O mode */ +#define P0MD_0_EYECLK 0x0003 /* test signal output (clock) */ +#define P0MD_1 0x000c +#define P0MD_1_IN 0x0000 +#define P0MD_1_OUT 0x0004 +#define P0MD_1_TM1IO 0x0008 /* timer 1 I/O mode */ +#define P0MD_1_EYED 0x000c /* test signal output (data) */ +#define P0MD_2 0x0030 +#define P0MD_2_IN 0x0000 +#define P0MD_2_OUT 0x0010 +#define P0MD_2_TM2IO 0x0020 /* timer 2 I/O mode */ +#define P0MD_3 0x00c0 +#define P0MD_3_IN 0x0000 +#define P0MD_3_OUT 0x0040 +#define P0MD_3_TM3IO 0x0080 /* timer 3 I/O mode */ +#define P0MD_4 0x0300 +#define P0MD_4_IN 0x0000 +#define P0MD_4_OUT 0x0100 +#define P0MD_4_TM4IO 0x0200 /* timer 4 I/O mode */ +#define P0MD_4_XCTS 0x0300 /* XCTS input for serial port 2 */ +#define P0MD_5 0x0c00 +#define P0MD_5_IN 0x0000 +#define P0MD_5_OUT 0x0400 +#define P0MD_5_TM5IO 0x0800 /* timer 5 I/O mode */ +#define P0MD_6 0x3000 +#define P0MD_6_IN 0x0000 +#define P0MD_6_OUT 0x1000 +#define P0MD_6_TM6IOA 0x2000 /* timer 6 I/O mode A */ +#define P0MD_7 0xc000 +#define P0MD_7_IN 0x0000 +#define P0MD_7_OUT 0x4000 +#define P0MD_7_TM6IOB 0x8000 /* timer 6 I/O mode B */ + +#define P0IN __SYSREG(0xdb000004, u8) /* in reg */ +#define P0OUT __SYSREG(0xdb000008, u8) /* out reg */ + +#define P0TMIO __SYSREG(0xdb00000c, u8) /* TM pin I/O control reg */ +#define P0TMIO_TM0_IN 0x00 +#define P0TMIO_TM0_OUT 0x01 +#define P0TMIO_TM1_IN 0x00 +#define P0TMIO_TM1_OUT 0x02 +#define P0TMIO_TM2_IN 0x00 +#define P0TMIO_TM2_OUT 0x04 +#define P0TMIO_TM3_IN 0x00 +#define P0TMIO_TM3_OUT 0x08 +#define P0TMIO_TM4_IN 0x00 +#define P0TMIO_TM4_OUT 0x10 +#define P0TMIO_TM5_IN 0x00 +#define P0TMIO_TM5_OUT 0x20 +#define P0TMIO_TM6A_IN 0x00 +#define P0TMIO_TM6A_OUT 0x40 +#define P0TMIO_TM6B_IN 0x00 +#define P0TMIO_TM6B_OUT 0x80 + +/* I/O port 1 */ +#define P1MD __SYSREG(0xdb000100, u16) /* mode reg */ +#define P1MD_0 0x0003 /* mask */ +#define P1MD_0_IN 0x0000 /* input mode */ +#define P1MD_0_OUT 0x0001 /* output mode */ +#define P1MD_0_TM7IO 0x0002 /* timer 7 I/O mode */ +#define P1MD_0_ADTRG 0x0003 /* A/D converter trigger mode */ +#define P1MD_1 0x000c +#define P1MD_1_IN 0x0000 +#define P1MD_1_OUT 0x0004 +#define P1MD_1_TM8IO 0x0008 /* timer 8 I/O mode */ +#define P1MD_1_XDMR0 0x000c /* DMA request input 0 mode */ +#define P1MD_2 0x0030 +#define P1MD_2_IN 0x0000 +#define P1MD_2_OUT 0x0010 +#define P1MD_2_TM9IO 0x0020 /* timer 9 I/O mode */ +#define P1MD_2_XDMR1 0x0030 /* DMA request input 1 mode */ +#define P1MD_3 0x00c0 +#define P1MD_3_IN 0x0000 +#define P1MD_3_OUT 0x0040 +#define P1MD_3_TM10IO 0x0080 /* timer 10 I/O mode */ +#define P1MD_3_FRQS0 0x00c0 /* CPU clock multiplier setting input 0 mode */ +#define P1MD_4 0x0300 +#define P1MD_4_IN 0x0000 +#define P1MD_4_OUT 0x0100 +#define P1MD_4_TM11IO 0x0200 /* timer 11 I/O mode */ +#define P1MD_4_FRQS1 0x0300 /* CPU clock multiplier setting input 1 mode */ + +#define P1IN __SYSREG(0xdb000104, u8) /* in reg */ +#define P1OUT __SYSREG(0xdb000108, u8) /* out reg */ +#define P1TMIO __SYSREG(0xdb00010c, u8) /* TM pin I/O control reg */ +#define P1TMIO_TM11_IN 0x00 +#define P1TMIO_TM11_OUT 0x01 +#define P1TMIO_TM10_IN 0x00 +#define P1TMIO_TM10_OUT 0x02 +#define P1TMIO_TM9_IN 0x00 +#define P1TMIO_TM9_OUT 0x04 +#define P1TMIO_TM8_IN 0x00 +#define P1TMIO_TM8_OUT 0x08 +#define P1TMIO_TM7_IN 0x00 +#define P1TMIO_TM7_OUT 0x10 + +/* I/O port 2 */ +#define P2MD __SYSREG(0xdb000200, u16) /* mode reg */ +#define P2MD_0 0x0003 /* mask */ +#define P2MD_0_IN 0x0000 /* input mode */ +#define P2MD_0_OUT 0x0001 /* output mode */ +#define P2MD_0_BOOTBW 0x0003 /* boot bus width selector mode */ +#define P2MD_1 0x000c +#define P2MD_1_IN 0x0000 +#define P2MD_1_OUT 0x0004 +#define P2MD_1_BOOTSEL 0x000c /* boot device selector mode */ +#define P2MD_2 0x0030 +#define P2MD_2_IN 0x0000 +#define P2MD_2_OUT 0x0010 +#define P2MD_3 0x00c0 +#define P2MD_3_IN 0x0000 +#define P2MD_3_OUT 0x0040 +#define P2MD_3_CKIO 0x00c0 /* mode */ +#define P2MD_4 0x0300 +#define P2MD_4_IN 0x0000 +#define P2MD_4_OUT 0x0100 +#define P2MD_4_CMOD 0x0300 /* mode */ + +#define P2IN __SYSREG(0xdb000204, u8) /* in reg */ +#define P2OUT __SYSREG(0xdb000208, u8) /* out reg */ +#define P2TMIO __SYSREG(0xdb00020c, u8) /* TM pin I/O control reg */ + +/* I/O port 3 */ +#define P3MD __SYSREG(0xdb000300, u16) /* mode reg */ +#define P3MD_0 0x0003 /* mask */ +#define P3MD_0_IN 0x0000 /* input mode */ +#define P3MD_0_OUT 0x0001 /* output mode */ +#define P3MD_0_AFRXD 0x0002 /* AFR interface mode */ +#define P3MD_1 0x000c +#define P3MD_1_IN 0x0000 +#define P3MD_1_OUT 0x0004 +#define P3MD_1_AFTXD 0x0008 /* AFR interface mode */ +#define P3MD_2 0x0030 +#define P3MD_2_IN 0x0000 +#define P3MD_2_OUT 0x0010 +#define P3MD_2_AFSCLK 0x0020 /* AFR interface mode */ +#define P3MD_3 0x00c0 +#define P3MD_3_IN 0x0000 +#define P3MD_3_OUT 0x0040 +#define P3MD_3_AFFS 0x0080 /* AFR interface mode */ +#define P3MD_4 0x0300 +#define P3MD_4_IN 0x0000 +#define P3MD_4_OUT 0x0100 +#define P3MD_4_AFEHC 0x0200 /* AFR interface mode */ + +#define P3IN __SYSREG(0xdb000304, u8) /* in reg */ +#define P3OUT __SYSREG(0xdb000308, u8) /* out reg */ + +/* I/O port 4 */ +#define P4MD __SYSREG(0xdb000400, u16) /* mode reg */ +#define P4MD_0 0x0003 /* mask */ +#define P4MD_0_IN 0x0000 /* input mode */ +#define P4MD_0_OUT 0x0001 /* output mode */ +#define P4MD_0_SCL0 0x0002 /* I2C/serial mode */ +#define P4MD_1 0x000c +#define P4MD_1_IN 0x0000 +#define P4MD_1_OUT 0x0004 +#define P4MD_1_SDA0 0x0008 +#define P4MD_2 0x0030 +#define P4MD_2_IN 0x0000 +#define P4MD_2_OUT 0x0010 +#define P4MD_2_SCL1 0x0020 +#define P4MD_3 0x00c0 +#define P4MD_3_IN 0x0000 +#define P4MD_3_OUT 0x0040 +#define P4MD_3_SDA1 0x0080 +#define P4MD_4 0x0300 +#define P4MD_4_IN 0x0000 +#define P4MD_4_OUT 0x0100 +#define P4MD_4_SBO0 0x0200 +#define P4MD_5 0x0c00 +#define P4MD_5_IN 0x0000 +#define P4MD_5_OUT 0x0400 +#define P4MD_5_SBO1 0x0800 +#define P4MD_6 0x3000 +#define P4MD_6_IN 0x0000 +#define P4MD_6_OUT 0x1000 +#define P4MD_6_SBT0 0x2000 +#define P4MD_7 0xc000 +#define P4MD_7_IN 0x0000 +#define P4MD_7_OUT 0x4000 +#define P4MD_7_SBT1 0x8000 + +#define P4IN __SYSREG(0xdb000404, u8) /* in reg */ +#define P4OUT __SYSREG(0xdb000408, u8) /* out reg */ + +/* I/O port 5 */ +#define P5MD __SYSREG(0xdb000500, u16) /* mode reg */ +#define P5MD_0 0x0003 /* mask */ +#define P5MD_0_IN 0x0000 /* input mode */ +#define P5MD_0_OUT 0x0001 /* output mode */ +#define P5MD_0_IRTXD 0x0002 /* IrDA mode */ +#define P5MD_0_SOUT 0x0004 /* serial mode */ +#define P5MD_1 0x000c +#define P5MD_1_IN 0x0000 +#define P5MD_1_OUT 0x0004 +#define P5MD_1_IRRXDS 0x0008 /* IrDA mode */ +#define P5MD_1_SIN 0x000c /* serial mode */ +#define P5MD_2 0x0030 +#define P5MD_2_IN 0x0000 +#define P5MD_2_OUT 0x0010 +#define P5MD_2_IRRXDF 0x0020 /* IrDA mode */ + +#define P5IN __SYSREG(0xdb000504, u8) /* in reg */ +#define P5OUT __SYSREG(0xdb000508, u8) /* out reg */ + + +#endif /* __KERNEL__ */ + +#endif /* _ASM_PIO_REGS_H */ diff --git a/include/asm-mn10300/poll.h b/include/asm-mn10300/poll.h new file mode 100644 index 00000000000..c98509d3149 --- /dev/null +++ b/include/asm-mn10300/poll.h @@ -0,0 +1 @@ +#include <asm-generic/poll.h> diff --git a/include/asm-mn10300/posix_types.h b/include/asm-mn10300/posix_types.h new file mode 100644 index 00000000000..077567c3779 --- /dev/null +++ b/include/asm-mn10300/posix_types.h @@ -0,0 +1,132 @@ +/* MN10300 POSIX types + * + * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_POSIX_TYPES_H +#define _ASM_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_timer_t; +typedef int __kernel_clockid_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; +typedef unsigned short __kernel_old_dev_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +static inline void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); +} + +#undef __FD_CLR +static inline void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); +} + + +#undef __FD_ISSET +static inline int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; +} + +/* + * This will unroll the loop for the normal constant case (8 ints, + * for a 256-bit fd_set) + */ +#undef __FD_ZERO +static inline void __FD_ZERO(__kernel_fd_set *__p) +{ + unsigned long *__tmp = __p->fds_bits; + int __i; + + if (__builtin_constant_p(__FDSET_LONGS)) { + switch (__FDSET_LONGS) { + case 16: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + __tmp[ 8] = 0; __tmp[ 9] = 0; + __tmp[10] = 0; __tmp[11] = 0; + __tmp[12] = 0; __tmp[13] = 0; + __tmp[14] = 0; __tmp[15] = 0; + return; + + case 8: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + return; + + case 4: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + return; + } + } + __i = __FDSET_LONGS; + while (__i) { + __i--; + *__tmp = 0; + __tmp++; + } +} + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif /* _ASM_POSIX_TYPES_H */ diff --git a/include/asm-mn10300/proc-mn103e010/cache.h b/include/asm-mn10300/proc-mn103e010/cache.h new file mode 100644 index 00000000000..bdc1f9a59b4 --- /dev/null +++ b/include/asm-mn10300/proc-mn103e010/cache.h @@ -0,0 +1,33 @@ +/* MN103E010 Cache specification + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_PROC_CACHE_H +#define _ASM_PROC_CACHE_H + +/* L1 cache */ + +#define L1_CACHE_NWAYS 4 /* number of ways in caches */ +#define L1_CACHE_NENTRIES 256 /* number of entries in each way */ +#define L1_CACHE_BYTES 16 /* bytes per entry */ +#define L1_CACHE_SHIFT 4 /* shift for bytes per entry */ +#define L1_CACHE_WAYDISP 0x1000 /* displacement of one way from the next */ + +#define L1_CACHE_TAG_VALID 0x00000001 /* cache tag valid bit */ +#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */ +#define L1_CACHE_TAG_ENTRY 0x00000ff0 /* cache tag entry address mask */ +#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */ + +/* + * specification of the interval between interrupt checking intervals whilst + * managing the cache with the interrupts disabled + */ +#define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL 4 + +#endif /* _ASM_PROC_CACHE_H */ diff --git a/include/asm-mn10300/proc-mn103e010/clock.h b/include/asm-mn10300/proc-mn103e010/clock.h new file mode 100644 index 00000000000..caf99835063 --- /dev/null +++ b/include/asm-mn10300/proc-mn103e010/clock.h @@ -0,0 +1,18 @@ +/* MN103E010-specific clocks + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_PROC_CLOCK_H +#define _ASM_PROC_CLOCK_H + +#include <asm/unit/clock.h> + +#define MN10300_WDCLK MN10300_IOCLK + +#endif /* _ASM_PROC_CLOCK_H */ diff --git a/include/asm-mn10300/proc-mn103e010/irq.h b/include/asm-mn10300/proc-mn103e010/irq.h new file mode 100644 index 00000000000..aa6ee8f98b1 --- /dev/null +++ b/include/asm-mn10300/proc-mn103e010/irq.h @@ -0,0 +1,34 @@ +/* MN103E010 On-board interrupt controller numbers + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_PROC_IRQ_H +#define _ASM_PROC_IRQ_H + +#ifdef __KERNEL__ + +#define GxICR_NUM_IRQS 42 + +#define GxICR_NUM_XIRQS 8 + +#define XIRQ0 34 +#define XIRQ1 35 +#define XIRQ2 36 +#define XIRQ3 37 +#define XIRQ4 38 +#define XIRQ5 39 +#define XIRQ6 40 +#define XIRQ7 41 + +#define XIRQ2IRQ(num) (XIRQ0 + num) + +#endif /* __KERNEL__ */ + +#endif /* _ASM_PROC_IRQ_H */ diff --git a/include/asm-mn10300/proc-mn103e010/proc.h b/include/asm-mn10300/proc-mn103e010/proc.h new file mode 100644 index 00000000000..22a2b93f70b --- /dev/null +++ b/include/asm-mn10300/proc-mn103e010/proc.h @@ -0,0 +1,18 @@ +/* MN103E010 Processor description + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_PROC_PROC_H +#define _ASM_PROC_PROC_H + +#define PROCESSOR_VENDOR_NAME "Matsushita" +#define PROCESSOR_MODEL_NAME "mn103e010" + +#endif /* _ASM_PROC_PROC_H */ diff --git a/include/asm-mn10300/processor.h b/include/asm-mn10300/processor.h new file mode 100644 index 00000000000..f1b081f5346 --- /dev/null +++ b/include/asm-mn10300/processor.h @@ -0,0 +1,186 @@ +/* MN10300 Processor specifics + * + * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_PROCESSOR_H +#define _ASM_PROCESSOR_H + +#include <asm/page.h> +#include <asm/ptrace.h> +#include <asm/cpu-regs.h> +#include <linux/threads.h> + +/* Forward declaration, a strange C thing */ +struct task_struct; +struct mm_struct; + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() \ +({ \ + void *__pc; \ + asm("mov pc,%0" : "=a"(__pc)); \ + __pc; \ +}) + +extern void show_registers(struct pt_regs *regs); + +/* + * CPU type and hardware bug flags. Kept separately for each CPU. + * Members of this structure are referenced in head.S, so think twice + * before touching them. [mj] + */ + +struct mn10300_cpuinfo { + int type; + unsigned long loops_per_sec; + char hard_math; + unsigned long *pgd_quick; + unsigned long *pte_quick; + unsigned long pgtable_cache_sz; +}; + +extern struct mn10300_cpuinfo boot_cpu_data; + +#define cpu_data &boot_cpu_data +#define current_cpu_data boot_cpu_data + +extern void identify_cpu(struct mn10300_cpuinfo *); +extern void print_cpu_info(struct mn10300_cpuinfo *); +extern void dodgy_tsc(void); +#define cpu_relax() do {} while (0) + +/* + * User space process size: 1.75GB (default). + */ +#define TASK_SIZE 0x70000000 + +/* + * Where to put the userspace stack by default + */ +#define STACK_TOP 0x70000000 +#define STACK_TOP_MAX STACK_TOP + +/* This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE 0x30000000 + +typedef struct { + unsigned long seg; +} mm_segment_t; + +struct fpu_state_struct { + unsigned long fs[32]; /* fpu registers */ + unsigned long fpcr; /* fpu control register */ +}; + +struct thread_struct { + struct pt_regs *uregs; /* userspace register frame */ + unsigned long pc; /* kernel PC */ + unsigned long sp; /* kernel SP */ + unsigned long a3; /* kernel FP */ + unsigned long wchan; + unsigned long usp; + struct pt_regs *__frame; + unsigned long fpu_flags; +#define THREAD_USING_FPU 0x00000001 /* T if this task is using the FPU */ + struct fpu_state_struct fpu_state; +}; + +#define INIT_THREAD \ +{ \ + .uregs = init_uregs, \ + .pc = 0, \ + .sp = 0, \ + .a3 = 0, \ + .wchan = 0, \ + .__frame = NULL, \ +} + +#define INIT_MMAP \ +{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, \ + NULL, NULL } + +/* + * do necessary setup to start up a newly executed thread + * - need to discard the frame stacked by the kernel thread invoking the execve + * syscall (see RESTORE_ALL macro) + */ +#define start_thread(regs, new_pc, new_sp) do { \ + set_fs(USER_DS); \ + __frame = current->thread.uregs; \ + __frame->epsw = EPSW_nSL | EPSW_IE | EPSW_IM; \ + __frame->pc = new_pc; \ + __frame->sp = new_sp; \ +} while (0) + +/* Free all resources held by a thread. */ +extern void release_thread(struct task_struct *); + +/* Prepare to copy thread state - unlazy all lazy status */ +extern void prepare_to_copy(struct task_struct *tsk); + +/* + * create a kernel thread without removing it from tasklists + */ +extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); + +/* + * Return saved PC of a blocked thread. + */ +extern unsigned long thread_saved_pc(struct task_struct *tsk); + +unsigned long get_wchan(struct task_struct *p); + +#define task_pt_regs(task) \ +({ \ + struct pt_regs *__regs__; \ + __regs__ = (struct pt_regs *) (KSTK_TOP(task_stack_page(task)) - 8); \ + __regs__ - 1; \ +}) + +#define KSTK_EIP(task) (task_pt_regs(task)->pc) +#define KSTK_ESP(task) (task_pt_regs(task)->sp) + +#define KSTK_TOP(info) \ +({ \ + (unsigned long)(info) + THREAD_SIZE; \ +}) + +#define ARCH_HAS_PREFETCH +#define ARCH_HAS_PREFETCHW + +static inline void prefetch(const void *x) +{ +#ifndef CONFIG_MN10300_CACHE_DISABLED +#ifdef CONFIG_MN10300_PROC_MN103E010 + asm volatile ("nop; nop; dcpf (%0)" : : "r"(x)); +#else + asm volatile ("dcpf (%0)" : : "r"(x)); +#endif +#endif +} + +static inline void prefetchw(const void *x) +{ +#ifndef CONFIG_MN10300_CACHE_DISABLED +#ifdef CONFIG_MN10300_PROC_MN103E010 + asm volatile ("nop; nop; dcpf (%0)" : : "r"(x)); +#else + asm volatile ("dcpf (%0)" : : "r"(x)); +#endif +#endif +} + +#endif /* _ASM_PROCESSOR_H */ diff --git a/include/asm-mn10300/ptrace.h b/include/asm-mn10300/ptrace.h new file mode 100644 index 00000000000..b3684689fcc --- /dev/null +++ b/include/asm-mn10300/ptrace.h @@ -0,0 +1,99 @@ +/* MN10300 Exception frame layout and ptrace constants + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_PTRACE_H +#define _ASM_PTRACE_H + +#define PT_A3 0 +#define PT_A2 1 +#define PT_D3 2 +#define PT_D2 3 +#define PT_MCVF 4 +#define PT_MCRL 5 +#define PT_MCRH 6 +#define PT_MDRQ 7 +#define PT_E1 8 +#define PT_E0 9 +#define PT_E7 10 +#define PT_E6 11 +#define PT_E5 12 +#define PT_E4 13 +#define PT_E3 14 +#define PT_E2 15 +#define PT_SP 16 +#define PT_LAR 17 +#define PT_LIR 18 +#define PT_MDR 19 +#define PT_A1 20 +#define PT_A0 21 +#define PT_D1 22 +#define PT_D0 23 +#define PT_ORIG_D0 24 +#define PT_EPSW 25 +#define PT_PC 26 +#define NR_PTREGS 27 + +#ifndef __ASSEMBLY__ +/* + * This defines the way registers are stored in the event of an exception + * - the strange order is due to the MOVM instruction + */ +struct pt_regs { + unsigned long a3; /* syscall arg 3 */ + unsigned long a2; /* syscall arg 4 */ + unsigned long d3; /* syscall arg 5 */ + unsigned long d2; /* syscall arg 6 */ + unsigned long mcvf; + unsigned long mcrl; + unsigned long mcrh; + unsigned long mdrq; + unsigned long e1; + unsigned long e0; + unsigned long e7; + unsigned long e6; + unsigned long e5; + unsigned long e4; + unsigned long e3; + unsigned long e2; + unsigned long sp; + unsigned long lar; + unsigned long lir; + unsigned long mdr; + unsigned long a1; + unsigned long a0; /* syscall arg 1 */ + unsigned long d1; /* syscall arg 2 */ + unsigned long d0; /* syscall ret */ + struct pt_regs *next; /* next frame pointer */ + unsigned long orig_d0; /* syscall number */ + unsigned long epsw; + unsigned long pc; +}; +#endif + +extern struct pt_regs *__frame; /* current frame pointer */ + +/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 +#define PTRACE_GETFPREGS 14 +#define PTRACE_SETFPREGS 15 + +/* options set using PTRACE_SETOPTIONS */ +#define PTRACE_O_TRACESYSGOOD 0x00000001 + +#if defined(__KERNEL__) && !defined(__ASSEMBLY__) +#define user_mode(regs) (((regs)->epsw & EPSW_nSL) == EPSW_nSL) +#define instruction_pointer(regs) ((regs)->pc) +extern void show_regs(struct pt_regs *); +#endif + +#define profile_pc(regs) ((regs)->pc) + +#endif /* _ASM_PTRACE_H */ diff --git a/include/asm-mn10300/reset-regs.h b/include/asm-mn10300/reset-regs.h new file mode 100644 index 00000000000..174523d5013 --- /dev/null +++ b/include/asm-mn10300/reset-regs.h @@ -0,0 +1,64 @@ +/* MN10300 Reset controller and watchdog timer definitions + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_RESET_REGS_H +#define _ASM_RESET_REGS_H + +#include <asm/cpu-regs.h> +#include <asm/exceptions.h> + +#ifdef __KERNEL__ + +#ifdef CONFIG_MN10300_WD_TIMER +#define ARCH_HAS_NMI_WATCHDOG /* See include/linux/nmi.h */ +#endif + +/* + * watchdog timer registers + */ +#define WDBC __SYSREGC(0xc0001000, u8) /* watchdog binary counter reg */ + +#define WDCTR __SYSREG(0xc0001002, u8) /* watchdog timer control reg */ +#define WDCTR_WDCK 0x07 /* clock source selection */ +#define WDCTR_WDCK_256th 0x00 /* - OSCI/256 */ +#define WDCTR_WDCK_1024th 0x01 /* - OSCI/1024 */ +#define WDCTR_WDCK_2048th 0x02 /* - OSCI/2048 */ +#define WDCTR_WDCK_16384th 0x03 /* - OSCI/16384 */ +#define WDCTR_WDCK_65536th 0x04 /* - OSCI/65536 */ +#define WDCTR_WDRST 0x40 /* binary counter reset */ +#define WDCTR_WDCNE 0x80 /* watchdog timer enable */ + +#define RSTCTR __SYSREG(0xc0001004, u8) /* reset control reg */ +#define RSTCTR_CHIPRST 0x01 /* chip reset */ +#define RSTCTR_DBFRST 0x02 /* double fault reset flag */ +#define RSTCTR_WDTRST 0x04 /* watchdog timer reset flag */ +#define RSTCTR_WDREN 0x08 /* watchdog timer reset enable */ + +#ifndef __ASSEMBLY__ + +static inline void mn10300_proc_hard_reset(void) +{ + RSTCTR &= ~RSTCTR_CHIPRST; + RSTCTR |= RSTCTR_CHIPRST; +} + +extern unsigned int watchdog_alert_counter; + +extern void watchdog_go(void); +extern asmlinkage void watchdog_handler(void); +extern asmlinkage +void watchdog_interrupt(struct pt_regs *, enum exception_code); + +#endif + +#endif /* __KERNEL__ */ + +#endif /* _ASM_RESET_REGS_H */ diff --git a/include/asm-mn10300/resource.h b/include/asm-mn10300/resource.h new file mode 100644 index 00000000000..04bc4db8921 --- /dev/null +++ b/include/asm-mn10300/resource.h @@ -0,0 +1 @@ +#include <asm-generic/resource.h> diff --git a/include/asm-mn10300/rtc-regs.h b/include/asm-mn10300/rtc-regs.h new file mode 100644 index 00000000000..c42deefaec1 --- /dev/null +++ b/include/asm-mn10300/rtc-regs.h @@ -0,0 +1,86 @@ +/* MN10300 on-chip Real-Time Clock registers + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_RTC_REGS_H +#define _ASM_RTC_REGS_H + +#include <asm/intctl-regs.h> + +#ifdef __KERNEL__ + +#define RTSCR __SYSREG(0xd8600000, u8) /* RTC seconds count reg */ +#define RTSAR __SYSREG(0xd8600001, u8) /* RTC seconds alarm reg */ +#define RTMCR __SYSREG(0xd8600002, u8) /* RTC minutes count reg */ +#define RTMAR __SYSREG(0xd8600003, u8) /* RTC minutes alarm reg */ +#define RTHCR __SYSREG(0xd8600004, u8) /* RTC hours count reg */ +#define RTHAR __SYSREG(0xd8600005, u8) /* RTC hours alarm reg */ +#define RTDWCR __SYSREG(0xd8600006, u8) /* RTC day of the week count reg */ +#define RTDMCR __SYSREG(0xd8600007, u8) /* RTC days count reg */ +#define RTMTCR __SYSREG(0xd8600008, u8) /* RTC months count reg */ +#define RTYCR __SYSREG(0xd8600009, u8) /* RTC years count reg */ + +#define RTCRA __SYSREG(0xd860000a, u8)/* RTC control reg A */ +#define RTCRA_RS 0x0f /* periodic timer interrupt cycle setting */ +#define RTCRA_RS_NONE 0x00 /* - off */ +#define RTCRA_RS_3_90625ms 0x01 /* - 3.90625ms (1/256s) */ +#define RTCRA_RS_7_8125ms 0x02 /* - 7.8125ms (1/128s) */ +#define RTCRA_RS_122_070us 0x03 /* - 122.070us (1/8192s) */ +#define RTCRA_RS_244_141us 0x04 /* - 244.141us (1/4096s) */ +#define RTCRA_RS_488_281us 0x05 /* - 488.281us (1/2048s) */ +#define RTCRA_RS_976_5625us 0x06 /* - 976.5625us (1/1024s) */ +#define RTCRA_RS_1_953125ms 0x07 /* - 1.953125ms (1/512s) */ +#define RTCRA_RS_3_90624ms 0x08 /* - 3.90624ms (1/256s) */ +#define RTCRA_RS_7_8125ms_b 0x09 /* - 7.8125ms (1/128s) */ +#define RTCRA_RS_15_625ms 0x0a /* - 15.625ms (1/64s) */ +#define RTCRA_RS_31_25ms 0x0b /* - 31.25ms (1/32s) */ +#define RTCRA_RS_62_5ms 0x0c /* - 62.5ms (1/16s) */ +#define RTCRA_RS_125ms 0x0d /* - 125ms (1/8s) */ +#define RTCRA_RS_250ms 0x0e /* - 250ms (1/4s) */ +#define RTCRA_RS_500ms 0x0f /* - 500ms (1/2s) */ +#define RTCRA_DVR 0x40 /* divider reset */ +#define RTCRA_UIP 0x80 /* clock update flag */ + +#define RTCRB __SYSREG(0xd860000b, u8) /* RTC control reg B */ +#define RTCRB_DSE 0x01 /* daylight savings time enable */ +#define RTCRB_TM 0x02 /* time format */ +#define RTCRB_TM_12HR 0x00 /* - 12 hour format */ +#define RTCRB_TM_24HR 0x02 /* - 24 hour format */ +#define RTCRB_DM 0x04 /* numeric value format */ +#define RTCRB_DM_BCD 0x00 /* - BCD */ +#define RTCRB_DM_BINARY 0x04 /* - binary */ +#define RTCRB_UIE 0x10 /* update interrupt disable */ +#define RTCRB_AIE 0x20 /* alarm interrupt disable */ +#define RTCRB_PIE 0x40 /* periodic interrupt disable */ +#define RTCRB_SET 0x80 /* clock update enable */ + +#define RTSRC __SYSREG(0xd860000c, u8) /* RTC status reg C */ +#define RTSRC_UF 0x10 /* update end interrupt flag */ +#define RTSRC_AF 0x20 /* alarm interrupt flag */ +#define RTSRC_PF 0x40 /* periodic interrupt flag */ +#define RTSRC_IRQF 0x80 /* interrupt flag */ + +#define RTIRQ 32 +#define RTICR GxICR(RTIRQ) + +/* + * MC146818 RTC compatibility defs for the MN10300 on-chip RTC + */ +#define RTC_PORT(x) 0xd8600000 +#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ + +#define CMOS_READ(addr) __SYSREG(0xd8600000 + (addr), u8) +#define CMOS_WRITE(val, addr) \ + do { __SYSREG(0xd8600000 + (addr), u8) = val; } while (0) + +#define RTC_IRQ RTIRQ + +#endif /* __KERNEL__ */ + +#endif /* _ASM_RTC_REGS_H */ diff --git a/include/asm-mn10300/rtc.h b/include/asm-mn10300/rtc.h new file mode 100644 index 00000000000..c295194cc70 --- /dev/null +++ b/include/asm-mn10300/rtc.h @@ -0,0 +1,41 @@ +/* MN10300 Real time clock definitions + * + * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_RTC_H +#define _ASM_RTC_H + +#ifdef CONFIG_MN10300_RTC + +#include <linux/init.h> + +extern void check_rtc_time(void); +extern void __init calibrate_clock(void); +extern unsigned long __init get_initial_rtc_time(void); + +#else /* !CONFIG_MN10300_RTC */ + +static inline void check_rtc_time(void) +{ +} + +static inline void calibrate_clock(void) +{ +} + +static inline unsigned long get_initial_rtc_time(void) +{ + return 0; +} + +#endif /* !CONFIG_MN10300_RTC */ + +#include <asm-generic/rtc.h> + +#endif /* _ASM_RTC_H */ diff --git a/include/asm-mn10300/scatterlist.h b/include/asm-mn10300/scatterlist.h new file mode 100644 index 00000000000..e29d91dbcf2 --- /dev/null +++ b/include/asm-mn10300/scatterlist.h @@ -0,0 +1,46 @@ +/* MN10300 Scatterlist definitions + * + * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_SCATTERLIST_H +#define _ASM_SCATTERLIST_H + +#include <asm/types.h> + +/* + * Drivers must set either ->address or (preferred) page and ->offset + * to indicate where data must be transferred to/from. + * + * Using page is recommended since it handles highmem data as well as + * low mem. ->address is restricted to data which has a virtual mapping, and + * it will go away in the future. Updating to page can be automated very + * easily -- something like + * + * sg->address = some_ptr; + * + * can be rewritten as + * + * sg_set_page(virt_to_page(some_ptr)); + * sg->offset = (unsigned long) some_ptr & ~PAGE_MASK; + * + * and that's it. There's no excuse for not highmem enabling YOUR driver. /jens + */ +struct scatterlist { +#ifdef CONFIG_DEBUG_SG + unsigned long sg_magic; +#endif + unsigned long page_link; + unsigned int offset; /* for highmem, page offset */ + dma_addr_t dma_address; + unsigned int length; +}; + +#define ISA_DMA_THRESHOLD (0x00ffffff) + +#endif /* _ASM_SCATTERLIST_H */ diff --git a/include/asm-mn10300/sections.h b/include/asm-mn10300/sections.h new file mode 100644 index 00000000000..2b8c5160388 --- /dev/null +++ b/include/asm-mn10300/sections.h @@ -0,0 +1 @@ +#include <asm-generic/sections.h> diff --git a/include/asm-mn10300/semaphore.h b/include/asm-mn10300/semaphore.h new file mode 100644 index 00000000000..5a9e1ad0b25 --- /dev/null +++ b/include/asm-mn10300/semaphore.h @@ -0,0 +1,169 @@ +/* MN10300 Semaphores + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_SEMAPHORE_H +#define _ASM_SEMAPHORE_H + +#ifndef __ASSEMBLY__ + +#include <linux/linkage.h> +#include <linux/wait.h> +#include <linux/spinlock.h> +#include <linux/rwsem.h> + +#define SEMAPHORE_DEBUG 0 + +/* + * the semaphore definition + * - if count is >0 then there are tokens available on the semaphore for down + * to collect + * - if count is <=0 then there are no spare tokens, and anyone that wants one + * must wait + * - if wait_list is not empty, then there are processes waiting for the + * semaphore + */ +struct semaphore { + atomic_t count; /* it's not really atomic, it's + * just that certain modules + * expect to be able to access + * it directly */ + spinlock_t wait_lock; + struct list_head wait_list; +#if SEMAPHORE_DEBUG + unsigned __magic; +#endif +}; + +#if SEMAPHORE_DEBUG +# define __SEM_DEBUG_INIT(name) , (long)&(name).__magic +#else +# define __SEM_DEBUG_INIT(name) +#endif + + +#define __SEMAPHORE_INITIALIZER(name, init_count) \ +{ \ + .count = ATOMIC_INIT(init_count), \ + .wait_lock = __SPIN_LOCK_UNLOCKED((name).wait_lock), \ + .wait_list = LIST_HEAD_INIT((name).wait_list) \ + __SEM_DEBUG_INIT(name) \ +} + +#define __DECLARE_SEMAPHORE_GENERIC(name,count) \ + struct semaphore name = __SEMAPHORE_INITIALIZER(name, count) + +#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1) +#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0) + +static inline void sema_init(struct semaphore *sem, int val) +{ + *sem = (struct semaphore) __SEMAPHORE_INITIALIZER(*sem, val); +} + +static inline void init_MUTEX(struct semaphore *sem) +{ + sema_init(sem, 1); +} + +static inline void init_MUTEX_LOCKED(struct semaphore *sem) +{ + sema_init(sem, 0); +} + +extern void __down(struct semaphore *sem, unsigned long flags); +extern int __down_interruptible(struct semaphore *sem, unsigned long flags); +extern void __up(struct semaphore *sem); + +static inline void down(struct semaphore *sem) +{ + unsigned long flags; + int count; + +#if SEMAPHORE_DEBUG + CHECK_MAGIC(sem->__magic); +#endif + + spin_lock_irqsave(&sem->wait_lock, flags); + count = atomic_read(&sem->count); + if (likely(count > 0)) { + atomic_set(&sem->count, count - 1); + spin_unlock_irqrestore(&sem->wait_lock, flags); + } else { + __down(sem, flags); + } +} + +static inline int down_interruptible(struct semaphore *sem) +{ + unsigned long flags; + int count, ret = 0; + +#if SEMAPHORE_DEBUG + CHECK_MAGIC(sem->__magic); +#endif + + spin_lock_irqsave(&sem->wait_lock, flags); + count = atomic_read(&sem->count); + if (likely(count > 0)) { + atomic_set(&sem->count, count - 1); + spin_unlock_irqrestore(&sem->wait_lock, flags); + } else { + ret = __down_interruptible(sem, flags); + } + return ret; +} + +/* + * non-blockingly attempt to down() a semaphore. + * - returns zero if we acquired it + */ +static inline int down_trylock(struct semaphore *sem) +{ + unsigned long flags; + int count, success = 0; + +#if SEMAPHORE_DEBUG + CHECK_MAGIC(sem->__magic); +#endif + + spin_lock_irqsave(&sem->wait_lock, flags); + count = atomic_read(&sem->count); + if (likely(count > 0)) { + atomic_set(&sem->count, count - 1); + success = 1; + } + spin_unlock_irqrestore(&sem->wait_lock, flags); + return !success; +} + +static inline void up(struct semaphore *sem) +{ + unsigned long flags; + +#if SEMAPHORE_DEBUG + CHECK_MAGIC(sem->__magic); +#endif + + spin_lock_irqsave(&sem->wait_lock, flags); + if (!list_empty(&sem->wait_list)) + __up(sem); + else + atomic_set(&sem->count, atomic_read(&sem->count) + 1); + spin_unlock_irqrestore(&sem->wait_lock, flags); +} + +static inline int sem_getcount(struct semaphore *sem) +{ + return atomic_read(&sem->count); +} + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/include/asm-mn10300/sembuf.h b/include/asm-mn10300/sembuf.h new file mode 100644 index 00000000000..301f3f9d8aa --- /dev/null +++ b/include/asm-mn10300/sembuf.h @@ -0,0 +1,25 @@ +#ifndef _ASM_SEMBUF_H +#define _ASM_SEMBUF_H + +/* + * The semid64_ds structure for MN10300 architecture. + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 64-bit time_t to solve y2038 problem + * - 2 miscellaneous 32-bit values + */ + +struct semid64_ds { + struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ + __kernel_time_t sem_otime; /* last semop time */ + unsigned long __unused1; + __kernel_time_t sem_ctime; /* last change time */ + unsigned long __unused2; + unsigned long sem_nsems; /* no. of semaphores in array */ + unsigned long __unused3; + unsigned long __unused4; +}; + +#endif /* _ASM_SEMBUF_H */ diff --git a/include/asm-mn10300/serial-regs.h b/include/asm-mn10300/serial-regs.h new file mode 100644 index 00000000000..6498469e93a --- /dev/null +++ b/include/asm-mn10300/serial-regs.h @@ -0,0 +1,160 @@ +/* MN10300 on-board serial port module registers + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_SERIAL_REGS_H +#define _ASM_SERIAL_REGS_H + +#include <asm/cpu-regs.h> +#include <asm/intctl-regs.h> + +#ifdef __KERNEL__ + +/* serial port 0 */ +#define SC0CTR __SYSREG(0xd4002000, u16) /* control reg */ +#define SC01CTR_CK 0x0007 /* clock source select */ +#define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */ +#define SC1CTR_CK_TM9UFLOW_8 0x0000 /* - 1/8 timer 9 underflow (serial port 1 only) */ +#define SC01CTR_CK_IOCLK_8 0x0001 /* - 1/8 IOCLK */ +#define SC01CTR_CK_IOCLK_32 0x0002 /* - 1/32 IOCLK */ +#define SC0CTR_CK_TM2UFLOW_2 0x0003 /* - 1/2 timer 2 underflow (serial port 0 only) */ +#define SC1CTR_CK_TM3UFLOW_2 0x0003 /* - 1/2 timer 3 underflow (serial port 1 only) */ +#define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 1 underflow (serial port 0 only) */ +#define SC1CTR_CK_TM1UFLOW_8 0x0004 /* - 1/8 timer 2 underflow (serial port 1 only) */ +#define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */ +#define SC1CTR_CK_TM3UFLOW_8 0x0005 /* - 1/8 timer 3 underflow (serial port 1 only) */ +#define SC01CTR_CK_EXTERN_8 0x0006 /* - 1/8 external closk */ +#define SC01CTR_CK_EXTERN 0x0007 /* - external closk */ +#define SC01CTR_STB 0x0008 /* stop bit select */ +#define SC01CTR_STB_1BIT 0x0000 /* - 1 stop bit */ +#define SC01CTR_STB_2BIT 0x0008 /* - 2 stop bits */ +#define SC01CTR_PB 0x0070 /* parity bit select */ +#define SC01CTR_PB_NONE 0x0000 /* - no parity */ +#define SC01CTR_PB_FIXED0 0x0040 /* - fixed at 0 */ +#define SC01CTR_PB_FIXED1 0x0050 /* - fixed at 1 */ +#define SC01CTR_PB_EVEN 0x0060 /* - even parity */ +#define SC01CTR_PB_ODD 0x0070 /* - odd parity */ +#define SC01CTR_CLN 0x0080 /* character length */ +#define SC01CTR_CLN_7BIT 0x0000 /* - 7 bit chars */ +#define SC01CTR_CLN_8BIT 0x0080 /* - 8 bit chars */ +#define SC01CTR_TOE 0x0100 /* T input output enable */ +#define SC01CTR_OD 0x0200 /* bit order select */ +#define SC01CTR_OD_LSBFIRST 0x0000 /* - LSB first */ +#define SC01CTR_OD_MSBFIRST 0x0200 /* - MSB first */ +#define SC01CTR_MD 0x0c00 /* mode select */ +#define SC01CTR_MD_STST_SYNC 0x0000 /* - start-stop synchronous */ +#define SC01CTR_MD_CLOCK_SYNC1 0x0400 /* - clock synchronous 1 */ +#define SC01CTR_MD_I2C 0x0800 /* - I2C mode */ +#define SC01CTR_MD_CLOCK_SYNC2 0x0c00 /* - clock synchronous 2 */ +#define SC01CTR_IIC 0x1000 /* I2C mode select */ +#define SC01CTR_BKE 0x2000 /* break transmit enable */ +#define SC01CTR_RXE 0x4000 /* receive enable */ +#define SC01CTR_TXE 0x8000 /* transmit enable */ + +#define SC0ICR __SYSREG(0xd4002004, u8) /* interrupt control reg */ +#define SC01ICR_DMD 0x80 /* output data mode */ +#define SC01ICR_TD 0x20 /* transmit DMA trigger cause */ +#define SC01ICR_TI 0x10 /* transmit interrupt cause */ +#define SC01ICR_RES 0x04 /* receive error select */ +#define SC01ICR_RI 0x01 /* receive interrupt cause */ + +#define SC0TXB __SYSREG(0xd4002008, u8) /* transmit buffer reg */ +#define SC0RXB __SYSREG(0xd4002009, u8) /* receive buffer reg */ + +#define SC0STR __SYSREG(0xd400200c, u16) /* status reg */ +#define SC01STR_OEF 0x0001 /* overrun error found */ +#define SC01STR_PEF 0x0002 /* parity error found */ +#define SC01STR_FEF 0x0004 /* framing error found */ +#define SC01STR_RBF 0x0010 /* receive buffer status */ +#define SC01STR_TBF 0x0020 /* transmit buffer status */ +#define SC01STR_RXF 0x0040 /* receive status */ +#define SC01STR_TXF 0x0080 /* transmit status */ +#define SC01STR_STF 0x0100 /* I2C start sequence found */ +#define SC01STR_SPF 0x0200 /* I2C stop sequence found */ + +#define SC0RXIRQ 20 /* timer 0 Receive IRQ */ +#define SC0TXIRQ 21 /* timer 0 Transmit IRQ */ + +#define SC0RXICR GxICR(SC0RXIRQ) /* serial 0 receive intr ctrl reg */ +#define SC0TXICR GxICR(SC0TXIRQ) /* serial 0 transmit intr ctrl reg */ + +/* serial port 1 */ +#define SC1CTR __SYSREG(0xd4002010, u16) /* serial port 1 control */ +#define SC1ICR __SYSREG(0xd4002014, u8) /* interrupt control reg */ +#define SC1TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */ +#define SC1RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */ +#define SC1STR __SYSREG(0xd400201c, u16) /* status reg */ + +#define SC1RXIRQ 22 /* timer 1 Receive IRQ */ +#define SC1TXIRQ 23 /* timer 1 Transmit IRQ */ + +#define SC1RXICR GxICR(SC1RXIRQ) /* serial 1 receive intr ctrl reg */ +#define SC1TXICR GxICR(SC1TXIRQ) /* serial 1 transmit intr ctrl reg */ + +/* serial port 2 */ +#define SC2CTR __SYSREG(0xd4002020, u16) /* control reg */ +#define SC2CTR_CK 0x0003 /* clock source select */ +#define SC2CTR_CK_TM10UFLOW 0x0000 /* - timer 10 underflow */ +#define SC2CTR_CK_TM2UFLOW 0x0001 /* - timer 2 underflow */ +#define SC2CTR_CK_EXTERN 0x0002 /* - external closk */ +#define SC2CTR_CK_TM3UFLOW 0x0003 /* - timer 3 underflow */ +#define SC2CTR_STB 0x0008 /* stop bit select */ +#define SC2CTR_STB_1BIT 0x0000 /* - 1 stop bit */ +#define SC2CTR_STB_2BIT 0x0008 /* - 2 stop bits */ +#define SC2CTR_PB 0x0070 /* parity bit select */ +#define SC2CTR_PB_NONE 0x0000 /* - no parity */ +#define SC2CTR_PB_FIXED0 0x0040 /* - fixed at 0 */ +#define SC2CTR_PB_FIXED1 0x0050 /* - fixed at 1 */ +#define SC2CTR_PB_EVEN 0x0060 /* - even parity */ +#define SC2CTR_PB_ODD 0x0070 /* - odd parity */ +#define SC2CTR_CLN 0x0080 /* character length */ +#define SC2CTR_CLN_7BIT 0x0000 /* - 7 bit chars */ +#define SC2CTR_CLN_8BIT 0x0080 /* - 8 bit chars */ +#define SC2CTR_TWE 0x0100 /* transmit wait enable (enable XCTS control) */ +#define SC2CTR_OD 0x0200 /* bit order select */ +#define SC2CTR_OD_LSBFIRST 0x0000 /* - LSB first */ +#define SC2CTR_OD_MSBFIRST 0x0200 /* - MSB first */ +#define SC2CTR_TWS 0x1000 /* transmit wait select */ +#define SC2CTR_TWS_XCTS_HIGH 0x0000 /* - interrupt TX when XCTS high */ +#define SC2CTR_TWS_XCTS_LOW 0x1000 /* - interrupt TX when XCTS low */ +#define SC2CTR_BKE 0x2000 /* break transmit enable */ +#define SC2CTR_RXE 0x4000 /* receive enable */ +#define SC2CTR_TXE 0x8000 /* transmit enable */ + +#define SC2ICR __SYSREG(0xd4002024, u8) /* interrupt control reg */ +#define SC2ICR_TD 0x20 /* transmit DMA trigger cause */ +#define SC2ICR_TI 0x10 /* transmit interrupt cause */ +#define SC2ICR_RES 0x04 /* receive error select */ +#define SC2ICR_RI 0x01 /* receive interrupt cause */ + +#define SC2TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */ +#define SC2RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */ +#define SC2STR __SYSREG(0xd400201c, u8) /* status reg */ +#define SC2STR_OEF 0x0001 /* overrun error found */ +#define SC2STR_PEF 0x0002 /* parity error found */ +#define SC2STR_FEF 0x0004 /* framing error found */ +#define SC2STR_CTS 0x0008 /* XCTS input pin status (0 means high) */ +#define SC2STR_RBF 0x0010 /* receive buffer status */ +#define SC2STR_TBF 0x0020 /* transmit buffer status */ +#define SC2STR_RXF 0x0040 /* receive status */ +#define SC2STR_TXF 0x0080 /* transmit status */ + +#define SC2TIM __SYSREG(0xd400202d, u8) /* status reg */ + +#define SC2RXIRQ 24 /* serial 2 Receive IRQ */ +#define SC2TXIRQ 25 /* serial 2 Transmit IRQ */ + +#define SC2RXICR GxICR(SC2RXIRQ) /* serial 2 receive intr ctrl reg */ +#define SC2TXICR GxICR(SC2TXIRQ) /* serial 2 transmit intr ctrl reg */ + + +#endif /* __KERNEL__ */ + +#endif /* _ASM_SERIAL_REGS_H */ diff --git a/include/asm-mn10300/serial.h b/include/asm-mn10300/serial.h new file mode 100644 index 00000000000..99785a9dead --- /dev/null +++ b/include/asm-mn10300/serial.h @@ -0,0 +1,36 @@ +/* Standard UART definitions + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +/* + * The ASB2305 has an 18.432 MHz clock the UART + */ +#define BASE_BAUD (18432000 / 16) + +/* Standard COM flags (except for COM4, because of the 8514 problem) */ +#ifdef CONFIG_SERIAL_DETECT_IRQ +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) +#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) +#else +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) +#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF +#endif + +#ifdef CONFIG_SERIAL_MANY_PORTS +#define FOURPORT_FLAGS ASYNC_FOURPORT +#define ACCENT_FLAGS 0 +#define BOCA_FLAGS 0 +#define HUB6_FLAGS 0 +#define RS_TABLE_SIZE 64 +#else +#define RS_TABLE_SIZE +#endif + +#include <asm/unit/serial.h> diff --git a/include/asm-mn10300/setup.h b/include/asm-mn10300/setup.h new file mode 100644 index 00000000000..08356c83228 --- /dev/null +++ b/include/asm-mn10300/setup.h @@ -0,0 +1,17 @@ +/* MN10300 Setup declarations + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_SETUP_H +#define _ASM_SETUP_H + +extern void __init unit_setup(void); +extern void __init unit_init_IRQ(void); + +#endif /* _ASM_SETUP_H */ diff --git a/include/asm-mn10300/shmbuf.h b/include/asm-mn10300/shmbuf.h new file mode 100644 index 00000000000..8f300cc35d6 --- /dev/null +++ b/include/asm-mn10300/shmbuf.h @@ -0,0 +1,42 @@ +#ifndef _ASM_SHMBUF_H +#define _ASM_SHMBUF_H + +/* + * The shmid64_ds structure for MN10300 architecture. + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 64-bit time_t to solve y2038 problem + * - 2 miscellaneous 32-bit values + */ + +struct shmid64_ds { + struct ipc64_perm shm_perm; /* operation perms */ + size_t shm_segsz; /* size of segment (bytes) */ + __kernel_time_t shm_atime; /* last attach time */ + unsigned long __unused1; + __kernel_time_t shm_dtime; /* last detach time */ + unsigned long __unused2; + __kernel_time_t shm_ctime; /* last change time */ + unsigned long __unused3; + __kernel_pid_t shm_cpid; /* pid of creator */ + __kernel_pid_t shm_lpid; /* pid of last operator */ + unsigned long shm_nattch; /* no. of current attaches */ + unsigned long __unused4; + unsigned long __unused5; +}; + +struct shminfo64 { + unsigned long shmmax; + unsigned long shmmin; + unsigned long shmmni; + unsigned long shmseg; + unsigned long shmall; + unsigned long __unused1; + unsigned long __unused2; + unsigned long __unused3; + unsigned long __unused4; +}; + +#endif /* _ASM_SHMBUF_H */ diff --git a/include/asm-mn10300/shmparam.h b/include/asm-mn10300/shmparam.h new file mode 100644 index 00000000000..ab666ed1a07 --- /dev/null +++ b/include/asm-mn10300/shmparam.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SHMPARAM_H +#define _ASM_SHMPARAM_H + +#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ + +#endif /* _ASM_SHMPARAM_H */ diff --git a/include/asm-mn10300/sigcontext.h b/include/asm-mn10300/sigcontext.h new file mode 100644 index 00000000000..4de3afff4ad --- /dev/null +++ b/include/asm-mn10300/sigcontext.h @@ -0,0 +1,52 @@ +/* MN10300 Userspace signal context + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_SIGCONTEXT_H +#define _ASM_SIGCONTEXT_H + +struct fpucontext { + /* Regular FPU environment */ + unsigned long fs[32]; /* fpu registers */ + unsigned long fpcr; /* fpu control register */ +}; + +struct sigcontext { + unsigned long d0; + unsigned long d1; + unsigned long d2; + unsigned long d3; + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; + unsigned long e0; + unsigned long e1; + unsigned long e2; + unsigned long e3; + unsigned long e4; + unsigned long e5; + unsigned long e6; + unsigned long e7; + unsigned long lar; + unsigned long lir; + unsigned long mdr; + unsigned long mcvf; + unsigned long mcrl; + unsigned long mcrh; + unsigned long mdrq; + unsigned long sp; + unsigned long epsw; + unsigned long pc; + struct fpucontext *fpucontext; + unsigned long oldmask; +}; + + +#endif /* _ASM_SIGCONTEXT_H */ diff --git a/include/asm-mn10300/siginfo.h b/include/asm-mn10300/siginfo.h new file mode 100644 index 00000000000..0815d29d82e --- /dev/null +++ b/include/asm-mn10300/siginfo.h @@ -0,0 +1 @@ +#include <asm-generic/siginfo.h> diff --git a/include/asm-mn10300/signal.h b/include/asm-mn10300/signal.h new file mode 100644 index 00000000000..e98817cec5f --- /dev/null +++ b/include/asm-mn10300/signal.h @@ -0,0 +1,171 @@ +/* MN10300 Signal definitions + * + * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_SIGNAL_H +#define _ASM_SIGNAL_H + +#include <linux/types.h> + +/* Avoid too many header ordering problems. */ +struct siginfo; + +#ifdef __KERNEL__ +/* Most things should be clean enough to redefine this at will, if care + is taken to make libc match. */ + +#define _NSIG 64 +#define _NSIG_BPW 32 +#define _NSIG_WORDS (_NSIG / _NSIG_BPW) + +typedef unsigned long old_sigset_t; /* at least 32 bits */ + +typedef struct { + unsigned long sig[_NSIG_WORDS]; +} sigset_t; + +#else +/* Here we must cater to libcs that poke about in kernel headers. */ + +#define NSIG 32 +typedef unsigned long sigset_t; + +#endif /* __KERNEL__ */ + +#define SIGHUP 1 +#define SIGINT 2 +#define SIGQUIT 3 +#define SIGILL 4 +#define SIGTRAP 5 +#define SIGABRT 6 +#define SIGIOT 6 +#define SIGBUS 7 +#define SIGFPE 8 +#define SIGKILL 9 +#define SIGUSR1 10 +#define SIGSEGV 11 +#define SIGUSR2 12 +#define SIGPIPE 13 +#define SIGALRM 14 +#define SIGTERM 15 +#define SIGSTKFLT 16 +#define SIGCHLD 17 +#define SIGCONT 18 +#define SIGSTOP 19 +#define SIGTSTP 20 +#define SIGTTIN 21 +#define SIGTTOU 22 +#define SIGURG 23 +#define SIGXCPU 24 +#define SIGXFSZ 25 +#define SIGVTALRM 26 +#define SIGPROF 27 +#define SIGWINCH 28 +#define SIGIO 29 +#define SIGPOLL SIGIO +/* +#define SIGLOST 29 +*/ +#define SIGPWR 30 +#define SIGSYS 31 +#define SIGUNUSED 31 + +/* These should not be considered constants from userland. */ +#define SIGRTMIN 32 +#define SIGRTMAX (_NSIG-1) + +/* + * SA_FLAGS values: + * + * SA_ONSTACK indicates that a registered stack_t will be used. + * SA_RESTART flag to get restarting signals (which were the default long ago) + * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. + * SA_RESETHAND clears the handler when the signal is delivered. + * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. + * SA_NODEFER prevents the current signal from being masked in the handler. + * + * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single + * Unix names RESETHAND and NODEFER respectively. + */ +#define SA_NOCLDSTOP 0x00000001U +#define SA_NOCLDWAIT 0x00000002U +#define SA_SIGINFO 0x00000004U +#define SA_ONSTACK 0x08000000U +#define SA_RESTART 0x10000000U +#define SA_NODEFER 0x40000000U +#define SA_RESETHAND 0x80000000U + +#define SA_NOMASK SA_NODEFER +#define SA_ONESHOT SA_RESETHAND + +#define SA_RESTORER 0x04000000 + +/* + * sigaltstack controls + */ +#define SS_ONSTACK 1 +#define SS_DISABLE 2 + +#define MINSIGSTKSZ 2048 +#define SIGSTKSZ 8192 + +#include <asm-generic/signal.h> + +#ifdef __KERNEL__ +struct old_sigaction { + __sighandler_t sa_handler; + old_sigset_t sa_mask; + unsigned long sa_flags; + __sigrestore_t sa_restorer; +}; + +struct sigaction { + __sighandler_t sa_handler; + unsigned long sa_flags; + __sigrestore_t sa_restorer; + sigset_t sa_mask; /* mask last for extensibility */ +}; + +struct k_sigaction { + struct sigaction sa; +}; +#else +/* Here we must cater to libcs that poke about in kernel headers. */ + +struct sigaction { + union { + __sighandler_t _sa_handler; + void (*_sa_sigaction)(int, struct siginfo *, void *); + } _u; + sigset_t sa_mask; + unsigned long sa_flags; + void (*sa_restorer)(void); +}; + +#define sa_handler _u._sa_handler +#define sa_sigaction _u._sa_sigaction + +#endif /* __KERNEL__ */ + +typedef struct sigaltstack { + void __user *ss_sp; + int ss_flags; + size_t ss_size; +} stack_t; + +#ifdef __KERNEL__ +#include <asm/sigcontext.h> + + +struct pt_regs; +#define ptrace_signal_deliver(regs, cookie) do { } while (0) + +#endif /* __KERNEL__ */ + +#endif /* _ASM_SIGNAL_H */ diff --git a/include/asm-mn10300/smp.h b/include/asm-mn10300/smp.h new file mode 100644 index 00000000000..4eb8c61b7da --- /dev/null +++ b/include/asm-mn10300/smp.h @@ -0,0 +1,18 @@ +/* MN10300 SMP support + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_SMP_H +#define _ASM_SMP_H + +#ifdef CONFIG_SMP +#error SMP not yet supported for MN10300 +#endif + +#endif diff --git a/include/asm-mn10300/socket.h b/include/asm-mn10300/socket.h new file mode 100644 index 00000000000..99ca648b94c --- /dev/null +++ b/include/asm-mn10300/socket.h @@ -0,0 +1,55 @@ +#ifndef _ASM_SOCKET_H +#define _ASM_SOCKET_H + +#include <asm/sockios.h> + +/* For setsockopt(2) */ +#define SOL_SOCKET 1 + +#define SO_DEBUG 1 +#define SO_REUSEADDR 2 +#define SO_TYPE 3 +#define SO_ERROR 4 +#define SO_DONTROUTE 5 +#define SO_BROADCAST 6 +#define SO_SNDBUF 7 +#define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 +#define SO_KEEPALIVE 9 +#define SO_OOBINLINE 10 +#define SO_NO_CHECK 11 +#define SO_PRIORITY 12 +#define SO_LINGER 13 +#define SO_BSDCOMPAT 14 +/* To add :#define SO_REUSEPORT 15 */ +#define SO_PASSCRED 16 +#define SO_PEERCRED 17 +#define SO_RCVLOWAT 18 +#define SO_SNDLOWAT 19 +#define SO_RCVTIMEO 20 +#define SO_SNDTIMEO 21 + +/* Security levels - as per NRL IPv6 - don't actually do anything */ +#define SO_SECURITY_AUTHENTICATION 22 +#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 +#define SO_SECURITY_ENCRYPTION_NETWORK 24 + +#define SO_BINDTODEVICE 25 + +/* Socket filtering */ +#define SO_ATTACH_FILTER 26 +#define SO_DETACH_FILTER 27 + +#define SO_PEERNAME 28 +#define SO_TIMESTAMP 29 +#define SCM_TIMESTAMP SO_TIMESTAMP + +#define SO_ACCEPTCONN 30 + +#define SO_PEERSEC 31 +#define SO_PASSSEC 34 +#define SO_TIMESTAMPNS 35 +#define SCM_TIMESTAMPNS SO_TIMESTAMPNS + +#endif /* _ASM_SOCKET_H */ diff --git a/include/asm-mn10300/sockios.h b/include/asm-mn10300/sockios.h new file mode 100644 index 00000000000..b03043a1c56 --- /dev/null +++ b/include/asm-mn10300/sockios.h @@ -0,0 +1,13 @@ +#ifndef _ASM_SOCKIOS_H +#define _ASM_SOCKIOS_H + +/* Socket-level I/O control calls. */ +#define FIOSETOWN 0x8901 +#define SIOCSPGRP 0x8902 +#define FIOGETOWN 0x8903 +#define SIOCGPGRP 0x8904 +#define SIOCATMARK 0x8905 +#define SIOCGSTAMP 0x8906 /* Get stamp */ +#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ + +#endif /* _ASM_SOCKIOS_H */ diff --git a/include/asm-mn10300/spinlock.h b/include/asm-mn10300/spinlock.h new file mode 100644 index 00000000000..4bf9c8b169e --- /dev/null +++ b/include/asm-mn10300/spinlock.h @@ -0,0 +1,16 @@ +/* MN10300 spinlock support + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_SPINLOCK_H +#define _ASM_SPINLOCK_H + +#error SMP spinlocks not implemented for MN10300 + +#endif /* _ASM_SPINLOCK_H */ diff --git a/include/asm-mn10300/stat.h b/include/asm-mn10300/stat.h new file mode 100644 index 00000000000..63ff8371cf2 --- /dev/null +++ b/include/asm-mn10300/stat.h @@ -0,0 +1,78 @@ +#ifndef _ASM_STAT_H +#define _ASM_STAT_H + +struct __old_kernel_stat { + unsigned short st_dev; + unsigned short st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned short st_rdev; + unsigned long st_size; + unsigned long st_atime; + unsigned long st_mtime; + unsigned long st_ctime; +}; + +struct stat { + unsigned long st_dev; + unsigned long st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned long st_rdev; + unsigned long st_size; + unsigned long st_blksize; + unsigned long st_blocks; + unsigned long st_atime; + unsigned long st_atime_nsec; + unsigned long st_mtime; + unsigned long st_mtime_nsec; + unsigned long st_ctime; + unsigned long st_ctime_nsec; + unsigned long __unused4; + unsigned long __unused5; +}; + +/* This matches struct stat64 in glibc2.1, hence the absolutely + * insane amounts of padding around dev_t's. + */ +struct stat64 { + unsigned long long st_dev; + unsigned char __pad0[4]; + +#define STAT64_HAS_BROKEN_ST_INO 1 + unsigned long __st_ino; + + unsigned int st_mode; + unsigned int st_nlink; + + unsigned long st_uid; + unsigned long st_gid; + + unsigned long long st_rdev; + unsigned char __pad3[4]; + + long long st_size; + unsigned long st_blksize; + + unsigned long st_blocks; /* Number 512-byte blocks allocated. */ + unsigned long __pad4; /* future possible st_blocks high bits */ + + unsigned long st_atime; + unsigned long st_atime_nsec; + + unsigned long st_mtime; + unsigned int st_mtime_nsec; + + unsigned long st_ctime; + unsigned long st_ctime_nsec; + + unsigned long long st_ino; +}; + +#define STAT_HAVE_NSEC 1 + +#endif /* _ASM_STAT_H */ diff --git a/include/asm-mn10300/statfs.h b/include/asm-mn10300/statfs.h new file mode 100644 index 00000000000..0b91fe198c2 --- /dev/null +++ b/include/asm-mn10300/statfs.h @@ -0,0 +1 @@ +#include <asm-generic/statfs.h> diff --git a/include/asm-mn10300/string.h b/include/asm-mn10300/string.h new file mode 100644 index 00000000000..47dbd4346c3 --- /dev/null +++ b/include/asm-mn10300/string.h @@ -0,0 +1,32 @@ +/* MN10300 Optimised string functions + * + * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Modified by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_STRING_H +#define _ASM_STRING_H + +#define __HAVE_ARCH_MEMSET +#define __HAVE_ARCH_MEMCPY +#define __HAVE_ARCH_MEMMOVE + +extern void *memset(void *dest, int ch, size_t count); +extern void *memcpy(void *dest, const void *src, size_t count); +extern void *memmove(void *dest, const void *src, size_t count); + + +extern void __struct_cpy_bug(void); +#define struct_cpy(x, y) \ +({ \ + if (sizeof(*(x)) != sizeof(*(y))) \ + __struct_cpy_bug; \ + memcpy(x, y, sizeof(*(x))); \ +}) + +#endif /* _ASM_STRING_H */ diff --git a/include/asm-mn10300/system.h b/include/asm-mn10300/system.h new file mode 100644 index 00000000000..8214fb7e7fe --- /dev/null +++ b/include/asm-mn10300/system.h @@ -0,0 +1,237 @@ +/* MN10300 System definitions + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_SYSTEM_H +#define _ASM_SYSTEM_H + +#include <asm/cpu-regs.h> + +#ifdef __KERNEL__ +#ifndef __ASSEMBLY__ + +#include <linux/kernel.h> + +struct task_struct; +struct thread_struct; + +extern asmlinkage +struct task_struct *__switch_to(struct thread_struct *prev, + struct thread_struct *next, + struct task_struct *prev_task); + +/* context switching is now performed out-of-line in switch_to.S */ +#define switch_to(prev, next, last) \ +do { \ + current->thread.wchan = (u_long) __builtin_return_address(0); \ + (last) = __switch_to(&(prev)->thread, &(next)->thread, (prev)); \ + mb(); \ + current->thread.wchan = 0; \ +} while (0) + +#define arch_align_stack(x) (x) + +#define nop() asm volatile ("nop") + +#endif /* !__ASSEMBLY__ */ + +/* + * Force strict CPU ordering. + * And yes, this is required on UP too when we're talking + * to devices. + * + * For now, "wmb()" doesn't actually do anything, as all + * Intel CPU's follow what Intel calls a *Processor Order*, + * in which all writes are seen in the program order even + * outside the CPU. + * + * I expect future Intel CPU's to have a weaker ordering, + * but I'd also expect them to finally get their act together + * and add some real memory barriers if so. + * + * Some non intel clones support out of order store. wmb() ceases to be a + * nop for these. + */ + +#define mb() asm volatile ("": : :"memory") +#define rmb() mb() +#define wmb() asm volatile ("": : :"memory") + +#ifdef CONFIG_SMP +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#else +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#endif + +#define set_mb(var, value) do { var = value; mb(); } while (0) +#define set_wmb(var, value) do { var = value; wmb(); } while (0) + +#define read_barrier_depends() do {} while (0) +#define smp_read_barrier_depends() do {} while (0) + +/*****************************************************************************/ +/* + * interrupt control + * - "disabled": run in IM1/2 + * - level 0 - GDB stub + * - level 1 - virtual serial DMA (if present) + * - level 5 - normal interrupt priority + * - level 6 - timer interrupt + * - "enabled": run in IM7 + */ +#ifdef CONFIG_MN10300_TTYSM +#define MN10300_CLI_LEVEL EPSW_IM_2 +#else +#define MN10300_CLI_LEVEL EPSW_IM_1 +#endif + +#define local_save_flags(x) \ +do { \ + typecheck(unsigned long, x); \ + asm volatile( \ + " mov epsw,%0 \n" \ + : "=d"(x) \ + ); \ +} while (0) + +#define local_irq_disable() \ +do { \ + asm volatile( \ + " and %0,epsw \n" \ + " or %1,epsw \n" \ + " nop \n" \ + " nop \n" \ + " nop \n" \ + : \ + : "i"(~EPSW_IM), "i"(EPSW_IE | MN10300_CLI_LEVEL) \ + ); \ +} while (0) + +#define local_irq_save(x) \ +do { \ + local_save_flags(x); \ + local_irq_disable(); \ +} while (0) + +/* + * we make sure local_irq_enable() doesn't cause priority inversion + */ +#ifndef __ASSEMBLY__ + +extern unsigned long __mn10300_irq_enabled_epsw; + +#endif + +#define local_irq_enable() \ +do { \ + unsigned long tmp; \ + \ + asm volatile( \ + " mov epsw,%0 \n" \ + " and %1,%0 \n" \ + " or %2,%0 \n" \ + " mov %0,epsw \n" \ + : "=&d"(tmp) \ + : "i"(~EPSW_IM), "r"(__mn10300_irq_enabled_epsw) \ + ); \ +} while (0) + +#define local_irq_restore(x) \ +do { \ + typecheck(unsigned long, x); \ + asm volatile( \ + " mov %0,epsw \n" \ + " nop \n" \ + " nop \n" \ + " nop \n" \ + : \ + : "d"(x) \ + : "memory", "cc" \ + ); \ +} while (0) + +#define irqs_disabled() \ +({ \ + unsigned long flags; \ + local_save_flags(flags); \ + (flags & EPSW_IM) <= MN10300_CLI_LEVEL; \ +}) + +/* hook to save power by halting the CPU + * - called from the idle loop + * - must reenable interrupts (which takes three instruction cycles to complete) + */ +#define safe_halt() \ +do { \ + asm volatile(" or %0,epsw \n" \ + " nop \n" \ + " nop \n" \ + " bset %2,(%1) \n" \ + : \ + : "i"(EPSW_IE|EPSW_IM), "n"(&CPUM), "i"(CPUM_SLEEP)\ + : "cc" \ + ); \ +} while (0) + +#define STI or EPSW_IE|EPSW_IM,epsw +#define CLI and ~EPSW_IM,epsw; or EPSW_IE|MN10300_CLI_LEVEL,epsw; nop; nop; nop + +/*****************************************************************************/ +/* + * MN10300 doesn't actually have an exchange instruction + */ +#ifndef __ASSEMBLY__ + +struct __xchg_dummy { unsigned long a[100]; }; +#define __xg(x) ((struct __xchg_dummy *)(x)) + +static inline +unsigned long __xchg(volatile unsigned long *m, unsigned long val) +{ + unsigned long retval; + unsigned long flags; + + local_irq_save(flags); + retval = *m; + *m = val; + local_irq_restore(flags); + return retval; +} + +#define xchg(ptr, v) \ + ((__typeof__(*(ptr))) __xchg((unsigned long *)(ptr), \ + (unsigned long)(v))) + +static inline unsigned long __cmpxchg(volatile unsigned long *m, + unsigned long old, unsigned long new) +{ + unsigned long retval; + unsigned long flags; + + local_irq_save(flags); + retval = *m; + if (retval == old) + *m = new; + local_irq_restore(flags); + return retval; +} + +#define cmpxchg(ptr, o, n) \ + ((__typeof__(*(ptr))) __cmpxchg((unsigned long *)(ptr), \ + (unsigned long)(o), \ + (unsigned long)(n))) + +#endif /* !__ASSEMBLY__ */ + +#endif /* __KERNEL__ */ +#endif /* _ASM_SYSTEM_H */ diff --git a/include/asm-mn10300/termbits.h b/include/asm-mn10300/termbits.h new file mode 100644 index 00000000000..eb2b0dc1f69 --- /dev/null +++ b/include/asm-mn10300/termbits.h @@ -0,0 +1,200 @@ +#ifndef _ASM_TERMBITS_H +#define _ASM_TERMBITS_H + +#include <linux/posix_types.h> + +typedef unsigned char cc_t; +typedef unsigned int speed_t; +typedef unsigned int tcflag_t; + +#define NCCS 19 +struct termios { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ +}; + +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + +struct ktermios { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + +/* c_cc characters */ +#define VINTR 0 +#define VQUIT 1 +#define VERASE 2 +#define VKILL 3 +#define VEOF 4 +#define VTIME 5 +#define VMIN 6 +#define VSWTC 7 +#define VSTART 8 +#define VSTOP 9 +#define VSUSP 10 +#define VEOL 11 +#define VREPRINT 12 +#define VDISCARD 13 +#define VWERASE 14 +#define VLNEXT 15 +#define VEOL2 16 + + +/* c_iflag bits */ +#define IGNBRK 0000001 +#define BRKINT 0000002 +#define IGNPAR 0000004 +#define PARMRK 0000010 +#define INPCK 0000020 +#define ISTRIP 0000040 +#define INLCR 0000100 +#define IGNCR 0000200 +#define ICRNL 0000400 +#define IUCLC 0001000 +#define IXON 0002000 +#define IXANY 0004000 +#define IXOFF 0010000 +#define IMAXBEL 0020000 +#define IUTF8 0040000 + +/* c_oflag bits */ +#define OPOST 0000001 +#define OLCUC 0000002 +#define ONLCR 0000004 +#define OCRNL 0000010 +#define ONOCR 0000020 +#define ONLRET 0000040 +#define OFILL 0000100 +#define OFDEL 0000200 +#define NLDLY 0000400 +#define NL0 0000000 +#define NL1 0000400 +#define CRDLY 0003000 +#define CR0 0000000 +#define CR1 0001000 +#define CR2 0002000 +#define CR3 0003000 +#define TABDLY 0014000 +#define TAB0 0000000 +#define TAB1 0004000 +#define TAB2 0010000 +#define TAB3 0014000 +#define XTABS 0014000 +#define BSDLY 0020000 +#define BS0 0000000 +#define BS1 0020000 +#define VTDLY 0040000 +#define VT0 0000000 +#define VT1 0040000 +#define FFDLY 0100000 +#define FF0 0000000 +#define FF1 0100000 + +/* c_cflag bit meaning */ +#define CBAUD 0010017 +#define B0 0000000 /* hang up */ +#define B50 0000001 +#define B75 0000002 +#define B110 0000003 +#define B134 0000004 +#define B150 0000005 +#define B200 0000006 +#define B300 0000007 +#define B600 0000010 +#define B1200 0000011 +#define B1800 0000012 +#define B2400 0000013 +#define B4800 0000014 +#define B9600 0000015 +#define B19200 0000016 +#define B38400 0000017 +#define EXTA B19200 +#define EXTB B38400 +#define CSIZE 0000060 +#define CS5 0000000 +#define CS6 0000020 +#define CS7 0000040 +#define CS8 0000060 +#define CSTOPB 0000100 +#define CREAD 0000200 +#define PARENB 0000400 +#define PARODD 0001000 +#define HUPCL 0002000 +#define CLOCAL 0004000 +#define CBAUDEX 0010000 +#define BOTHER 0010000 +#define B57600 0010001 +#define B115200 0010002 +#define B230400 0010003 +#define B460800 0010004 +#define B500000 0010005 +#define B576000 0010006 +#define B921600 0010007 +#define B1000000 0010010 +#define B1152000 0010011 +#define B1500000 0010012 +#define B2000000 0010013 +#define B2500000 0010014 +#define B3000000 0010015 +#define B3500000 0010016 +#define B4000000 0010017 +#define CIBAUD 002003600000 /* input baud rate (not used) */ +#define CTVB 004000000000 /* VisioBraille Terminal flow control */ +#define CMSPAR 010000000000 /* mark or space (stick) parity */ +#define CRTSCTS 020000000000 /* flow control */ + +#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ + +/* c_lflag bits */ +#define ISIG 0000001 +#define ICANON 0000002 +#define XCASE 0000004 +#define ECHO 0000010 +#define ECHOE 0000020 +#define ECHOK 0000040 +#define ECHONL 0000100 +#define NOFLSH 0000200 +#define TOSTOP 0000400 +#define ECHOCTL 0001000 +#define ECHOPRT 0002000 +#define ECHOKE 0004000 +#define FLUSHO 0010000 +#define PENDIN 0040000 +#define IEXTEN 0100000 + +/* tcflow() and TCXONC use these */ +#define TCOOFF 0 +#define TCOON 1 +#define TCIOFF 2 +#define TCION 3 + +/* tcflush() and TCFLSH use these */ +#define TCIFLUSH 0 +#define TCOFLUSH 1 +#define TCIOFLUSH 2 + +/* tcsetattr uses these */ +#define TCSANOW 0 +#define TCSADRAIN 1 +#define TCSAFLUSH 2 + +#endif /* _ASM_TERMBITS_H */ diff --git a/include/asm-mn10300/termios.h b/include/asm-mn10300/termios.h new file mode 100644 index 00000000000..dd7cf617e11 --- /dev/null +++ b/include/asm-mn10300/termios.h @@ -0,0 +1,92 @@ +#ifndef _ASM_TERMIOS_H +#define _ASM_TERMIOS_H + +#include <asm/termbits.h> +#include <asm/ioctls.h> + +struct winsize { + unsigned short ws_row; + unsigned short ws_col; + unsigned short ws_xpixel; + unsigned short ws_ypixel; +}; + +#define NCC 8 +struct termio { + unsigned short c_iflag; /* input mode flags */ + unsigned short c_oflag; /* output mode flags */ + unsigned short c_cflag; /* control mode flags */ + unsigned short c_lflag; /* local mode flags */ + unsigned char c_line; /* line discipline */ + unsigned char c_cc[NCC]; /* control characters */ +}; + +#ifdef __KERNEL__ +/* intr=^C quit=^| erase=del kill=^U + eof=^D vtime=\0 vmin=\1 sxtc=\0 + start=^Q stop=^S susp=^Z eol=\0 + reprint=^R discard=^U werase=^W lnext=^V + eol2=\0 +*/ +#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" +#endif + +/* modem lines */ +#define TIOCM_LE 0x001 +#define TIOCM_DTR 0x002 +#define TIOCM_RTS 0x004 +#define TIOCM_ST 0x008 +#define TIOCM_SR 0x010 +#define TIOCM_CTS 0x020 +#define TIOCM_CAR 0x040 +#define TIOCM_RNG 0x080 +#define TIOCM_DSR 0x100 +#define TIOCM_CD TIOCM_CAR +#define TIOCM_RI TIOCM_RNG +#define TIOCM_OUT1 0x2000 +#define TIOCM_OUT2 0x4000 +#define TIOCM_LOOP 0x8000 + +#define TIOCM_MODEM_BITS TIOCM_OUT2 /* IRDA support */ + +/* + * Translate a "termio" structure into a "termios". Ugh. + */ +#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ + unsigned short __tmp; \ + get_user(__tmp, &(termio)->x); \ + *(unsigned short *) &(termios)->x = __tmp; \ +} + +#define user_termio_to_kernel_termios(termios, termio) \ +({ \ + SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ + SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ + SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ + SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ + copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ +}) + +/* + * Translate a "termios" structure into a "termio". Ugh. + */ +#define kernel_termios_to_user_termio(termio, termios) \ +({ \ + put_user((termios)->c_iflag, &(termio)->c_iflag); \ + put_user((termios)->c_oflag, &(termio)->c_oflag); \ + put_user((termios)->c_cflag, &(termio)->c_cflag); \ + put_user((termios)->c_lflag, &(termio)->c_lflag); \ + put_user((termios)->c_line, &(termio)->c_line); \ + copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ +}) + +#define user_termios_to_kernel_termios(k, u) \ + copy_from_user(k, u, sizeof(struct termios2)) +#define kernel_termios_to_user_termios(u, k) \ + copy_to_user(u, k, sizeof(struct termios2)) +#define user_termios_to_kernel_termios_1(k, u) \ + copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios_1(u, k) \ + copy_to_user(u, k, sizeof(struct termios)) + +#endif /* _ASM_TERMIOS_H */ diff --git a/include/asm-mn10300/thread_info.h b/include/asm-mn10300/thread_info.h new file mode 100644 index 00000000000..e397e719278 --- /dev/null +++ b/include/asm-mn10300/thread_info.h @@ -0,0 +1,168 @@ +/* MN10300 Low-level thread information + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_THREAD_INFO_H +#define _ASM_THREAD_INFO_H + +#ifdef __KERNEL__ + +#include <asm/page.h> + +#ifndef __ASSEMBLY__ +#include <asm/processor.h> +#endif + +#define PREEMPT_ACTIVE 0x10000000 + +#ifdef CONFIG_4KSTACKS +#define THREAD_SIZE (4096) +#else +#define THREAD_SIZE (8192) +#endif + +#define STACK_WARN (THREAD_SIZE / 8) + +/* + * low level task data that entry.S needs immediate access to + * - this struct should fit entirely inside of one cache line + * - this struct shares the supervisor stack pages + * - if the contents of this structure are changed, the assembly constants + * must also be changed + */ +#ifndef __ASSEMBLY__ + +struct thread_info { + struct task_struct *task; /* main task structure */ + struct exec_domain *exec_domain; /* execution domain */ + unsigned long flags; /* low level flags */ + __u32 cpu; /* current CPU */ + __s32 preempt_count; /* 0 => preemptable, <0 => BUG */ + + mm_segment_t addr_limit; /* thread address space: + 0-0xBFFFFFFF for user-thead + 0-0xFFFFFFFF for kernel-thread + */ + struct restart_block restart_block; + + __u8 supervisor_stack[0]; +}; + +#else /* !__ASSEMBLY__ */ + +#ifndef __ASM_OFFSETS_H__ +#include <asm/asm-offsets.h> +#endif + +#endif + +/* + * macros/functions for gaining access to the thread information structure + * + * preempt_count needs to be 1 initially, until the scheduler is functional. + */ +#ifndef __ASSEMBLY__ + +#define INIT_THREAD_INFO(tsk) \ +{ \ + .task = &tsk, \ + .exec_domain = &default_exec_domain, \ + .flags = 0, \ + .cpu = 0, \ + .preempt_count = 1, \ + .addr_limit = KERNEL_DS, \ + .restart_block = { \ + .fn = do_no_restart_syscall, \ + }, \ +} + +#define init_thread_info (init_thread_union.thread_info) +#define init_stack (init_thread_union.stack) +#define init_uregs \ + ((struct pt_regs *) \ + ((unsigned long) init_stack + THREAD_SIZE - sizeof(struct pt_regs))) + +extern struct thread_info *__current_ti; + +/* how to get the thread information struct from C */ +static inline __attribute__((const)) +struct thread_info *current_thread_info(void) +{ + struct thread_info *ti; + asm("mov sp,%0\n" + "and %1,%0\n" + : "=d" (ti) + : "i" (~(THREAD_SIZE - 1)) + : "cc"); + return ti; +} + +/* how to get the current stack pointer from C */ +static inline unsigned long current_stack_pointer(void) +{ + unsigned long sp; + asm("mov sp,%0; ":"=r" (sp)); + return sp; +} + +/* thread information allocation */ +#ifdef CONFIG_DEBUG_STACK_USAGE +#define alloc_thread_info(tsk) kzalloc(THREAD_SIZE, GFP_KERNEL) +#else +#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) +#endif + +#define free_thread_info(ti) kfree((ti)) +#define get_thread_info(ti) get_task_struct((ti)->task) +#define put_thread_info(ti) put_task_struct((ti)->task) + +#else /* !__ASSEMBLY__ */ + +#ifndef __VMLINUX_LDS__ +/* how to get the thread information struct from ASM */ +.macro GET_THREAD_INFO reg + mov sp,\reg + and -THREAD_SIZE,\reg +.endm +#endif +#endif + +/* + * thread information flags + * - these are process state flags that various assembly files may need to + * access + * - pending work-to-be-done flags are in LSW + * - other flags in MSW + */ +#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ +#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ +#define TIF_SIGPENDING 2 /* signal pending */ +#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ +#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */ +#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ +#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ +#define TIF_MEMDIE 17 /* OOM killer killed process */ +#define TIF_FREEZE 18 /* freezing for suspend */ + +#define _TIF_SYSCALL_TRACE +(1 << TIF_SYSCALL_TRACE) +#define _TIF_NOTIFY_RESUME +(1 << TIF_NOTIFY_RESUME) +#define _TIF_SIGPENDING +(1 << TIF_SIGPENDING) +#define _TIF_NEED_RESCHED +(1 << TIF_NEED_RESCHED) +#define _TIF_SINGLESTEP +(1 << TIF_SINGLESTEP) +#define _TIF_RESTORE_SIGMASK +(1 << TIF_RESTORE_SIGMASK) +#define _TIF_POLLING_NRFLAG +(1 << TIF_POLLING_NRFLAG) +#define _TIF_FREEZE +(1 << TIF_FREEZE) + +#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ +#define _TIF_ALLWORK_MASK 0x0000FFFF /* work to do on any return to u-space */ + +#endif /* __KERNEL__ */ + +#endif /* _ASM_THREAD_INFO_H */ diff --git a/include/asm-mn10300/timer-regs.h b/include/asm-mn10300/timer-regs.h new file mode 100644 index 00000000000..1d883b7f94a --- /dev/null +++ b/include/asm-mn10300/timer-regs.h @@ -0,0 +1,293 @@ +/* AM33v2 on-board timer module registers + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_TIMER_REGS_H +#define _ASM_TIMER_REGS_H + +#include <asm/cpu-regs.h> +#include <asm/intctl-regs.h> + +#ifdef __KERNEL__ + +/* timer prescalar control */ +#define TMPSCNT __SYSREG(0xd4003071, u8) /* timer prescaler control */ +#define TMPSCNT_ENABLE 0x80 /* timer prescaler enable */ +#define TMPSCNT_DISABLE 0x00 /* timer prescaler disable */ + +/* 8 bit timers */ +#define TM0MD __SYSREG(0xd4003000, u8) /* timer 0 mode register */ +#define TM0MD_SRC 0x07 /* timer source */ +#define TM0MD_SRC_IOCLK 0x00 /* - IOCLK */ +#define TM0MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ +#define TM0MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ +#define TM0MD_SRC_TM2IO 0x03 /* - TM2IO pin input */ +#define TM0MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ +#define TM0MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ +#define TM0MD_SRC_TM0IO 0x07 /* - TM0IO pin input */ +#define TM0MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ +#define TM0MD_COUNT_ENABLE 0x80 /* timer count enable */ + +#define TM1MD __SYSREG(0xd4003001, u8) /* timer 1 mode register */ +#define TM1MD_SRC 0x07 /* timer source */ +#define TM1MD_SRC_IOCLK 0x00 /* - IOCLK */ +#define TM1MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ +#define TM1MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ +#define TM1MD_SRC_TM0CASCADE 0x03 /* - cascade with timer 0 */ +#define TM1MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ +#define TM1MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ +#define TM1MD_SRC_TM1IO 0x07 /* - TM1IO pin input */ +#define TM1MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ +#define TM1MD_COUNT_ENABLE 0x80 /* timer count enable */ + +#define TM2MD __SYSREG(0xd4003002, u8) /* timer 2 mode register */ +#define TM2MD_SRC 0x07 /* timer source */ +#define TM2MD_SRC_IOCLK 0x00 /* - IOCLK */ +#define TM2MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ +#define TM2MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ +#define TM2MD_SRC_TM1CASCADE 0x03 /* - cascade with timer 1 */ +#define TM2MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ +#define TM2MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ +#define TM2MD_SRC_TM2IO 0x07 /* - TM2IO pin input */ +#define TM2MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ +#define TM2MD_COUNT_ENABLE 0x80 /* timer count enable */ + +#define TM3MD __SYSREG(0xd4003003, u8) /* timer 3 mode register */ +#define TM3MD_SRC 0x07 /* timer source */ +#define TM3MD_SRC_IOCLK 0x00 /* - IOCLK */ +#define TM3MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ +#define TM3MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ +#define TM3MD_SRC_TM1CASCADE 0x03 /* - cascade with timer 2 */ +#define TM3MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ +#define TM3MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ +#define TM3MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ +#define TM3MD_SRC_TM3IO 0x07 /* - TM3IO pin input */ +#define TM3MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ +#define TM3MD_COUNT_ENABLE 0x80 /* timer count enable */ + +#define TM01MD __SYSREG(0xd4003000, u16) /* timer 0:1 mode register */ + +#define TM0BR __SYSREG(0xd4003010, u8) /* timer 0 base register */ +#define TM1BR __SYSREG(0xd4003011, u8) /* timer 1 base register */ +#define TM2BR __SYSREG(0xd4003012, u8) /* timer 2 base register */ +#define TM3BR __SYSREG(0xd4003013, u8) /* timer 3 base register */ +#define TM01BR __SYSREG(0xd4003010, u16) /* timer 0:1 base register */ + +#define TM0BC __SYSREGC(0xd4003020, u8) /* timer 0 binary counter */ +#define TM1BC __SYSREGC(0xd4003021, u8) /* timer 1 binary counter */ +#define TM2BC __SYSREGC(0xd4003022, u8) /* timer 2 binary counter */ +#define TM3BC __SYSREGC(0xd4003023, u8) /* timer 3 binary counter */ +#define TM01BC __SYSREGC(0xd4003020, u16) /* timer 0:1 binary counter */ + +#define TM0IRQ 2 /* timer 0 IRQ */ +#define TM1IRQ 3 /* timer 1 IRQ */ +#define TM2IRQ 4 /* timer 2 IRQ */ +#define TM3IRQ 5 /* timer 3 IRQ */ + +#define TM0ICR GxICR(TM0IRQ) /* timer 0 uflow intr ctrl reg */ +#define TM1ICR GxICR(TM1IRQ) /* timer 1 uflow intr ctrl reg */ +#define TM2ICR GxICR(TM2IRQ) /* timer 2 uflow intr ctrl reg */ +#define TM3ICR GxICR(TM3IRQ) /* timer 3 uflow intr ctrl reg */ + +/* 16-bit timers 4,5 & 7-11 */ +#define TM4MD __SYSREG(0xd4003080, u8) /* timer 4 mode register */ +#define TM4MD_SRC 0x07 /* timer source */ +#define TM4MD_SRC_IOCLK 0x00 /* - IOCLK */ +#define TM4MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ +#define TM4MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ +#define TM4MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ +#define TM4MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ +#define TM4MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ +#define TM4MD_SRC_TM4IO 0x07 /* - TM4IO pin input */ +#define TM4MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ +#define TM4MD_COUNT_ENABLE 0x80 /* timer count enable */ + +#define TM5MD __SYSREG(0xd4003082, u8) /* timer 5 mode register */ +#define TM5MD_SRC 0x07 /* timer source */ +#define TM5MD_SRC_IOCLK 0x00 /* - IOCLK */ +#define TM5MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ +#define TM5MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ +#define TM5MD_SRC_TM4CASCADE 0x03 /* - cascade with timer 4 */ +#define TM5MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ +#define TM5MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ +#define TM5MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ +#define TM5MD_SRC_TM5IO 0x07 /* - TM5IO pin input */ +#define TM5MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ +#define TM5MD_COUNT_ENABLE 0x80 /* timer count enable */ + +#define TM7MD __SYSREG(0xd4003086, u8) /* timer 7 mode register */ +#define TM7MD_SRC 0x07 /* timer source */ +#define TM7MD_SRC_IOCLK 0x00 /* - IOCLK */ +#define TM7MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ +#define TM7MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ +#define TM7MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ +#define TM7MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ +#define TM7MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ +#define TM7MD_SRC_TM7IO 0x07 /* - TM7IO pin input */ +#define TM7MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ +#define TM7MD_COUNT_ENABLE 0x80 /* timer count enable */ + +#define TM8MD __SYSREG(0xd4003088, u8) /* timer 8 mode register */ +#define TM8MD_SRC 0x07 /* timer source */ +#define TM8MD_SRC_IOCLK 0x00 /* - IOCLK */ +#define TM8MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ +#define TM8MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ +#define TM8MD_SRC_TM7CASCADE 0x03 /* - cascade with timer 7 */ +#define TM8MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ +#define TM8MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ +#define TM8MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ +#define TM8MD_SRC_TM8IO 0x07 /* - TM8IO pin input */ +#define TM8MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ +#define TM8MD_COUNT_ENABLE 0x80 /* timer count enable */ + +#define TM9MD __SYSREG(0xd400308a, u8) /* timer 9 mode register */ +#define TM9MD_SRC 0x07 /* timer source */ +#define TM9MD_SRC_IOCLK 0x00 /* - IOCLK */ +#define TM9MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ +#define TM9MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ +#define TM9MD_SRC_TM8CASCADE 0x03 /* - cascade with timer 8 */ +#define TM9MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ +#define TM9MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ +#define TM9MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ +#define TM9MD_SRC_TM9IO 0x07 /* - TM9IO pin input */ +#define TM9MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ +#define TM9MD_COUNT_ENABLE 0x80 /* timer count enable */ + +#define TM10MD __SYSREG(0xd400308c, u8) /* timer 10 mode register */ +#define TM10MD_SRC 0x07 /* timer source */ +#define TM10MD_SRC_IOCLK 0x00 /* - IOCLK */ +#define TM10MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ +#define TM10MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ +#define TM10MD_SRC_TM9CASCADE 0x03 /* - cascade with timer 9 */ +#define TM10MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ +#define TM10MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ +#define TM10MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ +#define TM10MD_SRC_TM10IO 0x07 /* - TM10IO pin input */ +#define TM10MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ +#define TM10MD_COUNT_ENABLE 0x80 /* timer count enable */ + +#define TM11MD __SYSREG(0xd400308e, u8) /* timer 11 mode register */ +#define TM11MD_SRC 0x07 /* timer source */ +#define TM11MD_SRC_IOCLK 0x00 /* - IOCLK */ +#define TM11MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ +#define TM11MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ +#define TM11MD_SRC_TM7CASCADE 0x03 /* - cascade with timer 7 */ +#define TM11MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ +#define TM11MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ +#define TM11MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ +#define TM11MD_SRC_TM11IO 0x07 /* - TM11IO pin input */ +#define TM11MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ +#define TM11MD_COUNT_ENABLE 0x80 /* timer count enable */ + +#define TM4BR __SYSREG(0xd4003090, u16) /* timer 4 base register */ +#define TM5BR __SYSREG(0xd4003092, u16) /* timer 5 base register */ +#define TM7BR __SYSREG(0xd4003096, u16) /* timer 7 base register */ +#define TM8BR __SYSREG(0xd4003098, u16) /* timer 8 base register */ +#define TM9BR __SYSREG(0xd400309a, u16) /* timer 9 base register */ +#define TM10BR __SYSREG(0xd400309c, u16) /* timer 10 base register */ +#define TM11BR __SYSREG(0xd400309e, u16) /* timer 11 base register */ +#define TM45BR __SYSREG(0xd4003090, u32) /* timer 4:5 base register */ + +#define TM4BC __SYSREG(0xd40030a0, u16) /* timer 4 binary counter */ +#define TM5BC __SYSREG(0xd40030a2, u16) /* timer 5 binary counter */ +#define TM45BC __SYSREG(0xd40030a0, u32) /* timer 4:5 binary counter */ + +#define TM7BC __SYSREG(0xd40030a6, u16) /* timer 7 binary counter */ +#define TM8BC __SYSREG(0xd40030a8, u16) /* timer 8 binary counter */ +#define TM9BC __SYSREG(0xd40030aa, u16) /* timer 9 binary counter */ +#define TM10BC __SYSREG(0xd40030ac, u16) /* timer 10 binary counter */ +#define TM11BC __SYSREG(0xd40030ae, u16) /* timer 11 binary counter */ + +#define TM4IRQ 6 /* timer 4 IRQ */ +#define TM5IRQ 7 /* timer 5 IRQ */ +#define TM7IRQ 11 /* timer 7 IRQ */ +#define TM8IRQ 12 /* timer 8 IRQ */ +#define TM9IRQ 13 /* timer 9 IRQ */ +#define TM10IRQ 14 /* timer 10 IRQ */ +#define TM11IRQ 15 /* timer 11 IRQ */ + +#define TM4ICR GxICR(TM4IRQ) /* timer 4 uflow intr ctrl reg */ +#define TM5ICR GxICR(TM5IRQ) /* timer 5 uflow intr ctrl reg */ +#define TM7ICR GxICR(TM7IRQ) /* timer 7 uflow intr ctrl reg */ +#define TM8ICR GxICR(TM8IRQ) /* timer 8 uflow intr ctrl reg */ +#define TM9ICR GxICR(TM9IRQ) /* timer 9 uflow intr ctrl reg */ +#define TM10ICR GxICR(TM10IRQ) /* timer 10 uflow intr ctrl reg */ +#define TM11ICR GxICR(TM11IRQ) /* timer 11 uflow intr ctrl reg */ + +/* 16-bit timer 6 */ +#define TM6MD __SYSREG(0xd4003084, u16) /* timer6 mode register */ +#define TM6MD_SRC 0x0007 /* timer source */ +#define TM6MD_SRC_IOCLK 0x0000 /* - IOCLK */ +#define TM6MD_SRC_IOCLK_8 0x0001 /* - 1/8 IOCLK */ +#define TM6MD_SRC_IOCLK_32 0x0002 /* - 1/32 IOCLK */ +#define TM6MD_SRC_TM0UFLOW 0x0004 /* - timer 0 underflow */ +#define TM6MD_SRC_TM1UFLOW 0x0005 /* - timer 1 underflow */ +#define TM6MD_SRC_TM6IOB_BOTH 0x0006 /* - TM6IOB pin input (both edges) */ +#define TM6MD_SRC_TM6IOB_SINGLE 0x0007 /* - TM6IOB pin input (single edge) */ +#define TM6MD_CLR_ENABLE 0x0010 /* clear count enable */ +#define TM6MD_ONESHOT_ENABLE 0x0040 /* oneshot count */ +#define TM6MD_TRIG_ENABLE 0x0080 /* TM6IOB pin trigger enable */ +#define TM6MD_PWM 0x3800 /* PWM output mode */ +#define TM6MD_PWM_DIS 0x0000 /* - disabled */ +#define TM6MD_PWM_10BIT 0x1000 /* - 10 bits mode */ +#define TM6MD_PWM_11BIT 0x1800 /* - 11 bits mode */ +#define TM6MD_PWM_12BIT 0x3000 /* - 12 bits mode */ +#define TM6MD_PWM_14BIT 0x3800 /* - 14 bits mode */ +#define TM6MD_INIT_COUNTER 0x4000 /* initialize TMnBC to zero */ +#define TM6MD_COUNT_ENABLE 0x8000 /* timer count enable */ + +#define TM6MDA __SYSREG(0xd40030b4, u8) /* timer6 cmp/cap A mode reg */ +#define TM6MDA_OUT 0x07 /* output select */ +#define TM6MDA_OUT_SETA_RESETB 0x00 /* - set at match A, reset at match B */ +#define TM6MDA_OUT_SETA_RESETOV 0x01 /* - set at match A, reset at overflow */ +#define TM6MDA_OUT_SETA 0x02 /* - set at match A */ +#define TM6MDA_OUT_RESETA 0x03 /* - reset at match A */ +#define TM6MDA_OUT_TOGGLE 0x04 /* - toggle on match A */ +#define TM6MDA_MODE 0xc0 /* compare A register mode */ +#define TM6MDA_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */ +#define TM6MDA_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */ +#define TM6MDA_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */ +#define TM6MDA_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */ +#define TM6MDA_EDGE 0x20 /* compare A edge select */ +#define TM6MDA_EDGE_FALLING 0x00 /* capture on falling edge */ +#define TM6MDA_EDGE_RISING 0x20 /* capture on rising edge */ +#define TM6MDA_CAPTURE_ENABLE 0x10 /* capture enable */ + +#define TM6MDB __SYSREG(0xd40030b5, u8) /* timer6 cmp/cap B mode reg */ +#define TM6MDB_OUT 0x07 /* output select */ +#define TM6MDB_OUT_SETB_RESETA 0x00 /* - set at match B, reset at match A */ +#define TM6MDB_OUT_SETB_RESETOV 0x01 /* - set at match B */ +#define TM6MDB_OUT_RESETB 0x03 /* - reset at match B */ +#define TM6MDB_OUT_TOGGLE 0x04 /* - toggle on match B */ +#define TM6MDB_MODE 0xc0 /* compare B register mode */ +#define TM6MDB_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */ +#define TM6MDB_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */ +#define TM6MDB_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */ +#define TM6MDB_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */ +#define TM6MDB_EDGE 0x20 /* compare B edge select */ +#define TM6MDB_EDGE_FALLING 0x00 /* capture on falling edge */ +#define TM6MDB_EDGE_RISING 0x20 /* capture on rising edge */ +#define TM6MDB_CAPTURE_ENABLE 0x10 /* capture enable */ + +#define TM6CA __SYSREG(0xd40030c4, u16) /* timer6 cmp/capture reg A */ +#define TM6CB __SYSREG(0xd40030d4, u16) /* timer6 cmp/capture reg B */ +#define TM6BC __SYSREG(0xd40030a4, u16) /* timer6 binary counter */ + +#define TM6IRQ 6 /* timer 6 IRQ */ +#define TM6AIRQ 9 /* timer 6A IRQ */ +#define TM6BIRQ 10 /* timer 6B IRQ */ + +#define TM6ICR GxICR(TM6IRQ) /* timer 6 uflow intr ctrl reg */ +#define TM6AICR GxICR(TM6AIRQ) /* timer 6A intr control reg */ +#define TM6BICR GxICR(TM6BIRQ) /* timer 6B intr control reg */ + +#endif /* __KERNEL__ */ + +#endif /* _ASM_TIMER_REGS_H */ diff --git a/include/asm-mn10300/timex.h b/include/asm-mn10300/timex.h new file mode 100644 index 00000000000..3944277dab6 --- /dev/null +++ b/include/asm-mn10300/timex.h @@ -0,0 +1,33 @@ +/* MN10300 Architecture time management specifications + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_TIMEX_H +#define _ASM_TIMEX_H + +#include <asm/hardirq.h> +#include <asm/unit/timex.h> + +#define TICK_SIZE (tick_nsec / 1000) + +#define CLOCK_TICK_RATE 1193180 /* Underlying HZ - this should probably be set + * to something appropriate, but what? */ + +extern cycles_t cacheflush_time; + +#ifdef __KERNEL__ + +static inline cycles_t get_cycles(void) +{ + return read_timestamp_counter(); +} + +#endif /* __KERNEL__ */ + +#endif /* _ASM_TIMEX_H */ diff --git a/include/asm-mn10300/tlb.h b/include/asm-mn10300/tlb.h new file mode 100644 index 00000000000..65d232b9661 --- /dev/null +++ b/include/asm-mn10300/tlb.h @@ -0,0 +1,34 @@ +/* MN10300 TLB definitions + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_TLB_H +#define _ASM_TLB_H + +#include <asm/tlbflush.h> + +extern void check_pgt_cache(void); + +/* + * we don't need any special per-pte or per-vma handling... + */ +#define tlb_start_vma(tlb, vma) do { } while (0) +#define tlb_end_vma(tlb, vma) do { } while (0) +#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) + +/* + * .. because we flush the whole mm when it fills up + */ +#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) + +/* for now, just use the generic stuff */ +#include <asm-generic/tlb.h> + +#endif /* _ASM_TLB_H */ diff --git a/include/asm-mn10300/tlbflush.h b/include/asm-mn10300/tlbflush.h new file mode 100644 index 00000000000..e0239865abc --- /dev/null +++ b/include/asm-mn10300/tlbflush.h @@ -0,0 +1,80 @@ +/* MN10300 TLB flushing functions + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_TLBFLUSH_H +#define _ASM_TLBFLUSH_H + +#include <asm/processor.h> + +#define __flush_tlb() \ +do { \ + int w; \ + __asm__ __volatile__ \ + (" mov %1,%0 \n" \ + " or %2,%0 \n" \ + " mov %0,%1 \n" \ + : "=d"(w) \ + : "m"(MMUCTR), "i"(MMUCTR_IIV|MMUCTR_DIV) \ + : "memory" \ + ); \ +} while (0) + +#define __flush_tlb_all() __flush_tlb() +#define __flush_tlb_one(addr) __flush_tlb() + + +/* + * TLB flushing: + * + * - flush_tlb() flushes the current mm struct TLBs + * - flush_tlb_all() flushes all processes TLBs + * - flush_tlb_mm(mm) flushes the specified mm context TLB's + * - flush_tlb_page(vma, vmaddr) flushes one page + * - flush_tlb_range(mm, start, end) flushes a range of pages + * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables + */ +#define flush_tlb_all() \ +do { \ + preempt_disable(); \ + __flush_tlb_all(); \ + preempt_enable(); \ +} while (0) + +#define flush_tlb_mm(mm) \ +do { \ + preempt_disable(); \ + __flush_tlb_all(); \ + preempt_enable(); \ +} while (0) + +#define flush_tlb_range(vma, start, end) \ +do { \ + unsigned long __s __attribute__((unused)) = (start); \ + unsigned long __e __attribute__((unused)) = (end); \ + preempt_disable(); \ + __flush_tlb_all(); \ + preempt_enable(); \ +} while (0) + + +#define __flush_tlb_global() flush_tlb_all() +#define flush_tlb() flush_tlb_all() +#define flush_tlb_kernel_range(start, end) \ +do { \ + unsigned long __s __attribute__((unused)) = (start); \ + unsigned long __e __attribute__((unused)) = (end); \ + flush_tlb_all(); \ +} while (0) + +extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); + +#define flush_tlb_pgtables(mm, start, end) do {} while (0) + +#endif /* _ASM_TLBFLUSH_H */ diff --git a/include/asm-mn10300/topology.h b/include/asm-mn10300/topology.h new file mode 100644 index 00000000000..5428f333a02 --- /dev/null +++ b/include/asm-mn10300/topology.h @@ -0,0 +1 @@ +#include <asm-generic/topology.h> diff --git a/include/asm-mn10300/types.h b/include/asm-mn10300/types.h new file mode 100644 index 00000000000..d40ea7628bf --- /dev/null +++ b/include/asm-mn10300/types.h @@ -0,0 +1,67 @@ +/* MN10300 Basic type definitions + * + * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_TYPES_H +#define _ASM_TYPES_H + +#ifndef __ASSEMBLY__ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +#endif /* __ASSEMBLY__ */ + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +#define BITS_PER_LONG 32 + +#ifndef __ASSEMBLY__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +/* Dma addresses are 32-bits wide. */ +typedef u32 dma_addr_t; + +#endif /* __ASSEMBLY__ */ + +#endif /* __KERNEL__ */ + +#endif /* _ASM_TYPES_H */ diff --git a/include/asm-mn10300/uaccess.h b/include/asm-mn10300/uaccess.h new file mode 100644 index 00000000000..46b9b647f3c --- /dev/null +++ b/include/asm-mn10300/uaccess.h @@ -0,0 +1,490 @@ +/* MN10300 userspace access functions + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_UACCESS_H +#define _ASM_UACCESS_H + +/* + * User space memory access functions + */ +#include <linux/sched.h> +#include <asm/page.h> +#include <asm/pgtable.h> +#include <asm/errno.h> + +#define VERIFY_READ 0 +#define VERIFY_WRITE 1 + +/* + * The fs value determines whether argument validity checking should be + * performed or not. If get_fs() == USER_DS, checking is performed, with + * get_fs() == KERNEL_DS, checking is bypassed. + * + * For historical reasons, these macros are grossly misnamed. + */ + +#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) + +#define KERNEL_XDS MAKE_MM_SEG(0xBFFFFFFF) +#define KERNEL_DS MAKE_MM_SEG(0x9FFFFFFF) +#define USER_DS MAKE_MM_SEG(TASK_SIZE) + +#define get_ds() (KERNEL_DS) +#define get_fs() (current_thread_info()->addr_limit) +#define set_fs(x) (current_thread_info()->addr_limit = (x)) +#define __kernel_ds_p() (current_thread_info()->addr_limit.seg == 0x9FFFFFFF) + +#define segment_eq(a, b) ((a).seg == (b).seg) + +#define __addr_ok(addr) \ + ((unsigned long)(addr) < (current_thread_info()->addr_limit.seg)) + +/* + * check that a range of addresses falls within the current address limit + */ +static inline int ___range_ok(unsigned long addr, unsigned int size) +{ + int flag = 1, tmp; + + asm(" add %3,%1 \n" /* set C-flag if addr + size > 4Gb */ + " bcs 0f \n" + " cmp %4,%1 \n" /* jump if addr+size>limit (error) */ + " bhi 0f \n" + " clr %0 \n" /* mark okay */ + "0: \n" + : "=r"(flag), "=&r"(tmp) + : "1"(addr), "ir"(size), + "r"(current_thread_info()->addr_limit.seg), "0"(flag) + : "cc" + ); + + return flag; +} + +#define __range_ok(addr, size) ___range_ok((unsigned long)(addr), (u32)(size)) + +#define access_ok(type, addr, size) (__range_ok((addr), (size)) == 0) +#define __access_ok(addr, size) (__range_ok((addr), (size)) == 0) + +static inline int verify_area(int type, const void *addr, unsigned long size) +{ + return access_ok(type, addr, size) ? 0 : -EFAULT; +} + + +/* + * The exception table consists of pairs of addresses: the first is the + * address of an instruction that is allowed to fault, and the second is + * the address at which the program should continue. No registers are + * modified, so it is entirely up to the continuation code to figure out + * what to do. + * + * All the routines below use bits of fixup code that are out of line + * with the main instruction path. This means when everything is well, + * we don't even have to jump over them. Further, they do not intrude + * on our cache or tlb entries. + */ + +struct exception_table_entry +{ + unsigned long insn, fixup; +}; + +/* Returns 0 if exception not found and fixup otherwise. */ +extern int fixup_exception(struct pt_regs *regs); + +#define put_user(x, ptr) __put_user_check((x), (ptr), sizeof(*(ptr))) +#define get_user(x, ptr) __get_user_check((x), (ptr), sizeof(*(ptr))) + +/* + * The "__xxx" versions do not do address space checking, useful when + * doing multiple accesses to the same area (the user has to do the + * checks by hand with "access_ok()") + */ +#define __put_user(x, ptr) __put_user_nocheck((x), (ptr), sizeof(*(ptr))) +#define __get_user(x, ptr) __get_user_nocheck((x), (ptr), sizeof(*(ptr))) + +/* + * The "xxx_ret" versions return constant specified in third argument, if + * something bad happens. These macros can be optimized for the + * case of just returning from the function xxx_ret is used. + */ + +#define put_user_ret(x, ptr, ret) \ + ({ if (put_user((x), (ptr))) return (ret); }) +#define get_user_ret(x, ptr, ret) \ + ({ if (get_user((x), (ptr))) return (ret); }) +#define __put_user_ret(x, ptr, ret) \ + ({ if (__put_user((x), (ptr))) return (ret); }) +#define __get_user_ret(x, ptr, ret) \ + ({ if (__get_user((x), (ptr))) return (ret); }) + +struct __large_struct { unsigned long buf[100]; }; +#define __m(x) (*(struct __large_struct *)(x)) + +#define __get_user_nocheck(x, ptr, size) \ +({ \ + __typeof(*(ptr)) __gu_val; \ + unsigned long __gu_addr; \ + int __gu_err; \ + __gu_addr = (unsigned long) (ptr); \ + switch (size) { \ + case 1: __get_user_asm("bu"); break; \ + case 2: __get_user_asm("hu"); break; \ + case 4: __get_user_asm("" ); break; \ + default: __get_user_unknown(); break; \ + } \ + x = (__typeof__(*(ptr))) __gu_val; \ + __gu_err; \ +}) + +#define __get_user_check(x, ptr, size) \ +({ \ + __typeof__(*(ptr)) __gu_val; \ + unsigned long __gu_addr; \ + int __gu_err; \ + __gu_addr = (unsigned long) (ptr); \ + if (likely(__access_ok(__gu_addr,size))) { \ + switch (size) { \ + case 1: __get_user_asm("bu"); break; \ + case 2: __get_user_asm("hu"); break; \ + case 4: __get_user_asm("" ); break; \ + default: __get_user_unknown(); break; \ + } \ + } \ + else { \ + __gu_err = -EFAULT; \ + __gu_val = 0; \ + } \ + x = (__typeof__(*(ptr))) __gu_val; \ + __gu_err; \ +}) + +#define __get_user_asm(INSN) \ +({ \ + asm volatile( \ + "1:\n" \ + " mov"INSN" %2,%1\n" \ + " mov 0,%0\n" \ + "2:\n" \ + " .section .fixup,\"ax\"\n" \ + "3:\n\t" \ + " mov %3,%0\n" \ + " jmp 2b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .balign 4\n" \ + " .long 1b, 3b\n" \ + " .previous" \ + : "=&r" (__gu_err), "=&r" (__gu_val) \ + : "m" (__m(__gu_addr)), "i" (-EFAULT)); \ +}) + +extern int __get_user_unknown(void); + +#define __put_user_nocheck(x, ptr, size) \ +({ \ + union { \ + __typeof__(*(ptr)) val; \ + u32 bits[2]; \ + } __pu_val; \ + unsigned long __pu_addr; \ + int __pu_err; \ + __pu_val.val = (x); \ + __pu_addr = (unsigned long) (ptr); \ + switch (size) { \ + case 1: __put_user_asm("bu"); break; \ + case 2: __put_user_asm("hu"); break; \ + case 4: __put_user_asm("" ); break; \ + case 8: __put_user_asm8(); break; \ + default: __pu_err = __put_user_unknown(); break; \ + } \ + __pu_err; \ +}) + +#define __put_user_check(x, ptr, size) \ +({ \ + union { \ + __typeof__(*(ptr)) val; \ + u32 bits[2]; \ + } __pu_val; \ + unsigned long __pu_addr; \ + int __pu_err; \ + __pu_val.val = (x); \ + __pu_addr = (unsigned long) (ptr); \ + if (likely(__access_ok(__pu_addr, size))) { \ + switch (size) { \ + case 1: __put_user_asm("bu"); break; \ + case 2: __put_user_asm("hu"); break; \ + case 4: __put_user_asm("" ); break; \ + case 8: __put_user_asm8(); break; \ + default: __pu_err = __put_user_unknown(); break; \ + } \ + } \ + else { \ + __pu_err = -EFAULT; \ + } \ + __pu_err; \ +}) + +#define __put_user_asm(INSN) \ +({ \ + asm volatile( \ + "1:\n" \ + " mov"INSN" %1,%2\n" \ + " mov 0,%0\n" \ + "2:\n" \ + " .section .fixup,\"ax\"\n" \ + "3:\n" \ + " mov %3,%0\n" \ + " jmp 2b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .balign 4\n" \ + " .long 1b, 3b\n" \ + " .previous" \ + : "=&r" (__pu_err) \ + : "r" (__pu_val.val), "m" (__m(__pu_addr)), \ + "i" (-EFAULT) \ + ); \ +}) + +#define __put_user_asm8() \ +({ \ + asm volatile( \ + "1: mov %1,%3 \n" \ + "2: mov %2,%4 \n" \ + " mov 0,%0 \n" \ + "3: \n" \ + " .section .fixup,\"ax\" \n" \ + "4: \n" \ + " mov %5,%0 \n" \ + " jmp 2b \n" \ + " .previous \n" \ + " .section __ex_table,\"a\"\n" \ + " .balign 4 \n" \ + " .long 1b, 4b \n" \ + " .long 2b, 4b \n" \ + " .previous \n" \ + : "=&r" (__pu_err) \ + : "r" (__pu_val.bits[0]), "r" (__pu_val.bits[1]), \ + "m" (__m(__pu_addr)), "m" (__m(__pu_addr+4)), \ + "i" (-EFAULT) \ + ); \ +}) + +extern int __put_user_unknown(void); + + +/* + * Copy To/From Userspace + */ +/* Generic arbitrary sized copy. */ +#define __copy_user(to, from, size) \ +do { \ + if (size) { \ + void *__to = to; \ + const void *__from = from; \ + int w; \ + asm volatile( \ + "0: movbu (%0),%3;\n" \ + "1: movbu %3,(%1);\n" \ + " inc %0;\n" \ + " inc %1;\n" \ + " add -1,%2;\n" \ + " bne 0b;\n" \ + "2:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: jmp 2b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .balign 4\n" \ + " .long 0b,3b\n" \ + " .long 1b,3b\n" \ + " .previous\n" \ + : "=a"(__from), "=a"(__to), "=r"(size), "=&r"(w)\ + : "0"(__from), "1"(__to), "2"(size) \ + : "memory"); \ + } \ +} while (0) + +#define __copy_user_zeroing(to, from, size) \ +do { \ + if (size) { \ + void *__to = to; \ + const void *__from = from; \ + int w; \ + asm volatile( \ + "0: movbu (%0),%3;\n" \ + "1: movbu %3,(%1);\n" \ + " inc %0;\n" \ + " inc %1;\n" \ + " add -1,%2;\n" \ + " bne 0b;\n" \ + "2:\n" \ + " .section .fixup,\"ax\"\n" \ + "3:\n" \ + " mov %2,%0\n" \ + " clr %3\n" \ + "4: movbu %3,(%1);\n" \ + " inc %1;\n" \ + " add -1,%2;\n" \ + " bne 4b;\n" \ + " mov %0,%2\n" \ + " jmp 2b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .balign 4\n" \ + " .long 0b,3b\n" \ + " .long 1b,3b\n" \ + " .previous\n" \ + : "=a"(__from), "=a"(__to), "=r"(size), "=&r"(w)\ + : "0"(__from), "1"(__to), "2"(size) \ + : "memory"); \ + } \ +} while (0) + +/* We let the __ versions of copy_from/to_user inline, because they're often + * used in fast paths and have only a small space overhead. + */ +static inline +unsigned long __generic_copy_from_user_nocheck(void *to, const void *from, + unsigned long n) +{ + __copy_user_zeroing(to, from, n); + return n; +} + +static inline +unsigned long __generic_copy_to_user_nocheck(void *to, const void *from, + unsigned long n) +{ + __copy_user(to, from, n); + return n; +} + + +#if 0 +#error don't use - these macros don't increment to & from pointers +/* Optimize just a little bit when we know the size of the move. */ +#define __constant_copy_user(to, from, size) \ +do { \ + asm volatile( \ + " mov %0,a0;\n" \ + "0: movbu (%1),d3;\n" \ + "1: movbu d3,(%2);\n" \ + " add -1,a0;\n" \ + " bne 0b;\n" \ + "2:;" \ + ".section .fixup,\"ax\"\n" \ + "3: jmp 2b\n" \ + ".previous\n" \ + ".section __ex_table,\"a\"\n" \ + " .balign 4\n" \ + " .long 0b,3b\n" \ + " .long 1b,3b\n" \ + ".previous" \ + : \ + : "d"(size), "d"(to), "d"(from) \ + : "d3", "a0"); \ +} while (0) + +/* Optimize just a little bit when we know the size of the move. */ +#define __constant_copy_user_zeroing(to, from, size) \ +do { \ + asm volatile( \ + " mov %0,a0;\n" \ + "0: movbu (%1),d3;\n" \ + "1: movbu d3,(%2);\n" \ + " add -1,a0;\n" \ + " bne 0b;\n" \ + "2:;" \ + ".section .fixup,\"ax\"\n" \ + "3: jmp 2b\n" \ + ".previous\n" \ + ".section __ex_table,\"a\"\n" \ + " .balign 4\n" \ + " .long 0b,3b\n" \ + " .long 1b,3b\n" \ + ".previous" \ + : \ + : "d"(size), "d"(to), "d"(from) \ + : "d3", "a0"); \ +} while (0) + +static inline +unsigned long __constant_copy_to_user(void *to, const void *from, + unsigned long n) +{ + if (access_ok(VERIFY_WRITE, to, n)) + __constant_copy_user(to, from, n); + return n; +} + +static inline +unsigned long __constant_copy_from_user(void *to, const void *from, + unsigned long n) +{ + if (access_ok(VERIFY_READ, from, n)) + __constant_copy_user_zeroing(to, from, n); + return n; +} + +static inline +unsigned long __constant_copy_to_user_nocheck(void *to, const void *from, + unsigned long n) +{ + __constant_copy_user(to, from, n); + return n; +} + +static inline +unsigned long __constant_copy_from_user_nocheck(void *to, const void *from, + unsigned long n) +{ + __constant_copy_user_zeroing(to, from, n); + return n; +} +#endif + +extern unsigned long __generic_copy_to_user(void __user *, const void *, + unsigned long); +extern unsigned long __generic_copy_from_user(void *, const void __user *, + unsigned long); + +#define __copy_to_user_inatomic(to, from, n) \ + __generic_copy_to_user_nocheck((to), (from), (n)) +#define __copy_from_user_inatomic(to, from, n) \ + __generic_copy_from_user_nocheck((to), (from), (n)) + +#define __copy_to_user(to, from, n) \ +({ \ + might_sleep(); \ + __copy_to_user_inatomic((to), (from), (n)); \ +}) + +#define __copy_from_user(to, from, n) \ +({ \ + might_sleep(); \ + __copy_from_user_inatomic((to), (from), (n)); \ +}) + + +#define copy_to_user(to, from, n) __generic_copy_to_user((to), (from), (n)) +#define copy_from_user(to, from, n) __generic_copy_from_user((to), (from), (n)) + +extern long strncpy_from_user(char *dst, const char __user *src, long count); +extern long __strncpy_from_user(char *dst, const char __user *src, long count); +extern long strnlen_user(const char __user *str, long n); +#define strlen_user(str) strnlen_user(str, ~0UL >> 1) +extern unsigned long clear_user(void __user *mem, unsigned long len); +extern unsigned long __clear_user(void __user *mem, unsigned long len); + +#endif /* _ASM_UACCESS_H */ diff --git a/include/asm-mn10300/ucontext.h b/include/asm-mn10300/ucontext.h new file mode 100644 index 00000000000..fcab5c1d8e1 --- /dev/null +++ b/include/asm-mn10300/ucontext.h @@ -0,0 +1,22 @@ +/* MN10300 User context + * + * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_UCONTEXT_H +#define _ASM_UCONTEXT_H + +struct ucontext { + unsigned long uc_flags; + struct ucontext *uc_link; + stack_t uc_stack; + struct sigcontext uc_mcontext; + sigset_t uc_sigmask; /* mask last for extensibility */ +}; + +#endif /* _ASM_UCONTEXT_H */ diff --git a/include/asm-mn10300/unaligned.h b/include/asm-mn10300/unaligned.h new file mode 100644 index 00000000000..cad3afbd035 --- /dev/null +++ b/include/asm-mn10300/unaligned.h @@ -0,0 +1,136 @@ +/* MN10300 Unaligned memory access handling + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_UNALIGNED_H +#define _ASM_UNALIGNED_H + +#include <asm/types.h> + +#if 0 +extern int __bug_unaligned_x(void *ptr); + +/* + * What is the most efficient way of loading/storing an unaligned value? + * + * That is the subject of this file. Efficiency here is defined as + * minimum code size with minimum register usage for the common cases. + * It is currently not believed that long longs are common, so we + * trade efficiency for the chars, shorts and longs against the long + * longs. + * + * Current stats with gcc 2.7.2.2 for these functions: + * + * ptrsize get: code regs put: code regs + * 1 1 1 1 2 + * 2 3 2 3 2 + * 4 7 3 7 3 + * 8 20 6 16 6 + * + * gcc 2.95.1 seems to code differently: + * + * ptrsize get: code regs put: code regs + * 1 1 1 1 2 + * 2 3 2 3 2 + * 4 7 4 7 4 + * 8 19 8 15 6 + * + * which may or may not be more efficient (depending upon whether + * you can afford the extra registers). Hopefully the gcc 2.95 + * is inteligent enough to decide if it is better to use the + * extra register, but evidence so far seems to suggest otherwise. + * + * Unfortunately, gcc is not able to optimise the high word + * out of long long >> 32, or the low word from long long << 32 + */ + +#define __get_unaligned_2(__p) \ + (__p[0] | __p[1] << 8) + +#define __get_unaligned_4(__p) \ + (__p[0] | __p[1] << 8 | __p[2] << 16 | __p[3] << 24) + +#define get_unaligned(ptr) \ +({ \ + unsigned int __v1, __v2; \ + __typeof__(*(ptr)) __v; \ + __u8 *__p = (__u8 *)(ptr); \ + \ + switch (sizeof(*(ptr))) { \ + case 1: __v = *(ptr); break; \ + case 2: __v = __get_unaligned_2(__p); break; \ + case 4: __v = __get_unaligned_4(__p); break; \ + case 8: \ + __v2 = __get_unaligned_4((__p+4)); \ + __v1 = __get_unaligned_4(__p); \ + __v = ((unsigned long long)__v2 << 32 | __v1); \ + break; \ + default: __v = __bug_unaligned_x(__p); break; \ + } \ + __v; \ +}) + + +static inline void __put_unaligned_2(__u32 __v, register __u8 *__p) +{ + *__p++ = __v; + *__p++ = __v >> 8; +} + +static inline void __put_unaligned_4(__u32 __v, register __u8 *__p) +{ + __put_unaligned_2(__v >> 16, __p + 2); + __put_unaligned_2(__v, __p); +} + +static inline void __put_unaligned_8(const unsigned long long __v, __u8 *__p) +{ + /* + * tradeoff: 8 bytes of stack for all unaligned puts (2 + * instructions), or an extra register in the long long + * case - go for the extra register. + */ + __put_unaligned_4(__v >> 32, __p + 4); + __put_unaligned_4(__v, __p); +} + +/* + * Try to store an unaligned value as efficiently as possible. + */ +#define put_unaligned(val, ptr) \ + ({ \ + switch (sizeof(*(ptr))) { \ + case 1: \ + *(ptr) = (val); \ + break; \ + case 2: \ + __put_unaligned_2((val), (__u8 *)(ptr)); \ + break; \ + case 4: \ + __put_unaligned_4((val), (__u8 *)(ptr)); \ + break; \ + case 8: \ + __put_unaligned_8((val), (__u8 *)(ptr)); \ + break; \ + default: \ + __bug_unaligned_x(ptr); \ + break; \ + } \ + (void) 0; \ + }) + + +#else + +#define get_unaligned(ptr) (*(ptr)) +#define put_unaligned(val, ptr) ({ *(ptr) = (val); (void) 0; }) + +#endif + +#endif diff --git a/include/asm-mn10300/unistd.h b/include/asm-mn10300/unistd.h new file mode 100644 index 00000000000..3721aa9e195 --- /dev/null +++ b/include/asm-mn10300/unistd.h @@ -0,0 +1,384 @@ +/* MN10300 System call number list + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_UNISTD_H +#define _ASM_UNISTD_H + +#define __NR_restart_syscall 0 +#define __NR_exit 1 +#define __NR_fork 2 +#define __NR_read 3 +#define __NR_write 4 +#define __NR_open 5 +#define __NR_close 6 +#define __NR_waitpid 7 +#define __NR_creat 8 +#define __NR_link 9 +#define __NR_unlink 10 +#define __NR_execve 11 +#define __NR_chdir 12 +#define __NR_time 13 +#define __NR_mknod 14 +#define __NR_chmod 15 +#define __NR_lchown 16 +#define __NR_break 17 +#define __NR_oldstat 18 +#define __NR_lseek 19 +#define __NR_getpid 20 +#define __NR_mount 21 +#define __NR_umount 22 +#define __NR_setuid 23 +#define __NR_getuid 24 +#define __NR_stime 25 +#define __NR_ptrace 26 +#define __NR_alarm 27 +#define __NR_oldfstat 28 +#define __NR_pause 29 +#define __NR_utime 30 +#define __NR_stty 31 +#define __NR_gtty 32 +#define __NR_access 33 +#define __NR_nice 34 +#define __NR_ftime 35 +#define __NR_sync 36 +#define __NR_kill 37 +#define __NR_rename 38 +#define __NR_mkdir 39 +#define __NR_rmdir 40 +#define __NR_dup 41 +#define __NR_pipe 42 +#define __NR_times 43 +#define __NR_prof 44 +#define __NR_brk 45 +#define __NR_setgid 46 +#define __NR_getgid 47 +#define __NR_signal 48 +#define __NR_geteuid 49 +#define __NR_getegid 50 +#define __NR_acct 51 +#define __NR_umount2 52 +#define __NR_lock 53 +#define __NR_ioctl 54 +#define __NR_fcntl 55 +#define __NR_mpx 56 +#define __NR_setpgid 57 +#define __NR_ulimit 58 +#define __NR_oldolduname 59 +#define __NR_umask 60 +#define __NR_chroot 61 +#define __NR_ustat 62 +#define __NR_dup2 63 +#define __NR_getppid 64 +#define __NR_getpgrp 65 +#define __NR_setsid 66 +#define __NR_sigaction 67 +#define __NR_sgetmask 68 +#define __NR_ssetmask 69 +#define __NR_setreuid 70 +#define __NR_setregid 71 +#define __NR_sigsuspend 72 +#define __NR_sigpending 73 +#define __NR_sethostname 74 +#define __NR_setrlimit 75 +#define __NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */ +#define __NR_getrusage 77 +#define __NR_gettimeofday 78 +#define __NR_settimeofday 79 +#define __NR_getgroups 80 +#define __NR_setgroups 81 +#define __NR_select 82 +#define __NR_symlink 83 +#define __NR_oldlstat 84 +#define __NR_readlink 85 +#define __NR_uselib 86 +#define __NR_swapon 87 +#define __NR_reboot 88 +#define __NR_readdir 89 +#define __NR_mmap 90 +#define __NR_munmap 91 +#define __NR_truncate 92 +#define __NR_ftruncate 93 +#define __NR_fchmod 94 +#define __NR_fchown 95 +#define __NR_getpriority 96 +#define __NR_setpriority 97 +#define __NR_profil 98 +#define __NR_statfs 99 +#define __NR_fstatfs 100 +#define __NR_ioperm 101 +#define __NR_socketcall 102 +#define __NR_syslog 103 +#define __NR_setitimer 104 +#define __NR_getitimer 105 +#define __NR_stat 106 +#define __NR_lstat 107 +#define __NR_fstat 108 +#define __NR_olduname 109 +#define __NR_iopl 110 +#define __NR_vhangup 111 +#define __NR_idle 112 +#define __NR_vm86old 113 +#define __NR_wait4 114 +#define __NR_swapoff 115 +#define __NR_sysinfo 116 +#define __NR_ipc 117 +#define __NR_fsync 118 +#define __NR_sigreturn 119 +#define __NR_clone 120 +#define __NR_setdomainname 121 +#define __NR_uname 122 +#define __NR_modify_ldt 123 +#define __NR_adjtimex 124 +#define __NR_mprotect 125 +#define __NR_sigprocmask 126 +#define __NR_create_module 127 +#define __NR_init_module 128 +#define __NR_delete_module 129 +#define __NR_get_kernel_syms 130 +#define __NR_quotactl 131 +#define __NR_getpgid 132 +#define __NR_fchdir 133 +#define __NR_bdflush 134 +#define __NR_sysfs 135 +#define __NR_personality 136 +#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ +#define __NR_setfsuid 138 +#define __NR_setfsgid 139 +#define __NR__llseek 140 +#define __NR_getdents 141 +#define __NR__newselect 142 +#define __NR_flock 143 +#define __NR_msync 144 +#define __NR_readv 145 +#define __NR_writev 146 +#define __NR_getsid 147 +#define __NR_fdatasync 148 +#define __NR__sysctl 149 +#define __NR_mlock 150 +#define __NR_munlock 151 +#define __NR_mlockall 152 +#define __NR_munlockall 153 +#define __NR_sched_setparam 154 +#define __NR_sched_getparam 155 +#define __NR_sched_setscheduler 156 +#define __NR_sched_getscheduler 157 +#define __NR_sched_yield 158 +#define __NR_sched_get_priority_max 159 +#define __NR_sched_get_priority_min 160 +#define __NR_sched_rr_get_interval 161 +#define __NR_nanosleep 162 +#define __NR_mremap 163 +#define __NR_setresuid 164 +#define __NR_getresuid 165 +#define __NR_vm86 166 +#define __NR_query_module 167 +#define __NR_poll 168 +#define __NR_nfsservctl 169 +#define __NR_setresgid 170 +#define __NR_getresgid 171 +#define __NR_prctl 172 +#define __NR_rt_sigreturn 173 +#define __NR_rt_sigaction 174 +#define __NR_rt_sigprocmask 175 +#define __NR_rt_sigpending 176 +#define __NR_rt_sigtimedwait 177 +#define __NR_rt_sigqueueinfo 178 +#define __NR_rt_sigsuspend 179 +#define __NR_pread64 180 +#define __NR_pwrite64 181 +#define __NR_chown 182 +#define __NR_getcwd 183 +#define __NR_capget 184 +#define __NR_capset 185 +#define __NR_sigaltstack 186 +#define __NR_sendfile 187 +#define __NR_getpmsg 188 /* some people actually want streams */ +#define __NR_putpmsg 189 /* some people actually want streams */ +#define __NR_vfork 190 +#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ +#define __NR_mmap2 192 +#define __NR_truncate64 193 +#define __NR_ftruncate64 194 +#define __NR_stat64 195 +#define __NR_lstat64 196 +#define __NR_fstat64 197 +#define __NR_lchown32 198 +#define __NR_getuid32 199 +#define __NR_getgid32 200 +#define __NR_geteuid32 201 +#define __NR_getegid32 202 +#define __NR_setreuid32 203 +#define __NR_setregid32 204 +#define __NR_getgroups32 205 +#define __NR_setgroups32 206 +#define __NR_fchown32 207 +#define __NR_setresuid32 208 +#define __NR_getresuid32 209 +#define __NR_setresgid32 210 +#define __NR_getresgid32 211 +#define __NR_chown32 212 +#define __NR_setuid32 213 +#define __NR_setgid32 214 +#define __NR_setfsuid32 215 +#define __NR_setfsgid32 216 +#define __NR_pivot_root 217 +#define __NR_mincore 218 +#define __NR_madvise 219 +#define __NR_madvise1 219 /* delete when C lib stub is removed */ +#define __NR_getdents64 220 +#define __NR_fcntl64 221 +/* 223 is unused */ +#define __NR_gettid 224 +#define __NR_readahead 225 +#define __NR_setxattr 226 +#define __NR_lsetxattr 227 +#define __NR_fsetxattr 228 +#define __NR_getxattr 229 +#define __NR_lgetxattr 230 +#define __NR_fgetxattr 231 +#define __NR_listxattr 232 +#define __NR_llistxattr 233 +#define __NR_flistxattr 234 +#define __NR_removexattr 235 +#define __NR_lremovexattr 236 +#define __NR_fremovexattr 237 +#define __NR_tkill 238 +#define __NR_sendfile64 239 +#define __NR_futex 240 +#define __NR_sched_setaffinity 241 +#define __NR_sched_getaffinity 242 +#define __NR_set_thread_area 243 +#define __NR_get_thread_area 244 +#define __NR_io_setup 245 +#define __NR_io_destroy 246 +#define __NR_io_getevents 247 +#define __NR_io_submit 248 +#define __NR_io_cancel 249 +#define __NR_fadvise64 250 + +#define __NR_exit_group 252 +#define __NR_lookup_dcookie 253 +#define __NR_epoll_create 254 +#define __NR_epoll_ctl 255 +#define __NR_epoll_wait 256 +#define __NR_remap_file_pages 257 +#define __NR_set_tid_address 258 +#define __NR_timer_create 259 +#define __NR_timer_settime (__NR_timer_create+1) +#define __NR_timer_gettime (__NR_timer_create+2) +#define __NR_timer_getoverrun (__NR_timer_create+3) +#define __NR_timer_delete (__NR_timer_create+4) +#define __NR_clock_settime (__NR_timer_create+5) +#define __NR_clock_gettime (__NR_timer_create+6) +#define __NR_clock_getres (__NR_timer_create+7) +#define __NR_clock_nanosleep (__NR_timer_create+8) +#define __NR_statfs64 268 +#define __NR_fstatfs64 269 +#define __NR_tgkill 270 +#define __NR_utimes 271 +#define __NR_fadvise64_64 272 +#define __NR_vserver 273 +#define __NR_mbind 274 +#define __NR_get_mempolicy 275 +#define __NR_set_mempolicy 276 +#define __NR_mq_open 277 +#define __NR_mq_unlink (__NR_mq_open+1) +#define __NR_mq_timedsend (__NR_mq_open+2) +#define __NR_mq_timedreceive (__NR_mq_open+3) +#define __NR_mq_notify (__NR_mq_open+4) +#define __NR_mq_getsetattr (__NR_mq_open+5) +#define __NR_kexec_load 283 +#define __NR_waitid 284 +#define __NR_add_key 286 +#define __NR_request_key 287 +#define __NR_keyctl 288 +#define __NR_cacheflush 289 +#define __NR_ioprio_set 290 +#define __NR_ioprio_get 291 +#define __NR_inotify_init 292 +#define __NR_inotify_add_watch 293 +#define __NR_inotify_rm_watch 294 +#define __NR_migrate_pages 295 +#define __NR_openat 296 +#define __NR_mkdirat 297 +#define __NR_mknodat 298 +#define __NR_fchownat 299 +#define __NR_futimesat 300 +#define __NR_fstatat64 301 +#define __NR_unlinkat 302 +#define __NR_renameat 303 +#define __NR_linkat 304 +#define __NR_symlinkat 305 +#define __NR_readlinkat 306 +#define __NR_fchmodat 307 +#define __NR_faccessat 308 +#define __NR_pselect6 309 +#define __NR_ppoll 310 +#define __NR_unshare 311 +#define __NR_set_robust_list 312 +#define __NR_get_robust_list 313 +#define __NR_splice 314 +#define __NR_sync_file_range 315 +#define __NR_tee 316 +#define __NR_vmsplice 317 +#define __NR_move_pages 318 +#define __NR_getcpu 319 +#define __NR_epoll_pwait 320 +#define __NR_utimensat 321 +#define __NR_signalfd 322 +#define __NR_timerfd_create 323 +#define __NR_eventfd 324 +#define __NR_fallocate 325 +#define __NR_timerfd_settime 326 +#define __NR_timerfd_gettime 327 + +#ifdef __KERNEL__ + +#define NR_syscalls 326 + +/* + * specify the deprecated syscalls we want to support on this arch + */ +#define __ARCH_WANT_IPC_PARSE_VERSION +#define __ARCH_WANT_OLD_READDIR +#define __ARCH_WANT_OLD_STAT +#define __ARCH_WANT_STAT64 +#define __ARCH_WANT_SYS_ALARM +#define __ARCH_WANT_SYS_GETHOSTNAME +#define __ARCH_WANT_SYS_PAUSE +#define __ARCH_WANT_SYS_SGETMASK +#define __ARCH_WANT_SYS_SIGNAL +#define __ARCH_WANT_SYS_TIME +#define __ARCH_WANT_SYS_UTIME +#define __ARCH_WANT_SYS_WAITPID +#define __ARCH_WANT_SYS_SOCKETCALL +#define __ARCH_WANT_SYS_FADVISE64 +#define __ARCH_WANT_SYS_GETPGRP +#define __ARCH_WANT_SYS_LLSEEK +#define __ARCH_WANT_SYS_NICE +#define __ARCH_WANT_SYS_OLD_GETRLIMIT +#define __ARCH_WANT_SYS_OLDUMOUNT +#define __ARCH_WANT_SYS_SIGPENDING +#define __ARCH_WANT_SYS_SIGPROCMASK +#define __ARCH_WANT_SYS_RT_SIGACTION +#define __ARCH_WANT_SYS_RT_SIGSUSPEND + +/* + * "Conditional" syscalls + * + * What we want is __attribute__((weak,alias("sys_ni_syscall"))), + * but it doesn't work on all toolchains, so we just do it by hand + */ +#ifndef cond_syscall +#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall"); +#endif + +#endif /* __KERNEL__ */ +#endif /* _ASM_UNISTD_H */ diff --git a/include/asm-mn10300/unit-asb2303/clock.h b/include/asm-mn10300/unit-asb2303/clock.h new file mode 100644 index 00000000000..8b450e920af --- /dev/null +++ b/include/asm-mn10300/unit-asb2303/clock.h @@ -0,0 +1,45 @@ +/* ASB2303-specific clocks + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_UNIT_CLOCK_H +#define _ASM_UNIT_CLOCK_H + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_MN10300_RTC + +extern unsigned long mn10300_ioclk; /* IOCLK (crystal speed) in HZ */ +extern unsigned long mn10300_iobclk; +extern unsigned long mn10300_tsc_per_HZ; + +#define MN10300_IOCLK ((unsigned long)mn10300_ioclk) +/* If this processors has a another clock, uncomment the below. */ +/* #define MN10300_IOBCLK ((unsigned long)mn10300_iobclk) */ + +#else /* !CONFIG_MN10300_RTC */ + +#define MN10300_IOCLK 33333333UL +/* #define MN10300_IOBCLK 66666666UL */ + +#endif /* !CONFIG_MN10300_RTC */ + +#define MN10300_JCCLK MN10300_IOCLK +#define MN10300_TSCCLK MN10300_IOCLK + +#ifdef CONFIG_MN10300_RTC +#define MN10300_TSC_PER_HZ ((unsigned long)mn10300_tsc_per_HZ) +#else /* !CONFIG_MN10300_RTC */ +#define MN10300_TSC_PER_HZ (MN10300_TSCCLK/HZ) +#endif /* !CONFIG_MN10300_RTC */ + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_UNIT_CLOCK_H */ diff --git a/include/asm-mn10300/unit-asb2303/leds.h b/include/asm-mn10300/unit-asb2303/leds.h new file mode 100644 index 00000000000..3a7543ea7b5 --- /dev/null +++ b/include/asm-mn10300/unit-asb2303/leds.h @@ -0,0 +1,43 @@ +/* ASB2303-specific LEDs + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_UNIT_LEDS_H +#define _ASM_UNIT_LEDS_H + +#include <asm/pio-regs.h> +#include <asm/cpu-regs.h> +#include <asm/exceptions.h> + +#define ASB2303_GPIO0DEF __SYSREG(0xDB000000, u32) +#define ASB2303_7SEGLEDS __SYSREG(0xDB000008, u32) + +/* + * use the 7-segment LEDs to indicate states + */ + +/* flip the 7-segment LEDs between "G" and "-" */ +#define mn10300_set_gdbleds(ONOFF) \ +do { \ + ASB2303_7SEGLEDS = (ONOFF) ? 0x85 : 0x7f; \ +} while (0) + +/* indicate double-fault by displaying "d" on the LEDs */ +#define mn10300_set_dbfleds \ + mov 0x43,d0 ; \ + movbu d0,(ASB2303_7SEGLEDS) + +#ifndef __ASSEMBLY__ +extern void peripheral_leds_display_exception(enum exception_code code); +extern void peripheral_leds_led_chase(void); +extern void debug_to_serial(const char *p, int n); +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_UNIT_LEDS_H */ diff --git a/include/asm-mn10300/unit-asb2303/serial.h b/include/asm-mn10300/unit-asb2303/serial.h new file mode 100644 index 00000000000..0d55cf5896a --- /dev/null +++ b/include/asm-mn10300/unit-asb2303/serial.h @@ -0,0 +1,136 @@ +/* ASB2303-specific 8250 serial ports + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_UNIT_SERIAL_H +#define _ASM_UNIT_SERIAL_H + +#include <asm/cpu-regs.h> +#include <asm/proc/irq.h> +#include <linux/serial_reg.h> + +#define SERIAL_PORT0_BASE_ADDRESS 0xA6FB0000 +#define SERIAL_PORT1_BASE_ADDRESS 0xA6FC0000 + +#define SERIAL_IRQ XIRQ0 /* Dual serial (PC16552) (Hi) */ + +/* + * dispose of the /dev/ttyS0 and /dev/ttyS1 serial ports + */ +#ifndef CONFIG_GDBSTUB_ON_TTYSx + +#define SERIAL_PORT_DFNS \ + { \ + .baud_base = BASE_BAUD, \ + .irq = SERIAL_IRQ, \ + .flags = STD_COM_FLAGS, \ + .iomem_base = (u8 *) SERIAL_PORT0_BASE_ADDRESS, \ + .iomem_reg_shift = 2, \ + .io_type = SERIAL_IO_MEM, \ + }, \ + { \ + .baud_base = BASE_BAUD, \ + .irq = SERIAL_IRQ, \ + .flags = STD_COM_FLAGS, \ + .iomem_base = (u8 *) SERIAL_PORT1_BASE_ADDRESS, \ + .iomem_reg_shift = 2, \ + .io_type = SERIAL_IO_MEM, \ + }, + +#ifndef __ASSEMBLY__ + +static inline void __debug_to_serial(const char *p, int n) +{ +} + +#endif /* !__ASSEMBLY__ */ + +#else /* CONFIG_GDBSTUB_ON_TTYSx */ + +#define SERIAL_PORT_DFNS /* both stolen by gdb-stub because they share an IRQ */ + +#if defined(CONFIG_GDBSTUB_ON_TTYS0) +#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8) +#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8) +#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8) +#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8) +#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8) +#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8) +#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8) +#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8) +#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8) +#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8) +#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8) +#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 4, u8) +#define GDBPORT_SERIAL_IRQ SERIAL_IRQ + +#elif defined(CONFIG_GDBSTUB_ON_TTYS1) +#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_RX * 4, u8) +#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_TX * 4, u8) +#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_DLL * 4, u8) +#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_DLM * 4, u8) +#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_IER * 4, u8) +#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_IIR * 4, u8) +#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_FCR * 4, u8) +#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_LCR * 4, u8) +#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_MCR * 4, u8) +#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_LSR * 4, u8) +#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_MSR * 4, u8) +#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_SCR * 4, u8) +#define GDBPORT_SERIAL_IRQ SERIAL_IRQ +#endif + +#ifndef __ASSEMBLY__ + +#define LSR_WAIT_FOR(STATE) \ +do { \ + while (!(GDBPORT_SERIAL_LSR & UART_LSR_##STATE)) {} \ +} while (0) +#define FLOWCTL_WAIT_FOR(LINE) \ +do { \ + while (!(GDBPORT_SERIAL_MSR & UART_MSR_##LINE)) {} \ +} while (0) +#define FLOWCTL_CLEAR(LINE) \ +do { \ + GDBPORT_SERIAL_MCR &= ~UART_MCR_##LINE; \ +} while (0) +#define FLOWCTL_SET(LINE) \ +do { \ + GDBPORT_SERIAL_MCR |= UART_MCR_##LINE; \ +} while (0) +#define FLOWCTL_QUERY(LINE) ({ GDBPORT_SERIAL_MSR & UART_MSR_##LINE; }) + +static inline void __debug_to_serial(const char *p, int n) +{ + char ch; + + FLOWCTL_SET(DTR); + + for (; n > 0; n--) { + LSR_WAIT_FOR(THRE); + FLOWCTL_WAIT_FOR(CTS); + + ch = *p++; + if (ch == 0x0a) { + GDBPORT_SERIAL_TX = 0x0d; + LSR_WAIT_FOR(THRE); + FLOWCTL_WAIT_FOR(CTS); + } + GDBPORT_SERIAL_TX = ch; + } + + FLOWCTL_CLEAR(DTR); +} + +#endif /* !__ASSEMBLY__ */ + +#endif /* CONFIG_GDBSTUB_ON_TTYSx */ + +#endif /* _ASM_UNIT_SERIAL_H */ diff --git a/include/asm-mn10300/unit-asb2303/smc91111.h b/include/asm-mn10300/unit-asb2303/smc91111.h new file mode 100644 index 00000000000..dd456e9c513 --- /dev/null +++ b/include/asm-mn10300/unit-asb2303/smc91111.h @@ -0,0 +1,50 @@ +/* Support for the SMC91C111 NIC on an ASB2303 + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_UNIT_SMC91111_H +#define _ASM_UNIT_SMC91111_H + +#include <asm/intctl-regs.h> + +#define SMC91111_BASE 0xAA000300UL +#define SMC91111_BASE_END 0xAA000400UL +#define SMC91111_IRQ XIRQ3 + +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_NOWAIT 1 +#define SMC_IRQ_FLAGS (0) + +#if SMC_CAN_USE_8BIT +#define SMC_inb(a, r) inb((unsigned long) ((a) + (r))) +#define SMC_outb(v, a, r) outb(v, (unsigned long) ((a) + (r))) +#endif + +#if SMC_CAN_USE_16BIT +#define SMC_inw(a, r) inw((unsigned long) ((a) + (r))) +#define SMC_outw(v, a, r) outw(v, (unsigned long) ((a) + (r))) +#define SMC_insw(a, r, p, l) insw((unsigned long) ((a) + (r)), (p), (l)) +#define SMC_outsw(a, r, p, l) outsw((unsigned long) ((a) + (r)), (p), (l)) +#endif + +#if SMC_CAN_USE_32BIT +#define SMC_inl(a, r) inl((unsigned long) ((a) + (r))) +#define SMC_outl(v, a, r) outl(v, (unsigned long) ((a) + (r))) +#define SMC_insl(a, r, p, l) insl((unsigned long) ((a) + (r)), (p), (l)) +#define SMC_outsl(a, r, p, l) outsl((unsigned long) ((a) + (r)), (p), (l)) +#endif + +#define RPC_LSA_DEFAULT RPC_LED_100_10 +#define RPC_LSB_DEFAULT RPC_LED_TX_RX + +#define set_irq_type(irq, type) + +#endif /* _ASM_UNIT_SMC91111_H */ diff --git a/include/asm-mn10300/unit-asb2303/timex.h b/include/asm-mn10300/unit-asb2303/timex.h new file mode 100644 index 00000000000..7e54b0cfdd0 --- /dev/null +++ b/include/asm-mn10300/unit-asb2303/timex.h @@ -0,0 +1,135 @@ +/* ASB2303-specific timer specifcations + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_UNIT_TIMEX_H +#define _ASM_UNIT_TIMEX_H + +#ifndef __ASSEMBLY__ +#include <linux/irq.h> +#endif /* __ASSEMBLY__ */ + +#include <asm/timer-regs.h> +#include <asm/unit/clock.h> + +/* + * jiffies counter specifications + */ + +#define TMJCBR_MAX 0xffff +#define TMJCBC TM01BC + +#define TMJCMD TM01MD +#define TMJCBR TM01BR +#define TMJCIRQ TM1IRQ +#define TMJCICR TM1ICR +#define TMJCICR_LEVEL GxICR_LEVEL_5 + +#ifndef __ASSEMBLY__ + +static inline void startup_jiffies_counter(void) +{ + unsigned rate; + u16 md, t16; + + /* use as little prescaling as possible to avoid losing accuracy */ + md = TM0MD_SRC_IOCLK; + rate = MN10300_JCCLK / HZ; + + if (rate > TMJCBR_MAX) { + md = TM0MD_SRC_IOCLK_8; + rate = MN10300_JCCLK / 8 / HZ; + + if (rate > TMJCBR_MAX) { + md = TM0MD_SRC_IOCLK_32; + rate = MN10300_JCCLK / 32 / HZ; + + if (rate > TMJCBR_MAX) + BUG(); + } + } + + TMJCBR = rate - 1; + t16 = TMJCBR; + + TMJCMD = + md | + TM1MD_SRC_TM0CASCADE << 8 | + TM0MD_INIT_COUNTER | + TM1MD_INIT_COUNTER << 8; + + TMJCMD = + md | + TM1MD_SRC_TM0CASCADE << 8 | + TM0MD_COUNT_ENABLE | + TM1MD_COUNT_ENABLE << 8; + + t16 = TMJCMD; + + TMJCICR |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST; + t16 = TMJCICR; +} + +static inline void shutdown_jiffies_counter(void) +{ +} + +#endif /* !__ASSEMBLY__ */ + + +/* + * timestamp counter specifications + */ + +#define TMTSCBR_MAX 0xffffffff +#define TMTSCBC TM45BC + +#ifndef __ASSEMBLY__ + +static inline void startup_timestamp_counter(void) +{ + /* set up timer 4 & 5 cascaded as a 32-bit counter to count real time + * - count down from 4Gig-1 to 0 and wrap at IOCLK rate + */ + TM45BR = TMTSCBR_MAX; + + TM4MD = TM4MD_SRC_IOCLK; + TM4MD |= TM4MD_INIT_COUNTER; + TM4MD &= ~TM4MD_INIT_COUNTER; + TM4ICR = 0; + + TM5MD = TM5MD_SRC_TM4CASCADE; + TM5MD |= TM5MD_INIT_COUNTER; + TM5MD &= ~TM5MD_INIT_COUNTER; + TM5ICR = 0; + + TM5MD |= TM5MD_COUNT_ENABLE; + TM4MD |= TM4MD_COUNT_ENABLE; +} + +static inline void shutdown_timestamp_counter(void) +{ + TM4MD = 0; + TM5MD = 0; +} + +/* + * we use a cascaded pair of 16-bit down-counting timers to count I/O + * clock cycles for the purposes of time keeping + */ +typedef unsigned long cycles_t; + +static inline cycles_t read_timestamp_counter(void) +{ + return (cycles_t)TMTSCBC; +} + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_UNIT_TIMEX_H */ diff --git a/include/asm-mn10300/unit-asb2305/clock.h b/include/asm-mn10300/unit-asb2305/clock.h new file mode 100644 index 00000000000..7d514841ffd --- /dev/null +++ b/include/asm-mn10300/unit-asb2305/clock.h @@ -0,0 +1,45 @@ +/* ASB2305-specific clocks + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_UNIT_CLOCK_H +#define _ASM_UNIT_CLOCK_H + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_MN10300_RTC + +extern unsigned long mn10300_ioclk; /* IOCLK (crystal speed) in HZ */ +extern unsigned long mn10300_iobclk; +extern unsigned long mn10300_tsc_per_HZ; + +#define MN10300_IOCLK ((unsigned long)mn10300_ioclk) +/* If this processors has a another clock, uncomment the below. */ +/* #define MN10300_IOBCLK ((unsigned long)mn10300_iobclk) */ + +#else /* !CONFIG_MN10300_RTC */ + +#define MN10300_IOCLK 33333333UL +/* #define MN10300_IOBCLK 66666666UL */ + +#endif /* !CONFIG_MN10300_RTC */ + +#define MN10300_JCCLK MN10300_IOCLK +#define MN10300_TSCCLK MN10300_IOCLK + +#ifdef CONFIG_MN10300_RTC +#define MN10300_TSC_PER_HZ ((unsigned long)mn10300_tsc_per_HZ) +#else /* !CONFIG_MN10300_RTC */ +#define MN10300_TSC_PER_HZ (MN10300_TSCCLK/HZ) +#endif /* !CONFIG_MN10300_RTC */ + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_UNIT_CLOCK_H */ diff --git a/include/asm-mn10300/unit-asb2305/leds.h b/include/asm-mn10300/unit-asb2305/leds.h new file mode 100644 index 00000000000..bc471f617fd --- /dev/null +++ b/include/asm-mn10300/unit-asb2305/leds.h @@ -0,0 +1,51 @@ +/* ASB2305-specific LEDs + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_UNIT_LEDS_H +#define _ASM_UNIT_LEDS_H + +#include <asm/pio-regs.h> +#include <asm/cpu-regs.h> +#include <asm/exceptions.h> + +#define ASB2305_7SEGLEDS __SYSREG(0xA6F90000, u32) + +/* perform a hard reset by driving PIO06 low */ +#define mn10300_unit_hard_reset() \ +do { \ + P0OUT &= 0xbf; \ + P0MD = (P0MD & P0MD_6) | P0MD_6_OUT; \ +} while (0) + +/* + * use the 7-segment LEDs to indicate states + */ +/* indicate double-fault by displaying "db-f" on the LEDs */ +#define mn10300_set_dbfleds \ + mov 0x43077f1d,d0 ; \ + mov d0,(ASB2305_7SEGLEDS) + +/* flip the 7-segment LEDs between "Gdb-" and "----" */ +#define mn10300_set_gdbleds(ONOFF) \ +do { \ + ASB2305_7SEGLEDS = (ONOFF) ? 0x8543077f : 0x7f7f7f7f; \ +} while (0) + +#ifndef __ASSEMBLY__ +extern void peripheral_leds_display_exception(enum exception_code); +extern void peripheral_leds_led_chase(void); +extern void peripheral_leds7x4_display_dec(unsigned int, unsigned int); +extern void peripheral_leds7x4_display_hex(unsigned int, unsigned int); +extern void peripheral_leds7x4_display_minssecs(unsigned int, unsigned int); +extern void peripheral_leds7x4_display_rtc(void); +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_UNIT_LEDS_H */ diff --git a/include/asm-mn10300/unit-asb2305/serial.h b/include/asm-mn10300/unit-asb2305/serial.h new file mode 100644 index 00000000000..73d31d67bb7 --- /dev/null +++ b/include/asm-mn10300/unit-asb2305/serial.h @@ -0,0 +1,120 @@ +/* ASB2305-specific 8250 serial ports + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_UNIT_SERIAL_H +#define _ASM_UNIT_SERIAL_H + +#include <asm/cpu/cpu-regs.h> +#include <asm/proc/irq.h> +#include <linux/serial_reg.h> + +#define SERIAL_PORT0_BASE_ADDRESS 0xA6FB0000 +#define ASB2305_DEBUG_MCR __SYSREG(0xA6FB0000 + UART_MCR * 2, u8) + +#define SERIAL_IRQ XIRQ0 /* Dual serial (PC16552) (Hi) */ + +/* + * dispose of the /dev/ttyS0 serial port + */ +#ifndef CONFIG_GDBSTUB_ON_TTYSx + +#define SERIAL_PORT_DFNS \ + { \ + .baud_base = BASE_BAUD, \ + .irq = SERIAL_IRQ, \ + .flags = STD_COM_FLAGS, \ + .iomem_base = (u8 *) SERIAL_PORT0_BASE_ADDRESS, \ + .iomem_reg_shift = 2, \ + .io_type = SERIAL_IO_MEM, \ + }, + +#ifndef __ASSEMBLY__ + +static inline void __debug_to_serial(const char *p, int n) +{ +} + +#endif /* !__ASSEMBLY__ */ + +#else /* CONFIG_GDBSTUB_ON_TTYSx */ + +#define SERIAL_PORT_DFNS /* stolen by gdb-stub */ + +#if defined(CONFIG_GDBSTUB_ON_TTYS0) +#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8) +#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8) +#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8) +#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8) +#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8) +#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8) +#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8) +#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8) +#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8) +#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8) +#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8) +#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 4, u8) +#define GDBPORT_SERIAL_IRQ SERIAL_IRQ + +#elif defined(CONFIG_GDBSTUB_ON_TTYS1) +#error The ASB2305 doesnt have a /dev/ttyS1 +#endif + +#ifndef __ASSEMBLY__ + +#define TTYS0_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8) +#define TTYS0_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8) +#define TTYS0_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8) +#define TTYS0_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8) + +#define LSR_WAIT_FOR(STATE) \ +do { \ + while (!(TTYS0_LSR & UART_LSR_##STATE)) {} \ +} while (0) +#define FLOWCTL_WAIT_FOR(LINE) \ +do { \ + while (!(TTYS0_MSR & UART_MSR_##LINE)) {} \ +} while (0) +#define FLOWCTL_CLEAR(LINE) \ +do { \ + TTYS0_MCR &= ~UART_MCR_##LINE; \ +} while (0) +#define FLOWCTL_SET(LINE) \ +do { \ + TTYS0_MCR |= UART_MCR_##LINE; \ +} while (0) +#define FLOWCTL_QUERY(LINE) ({ TTYS0_MSR & UART_MSR_##LINE; }) + +static inline void __debug_to_serial(const char *p, int n) +{ + char ch; + + FLOWCTL_SET(DTR); + + for (; n > 0; n--) { + LSR_WAIT_FOR(THRE); + FLOWCTL_WAIT_FOR(CTS); + + ch = *p++; + if (ch == 0x0a) { + TTYS0_TX = 0x0d; + LSR_WAIT_FOR(THRE); + FLOWCTL_WAIT_FOR(CTS); + } + TTYS0_TX = ch; + } + + FLOWCTL_CLEAR(DTR); +} + +#endif /* !__ASSEMBLY__ */ + +#endif /* CONFIG_GDBSTUB_ON_TTYSx */ + +#endif /* _ASM_UNIT_SERIAL_H */ diff --git a/include/asm-mn10300/unit-asb2305/timex.h b/include/asm-mn10300/unit-asb2305/timex.h new file mode 100644 index 00000000000..10e1bfe3446 --- /dev/null +++ b/include/asm-mn10300/unit-asb2305/timex.h @@ -0,0 +1,135 @@ +/* ASB2305 timer specifcations + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_UNIT_TIMEX_H +#define _ASM_UNIT_TIMEX_H + +#ifndef __ASSEMBLY__ +#include <linux/irq.h> +#endif /* __ASSEMBLY__ */ + +#include <asm/cpu/timer-regs.h> +#include <asm/unit/clock.h> + +/* + * jiffies counter specifications + */ + +#define TMJCBR_MAX 0xffff +#define TMJCBC TM01BC + +#define TMJCMD TM01MD +#define TMJCBR TM01BR +#define TMJCIRQ TM1IRQ +#define TMJCICR TM1ICR +#define TMJCICR_LEVEL GxICR_LEVEL_5 + +#ifndef __ASSEMBLY__ + +static inline void startup_jiffies_counter(void) +{ + unsigned rate; + u16 md, t16; + + /* use as little prescaling as possible to avoid losing accuracy */ + md = TM0MD_SRC_IOCLK; + rate = MN10300_JCCLK / HZ; + + if (rate > TMJCBR_MAX) { + md = TM0MD_SRC_IOCLK_8; + rate = MN10300_JCCLK / 8 / HZ; + + if (rate > TMJCBR_MAX) { + md = TM0MD_SRC_IOCLK_32; + rate = MN10300_JCCLK / 32 / HZ; + + if (rate > TMJCBR_MAX) + BUG(); + } + } + + TMJCBR = rate - 1; + t16 = TMJCBR; + + TMJCMD = + md | + TM1MD_SRC_TM0CASCADE << 8 | + TM0MD_INIT_COUNTER | + TM1MD_INIT_COUNTER << 8; + + TMJCMD = + md | + TM1MD_SRC_TM0CASCADE << 8 | + TM0MD_COUNT_ENABLE | + TM1MD_COUNT_ENABLE << 8; + + t16 = TMJCMD; + + TMJCICR |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST; + t16 = TMJCICR; +} + +static inline void shutdown_jiffies_counter(void) +{ +} + +#endif /* !__ASSEMBLY__ */ + + +/* + * timestamp counter specifications + */ + +#define TMTSCBR_MAX 0xffffffff +#define TMTSCBC TM45BC + +#ifndef __ASSEMBLY__ + +static inline void startup_timestamp_counter(void) +{ + /* set up timer 4 & 5 cascaded as a 32-bit counter to count real time + * - count down from 4Gig-1 to 0 and wrap at IOCLK rate + */ + TM45BR = TMTSCBR_MAX; + + TM4MD = TM4MD_SRC_IOCLK; + TM4MD |= TM4MD_INIT_COUNTER; + TM4MD &= ~TM4MD_INIT_COUNTER; + TM4ICR = 0; + + TM5MD = TM5MD_SRC_TM4CASCADE; + TM5MD |= TM5MD_INIT_COUNTER; + TM5MD &= ~TM5MD_INIT_COUNTER; + TM5ICR = 0; + + TM5MD |= TM5MD_COUNT_ENABLE; + TM4MD |= TM4MD_COUNT_ENABLE; +} + +static inline void shutdown_timestamp_counter(void) +{ + TM4MD = 0; + TM5MD = 0; +} + +/* + * we use a cascaded pair of 16-bit down-counting timers to count I/O + * clock cycles for the purposes of time keeping + */ +typedef unsigned long cycles_t; + +static inline cycles_t read_timestamp_counter(void) +{ + return (cycles_t) TMTSCBC; +} + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_UNIT_TIMEX_H */ diff --git a/include/asm-mn10300/user.h b/include/asm-mn10300/user.h new file mode 100644 index 00000000000..e1193908b78 --- /dev/null +++ b/include/asm-mn10300/user.h @@ -0,0 +1,53 @@ +/* MN10300 User process data + * + * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ +#ifndef _ASM_USER_H +#define _ASM_USER_H + +#include <asm/page.h> +#include <linux/ptrace.h> + +#ifndef __ASSEMBLY__ +/* + * When the kernel dumps core, it starts by dumping the user struct - this will + * be used by gdb to figure out where the data and stack segments are within + * the file, and what virtual addresses to use. + */ +struct user { + /* We start with the registers, to mimic the way that "memory" is + * returned from the ptrace(3,...) function. + */ + struct pt_regs regs; /* Where the registers are actually stored */ + + /* The rest of this junk is to help gdb figure out what goes where */ + unsigned long int u_tsize; /* Text segment size (pages). */ + unsigned long int u_dsize; /* Data segment size (pages). */ + unsigned long int u_ssize; /* Stack segment size (pages). */ + unsigned long start_code; /* Starting virtual address of text. */ + unsigned long start_stack; /* Starting virtual address of stack area. + This is actually the bottom of the stack, + the top of the stack is always found in the + esp register. */ + long int signal; /* Signal that caused the core dump. */ + int reserved; /* No longer used */ + struct user_pt_regs *u_ar0; /* Used by gdb to help find the values for */ + + /* the registers */ + unsigned long magic; /* To uniquely identify a core file */ + char u_comm[32]; /* User command that was responsible */ +}; +#endif + +#define NBPG PAGE_SIZE +#define UPAGES 1 +#define HOST_TEXT_START_ADDR +(u.start_code) +#define HOST_STACK_END_ADDR +(u.start_stack + u.u_ssize * NBPG) + +#endif /* _ASM_USER_H */ diff --git a/include/asm-mn10300/vga.h b/include/asm-mn10300/vga.h new file mode 100644 index 00000000000..0163e50a345 --- /dev/null +++ b/include/asm-mn10300/vga.h @@ -0,0 +1,17 @@ +/* MN10300 VGA register definitions + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_VGA_H +#define _ASM_VGA_H + + + +#endif /* _ASM_VGA_H */ diff --git a/include/asm-mn10300/xor.h b/include/asm-mn10300/xor.h new file mode 100644 index 00000000000..c82eb12a5b1 --- /dev/null +++ b/include/asm-mn10300/xor.h @@ -0,0 +1 @@ +#include <asm-generic/xor.h> diff --git a/include/asm-parisc/a.out.h b/include/asm-parisc/a.out.h index 23e2c90943e..eb04e34c5bb 100644 --- a/include/asm-parisc/a.out.h +++ b/include/asm-parisc/a.out.h @@ -17,14 +17,4 @@ struct exec #define N_DRSIZE(a) ((a).a_drsize) #define N_SYMSIZE(a) ((a).a_syms) -#ifdef __KERNEL__ - -/* XXX: STACK_TOP actually should be STACK_BOTTOM for parisc. - * prumpf */ - -#define STACK_TOP TASK_SIZE -#define STACK_TOP_MAX DEFAULT_TASK_SIZE - -#endif - #endif /* __A_OUT_GNU_H__ */ diff --git a/include/asm-parisc/page.h b/include/asm-parisc/page.h index b08d9151c71..27d50b85954 100644 --- a/include/asm-parisc/page.h +++ b/include/asm-parisc/page.h @@ -91,6 +91,7 @@ typedef unsigned long pgprot_t; #endif /* STRICT_MM_TYPECHECKS */ +typedef struct page *pgtable_t; typedef struct __physmem_range { unsigned long start_pfn; diff --git a/include/asm-parisc/pgalloc.h b/include/asm-parisc/pgalloc.h index aab66f1bea1..3996dfc30a3 100644 --- a/include/asm-parisc/pgalloc.h +++ b/include/asm-parisc/pgalloc.h @@ -115,11 +115,14 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) #define pmd_populate(mm, pmd, pte_page) \ pmd_populate_kernel(mm, pmd, page_address(pte_page)) +#define pmd_pgtable(pmd) pmd_page(pmd) -static inline struct page * +static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) { struct page *page = alloc_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); + if (page) + pgtable_page_ctor(page); return page; } @@ -135,7 +138,11 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) free_page((unsigned long)pte); } -#define pte_free(mm, page) pte_free_kernel(page_address(page)) +static inline void pte_free_kernel(struct mm_struct *mm, struct page *pte) +{ + pgtable_page_dtor(pte); + pte_free_kernel(page_address((pte)); +} #define check_pgt_cache() do { } while (0) diff --git a/include/asm-parisc/posix_types.h b/include/asm-parisc/posix_types.h index b634e3c47fd..bb725a6630b 100644 --- a/include/asm-parisc/posix_types.h +++ b/include/asm-parisc/posix_types.h @@ -47,18 +47,14 @@ typedef unsigned long long __kernel_ino64_t; typedef unsigned int __kernel_old_dev_t; typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; /* compatibility stuff */ typedef __kernel_uid_t __kernel_old_uid_t; typedef __kernel_gid_t __kernel_old_gid_t; -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) +#if defined(__KERNEL__) #undef __FD_SET static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) @@ -128,6 +124,6 @@ static __inline__ void __FD_ZERO(__kernel_fd_set *__p) } } -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* defined(__KERNEL__) */ #endif diff --git a/include/asm-parisc/processor.h b/include/asm-parisc/processor.h index 3bb06e898fd..3c9d34844c8 100644 --- a/include/asm-parisc/processor.h +++ b/include/asm-parisc/processor.h @@ -47,6 +47,16 @@ #define DEFAULT_MAP_BASE DEFAULT_MAP_BASE32 #endif +#ifdef __KERNEL__ + +/* XXX: STACK_TOP actually should be STACK_BOTTOM for parisc. + * prumpf */ + +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX DEFAULT_TASK_SIZE + +#endif + #ifndef __ASSEMBLY__ /* diff --git a/include/asm-powerpc/a.out.h b/include/asm-powerpc/a.out.h index 5c5ea83f934..89cead6b176 100644 --- a/include/asm-powerpc/a.out.h +++ b/include/asm-powerpc/a.out.h @@ -17,23 +17,4 @@ struct exec #define N_DRSIZE(a) ((a).a_drsize) #define N_SYMSIZE(a) ((a).a_syms) -#ifdef __KERNEL__ -#ifdef __powerpc64__ - -#define STACK_TOP_USER64 TASK_SIZE_USER64 -#define STACK_TOP_USER32 TASK_SIZE_USER32 - -#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ - STACK_TOP_USER32 : STACK_TOP_USER64) - -#define STACK_TOP_MAX STACK_TOP_USER64 - -#else /* __powerpc64__ */ - -#define STACK_TOP TASK_SIZE -#define STACK_TOP_MAX STACK_TOP - -#endif /* __powerpc64__ */ -#endif /* __KERNEL__ */ - #endif /* _ASM_POWERPC_A_OUT_H */ diff --git a/include/asm-powerpc/page.h b/include/asm-powerpc/page.h index 61e3725bbd3..df47bbb6ea1 100644 --- a/include/asm-powerpc/page.h +++ b/include/asm-powerpc/page.h @@ -190,6 +190,8 @@ extern int page_is_ram(unsigned long pfn); struct vm_area_struct; +typedef struct page *pgtable_t; + #include <asm-generic/memory_model.h> #endif /* __ASSEMBLY__ */ diff --git a/include/asm-powerpc/pgalloc-32.h b/include/asm-powerpc/pgalloc-32.h index c162a4c37b3..58c07147b3e 100644 --- a/include/asm-powerpc/pgalloc-32.h +++ b/include/asm-powerpc/pgalloc-32.h @@ -22,17 +22,19 @@ extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT) #define pmd_populate(mm, pmd, pte) \ (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT) +#define pmd_pgtable(pmd) pmd_page(pmd) #else #define pmd_populate_kernel(mm, pmd, pte) \ (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT) #define pmd_populate(mm, pmd, pte) \ (pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT) +#define pmd_pgtable(pmd) pmd_page(pmd) #endif extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr); -extern struct page *pte_alloc_one(struct mm_struct *mm, unsigned long addr); +extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr); extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte); -extern void pte_free(struct mm_struct *mm, struct page *pte); +extern void pte_free(struct mm_struct *mm, pgtable_t pte); #define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, (pte)) diff --git a/include/asm-powerpc/pgalloc-64.h b/include/asm-powerpc/pgalloc-64.h index 5afae859393..68980990f62 100644 --- a/include/asm-powerpc/pgalloc-64.h +++ b/include/asm-powerpc/pgalloc-64.h @@ -58,6 +58,7 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) #define pmd_populate(mm, pmd, pte_page) \ pmd_populate_kernel(mm, pmd, page_address(pte_page)) #define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, (unsigned long)(pte)) +#define pmd_pgtable(pmd) pmd_page(pmd) #else /* CONFIG_PPC_64K_PAGES */ @@ -72,6 +73,7 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, #define pmd_populate(mm, pmd, pte_page) \ pmd_populate_kernel(mm, pmd, page_address(pte_page)) +#define pmd_pgtable(pmd) pmd_page(pmd) #endif /* CONFIG_PPC_64K_PAGES */ @@ -92,11 +94,18 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO); } -static inline struct page *pte_alloc_one(struct mm_struct *mm, - unsigned long address) +static inline pgtable_t pte_alloc_one(struct mm_struct *mm, + unsigned long address) { - pte_t *pte = pte_alloc_one_kernel(mm, address); - return pte ? virt_to_page(pte) : NULL; + struct page *page; + pte_t *pte; + + pte = pte_alloc_one_kernel(mm, address); + if (!pte) + return NULL; + page = virt_to_page(pte); + pgtable_page_ctor(page); + return page; } static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) @@ -104,8 +113,9 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) free_page((unsigned long)pte); } -static inline void pte_free(struct mm_struct *mm, struct page *ptepage) +static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage) { + pgtable_page_dtor(ptepage); __free_page(ptepage); } @@ -136,9 +146,12 @@ static inline void pgtable_free(pgtable_free_t pgf) extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf); -#define __pte_free_tlb(tlb, ptepage) \ +#define __pte_free_tlb(tlb,ptepage) \ +do { \ + pgtable_page_dtor(ptepage); \ pgtable_free_tlb(tlb, pgtable_free_cache(page_address(ptepage), \ - PTE_NONCACHE_NUM, PTE_TABLE_SIZE-1)) + PTE_NONCACHE_NUM, PTE_TABLE_SIZE-1)); \ +} while (0) #define __pmd_free_tlb(tlb, pmd) \ pgtable_free_tlb(tlb, pgtable_free_cache(pmd, \ PMD_CACHE_NUM, PMD_TABLE_SIZE-1)) diff --git a/include/asm-powerpc/pmac_feature.h b/include/asm-powerpc/pmac_feature.h index 26bcb0aa164..877c35a4356 100644 --- a/include/asm-powerpc/pmac_feature.h +++ b/include/asm-powerpc/pmac_feature.h @@ -392,6 +392,14 @@ extern u32 __iomem *uninorth_base; #define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v))) #define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v))) +/* Uninorth variant: + * + * 0 = not uninorth + * 1 = U1.x or U2.x + * 3 = U3 + * 4 = U4 + */ +extern int pmac_get_uninorth_variant(void); #endif /* __ASM_POWERPC_PMAC_FEATURE_H */ #endif /* __KERNEL__ */ diff --git a/include/asm-powerpc/posix_types.h b/include/asm-powerpc/posix_types.h index 2f2288f520b..c4e396b540d 100644 --- a/include/asm-powerpc/posix_types.h +++ b/include/asm-powerpc/posix_types.h @@ -64,8 +64,7 @@ typedef struct { #else /* __GNUC__ */ -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \ - || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0) +#if defined(__KERNEL__) /* With GNU C, use inline functions instead so args are evaluated only once: */ #undef __FD_SET @@ -124,6 +123,6 @@ static __inline__ void __FD_ZERO(__kernel_fd_set *p) } } -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* defined(__KERNEL__) */ #endif /* __GNUC__ */ #endif /* _ASM_POWERPC_POSIX_TYPES_H */ diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h index 1f4765d6546..fd98ca998b4 100644 --- a/include/asm-powerpc/processor.h +++ b/include/asm-powerpc/processor.h @@ -113,6 +113,25 @@ extern struct task_struct *last_task_used_spe; TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 ) #endif +#ifdef __KERNEL__ +#ifdef __powerpc64__ + +#define STACK_TOP_USER64 TASK_SIZE_USER64 +#define STACK_TOP_USER32 TASK_SIZE_USER32 + +#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ + STACK_TOP_USER32 : STACK_TOP_USER64) + +#define STACK_TOP_MAX STACK_TOP_USER64 + +#else /* __powerpc64__ */ + +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP + +#endif /* __powerpc64__ */ +#endif /* __KERNEL__ */ + typedef struct { unsigned long seg; } mm_segment_t; diff --git a/include/asm-ppc/pgalloc.h b/include/asm-ppc/pgalloc.h index 7c39a95829c..fd4d1d74cfb 100644 --- a/include/asm-ppc/pgalloc.h +++ b/include/asm-ppc/pgalloc.h @@ -23,17 +23,19 @@ extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT) #define pmd_populate(mm, pmd, pte) \ (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT) +#define pmd_pgtable(pmd) pmd_page(pmd) #else #define pmd_populate_kernel(mm, pmd, pte) \ (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT) #define pmd_populate(mm, pmd, pte) \ (pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT) +#define pmd_pgtable(pmd) pmd_page(pmd) #endif extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr); -extern struct page *pte_alloc_one(struct mm_struct *mm, unsigned long addr); +extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr); extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte); -extern void pte_free(struct mm_struct *mm, struct page *pte); +extern void pte_free(struct mm_struct *mm, pgtable_t pte); #define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, (pte)) diff --git a/include/asm-s390/a.out.h b/include/asm-s390/a.out.h index 46158dcaf51..8d6bd9c2952 100644 --- a/include/asm-s390/a.out.h +++ b/include/asm-s390/a.out.h @@ -29,11 +29,4 @@ struct exec #define N_DRSIZE(a) ((a).a_drsize) #define N_SYMSIZE(a) ((a).a_syms) -#ifdef __KERNEL__ - -#define STACK_TOP TASK_SIZE -#define STACK_TOP_MAX DEFAULT_TASK_SIZE - -#endif - #endif /* __A_OUT_GNU_H__ */ diff --git a/include/asm-s390/ioctls.h b/include/asm-s390/ioctls.h index 07e19b2dd73..40e481b1b46 100644 --- a/include/asm-s390/ioctls.h +++ b/include/asm-s390/ioctls.h @@ -54,6 +54,10 @@ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define TIOCGSID 0x5429 /* Return the session ID of FD */ +#define TCGETS2 _IOR('T',0x2A, struct termios2) +#define TCSETS2 _IOW('T',0x2B, struct termios2) +#define TCSETSW2 _IOW('T',0x2C, struct termios2) +#define TCSETSF2 _IOW('T',0x2D, struct termios2) #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ diff --git a/include/asm-s390/page.h b/include/asm-s390/page.h index a55f9d979df..7f29a981f48 100644 --- a/include/asm-s390/page.h +++ b/include/asm-s390/page.h @@ -109,6 +109,8 @@ typedef struct { unsigned long pgd; } pgd_t; #endif /* __s390x__ */ +typedef struct page *pgtable_t; + #define __pte(x) ((pte_t) { (x) } ) #define __pmd(x) ((pmd_t) { (x) } ) #define __pgd(x) ((pgd_t) { (x) } ) diff --git a/include/asm-s390/pgalloc.h b/include/asm-s390/pgalloc.h index 6f6619ba898..900d44807e1 100644 --- a/include/asm-s390/pgalloc.h +++ b/include/asm-s390/pgalloc.h @@ -132,7 +132,7 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) } static inline void -pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *page) +pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t page) { pte_t *pte = (pte_t *)page_to_phys(page); pmd_t *shadow_pmd = get_shadow_table(pmd); @@ -142,6 +142,7 @@ pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *page) if (shadow_pmd && shadow_pte) pmd_populate_kernel(mm, shadow_pmd, shadow_pte); } +#define pmd_pgtable(pmd) pmd_page(pmd) /* * page table entry allocation/free routines. diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h index 4f744609cd1..e8785634cbd 100644 --- a/include/asm-s390/processor.h +++ b/include/asm-s390/processor.h @@ -78,6 +78,13 @@ extern int get_cpu_capability(unsigned int *); #endif /* __s390x__ */ +#ifdef __KERNEL__ + +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX DEFAULT_TASK_SIZE + +#endif + #define HAVE_ARCH_PICK_MMAP_LAYOUT typedef struct { @@ -161,6 +168,7 @@ struct stack_frame { /* Forward declaration, a strange C thing */ struct task_struct; struct mm_struct; +struct seq_file; /* Free all resources held by a thread. */ extern void release_thread(struct task_struct *); @@ -177,7 +185,7 @@ extern unsigned long thread_saved_pc(struct task_struct *t); /* * Print register of task into buffer. Used in fs/proc/array.c. */ -extern char *task_show_regs(struct task_struct *task, char *buffer); +extern void task_show_regs(struct seq_file *m, struct task_struct *task); extern void show_registers(struct pt_regs *regs); extern void show_code(struct pt_regs *regs); diff --git a/include/asm-s390/termbits.h b/include/asm-s390/termbits.h index 811b9a9cdc0..58731853d52 100644 --- a/include/asm-s390/termbits.h +++ b/include/asm-s390/termbits.h @@ -148,6 +148,7 @@ struct ktermios { #define HUPCL 0002000 #define CLOCAL 0004000 #define CBAUDEX 0010000 +#define BOTHER 0010000 #define B57600 0010001 #define B115200 0010002 #define B230400 0010003 @@ -163,10 +164,12 @@ struct ktermios { #define B3000000 0010015 #define B3500000 0010016 #define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate (not used) */ +#define CIBAUD 002003600000 /* input baud rate */ #define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ +#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ + /* c_lflag bits */ #define ISIG 0000001 #define ICANON 0000002 diff --git a/include/asm-s390/termios.h b/include/asm-s390/termios.h index a3480e25eb4..67f66278f53 100644 --- a/include/asm-s390/termios.h +++ b/include/asm-s390/termios.h @@ -57,6 +57,9 @@ struct termio { */ #define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" +#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) +#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) + #include <asm-generic/termios.h> #endif /* __KERNEL__ */ diff --git a/include/asm-s390/tlb.h b/include/asm-s390/tlb.h index 985de2b8827..3c8177fa9e0 100644 --- a/include/asm-s390/tlb.h +++ b/include/asm-s390/tlb.h @@ -95,7 +95,7 @@ static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page) * pte_free_tlb frees a pte table and clears the CRSTE for the * page table from the tlb. */ -static inline void pte_free_tlb(struct mmu_gather *tlb, struct page *page) +static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t page) { if (!tlb->fullmm) { tlb->array[tlb->nr_ptes++] = page; diff --git a/include/asm-sh/a.out.h b/include/asm-sh/a.out.h index 685d0f6125f..1f93130e179 100644 --- a/include/asm-sh/a.out.h +++ b/include/asm-sh/a.out.h @@ -17,11 +17,4 @@ struct exec #define N_DRSIZE(a) ((a).a_drsize) #define N_SYMSIZE(a) ((a).a_syms) -#ifdef __KERNEL__ - -#define STACK_TOP TASK_SIZE -#define STACK_TOP_MAX STACK_TOP - -#endif - #endif /* __ASM_SH_A_OUT_H */ diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h index e0fe02950f5..134562dc8c4 100644 --- a/include/asm-sh/page.h +++ b/include/asm-sh/page.h @@ -100,6 +100,8 @@ typedef struct { unsigned long pgd; } pgd_t; #define __pgd(x) ((pgd_t) { (x) } ) #define __pgprot(x) ((pgprot_t) { (x) } ) +typedef struct page *pgtable_t; + #endif /* !__ASSEMBLY__ */ /* diff --git a/include/asm-sh/pgalloc.h b/include/asm-sh/pgalloc.h index 59ca16d77a1..84dd2db7104 100644 --- a/include/asm-sh/pgalloc.h +++ b/include/asm-sh/pgalloc.h @@ -14,10 +14,11 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, } static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, - struct page *pte) + pgtable_t pte) { set_pmd(pmd, __pmd((unsigned long)page_address(pte))); } +#define pmd_pgtable(pmd) pmd_page(pmd) static inline void pgd_ctor(void *x) { @@ -47,11 +48,18 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, return quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL); } -static inline struct page *pte_alloc_one(struct mm_struct *mm, - unsigned long address) +static inline pgtable_t pte_alloc_one(struct mm_struct *mm, + unsigned long address) { - void *pg = quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL); - return pg ? virt_to_page(pg) : NULL; + struct page *page; + void *pg; + + pg = quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL); + if (!pg) + return NULL; + page = virt_to_page(pg); + pgtable_page_ctor(page); + return page; } static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) @@ -59,12 +67,17 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) quicklist_free(QUICK_PT, NULL, pte); } -static inline void pte_free(struct mm_struct *mm, struct page *pte) +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) { + pgtable_page_dtor(pte); quicklist_free_page(QUICK_PT, NULL, pte); } -#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) +#define __pte_free_tlb(tlb,pte) \ +do { \ + pgtable_page_dtor(pte); \ + tlb_remove_page((tlb), (pte)); \ +} while (0) /* * allocating and freeing a pmd is trivial: the 1-entry pmd is diff --git a/include/asm-sh/processor_32.h b/include/asm-sh/processor_32.h index a7edaa1a870..df2d5b039ef 100644 --- a/include/asm-sh/processor_32.h +++ b/include/asm-sh/processor_32.h @@ -50,6 +50,9 @@ extern struct sh_cpuinfo cpu_data[]; */ #define TASK_SIZE 0x7c000000UL +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP + /* This decides where the kernel will search for a free chunk of vm * space during mmap's. */ diff --git a/include/asm-sh/processor_64.h b/include/asm-sh/processor_64.h index 99c22b14a85..eda4bef448e 100644 --- a/include/asm-sh/processor_64.h +++ b/include/asm-sh/processor_64.h @@ -83,6 +83,9 @@ extern struct sh_cpuinfo cpu_data[]; */ #define TASK_SIZE 0x7ffff000UL +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP + /* This decides where the kernel will search for a free chunk of vm * space during mmap's. */ diff --git a/include/asm-sparc/a.out-core.h b/include/asm-sparc/a.out-core.h new file mode 100644 index 00000000000..e8fd338ed0b --- /dev/null +++ b/include/asm-sparc/a.out-core.h @@ -0,0 +1,52 @@ +/* a.out coredump register dumper + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_A_OUT_CORE_H +#define _ASM_A_OUT_CORE_H + +#ifdef __KERNEL__ + +#include <linux/user.h> + +/* + * fill in the user structure for an a.out core dump + */ +static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) +{ + unsigned long first_stack_page; + + dump->magic = SUNOS_CORE_MAGIC; + dump->len = sizeof(struct user); + dump->regs.psr = regs->psr; + dump->regs.pc = regs->pc; + dump->regs.npc = regs->npc; + dump->regs.y = regs->y; + /* fuck me plenty */ + memcpy(&dump->regs.regs[0], ®s->u_regs[1], (sizeof(unsigned long) * 15)); + dump->uexec = current->thread.core_exec; + dump->u_tsize = (((unsigned long) current->mm->end_code) - + ((unsigned long) current->mm->start_code)) & ~(PAGE_SIZE - 1); + dump->u_dsize = ((unsigned long) (current->mm->brk + (PAGE_SIZE-1))); + dump->u_dsize -= dump->u_tsize; + dump->u_dsize &= ~(PAGE_SIZE - 1); + first_stack_page = (regs->u_regs[UREG_FP] & ~(PAGE_SIZE - 1)); + dump->u_ssize = (TASK_SIZE - first_stack_page) & ~(PAGE_SIZE - 1); + memcpy(&dump->fpu.fpstatus.fregs.regs[0], ¤t->thread.float_regs[0], (sizeof(unsigned long) * 32)); + dump->fpu.fpstatus.fsr = current->thread.fsr; + dump->fpu.fpstatus.flags = dump->fpu.fpstatus.extra = 0; + dump->fpu.fpstatus.fpq_count = current->thread.fpqdepth; + memcpy(&dump->fpu.fpstatus.fpq[0], ¤t->thread.fpqueue[0], + ((sizeof(unsigned long) * 2) * 16)); + dump->sigcode = 0; +} + +#endif /* __KERNEL__ */ +#endif /* _ASM_A_OUT_CORE_H */ diff --git a/include/asm-sparc/a.out.h b/include/asm-sparc/a.out.h index 917e0425069..744cfe6c0de 100644 --- a/include/asm-sparc/a.out.h +++ b/include/asm-sparc/a.out.h @@ -87,13 +87,4 @@ struct relocation_info /* used when header.a_machtype == M_SPARC */ #define N_RELOCATION_INFO_DECLARED 1 -#ifdef __KERNEL__ - -#include <asm/page.h> - -#define STACK_TOP (PAGE_OFFSET - PAGE_SIZE) -#define STACK_TOP_MAX STACK_TOP - -#endif /* __KERNEL__ */ - #endif /* __SPARC_A_OUT_H__ */ diff --git a/include/asm-sparc/page.h b/include/asm-sparc/page.h index cbc48c0c4e1..39ccf2da297 100644 --- a/include/asm-sparc/page.h +++ b/include/asm-sparc/page.h @@ -123,6 +123,8 @@ typedef unsigned long iopgprot_t; #endif +typedef struct page *pgtable_t; + extern unsigned long sparc_unmapped_base; BTFIXUPDEF_SETHI(sparc_unmapped_base) diff --git a/include/asm-sparc/param.h b/include/asm-sparc/param.h index beaf02d364f..86ba59af9d2 100644 --- a/include/asm-sparc/param.h +++ b/include/asm-sparc/param.h @@ -3,7 +3,7 @@ #define _ASMSPARC_PARAM_H #ifdef __KERNEL__ -# define HZ 100 /* Internal kernel timer frequency */ +# define HZ CONFIG_HZ /* Internal kernel timer frequency */ # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ # define CLOCKS_PER_SEC (USER_HZ) #endif diff --git a/include/asm-sparc/pgalloc.h b/include/asm-sparc/pgalloc.h index b5fbdd36447..6292cd00e5a 100644 --- a/include/asm-sparc/pgalloc.h +++ b/include/asm-sparc/pgalloc.h @@ -50,10 +50,11 @@ BTFIXUPDEF_CALL(void, free_pmd_fast, pmd_t *) BTFIXUPDEF_CALL(void, pmd_populate, pmd_t *, struct page *) #define pmd_populate(MM, PMD, PTE) BTFIXUP_CALL(pmd_populate)(PMD, PTE) +#define pmd_pgtable(pmd) pmd_page(pmd) BTFIXUPDEF_CALL(void, pmd_set, pmd_t *, pte_t *) #define pmd_populate_kernel(MM, PMD, PTE) BTFIXUP_CALL(pmd_set)(PMD, PTE) -BTFIXUPDEF_CALL(struct page *, pte_alloc_one, struct mm_struct *, unsigned long) +BTFIXUPDEF_CALL(pgtable_t , pte_alloc_one, struct mm_struct *, unsigned long) #define pte_alloc_one(mm, address) BTFIXUP_CALL(pte_alloc_one)(mm, address) BTFIXUPDEF_CALL(pte_t *, pte_alloc_one_kernel, struct mm_struct *, unsigned long) #define pte_alloc_one_kernel(mm, addr) BTFIXUP_CALL(pte_alloc_one_kernel)(mm, addr) @@ -61,7 +62,7 @@ BTFIXUPDEF_CALL(pte_t *, pte_alloc_one_kernel, struct mm_struct *, unsigned long BTFIXUPDEF_CALL(void, free_pte_fast, pte_t *) #define pte_free_kernel(mm, pte) BTFIXUP_CALL(free_pte_fast)(pte) -BTFIXUPDEF_CALL(void, pte_free, struct page *) +BTFIXUPDEF_CALL(void, pte_free, pgtable_t ) #define pte_free(mm, pte) BTFIXUP_CALL(pte_free)(pte) #define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, pte) diff --git a/include/asm-sparc/posix_types.h b/include/asm-sparc/posix_types.h index 62c8fa7b36d..dcc07eb5e18 100644 --- a/include/asm-sparc/posix_types.h +++ b/include/asm-sparc/posix_types.h @@ -39,14 +39,10 @@ typedef long long __kernel_loff_t; #endif typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) +#if defined(__KERNEL__) #undef __FD_SET static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp) @@ -117,6 +113,6 @@ static inline void __FD_ZERO(__kernel_fd_set *p) } } -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* defined(__KERNEL__) */ #endif /* !(__ARCH_SPARC_POSIX_TYPES_H) */ diff --git a/include/asm-sparc/processor.h b/include/asm-sparc/processor.h index 6fbb3f0af8d..40b1e41fdea 100644 --- a/include/asm-sparc/processor.h +++ b/include/asm-sparc/processor.h @@ -33,6 +33,10 @@ * we can make our access_ok test faster */ #define TASK_SIZE PAGE_OFFSET +#ifdef __KERNEL__ +#define STACK_TOP (PAGE_OFFSET - PAGE_SIZE) +#define STACK_TOP_MAX STACK_TOP +#endif /* __KERNEL__ */ struct task_struct; diff --git a/include/asm-sparc/uaccess.h b/include/asm-sparc/uaccess.h index 3cf132e1aa2..366b11696ee 100644 --- a/include/asm-sparc/uaccess.h +++ b/include/asm-sparc/uaccess.h @@ -13,7 +13,6 @@ #include <linux/string.h> #include <linux/errno.h> #include <asm/vac-ops.h> -#include <asm/a.out.h> #endif #ifndef __ASSEMBLY__ diff --git a/include/asm-sparc64/a.out-core.h b/include/asm-sparc64/a.out-core.h new file mode 100644 index 00000000000..3499b3c425c --- /dev/null +++ b/include/asm-sparc64/a.out-core.h @@ -0,0 +1,31 @@ +/* a.out coredump register dumper + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_A_OUT_CORE_H +#define _ASM_A_OUT_CORE_H + +#ifdef __KERNEL__ + +#include <linux/user.h> + +/* + * fill in the user structure for an a.out core dump + */ +static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) +{ + /* Only should be used for SunOS and ancient a.out + * SparcLinux binaries... Not worth implementing. + */ + memset(dump, 0, sizeof(struct user)); +} + +#endif /* __KERNEL__ */ +#endif /* _ASM_A_OUT_CORE_H */ diff --git a/include/asm-sparc64/a.out.h b/include/asm-sparc64/a.out.h index 902e07f89a4..53c95bdfc66 100644 --- a/include/asm-sparc64/a.out.h +++ b/include/asm-sparc64/a.out.h @@ -93,18 +93,6 @@ struct relocation_info /* used when header.a_machtype == M_SPARC */ #define N_RELOCATION_INFO_DECLARED 1 -#ifdef __KERNEL__ - -#define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE) -#define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL)) - -#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ - STACK_TOP32 : STACK_TOP64) - -#define STACK_TOP_MAX STACK_TOP64 - -#endif - #endif /* !(__ASSEMBLY__) */ #endif /* !(__SPARC64_A_OUT_H__) */ diff --git a/include/asm-sparc64/elf.h b/include/asm-sparc64/elf.h index 272a65873f2..11c8e68d712 100644 --- a/include/asm-sparc64/elf.h +++ b/include/asm-sparc64/elf.h @@ -75,7 +75,6 @@ /* * These are used to set parameters in the core dumps. */ -#ifndef ELF_ARCH #define ELF_ARCH EM_SPARCV9 #define ELF_CLASS ELFCLASS64 #define ELF_DATA ELFDATA2MSB @@ -100,14 +99,59 @@ typedef struct { unsigned long pr_gsr; unsigned long pr_fprs; } elf_fpregset_t; -#endif + +/* Format of 32-bit elf_gregset_t is: + * G0 --> G7 + * O0 --> O7 + * L0 --> L7 + * I0 --> I7 + * PSR, PC, nPC, Y, WIM, TBR + */ +typedef unsigned int compat_elf_greg_t; +#define COMPAT_ELF_NGREG 38 +typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG]; + +typedef struct { + union { + unsigned int pr_regs[32]; + unsigned long pr_dregs[16]; + } pr_fr; + unsigned int __unused; + unsigned int pr_fsr; + unsigned char pr_qcnt; + unsigned char pr_q_entrysize; + unsigned char pr_en; + unsigned int pr_q[64]; +} compat_elf_fpregset_t; + +/* UltraSparc extensions. Still unused, but will be eventually. */ +typedef struct { + unsigned int pr_type; + unsigned int pr_align; + union { + struct { + union { + unsigned int pr_regs[32]; + unsigned long pr_dregs[16]; + long double pr_qregs[8]; + } pr_xfr; + } pr_v8p; + unsigned int pr_xfsr; + unsigned int pr_fprs; + unsigned int pr_xg[8]; + unsigned int pr_xo[8]; + unsigned long pr_tstate; + unsigned int pr_filler[8]; + } pr_un; +} elf_xregset_t; /* * This is used to ensure we don't load something for the wrong architecture. */ -#ifndef elf_check_arch -#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) /* Might be EM_SPARCV9 or EM_SPARC */ -#endif +#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) +#define compat_elf_check_arch(x) ((x)->e_machine == EM_SPARC || \ + (x)->e_machine == EM_SPARC32PLUS) +#define compat_start_thread start_thread32 #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE PAGE_SIZE @@ -117,9 +161,8 @@ typedef struct { the loader. We need to make sure that it is out of the way of the program that it will "exec", and that there is sufficient room for the brk. */ -#ifndef ELF_ET_DYN_BASE -#define ELF_ET_DYN_BASE 0x0000010000000000UL -#endif +#define ELF_ET_DYN_BASE 0x0000010000000000UL +#define COMPAT_ELF_ET_DYN_BASE 0x0000000070000000UL /* This yields a mask that user programs can use to figure out what diff --git a/include/asm-sparc64/page.h b/include/asm-sparc64/page.h index cdf950e017e..e93a482aa24 100644 --- a/include/asm-sparc64/page.h +++ b/include/asm-sparc64/page.h @@ -104,6 +104,8 @@ typedef unsigned long pgprot_t; #endif /* (STRICT_MM_TYPECHECKS) */ +typedef struct page *pgtable_t; + #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_32BIT) ? \ (_AC(0x0000000070000000,UL)) : \ (_AC(0xfffff80000000000,UL) + (1UL << 32UL))) diff --git a/include/asm-sparc64/pgalloc.h b/include/asm-sparc64/pgalloc.h index b48f73c2274..3ee2d406373 100644 --- a/include/asm-sparc64/pgalloc.h +++ b/include/asm-sparc64/pgalloc.h @@ -43,11 +43,18 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, return quicklist_alloc(0, GFP_KERNEL, NULL); } -static inline struct page *pte_alloc_one(struct mm_struct *mm, - unsigned long address) +static inline pgtable_t pte_alloc_one(struct mm_struct *mm, + unsigned long address) { - void *pg = quicklist_alloc(0, GFP_KERNEL, NULL); - return pg ? virt_to_page(pg) : NULL; + struct page *page; + void *pg; + + pg = quicklist_alloc(0, GFP_KERNEL, NULL); + if (!pg) + return NULL; + page = virt_to_page(pg); + pgtable_page_ctor(page); + return page; } static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) @@ -55,8 +62,9 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) quicklist_free(0, NULL, pte); } -static inline void pte_free(struct mm_struct *mm, struct page *ptepage) +static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage) { + pgtable_page_dtor(ptepage); quicklist_free_page(0, NULL, ptepage); } @@ -64,6 +72,7 @@ static inline void pte_free(struct mm_struct *mm, struct page *ptepage) #define pmd_populate_kernel(MM, PMD, PTE) pmd_set(PMD, PTE) #define pmd_populate(MM,PMD,PTE_PAGE) \ pmd_populate_kernel(MM,PMD,page_address(PTE_PAGE)) +#define pmd_pgtable(pmd) pmd_page(pmd) static inline void check_pgt_cache(void) { diff --git a/include/asm-sparc64/posix_types.h b/include/asm-sparc64/posix_types.h index 3426a65ecd3..4eaaa019663 100644 --- a/include/asm-sparc64/posix_types.h +++ b/include/asm-sparc64/posix_types.h @@ -43,14 +43,10 @@ typedef long long __kernel_loff_t; #endif typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) +#if defined(__KERNEL__) #undef __FD_SET static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp) @@ -121,6 +117,6 @@ static inline void __FD_ZERO(__kernel_fd_set *p) } } -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* defined(__KERNEL__) */ #endif /* !(__ARCH_SPARC64_POSIX_TYPES_H) */ diff --git a/include/asm-sparc64/processor.h b/include/asm-sparc64/processor.h index 66dd2fa0e31..8da484c1982 100644 --- a/include/asm-sparc64/processor.h +++ b/include/asm-sparc64/processor.h @@ -14,7 +14,6 @@ #define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; }) #include <asm/asi.h> -#include <asm/a.out.h> #include <asm/pstate.h> #include <asm/ptrace.h> #include <asm/page.h> @@ -36,7 +35,19 @@ #else #define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3)) #endif + #define TASK_SIZE ((unsigned long)-VPTE_SIZE) +#ifdef __KERNEL__ + +#define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE) +#define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL)) + +#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ + STACK_TOP32 : STACK_TOP64) + +#define STACK_TOP_MAX STACK_TOP64 + +#endif #ifndef __ASSEMBLY__ diff --git a/include/asm-sparc64/ptrace.h b/include/asm-sparc64/ptrace.h index 734a767f0a4..8617c3a5143 100644 --- a/include/asm-sparc64/ptrace.h +++ b/include/asm-sparc64/ptrace.h @@ -95,6 +95,8 @@ struct sparc_trapf { #ifdef __KERNEL__ +#define __ARCH_WANT_COMPAT_SYS_PTRACE + #define force_successful_syscall_return() \ do { current_thread_info()->syscall_noerror = 1; \ } while (0) diff --git a/include/asm-sparc64/uaccess.h b/include/asm-sparc64/uaccess.h index 93720e7b028..d8547b87e73 100644 --- a/include/asm-sparc64/uaccess.h +++ b/include/asm-sparc64/uaccess.h @@ -10,7 +10,6 @@ #include <linux/compiler.h> #include <linux/sched.h> #include <linux/string.h> -#include <asm/a.out.h> #include <asm/asi.h> #include <asm/system.h> #include <asm/spitfire.h> diff --git a/include/asm-sparc64/user.h b/include/asm-sparc64/user.h index fce4e857dfc..02b13894383 100644 --- a/include/asm-sparc64/user.h +++ b/include/asm-sparc64/user.h @@ -8,7 +8,7 @@ #ifndef _SPARC64_USER_H #define _SPARC64_USER_H -#include <asm/a.out.h> +#include <linux/a.out.h> struct sunos_regs { unsigned int psr, pc, npc, y; unsigned int regs[15]; diff --git a/include/asm-um/a.out-core.h b/include/asm-um/a.out-core.h new file mode 100644 index 00000000000..995643b1830 --- /dev/null +++ b/include/asm-um/a.out-core.h @@ -0,0 +1,27 @@ +/* a.out coredump register dumper + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef __UM_A_OUT_CORE_H +#define __UM_A_OUT_CORE_H + +#ifdef __KERNEL__ + +#include <linux/user.h> + +/* + * fill in the user structure for an a.out core dump + */ +static inline void aout_dump_thread(struct pt_regs *regs, struct user *u) +{ +} + +#endif /* __KERNEL__ */ +#endif /* __UM_A_OUT_CORE_H */ diff --git a/include/asm-um/a.out.h b/include/asm-um/a.out.h index f42ff14577f..754181ee868 100644 --- a/include/asm-um/a.out.h +++ b/include/asm-um/a.out.h @@ -8,15 +8,4 @@ #include "asm/arch/a.out.h" -#undef STACK_TOP -#undef STACK_TOP_MAX - -extern unsigned long stacksizelim; - -#define STACK_ROOM (stacksizelim) - -#define STACK_TOP (TASK_SIZE - 2 * PAGE_SIZE) - -#define STACK_TOP_MAX STACK_TOP - #endif diff --git a/include/asm-um/fixmap.h b/include/asm-um/fixmap.h index 89a87c18b92..9d2be52b865 100644 --- a/include/asm-um/fixmap.h +++ b/include/asm-um/fixmap.h @@ -1,6 +1,7 @@ #ifndef __UM_FIXMAP_H #define __UM_FIXMAP_H +#include <asm/processor.h> #include <asm/system.h> #include <asm/kmap_types.h> #include <asm/archparam.h> @@ -57,7 +58,7 @@ extern void __set_fixmap (enum fixed_addresses idx, * at the top of mem.. */ -#define FIXADDR_TOP (CONFIG_TOP_ADDR - 2 * PAGE_SIZE) +#define FIXADDR_TOP (TASK_SIZE - 2 * PAGE_SIZE) #define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) diff --git a/include/asm-um/page.h b/include/asm-um/page.h index fe2374d705d..381f96b1c82 100644 --- a/include/asm-um/page.h +++ b/include/asm-um/page.h @@ -79,6 +79,8 @@ typedef unsigned long phys_t; typedef struct { unsigned long pgprot; } pgprot_t; +typedef struct page *pgtable_t; + #define pgd_val(x) ((x).pgd) #define pgprot_val(x) ((x).pgprot) diff --git a/include/asm-um/pgalloc.h b/include/asm-um/pgalloc.h index 4f3e62b0286..9062a6e7224 100644 --- a/include/asm-um/pgalloc.h +++ b/include/asm-um/pgalloc.h @@ -18,6 +18,7 @@ set_pmd(pmd, __pmd(_PAGE_TABLE + \ ((unsigned long long)page_to_pfn(pte) << \ (unsigned long long) PAGE_SHIFT))) +#define pmd_pgtable(pmd) pmd_page(pmd) /* * Allocate and free page tables. @@ -26,19 +27,24 @@ extern pgd_t *pgd_alloc(struct mm_struct *); extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long); -extern struct page *pte_alloc_one(struct mm_struct *, unsigned long); +extern pgtable_t pte_alloc_one(struct mm_struct *, unsigned long); static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) { free_page((unsigned long) pte); } -static inline void pte_free(struct mm_struct *mm, struct page *pte) +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) { + pgtable_page_dtor(pte); __free_page(pte); } -#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) +#define __pte_free_tlb(tlb,pte) \ +do { \ + pgtable_page_dtor(pte); \ + tlb_remove_page((tlb),(pte)); \ +} while (0) #ifdef CONFIG_3_LEVEL_PGTABLES diff --git a/include/asm-um/processor-generic.h b/include/asm-um/processor-generic.h index b7d9a16a745..bed668824b5 100644 --- a/include/asm-um/processor-generic.h +++ b/include/asm-um/processor-generic.h @@ -11,7 +11,6 @@ struct pt_regs; struct task_struct; #include "asm/ptrace.h" -#include "asm/pgtable.h" #include "registers.h" #include "sysdep/archsetjmp.h" @@ -92,7 +91,18 @@ static inline void mm_copy_segments(struct mm_struct *from_mm, /* * User space process size: 3GB (default). */ -#define TASK_SIZE (CONFIG_TOP_ADDR & PGDIR_MASK) +extern unsigned long task_size; + +#define TASK_SIZE (task_size) + +#undef STACK_TOP +#undef STACK_TOP_MAX + +extern unsigned long stacksizelim; + +#define STACK_ROOM (stacksizelim) +#define STACK_TOP (TASK_SIZE - 2 * PAGE_SIZE) +#define STACK_TOP_MAX STACK_TOP /* This decides where the kernel will search for a free chunk of vm * space during mmap's. diff --git a/include/asm-um/processor-x86_64.h b/include/asm-um/processor-x86_64.h index d946bf2d334..e50933175e9 100644 --- a/include/asm-um/processor-x86_64.h +++ b/include/asm-um/processor-x86_64.h @@ -26,7 +26,7 @@ static inline void rep_nop(void) #define cpu_relax() rep_nop() #define INIT_ARCH_THREAD { .debugregs = { [ 0 ... 7 ] = 0 }, \ - .debugregs_seq = 0, \ + .debugregs_seq = 0, \ .fs = 0, \ .faultinfo = { 0, 0, 0 } } @@ -37,6 +37,7 @@ static inline void arch_flush_thread(struct arch_thread *thread) static inline void arch_copy_thread(struct arch_thread *from, struct arch_thread *to) { + to->fs = from->fs; } #include "asm/arch/user.h" diff --git a/include/asm-v850/anna.h b/include/asm-v850/anna.h index 3be77d5ecfc..cd5eaee103b 100644 --- a/include/asm-v850/anna.h +++ b/include/asm-v850/anna.h @@ -134,10 +134,4 @@ extern void anna_uart_pre_configure (unsigned chan, #define V850E_TIMER_D_TMCD_CS_MIN 1 /* min 2^1 divider */ -/* For <asm/param.h> */ -#ifndef HZ -#define HZ 100 -#endif - - #endif /* __V850_ANNA_H__ */ diff --git a/include/asm-v850/as85ep1.h b/include/asm-v850/as85ep1.h index 659bc910ffd..5a5ca9073d0 100644 --- a/include/asm-v850/as85ep1.h +++ b/include/asm-v850/as85ep1.h @@ -149,10 +149,4 @@ extern void as85ep1_uart_pre_configure (unsigned chan, #define V850E_TIMER_D_TMCD_CS_MIN 2 /* min 2^2 divider */ -/* For <asm/param.h> */ -#ifndef HZ -#define HZ 100 -#endif - - #endif /* __V850_AS85EP1_H__ */ diff --git a/include/asm-v850/fpga85e2c.h b/include/asm-v850/fpga85e2c.h index d32f04504b1..23aae666c71 100644 --- a/include/asm-v850/fpga85e2c.h +++ b/include/asm-v850/fpga85e2c.h @@ -79,10 +79,4 @@ extern char _r0_ram; #endif -/* For <asm/param.h> */ -#ifndef HZ -#define HZ 122 /* actually, 8.192ms ticks =~ 122.07 */ -#endif - - #endif /* __V850_FPGA85E2C_H__ */ diff --git a/include/asm-v850/param.h b/include/asm-v850/param.h index 3c65bd57378..28183269029 100644 --- a/include/asm-v850/param.h +++ b/include/asm-v850/param.h @@ -23,8 +23,7 @@ #define MAXHOSTNAMELEN 64 /* max length of hostname */ #ifdef __KERNEL__ -#include <asm/machdep.h> /* For HZ */ - +# define HZ CONFIG_HZ # define USER_HZ 100 # define CLOCKS_PER_SEC USER_HZ #endif diff --git a/include/asm-v850/posix_types.h b/include/asm-v850/posix_types.h index ccb7297a0ed..7f403b76539 100644 --- a/include/asm-v850/posix_types.h +++ b/include/asm-v850/posix_types.h @@ -44,15 +44,11 @@ typedef __kernel_uid_t __kernel_old_uid_t; typedef unsigned int __kernel_old_dev_t; typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) +#if defined(__KERNEL__) /* We used to include <asm/bitops.h> here, which seems the right thing, but it caused nasty include-file definition order problems. Removing the @@ -71,6 +67,6 @@ typedef struct { #define __FD_ZERO(fd_set) \ memset (fd_set, 0, sizeof (*(fd_set *)fd_set)) -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* defined(__KERNEL__) */ #endif /* __V850_POSIX_TYPES_H__ */ diff --git a/include/asm-v850/rte_cb.h b/include/asm-v850/rte_cb.h index e85d261b79b..db9879f00aa 100644 --- a/include/asm-v850/rte_cb.h +++ b/include/asm-v850/rte_cb.h @@ -69,12 +69,6 @@ #endif /* CONFIG_RTE_MB_A_PCI */ -/* For <asm/param.h> */ -#ifndef HZ -#define HZ 100 -#endif - - #ifndef __ASSEMBLY__ extern void rte_cb_early_init (void); extern void rte_cb_init_irqs (void); diff --git a/include/asm-v850/sim.h b/include/asm-v850/sim.h index 10236abbe9b..026932d476c 100644 --- a/include/asm-v850/sim.h +++ b/include/asm-v850/sim.h @@ -40,11 +40,6 @@ #define R0_RAM_ADDR 0xFFFFF000 -/* For <asm/param.h> */ -#ifndef HZ -#define HZ 24 /* Minimum supported frequency. */ -#endif - /* For <asm/irq.h> */ #define NUM_CPU_IRQS 6 diff --git a/include/asm-v850/sim85e2.h b/include/asm-v850/sim85e2.h index 17dd4fa318e..8b4d6974066 100644 --- a/include/asm-v850/sim85e2.h +++ b/include/asm-v850/sim85e2.h @@ -66,10 +66,4 @@ #define R0_RAM_ADDR 0xFFFFE000 -/* For <asm/param.h> */ -#ifndef HZ -#define HZ 24 /* Minimum supported frequency. */ -#endif - - #endif /* __V850_SIM85E2_H__ */ diff --git a/include/asm-x86/a.out-core.h b/include/asm-x86/a.out-core.h new file mode 100644 index 00000000000..d2b6e11d3e9 --- /dev/null +++ b/include/asm-x86/a.out-core.h @@ -0,0 +1,71 @@ +/* a.out coredump register dumper + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_A_OUT_CORE_H +#define _ASM_A_OUT_CORE_H + +#ifdef __KERNEL__ +#ifdef CONFIG_X86_32 + +#include <linux/user.h> +#include <linux/elfcore.h> + +/* + * fill in the user structure for an a.out core dump + */ +static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) +{ + u16 gs; + +/* changed the size calculations - should hopefully work better. lbt */ + dump->magic = CMAGIC; + dump->start_code = 0; + dump->start_stack = regs->sp & ~(PAGE_SIZE - 1); + dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT; + dump->u_dsize = ((unsigned long) (current->mm->brk + (PAGE_SIZE-1))) >> PAGE_SHIFT; + dump->u_dsize -= dump->u_tsize; + dump->u_ssize = 0; + dump->u_debugreg[0] = current->thread.debugreg0; + dump->u_debugreg[1] = current->thread.debugreg1; + dump->u_debugreg[2] = current->thread.debugreg2; + dump->u_debugreg[3] = current->thread.debugreg3; + dump->u_debugreg[4] = 0; + dump->u_debugreg[5] = 0; + dump->u_debugreg[6] = current->thread.debugreg6; + dump->u_debugreg[7] = current->thread.debugreg7; + + if (dump->start_stack < TASK_SIZE) + dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT; + + dump->regs.bx = regs->bx; + dump->regs.cx = regs->cx; + dump->regs.dx = regs->dx; + dump->regs.si = regs->si; + dump->regs.di = regs->di; + dump->regs.bp = regs->bp; + dump->regs.ax = regs->ax; + dump->regs.ds = (u16)regs->ds; + dump->regs.es = (u16)regs->es; + dump->regs.fs = (u16)regs->fs; + savesegment(gs,gs); + dump->regs.orig_ax = regs->orig_ax; + dump->regs.ip = regs->ip; + dump->regs.cs = (u16)regs->cs; + dump->regs.flags = regs->flags; + dump->regs.sp = regs->sp; + dump->regs.ss = (u16)regs->ss; + + dump->u_fpvalid = dump_fpu (regs, &dump->i387); +} + +#endif /* CONFIG_X86_32 */ +#endif /* __KERNEL__ */ +#endif /* _ASM_A_OUT_CORE_H */ diff --git a/include/asm-x86/a.out.h b/include/asm-x86/a.out.h index a62443e38eb..4684f97a5bb 100644 --- a/include/asm-x86/a.out.h +++ b/include/asm-x86/a.out.h @@ -17,14 +17,4 @@ struct exec #define N_DRSIZE(a) ((a).a_drsize) #define N_SYMSIZE(a) ((a).a_syms) -#ifdef __KERNEL__ -# include <linux/thread_info.h> -# define STACK_TOP TASK_SIZE -# ifdef CONFIG_X86_32 -# define STACK_TOP_MAX STACK_TOP -# else -# define STACK_TOP_MAX TASK_SIZE64 -# endif -#endif - #endif /* _ASM_X86_A_OUT_H */ diff --git a/include/asm-x86/page_32.h b/include/asm-x86/page_32.h index a6fd10f230d..984998a3074 100644 --- a/include/asm-x86/page_32.h +++ b/include/asm-x86/page_32.h @@ -53,6 +53,10 @@ typedef pte_t boot_pte_t; #endif /* __ASSEMBLY__ */ #endif /* CONFIG_X86_PAE */ +#ifndef __ASSEMBLY__ +typedef struct page *pgtable_t; +#endif + #ifdef CONFIG_HUGETLB_PAGE #define HAVE_ARCH_HUGETLB_UNMAPPED_AREA #endif diff --git a/include/asm-x86/page_64.h b/include/asm-x86/page_64.h index dcf0c074607..f7393bc516e 100644 --- a/include/asm-x86/page_64.h +++ b/include/asm-x86/page_64.h @@ -71,6 +71,8 @@ typedef unsigned long pgdval_t; typedef unsigned long pgprotval_t; typedef unsigned long phys_addr_t; +typedef struct page *pgtable_t; + typedef struct { pteval_t pte; } pte_t; #define vmemmap ((struct page *)VMEMMAP_START) diff --git a/include/asm-x86/pgalloc_32.h b/include/asm-x86/pgalloc_32.h index bab12718a91..6bea6e5b5ee 100644 --- a/include/asm-x86/pgalloc_32.h +++ b/include/asm-x86/pgalloc_32.h @@ -31,6 +31,7 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *p paravirt_alloc_pt(mm, pfn); set_pmd(pmd, __pmd(((pteval_t)pfn << PAGE_SHIFT) | _PAGE_TABLE)); } +#define pmd_pgtable(pmd) pmd_page(pmd) /* * Allocate and free page tables. @@ -39,15 +40,16 @@ extern pgd_t *pgd_alloc(struct mm_struct *); extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long); -extern struct page *pte_alloc_one(struct mm_struct *, unsigned long); +extern pgtable_t pte_alloc_one(struct mm_struct *, unsigned long); static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) { free_page((unsigned long)pte); } -static inline void pte_free(struct mm_struct *mm, struct page *pte) +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) { + pgtable_page_dtor(pte); __free_page(pte); } diff --git a/include/asm-x86/pgalloc_64.h b/include/asm-x86/pgalloc_64.h index 4f6220db22b..8d6722320dc 100644 --- a/include/asm-x86/pgalloc_64.h +++ b/include/asm-x86/pgalloc_64.h @@ -12,6 +12,8 @@ #define pgd_populate(mm, pgd, pud) \ set_pgd(pgd, __pgd(_PAGE_TABLE | __pa(pud))) +#define pmd_pgtable(pmd) pmd_page(pmd) + static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *pte) { set_pmd(pmd, __pmd(_PAGE_TABLE | (page_to_pfn(pte) << PAGE_SHIFT))); @@ -91,12 +93,17 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long ad return (pte_t *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT); } -static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address) +static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) { - void *p = (void *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT); + struct page *page; + void *p; + + p = (void *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT); if (!p) return NULL; - return virt_to_page(p); + page = virt_to_page(p); + pgtable_page_ctor(page); + return page; } /* Should really implement gc for free page table pages. This could be @@ -108,12 +115,17 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) free_page((unsigned long)pte); } -static inline void pte_free(struct mm_struct *mm, struct page *pte) +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) { + pgtable_page_dtor(pte); __free_page(pte); } -#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) +#define __pte_free_tlb(tlb,pte) \ +do { \ + pgtable_page_dtor((pte)); \ + tlb_remove_page((tlb), (pte)); \ +} while (0) #define __pmd_free_tlb(tlb,x) tlb_remove_page((tlb),virt_to_page(x)) #define __pud_free_tlb(tlb,x) tlb_remove_page((tlb),virt_to_page(x)) diff --git a/include/asm-x86/posix_types_32.h b/include/asm-x86/posix_types_32.h index 133e31e7dfd..015e539cdef 100644 --- a/include/asm-x86/posix_types_32.h +++ b/include/asm-x86/posix_types_32.h @@ -39,14 +39,10 @@ typedef long long __kernel_loff_t; #endif typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) +#if defined(__KERNEL__) #undef __FD_SET #define __FD_SET(fd,fdsetp) \ @@ -77,6 +73,6 @@ do { \ "2" ((__kernel_fd_set *) (fdsetp)) : "memory"); \ } while (0) -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* defined(__KERNEL__) */ #endif diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h index ab4d0c2a3f8..149920dcd34 100644 --- a/include/asm-x86/processor.h +++ b/include/asm-x86/processor.h @@ -719,6 +719,8 @@ static inline void prefetchw(const void *x) * User space process size: 3GB (default). */ #define TASK_SIZE (PAGE_OFFSET) +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP #define INIT_THREAD { \ .sp0 = sizeof(init_stack) + (long)&init_stack, \ @@ -802,6 +804,9 @@ extern unsigned long thread_saved_pc(struct task_struct *tsk); #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \ IA32_PAGE_OFFSET : TASK_SIZE64) +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX TASK_SIZE64 + #define INIT_THREAD { \ .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ } diff --git a/include/asm-xtensa/a.out.h b/include/asm-xtensa/a.out.h index 05a2f67c676..fdf13702924 100644 --- a/include/asm-xtensa/a.out.h +++ b/include/asm-xtensa/a.out.h @@ -14,11 +14,6 @@ #ifndef _XTENSA_A_OUT_H #define _XTENSA_A_OUT_H -/* Note: the kernel needs the a.out definitions, even if only ELF is used. */ - -#define STACK_TOP TASK_SIZE -#define STACK_TOP_MAX STACK_TOP - struct exec { unsigned long a_info; diff --git a/include/asm-xtensa/page.h b/include/asm-xtensa/page.h index 1adedbf41d0..80a6ae0dd25 100644 --- a/include/asm-xtensa/page.h +++ b/include/asm-xtensa/page.h @@ -98,6 +98,7 @@ typedef struct { unsigned long pte; } pte_t; /* page table entry */ typedef struct { unsigned long pgd; } pgd_t; /* PGD table entry */ typedef struct { unsigned long pgprot; } pgprot_t; +typedef struct page *pgtable_t; #define pte_val(x) ((x).pte) #define pgd_val(x) ((x).pgd) diff --git a/include/asm-xtensa/param.h b/include/asm-xtensa/param.h index ce3a336cad0..82ad34d92d3 100644 --- a/include/asm-xtensa/param.h +++ b/include/asm-xtensa/param.h @@ -12,7 +12,7 @@ #define _XTENSA_PARAM_H #ifdef __KERNEL__ -# define HZ 100 /* internal timer frequency */ +# define HZ CONFIG_HZ /* internal timer frequency */ # define USER_HZ 100 /* for user interfaces in "ticks" */ # define CLOCKS_PER_SEC (USER_HZ) /* frequnzy at which times() counts */ #endif diff --git a/include/asm-xtensa/pgalloc.h b/include/asm-xtensa/pgalloc.h index 1d51ba5463f..8d1544eb461 100644 --- a/include/asm-xtensa/pgalloc.h +++ b/include/asm-xtensa/pgalloc.h @@ -24,6 +24,7 @@ (pmd_val(*(pmdp)) = ((unsigned long)ptep)) #define pmd_populate(mm, pmdp, page) \ (pmd_val(*(pmdp)) = ((unsigned long)page_to_virt(page))) +#define pmd_pgtable(pmd) pmd_page(pmd) static inline pgd_t* pgd_alloc(struct mm_struct *mm) @@ -46,10 +47,14 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, return kmem_cache_alloc(pgtable_cache, GFP_KERNEL|__GFP_REPEAT); } -static inline struct page *pte_alloc_one(struct mm_struct *mm, - unsigned long addr) +static inline pte_token_t pte_alloc_one(struct mm_struct *mm, + unsigned long addr) { - return virt_to_page(pte_alloc_one_kernel(mm, addr)); + struct page *page; + + page = virt_to_page(pte_alloc_one_kernel(mm, addr)); + pgtable_page_ctor(page); + return page; } static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) @@ -57,10 +62,12 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) kmem_cache_free(pgtable_cache, pte); } -static inline void pte_free(struct mm_struct *mm, struct page *page) +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) { - kmem_cache_free(pgtable_cache, page_address(page)); + pgtable_page_dtor(pte); + kmem_cache_free(pgtable_cache, page_address(pte)); } +#define pmd_pgtable(pmd) pmd_page(pmd) #endif /* __KERNEL__ */ #endif /* _XTENSA_PGALLOC_H */ diff --git a/include/asm-xtensa/posix_types.h b/include/asm-xtensa/posix_types.h index 4ad77dda6d5..43f9dd1126a 100644 --- a/include/asm-xtensa/posix_types.h +++ b/include/asm-xtensa/posix_types.h @@ -64,8 +64,7 @@ typedef struct { #else /* __GNUC__ */ -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \ - || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0) +#if defined(__KERNEL__) /* With GNU C, use inline functions instead so args are evaluated only once: */ #undef __FD_SET @@ -118,6 +117,6 @@ static __inline__ void __FD_ZERO(__kernel_fd_set *p) } } -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* defined(__KERNEL__) */ #endif /* __GNUC__ */ #endif /* _XTENSA_POSIX_TYPES_H */ diff --git a/include/asm-xtensa/processor.h b/include/asm-xtensa/processor.h index 35145bcd96e..96408f43662 100644 --- a/include/asm-xtensa/processor.h +++ b/include/asm-xtensa/processor.h @@ -34,6 +34,8 @@ */ #define TASK_SIZE __XTENSA_UL_CONST(0x40000000) +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP /* * General exception cause assigned to debug exceptions. Debug exceptions go diff --git a/include/asm-xtensa/unistd.h b/include/asm-xtensa/unistd.h index 92968aabe34..c092c8fbb2c 100644 --- a/include/asm-xtensa/unistd.h +++ b/include/asm-xtensa/unistd.h @@ -677,8 +677,8 @@ __SYSCALL(303, sys_ni_syscall, 0) #define __NR_signalfd 304 __SYSCALL(304, sys_signalfd, 3) -#define __NR_timerfd 305 -__SYSCALL(305, sys_timerfd, 4) +/* 305 was __NR_timerfd */ +__SYSCALL(305, sys_ni_syscall, 0) #define __NR_eventfd 306 __SYSCALL(306, sys_eventfd, 1) diff --git a/include/linux/Kbuild b/include/linux/Kbuild index 2ebf068ba50..5cae9b5960e 100644 --- a/include/linux/Kbuild +++ b/include/linux/Kbuild @@ -338,7 +338,6 @@ unifdef-y += tty.h unifdef-y += types.h unifdef-y += udf_fs_i.h unifdef-y += udp.h -unifdef-y += ufs_fs.h unifdef-y += uinput.h unifdef-y += uio.h unifdef-y += unistd.h diff --git a/include/linux/a.out.h b/include/linux/a.out.h index 82cd918f2ab..208f4e8ed30 100644 --- a/include/linux/a.out.h +++ b/include/linux/a.out.h @@ -1,6 +1,8 @@ #ifndef __A_OUT_GNU_H__ #define __A_OUT_GNU_H__ +#ifdef CONFIG_ARCH_SUPPORTS_AOUT + #define __GNU_EXEC_MACROS__ #ifndef __STRUCT_EXEC_OVERRIDE__ @@ -9,6 +11,8 @@ #endif /* __STRUCT_EXEC_OVERRIDE__ */ +#ifndef __ASSEMBLY__ + /* these go in the N_MACHTYPE field */ enum machine_type { #if defined (M_OLDSUN2) @@ -272,5 +276,11 @@ struct relocation_info }; #endif /* no N_RELOCATION_INFO_DECLARED. */ - +#endif /*__ASSEMBLY__ */ +#else /* CONFIG_ARCH_SUPPORTS_AOUT */ +#ifndef __ASSEMBLY__ +struct exec { +}; +#endif +#endif /* CONFIG_ARCH_SUPPORTS_AOUT */ #endif /* __A_OUT_GNU_H__ */ diff --git a/include/linux/atmel_pwm.h b/include/linux/atmel_pwm.h new file mode 100644 index 00000000000..ea04abb3db8 --- /dev/null +++ b/include/linux/atmel_pwm.h @@ -0,0 +1,70 @@ +#ifndef __LINUX_ATMEL_PWM_H +#define __LINUX_ATMEL_PWM_H + +/** + * struct pwm_channel - driver handle to a PWM channel + * @regs: base of this channel's registers + * @index: number of this channel (0..31) + * @mck: base clock rate, which can be prescaled and maybe subdivided + * + * Drivers initialize a pwm_channel structure using pwm_channel_alloc(). + * Then they configure its clock rate (derived from MCK), alignment, + * polarity, and duty cycle by writing directly to the channel registers, + * before enabling the channel by calling pwm_channel_enable(). + * + * After emitting a PWM signal for the desired length of time, drivers + * may then pwm_channel_disable() or pwm_channel_free(). Both of these + * disable the channel, but when it's freed the IRQ is deconfigured and + * the channel must later be re-allocated and reconfigured. + * + * Note that if the period or duty cycle need to be changed while the + * PWM channel is operating, drivers must use the PWM_CUPD double buffer + * mechanism, either polling until they change or getting implicitly + * notified through a once-per-period interrupt handler. + */ +struct pwm_channel { + void __iomem *regs; + unsigned index; + unsigned long mck; +}; + +extern int pwm_channel_alloc(int index, struct pwm_channel *ch); +extern int pwm_channel_free(struct pwm_channel *ch); + +extern int pwm_clk_alloc(unsigned prescale, unsigned div); +extern void pwm_clk_free(unsigned clk); + +extern int __pwm_channel_onoff(struct pwm_channel *ch, int enabled); + +#define pwm_channel_enable(ch) __pwm_channel_onoff((ch), 1) +#define pwm_channel_disable(ch) __pwm_channel_onoff((ch), 0) + +/* periodic interrupts, mostly for CUPD changes to period or cycle */ +extern int pwm_channel_handler(struct pwm_channel *ch, + void (*handler)(struct pwm_channel *ch)); + +/* per-channel registers (banked at pwm_channel->regs) */ +#define PWM_CMR 0x00 /* mode register */ +#define PWM_CPR_CPD (1 << 10) /* set: CUPD modifies period */ +#define PWM_CPR_CPOL (1 << 9) /* set: idle high */ +#define PWM_CPR_CALG (1 << 8) /* set: center align */ +#define PWM_CPR_CPRE (0xf << 0) /* mask: rate is mck/(2^pre) */ +#define PWM_CPR_CLKA (0xb << 0) /* rate CLKA */ +#define PWM_CPR_CLKB (0xc << 0) /* rate CLKB */ +#define PWM_CDTY 0x04 /* duty cycle (max of CPRD) */ +#define PWM_CPRD 0x08 /* period (count up from zero) */ +#define PWM_CCNT 0x0c /* counter (20 bits?) */ +#define PWM_CUPD 0x10 /* update CPRD (or CDTY) next period */ + +static inline void +pwm_channel_writel(struct pwm_channel *pwmc, unsigned offset, u32 val) +{ + __raw_writel(val, pwmc->regs + offset); +} + +static inline u32 pwm_channel_readl(struct pwm_channel *pwmc, unsigned offset) +{ + return __raw_readl(pwmc->regs + offset); +} + +#endif /* __LINUX_ATMEL_PWM_H */ diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index 90392a9d7a9..e1888cc5b8a 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -137,7 +137,9 @@ enum rq_flag_bits { #define BLK_MAX_CDB 16 /* - * try to put the fields that are referenced together in the same cacheline + * try to put the fields that are referenced together in the same cacheline. + * if you modify this structure, be sure to check block/blk-core.c:rq_init() + * as well! */ struct request { struct list_head queuelist; diff --git a/include/linux/byteorder/generic.h b/include/linux/byteorder/generic.h index 3dc715b0250..d3771551fdd 100644 --- a/include/linux/byteorder/generic.h +++ b/include/linux/byteorder/generic.h @@ -146,6 +146,36 @@ #define htons(x) ___htons(x) #define ntohs(x) ___ntohs(x) +static inline void le16_add_cpu(__le16 *var, u16 val) +{ + *var = cpu_to_le16(le16_to_cpu(*var) + val); +} + +static inline void le32_add_cpu(__le32 *var, u32 val) +{ + *var = cpu_to_le32(le32_to_cpu(*var) + val); +} + +static inline void le64_add_cpu(__le64 *var, u64 val) +{ + *var = cpu_to_le64(le64_to_cpu(*var) + val); +} + +static inline void be16_add_cpu(__be16 *var, u16 val) +{ + *var = cpu_to_be16(be16_to_cpu(*var) + val); +} + +static inline void be32_add_cpu(__be32 *var, u32 val) +{ + *var = cpu_to_be32(be32_to_cpu(*var) + val); +} + +static inline void be64_add_cpu(__be64 *var, u64 val) +{ + *var = cpu_to_be64(be64_to_cpu(*var) + val); +} + #endif /* KERNEL */ #endif /* _LINUX_BYTEORDER_GENERIC_H */ diff --git a/include/linux/cpuset.h b/include/linux/cpuset.h index ecae585ec3d..f8c9a2752f0 100644 --- a/include/linux/cpuset.h +++ b/include/linux/cpuset.h @@ -57,7 +57,9 @@ extern int cpuset_memory_pressure_enabled; extern void __cpuset_memory_pressure_bump(void); extern const struct file_operations proc_cpuset_operations; -extern char *cpuset_task_status_allowed(struct task_struct *task, char *buffer); +struct seq_file; +extern void cpuset_task_status_allowed(struct seq_file *m, + struct task_struct *task); extern void cpuset_lock(void); extern void cpuset_unlock(void); @@ -126,10 +128,9 @@ static inline int cpuset_mems_allowed_intersects(const struct task_struct *tsk1, static inline void cpuset_memory_pressure_bump(void) {} -static inline char *cpuset_task_status_allowed(struct task_struct *task, - char *buffer) +static inline void cpuset_task_status_allowed(struct seq_file *m, + struct task_struct *task) { - return buffer; } static inline void cpuset_lock(void) {} diff --git a/include/linux/dca.h b/include/linux/dca.h index 83eaecc6f8a..af61cd1f37e 100644 --- a/include/linux/dca.h +++ b/include/linux/dca.h @@ -11,7 +11,7 @@ void dca_unregister_notify(struct notifier_block *nb); struct dca_provider { struct dca_ops *ops; - struct class_device *cd; + struct device *cd; int id; }; diff --git a/include/linux/dmar.h b/include/linux/dmar.h index ffb6439cb5e..56c73b84755 100644 --- a/include/linux/dmar.h +++ b/include/linux/dmar.h @@ -28,7 +28,7 @@ #ifdef CONFIG_DMAR struct intel_iommu; -extern char *dmar_get_fault_reason(u8 fault_reason); +extern const char *dmar_get_fault_reason(u8 fault_reason); /* Can't use the common MSI interrupt functions * since DMAR is not a pci device diff --git a/include/linux/dmi.h b/include/linux/dmi.h index bbc9992ec37..325acdf5c46 100644 --- a/include/linux/dmi.h +++ b/include/linux/dmi.h @@ -35,8 +35,11 @@ enum dmi_device_type { DMI_DEV_TYPE_ETHERNET, DMI_DEV_TYPE_TOKENRING, DMI_DEV_TYPE_SOUND, + DMI_DEV_TYPE_PATA, + DMI_DEV_TYPE_SATA, + DMI_DEV_TYPE_SAS, DMI_DEV_TYPE_IPMI = -1, - DMI_DEV_TYPE_OEM_STRING = -2 + DMI_DEV_TYPE_OEM_STRING = -2, }; struct dmi_header { diff --git a/include/linux/elf-em.h b/include/linux/elf-em.h index 5834e843a94..18bea78fe47 100644 --- a/include/linux/elf-em.h +++ b/include/linux/elf-em.h @@ -31,6 +31,7 @@ #define EM_V850 87 /* NEC v850 */ #define EM_M32R 88 /* Renesas M32R */ #define EM_H8_300 46 /* Renesas H8/300,300H,H8S */ +#define EM_MN10300 89 /* Panasonic/MEI MN10300, AM33 */ #define EM_BLACKFIN 106 /* ADI Blackfin Processor */ #define EM_FRV 0x5441 /* Fujitsu FR-V */ #define EM_AVR32 0x18ad /* Atmel AVR32 */ @@ -47,6 +48,8 @@ #define EM_CYGNUS_M32R 0x9041 /* This is the old interim value for S/390 architecture */ #define EM_S390_OLD 0xA390 +/* Also Panasonic/MEI MN10300, AM33 */ +#define EM_CYGNUS_MN10300 0xbeef #endif /* _LINUX_ELF_EM_H */ diff --git a/include/linux/fs.h b/include/linux/fs.h index 36b7abefacb..18cfbf76ec5 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -1038,6 +1038,12 @@ struct super_block { * in /proc/mounts will be "type.subtype" */ char *s_subtype; + + /* + * Saved mount options for lazy filesystems using + * generic_show_options() + */ + char *s_options; }; extern struct timespec current_fs_time(struct super_block *sb); @@ -1618,7 +1624,6 @@ extern int register_chrdev(unsigned int, const char *, const struct file_operations *); extern void unregister_chrdev(unsigned int, const char *); extern void unregister_chrdev_region(dev_t, unsigned); -extern int chrdev_open(struct inode *, struct file *); extern void chrdev_show(struct seq_file *,off_t); /* fs/block_dev.c */ @@ -1807,9 +1812,6 @@ extern ssize_t generic_file_buffered_write(struct kiocb *, const struct iovec *, unsigned long, loff_t, loff_t *, size_t, ssize_t); extern ssize_t do_sync_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos); extern ssize_t do_sync_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos); -extern void do_generic_mapping_read(struct address_space *mapping, - struct file_ra_state *, struct file *, - loff_t *, read_descriptor_t *, read_actor_t); extern int generic_segment_checks(const struct iovec *iov, unsigned long *nr_segs, size_t *count, int access_flags); @@ -1847,18 +1849,6 @@ static inline int xip_truncate_page(struct address_space *mapping, loff_t from) } #endif -static inline void do_generic_file_read(struct file * filp, loff_t *ppos, - read_descriptor_t * desc, - read_actor_t actor) -{ - do_generic_mapping_read(filp->f_mapping, - &filp->f_ra, - filp, - ppos, - desc, - actor); -} - #ifdef CONFIG_BLOCK ssize_t __blockdev_direct_IO(int rw, struct kiocb *iocb, struct inode *inode, struct block_device *bdev, const struct iovec *iov, loff_t offset, @@ -1985,6 +1975,9 @@ extern int __must_check inode_setattr(struct inode *, struct iattr *); extern void file_update_time(struct file *file); +extern int generic_show_options(struct seq_file *m, struct vfsmount *mnt); +extern void save_mount_options(struct super_block *sb, char *options); + static inline ino_t parent_ino(struct dentry *dentry) { ino_t res; @@ -2056,7 +2049,7 @@ static int __fops ## _open(struct inode *inode, struct file *file) \ static struct file_operations __fops = { \ .owner = THIS_MODULE, \ .open = __fops ## _open, \ - .release = simple_attr_close, \ + .release = simple_attr_release, \ .read = simple_attr_read, \ .write = simple_attr_write, \ }; @@ -2068,9 +2061,9 @@ __simple_attr_check_format(const char *fmt, ...) } int simple_attr_open(struct inode *inode, struct file *file, - u64 (*get)(void *), void (*set)(void *, u64), + int (*get)(void *, u64 *), int (*set)(void *, u64), const char *fmt); -int simple_attr_close(struct inode *inode, struct file *file); +int simple_attr_release(struct inode *inode, struct file *file); ssize_t simple_attr_read(struct file *file, char __user *buf, size_t len, loff_t *ppos); ssize_t simple_attr_write(struct file *file, const char __user *buf, diff --git a/include/linux/genhd.h b/include/linux/genhd.h index 1dbea0ac569..09a3b18918c 100644 --- a/include/linux/genhd.h +++ b/include/linux/genhd.h @@ -91,16 +91,31 @@ struct partition { __le32 nr_sects; /* nr of sectors in partition */ } __attribute__((packed)); +struct disk_stats { + unsigned long sectors[2]; /* READs and WRITEs */ + unsigned long ios[2]; + unsigned long merges[2]; + unsigned long ticks[2]; + unsigned long io_ticks; + unsigned long time_in_queue; +}; + struct hd_struct { sector_t start_sect; sector_t nr_sects; struct device dev; struct kobject *holder_dir; - unsigned ios[2], sectors[2]; /* READs and WRITEs */ int policy, partno; #ifdef CONFIG_FAIL_MAKE_REQUEST int make_it_fail; #endif + unsigned long stamp; + int in_flight; +#ifdef CONFIG_SMP + struct disk_stats *dkstats; +#else + struct disk_stats dkstats; +#endif }; #define GENHD_FL_REMOVABLE 1 @@ -111,15 +126,7 @@ struct hd_struct { #define GENHD_FL_SUPPRESS_PARTITION_INFO 32 #define GENHD_FL_FAIL 64 -struct disk_stats { - unsigned long sectors[2]; /* READs and WRITEs */ - unsigned long ios[2]; - unsigned long merges[2]; - unsigned long ticks[2]; - unsigned long io_ticks; - unsigned long time_in_queue; -}; - + struct gendisk { int major; /* major number of driver */ int first_minor; @@ -158,6 +165,20 @@ struct gendisk { * The __ variants should only be called in critical sections. The full * variants disable/enable preemption. */ +static inline struct hd_struct *get_part(struct gendisk *gendiskp, + sector_t sector) +{ + struct hd_struct *part; + int i; + for (i = 0; i < gendiskp->minors - 1; i++) { + part = gendiskp->part[i]; + if (part && part->start_sect <= sector + && sector < part->start_sect + part->nr_sects) + return part; + } + return NULL; +} + #ifdef CONFIG_SMP #define __disk_stat_add(gendiskp, field, addnd) \ (per_cpu_ptr(gendiskp->dkstats, smp_processor_id())->field += addnd) @@ -177,15 +198,62 @@ static inline void disk_stat_set_all(struct gendisk *gendiskp, int value) { memset(per_cpu_ptr(gendiskp->dkstats, i), value, sizeof (struct disk_stats)); } + +#define __part_stat_add(part, field, addnd) \ + (per_cpu_ptr(part->dkstats, smp_processor_id())->field += addnd) + +#define __all_stat_add(gendiskp, field, addnd, sector) \ +({ \ + struct hd_struct *part = get_part(gendiskp, sector); \ + if (part) \ + __part_stat_add(part, field, addnd); \ + __disk_stat_add(gendiskp, field, addnd); \ +}) + +#define part_stat_read(part, field) \ +({ \ + typeof(part->dkstats->field) res = 0; \ + int i; \ + for_each_possible_cpu(i) \ + res += per_cpu_ptr(part->dkstats, i)->field; \ + res; \ +}) + +static inline void part_stat_set_all(struct hd_struct *part, int value) { + int i; + for_each_possible_cpu(i) + memset(per_cpu_ptr(part->dkstats, i), value, + sizeof(struct disk_stats)); +} #else #define __disk_stat_add(gendiskp, field, addnd) \ (gendiskp->dkstats.field += addnd) #define disk_stat_read(gendiskp, field) (gendiskp->dkstats.field) -static inline void disk_stat_set_all(struct gendisk *gendiskp, int value) { +static inline void disk_stat_set_all(struct gendisk *gendiskp, int value) +{ memset(&gendiskp->dkstats, value, sizeof (struct disk_stats)); } + +#define __part_stat_add(part, field, addnd) \ + (part->dkstats.field += addnd) + +#define __all_stat_add(gendiskp, field, addnd, sector) \ +({ \ + struct hd_struct *part = get_part(gendiskp, sector); \ + if (part) \ + part->dkstats.field += addnd; \ + __disk_stat_add(gendiskp, field, addnd); \ +}) + +#define part_stat_read(part, field) (part->dkstats.field) + +static inline void part_stat_set_all(struct hd_struct *part, int value) +{ + memset(&part->dkstats, value, sizeof(struct disk_stats)); +} + #endif #define disk_stat_add(gendiskp, field, addnd) \ @@ -206,6 +274,45 @@ static inline void disk_stat_set_all(struct gendisk *gendiskp, int value) { #define disk_stat_sub(gendiskp, field, subnd) \ disk_stat_add(gendiskp, field, -subnd) +#define part_stat_add(gendiskp, field, addnd) \ + do { \ + preempt_disable(); \ + __part_stat_add(gendiskp, field, addnd);\ + preempt_enable(); \ + } while (0) + +#define __part_stat_dec(gendiskp, field) __part_stat_add(gendiskp, field, -1) +#define part_stat_dec(gendiskp, field) part_stat_add(gendiskp, field, -1) + +#define __part_stat_inc(gendiskp, field) __part_stat_add(gendiskp, field, 1) +#define part_stat_inc(gendiskp, field) part_stat_add(gendiskp, field, 1) + +#define __part_stat_sub(gendiskp, field, subnd) \ + __part_stat_add(gendiskp, field, -subnd) +#define part_stat_sub(gendiskp, field, subnd) \ + part_stat_add(gendiskp, field, -subnd) + +#define all_stat_add(gendiskp, field, addnd, sector) \ + do { \ + preempt_disable(); \ + __all_stat_add(gendiskp, field, addnd, sector); \ + preempt_enable(); \ + } while (0) + +#define __all_stat_dec(gendiskp, field, sector) \ + __all_stat_add(gendiskp, field, -1, sector) +#define all_stat_dec(gendiskp, field, sector) \ + all_stat_add(gendiskp, field, -1, sector) + +#define __all_stat_inc(gendiskp, field, sector) \ + __all_stat_add(gendiskp, field, 1, sector) +#define all_stat_inc(gendiskp, field, sector) \ + all_stat_add(gendiskp, field, 1, sector) + +#define __all_stat_sub(gendiskp, field, subnd, sector) \ + __all_stat_add(gendiskp, field, -subnd, sector) +#define all_stat_sub(gendiskp, field, subnd, sector) \ + all_stat_add(gendiskp, field, -subnd, sector) /* Inlines to alloc and free disk stats in struct gendisk */ #ifdef CONFIG_SMP @@ -221,6 +328,20 @@ static inline void free_disk_stats(struct gendisk *disk) { free_percpu(disk->dkstats); } + +static inline int init_part_stats(struct hd_struct *part) +{ + part->dkstats = alloc_percpu(struct disk_stats); + if (!part->dkstats) + return 0; + return 1; +} + +static inline void free_part_stats(struct hd_struct *part) +{ + free_percpu(part->dkstats); +} + #else /* CONFIG_SMP */ static inline int init_disk_stats(struct gendisk *disk) { @@ -230,10 +351,20 @@ static inline int init_disk_stats(struct gendisk *disk) static inline void free_disk_stats(struct gendisk *disk) { } + +static inline int init_part_stats(struct hd_struct *part) +{ + return 1; +} + +static inline void free_part_stats(struct hd_struct *part) +{ +} #endif /* CONFIG_SMP */ /* drivers/block/ll_rw_blk.c */ extern void disk_round_stats(struct gendisk *disk); +extern void part_round_stats(struct hd_struct *part); /* drivers/block/genhd.c */ extern int get_blkdev_list(char *, int); diff --git a/include/linux/hrtimer.h b/include/linux/hrtimer.h index 203591e2321..600fc3bcf63 100644 --- a/include/linux/hrtimer.h +++ b/include/linux/hrtimer.h @@ -78,7 +78,7 @@ enum hrtimer_cb_mode { * as otherwise the timer could be removed before the softirq code finishes the * the handling of the timer. * - * The HRTIMER_STATE_ENQUEUE bit is always or'ed to the current state to + * The HRTIMER_STATE_ENQUEUED bit is always or'ed to the current state to * preserve the HRTIMER_STATE_CALLBACK bit in the above scenario. * * All state transitions are protected by cpu_base->lock. diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h index 30d606afcaf..7ca198b379a 100644 --- a/include/linux/hugetlb.h +++ b/include/linux/hugetlb.h @@ -17,6 +17,7 @@ static inline int is_vm_hugetlb_page(struct vm_area_struct *vma) } int hugetlb_sysctl_handler(struct ctl_table *, int, struct file *, void __user *, size_t *, loff_t *); +int hugetlb_overcommit_handler(struct ctl_table *, int, struct file *, void __user *, size_t *, loff_t *); int hugetlb_treat_movable_handler(struct ctl_table *, int, struct file *, void __user *, size_t *, loff_t *); int copy_hugetlb_page_range(struct mm_struct *, struct mm_struct *, struct vm_area_struct *); int follow_hugetlb_page(struct mm_struct *, struct vm_area_struct *, struct page **, struct vm_area_struct **, unsigned long *, int *, int, int); diff --git a/include/linux/ipc.h b/include/linux/ipc.h index 408696ea518..b8826107b51 100644 --- a/include/linux/ipc.h +++ b/include/linux/ipc.h @@ -100,58 +100,6 @@ struct kern_ipc_perm void *security; }; -struct ipc_ids; -struct ipc_namespace { - struct kref kref; - struct ipc_ids *ids[3]; - - int sem_ctls[4]; - int used_sems; - - int msg_ctlmax; - int msg_ctlmnb; - int msg_ctlmni; - atomic_t msg_bytes; - atomic_t msg_hdrs; - - size_t shm_ctlmax; - size_t shm_ctlall; - int shm_ctlmni; - int shm_tot; -}; - -extern struct ipc_namespace init_ipc_ns; - -#ifdef CONFIG_SYSVIPC -#define INIT_IPC_NS(ns) .ns = &init_ipc_ns, -extern void free_ipc_ns(struct kref *kref); -extern struct ipc_namespace *copy_ipcs(unsigned long flags, - struct ipc_namespace *ns); -#else -#define INIT_IPC_NS(ns) -static inline struct ipc_namespace *copy_ipcs(unsigned long flags, - struct ipc_namespace *ns) -{ - return ns; -} -#endif - -static inline struct ipc_namespace *get_ipc_ns(struct ipc_namespace *ns) -{ -#ifdef CONFIG_SYSVIPC - if (ns) - kref_get(&ns->kref); -#endif - return ns; -} - -static inline void put_ipc_ns(struct ipc_namespace *ns) -{ -#ifdef CONFIG_SYSVIPC - kref_put(&ns->kref, free_ipc_ns); -#endif -} - #endif /* __KERNEL__ */ #endif /* _LINUX_IPC_H */ diff --git a/include/linux/ipc_namespace.h b/include/linux/ipc_namespace.h new file mode 100644 index 00000000000..e4451d1da75 --- /dev/null +++ b/include/linux/ipc_namespace.h @@ -0,0 +1,81 @@ +#ifndef __IPC_NAMESPACE_H__ +#define __IPC_NAMESPACE_H__ + +#include <linux/err.h> +#include <linux/idr.h> +#include <linux/rwsem.h> + +struct ipc_ids { + int in_use; + unsigned short seq; + unsigned short seq_max; + struct rw_semaphore rw_mutex; + struct idr ipcs_idr; +}; + +struct ipc_namespace { + struct kref kref; + struct ipc_ids ids[3]; + + int sem_ctls[4]; + int used_sems; + + int msg_ctlmax; + int msg_ctlmnb; + int msg_ctlmni; + atomic_t msg_bytes; + atomic_t msg_hdrs; + + size_t shm_ctlmax; + size_t shm_ctlall; + int shm_ctlmni; + int shm_tot; +}; + +extern struct ipc_namespace init_ipc_ns; + +#ifdef CONFIG_SYSVIPC +#define INIT_IPC_NS(ns) .ns = &init_ipc_ns, +#else +#define INIT_IPC_NS(ns) +#endif + +#if defined(CONFIG_SYSVIPC) && defined(CONFIG_IPC_NS) +extern void free_ipc_ns(struct kref *kref); +extern struct ipc_namespace *copy_ipcs(unsigned long flags, + struct ipc_namespace *ns); +extern void free_ipcs(struct ipc_namespace *ns, struct ipc_ids *ids, + void (*free)(struct ipc_namespace *, + struct kern_ipc_perm *)); + +static inline struct ipc_namespace *get_ipc_ns(struct ipc_namespace *ns) +{ + if (ns) + kref_get(&ns->kref); + return ns; +} + +static inline void put_ipc_ns(struct ipc_namespace *ns) +{ + kref_put(&ns->kref, free_ipc_ns); +} +#else +static inline struct ipc_namespace *copy_ipcs(unsigned long flags, + struct ipc_namespace *ns) +{ + if (flags & CLONE_NEWIPC) + return ERR_PTR(-EINVAL); + + return ns; +} + +static inline struct ipc_namespace *get_ipc_ns(struct ipc_namespace *ns) +{ + return ns; +} + +static inline void put_ipc_ns(struct ipc_namespace *ns) +{ +} +#endif +#endif diff --git a/include/linux/irq.h b/include/linux/irq.h index 4669be08061..bfd9efb5cb4 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -25,7 +25,7 @@ #include <asm/irq_regs.h> struct irq_desc; -typedef void fastcall (*irq_flow_handler_t)(unsigned int irq, +typedef void (*irq_flow_handler_t)(unsigned int irq, struct irq_desc *desc); @@ -276,19 +276,19 @@ extern int handle_IRQ_event(unsigned int irq, struct irqaction *action); * Built-in IRQ handlers for various IRQ types, * callable via desc->chip->handle_irq() */ -extern void fastcall handle_level_irq(unsigned int irq, struct irq_desc *desc); -extern void fastcall handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); -extern void fastcall handle_edge_irq(unsigned int irq, struct irq_desc *desc); -extern void fastcall handle_simple_irq(unsigned int irq, struct irq_desc *desc); -extern void fastcall handle_percpu_irq(unsigned int irq, struct irq_desc *desc); -extern void fastcall handle_bad_irq(unsigned int irq, struct irq_desc *desc); +extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); +extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); +extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); +extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); +extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); +extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); /* * Monolithic do_IRQ implementation. * (is an explicit fastcall, because i386 4KSTACKS calls it from assembly) */ #ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ -extern fastcall unsigned int __do_IRQ(unsigned int irq); +extern unsigned int __do_IRQ(unsigned int irq); #endif /* @@ -367,6 +367,9 @@ set_irq_chained_handler(unsigned int irq, __set_irq_handler(irq, handle, 1, NULL); } +extern void set_irq_noprobe(unsigned int irq); +extern void set_irq_probe(unsigned int irq); + /* Handle dynamic irq creation and destruction */ extern int create_irq(void); extern void destroy_irq(unsigned int irq); diff --git a/include/linux/jiffies.h b/include/linux/jiffies.h index 7ba9e47bf06..e0b5b684d83 100644 --- a/include/linux/jiffies.h +++ b/include/linux/jiffies.h @@ -42,7 +42,7 @@ /* LATCH is used in the interval timer and ftape setup. */ #define LATCH ((CLOCK_TICK_RATE + HZ/2) / HZ) /* For divider */ -/* Suppose we want to devide two numbers NOM and DEN: NOM/DEN, the we can +/* Suppose we want to devide two numbers NOM and DEN: NOM/DEN, then we can * improve accuracy by shifting LSH bits, hence calculating: * (NOM << LSH) / DEN * This however means trouble for large NOM, because (NOM << LSH) may no @@ -160,7 +160,7 @@ extern unsigned long preset_lpj; * We want to do realistic conversions of time so we need to use the same * values the update wall clock code uses as the jiffies size. This value * is: TICK_NSEC (which is defined in timex.h). This - * is a constant and is in nanoseconds. We will used scaled math + * is a constant and is in nanoseconds. We will use scaled math * with a set of scales defined here as SEC_JIFFIE_SC, USEC_JIFFIE_SC and * NSEC_JIFFIE_SC. Note that these defines contain nothing but * constants and so are computed at compile time. SHIFT_HZ (computed in @@ -204,7 +204,7 @@ extern unsigned long preset_lpj; * operator if the result is a long long AND at least one of the * operands is cast to long long (usually just prior to the "*" so as * not to confuse it into thinking it really has a 64-bit operand, - * which, buy the way, it can do, but it take more code and at least 2 + * which, buy the way, it can do, but it takes more code and at least 2 * mpys). * We also need to be aware that one second in nanoseconds is only a diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 9e01f376840..2df44e77327 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -133,7 +133,7 @@ NORET_TYPE void panic(const char * fmt, ...) extern void oops_enter(void); extern void oops_exit(void); extern int oops_may_print(void); -fastcall NORET_TYPE void do_exit(long error_code) +NORET_TYPE void do_exit(long error_code) ATTRIB_NORET; NORET_TYPE void complete_and_exit(struct completion *, long) ATTRIB_NORET; @@ -141,6 +141,10 @@ extern unsigned long simple_strtoul(const char *,char **,unsigned int); extern long simple_strtol(const char *,char **,unsigned int); extern unsigned long long simple_strtoull(const char *,char **,unsigned int); extern long long simple_strtoll(const char *,char **,unsigned int); +extern int strict_strtoul(const char *, unsigned int, unsigned long *); +extern int strict_strtol(const char *, unsigned int, long *); +extern int strict_strtoull(const char *, unsigned int, unsigned long long *); +extern int strict_strtoll(const char *, unsigned int, long long *); extern int sprintf(char * buf, const char * fmt, ...) __attribute__ ((format (printf, 2, 3))); extern int vsprintf(char *buf, const char *, va_list) @@ -172,8 +176,6 @@ extern int kernel_text_address(unsigned long addr); struct pid; extern struct pid *session_of_pgrp(struct pid *pgrp); -extern void dump_thread(struct pt_regs *regs, struct user *dump); - #ifdef CONFIG_PRINTK asmlinkage int vprintk(const char *fmt, va_list args) __attribute__ ((format (printf, 1, 0))); @@ -182,6 +184,13 @@ asmlinkage int printk(const char * fmt, ...) extern int log_buf_get_len(void); extern int log_buf_read(int idx); extern int log_buf_copy(char *dest, int idx, int len); + +extern int printk_ratelimit_jiffies; +extern int printk_ratelimit_burst; +extern int printk_ratelimit(void); +extern int __printk_ratelimit(int ratelimit_jiffies, int ratelimit_burst); +extern bool printk_timed_ratelimit(unsigned long *caller_jiffies, + unsigned int interval_msec); #else static inline int vprintk(const char *s, va_list args) __attribute__ ((format (printf, 1, 0))); @@ -192,6 +201,12 @@ static inline int __cold printk(const char *s, ...) { return 0; } static inline int log_buf_get_len(void) { return 0; } static inline int log_buf_read(int idx) { return 0; } static inline int log_buf_copy(char *dest, int idx, int len) { return 0; } +static inline int printk_ratelimit(void) { return 0; } +static inline int __printk_ratelimit(int ratelimit_jiffies, \ + int ratelimit_burst) { return 0; } +static inline bool printk_timed_ratelimit(unsigned long *caller_jiffies, \ + unsigned int interval_msec) \ + { return false; } #endif extern void __attribute__((format(printf, 1, 2))) @@ -199,11 +214,6 @@ extern void __attribute__((format(printf, 1, 2))) unsigned long int_sqrt(unsigned long); -extern int printk_ratelimit(void); -extern int __printk_ratelimit(int ratelimit_jiffies, int ratelimit_burst); -extern bool printk_timed_ratelimit(unsigned long *caller_jiffies, - unsigned int interval_msec); - static inline void console_silent(void) { console_loglevel = 0; @@ -224,6 +234,7 @@ extern int panic_on_unrecovered_nmi; extern int tainted; extern const char *print_tainted(void); extern void add_taint(unsigned); +extern int root_mountflags; /* Values used for system_state */ extern enum system_states { diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index 222815d91c4..6cdf813cd47 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h @@ -133,6 +133,11 @@ enum { MLX4_STAT_RATE_OFFSET = 5 }; +static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) +{ + return (major << 32) | (minor << 16) | subminor; +} + struct mlx4_caps { u64 fw_ver; int num_ports; @@ -189,10 +194,8 @@ struct mlx4_buf_list { }; struct mlx4_buf { - union { - struct mlx4_buf_list direct; - struct mlx4_buf_list *page_list; - } u; + struct mlx4_buf_list direct; + struct mlx4_buf_list *page_list; int nbufs; int npages; int page_shift; @@ -308,6 +311,14 @@ struct mlx4_init_port_param { int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, struct mlx4_buf *buf); void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); +static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) +{ + if (BITS_PER_LONG == 64 || buf->nbufs == 1) + return buf->direct.buf + offset; + else + return buf->page_list[offset >> PAGE_SHIFT].buf + + (offset & (PAGE_SIZE - 1)); +} int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h index 3968b943259..09a2230923f 100644 --- a/include/linux/mlx4/qp.h +++ b/include/linux/mlx4/qp.h @@ -154,7 +154,11 @@ struct mlx4_qp_context { u32 reserved5[10]; }; +/* Which firmware version adds support for NEC (NoErrorCompletion) bit */ +#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) + enum { + MLX4_WQE_CTRL_NEC = 1 << 29, MLX4_WQE_CTRL_FENCE = 1 << 6, MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, MLX4_WQE_CTRL_SOLICITED = 1 << 1, diff --git a/include/linux/mm.h b/include/linux/mm.h index 89d7c691b93..e8abb381420 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -894,6 +894,18 @@ static inline pmd_t *pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long a #define pte_lockptr(mm, pmd) ({(void)(pmd); &(mm)->page_table_lock;}) #endif /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */ +static inline void pgtable_page_ctor(struct page *page) +{ + pte_lock_init(page); + inc_zone_page_state(page, NR_PAGETABLE); +} + +static inline void pgtable_page_dtor(struct page *page) +{ + pte_lock_deinit(page); + dec_zone_page_state(page, NR_PAGETABLE); +} + #define pte_offset_map_lock(mm, pmd, address, ptlp) \ ({ \ spinlock_t *__ptl = pte_lockptr(mm, pmd); \ @@ -1136,7 +1148,7 @@ struct page *follow_page(struct vm_area_struct *, unsigned long address, #define FOLL_GET 0x04 /* do get_page on page */ #define FOLL_ANON 0x08 /* give ZERO_PAGE if no pgtable */ -typedef int (*pte_fn_t)(pte_t *pte, struct page *pmd_page, unsigned long addr, +typedef int (*pte_fn_t)(pte_t *pte, pgtable_t token, unsigned long addr, void *data); extern int apply_to_page_range(struct mm_struct *mm, unsigned long address, unsigned long size, pte_fn_t fn, void *data); diff --git a/include/linux/module.h b/include/linux/module.h index ac481e2094f..ac28e8761e8 100644 --- a/include/linux/module.h +++ b/include/linux/module.h @@ -449,7 +449,7 @@ static inline void __module_get(struct module *module) /* For kallsyms to ask for address resolution. namebuf should be at * least KSYM_NAME_LEN long: a pointer to namebuf is returned if * found, otherwise NULL. */ -char *module_address_lookup(unsigned long addr, +const char *module_address_lookup(unsigned long addr, unsigned long *symbolsize, unsigned long *offset, char **modname, @@ -519,7 +519,7 @@ static inline void module_put(struct module *module) #define module_name(mod) "kernel" /* For kallsyms to ask for address resolution. NULL means not found. */ -static inline char *module_address_lookup(unsigned long addr, +static inline const char *module_address_lookup(unsigned long addr, unsigned long *symbolsize, unsigned long *offset, char **modname, diff --git a/include/linux/mutex.h b/include/linux/mutex.h index 05c590352dd..bc6da10ceee 100644 --- a/include/linux/mutex.h +++ b/include/linux/mutex.h @@ -112,7 +112,7 @@ extern void __mutex_init(struct mutex *lock, const char *name, * * Returns 1 if the mutex is locked, 0 if unlocked. */ -static inline int fastcall mutex_is_locked(struct mutex *lock) +static inline int mutex_is_locked(struct mutex *lock) { return atomic_read(&lock->count) != 1; } @@ -132,9 +132,9 @@ extern int __must_check mutex_lock_killable_nested(struct mutex *lock, #define mutex_lock_interruptible(lock) mutex_lock_interruptible_nested(lock, 0) #define mutex_lock_killable(lock) mutex_lock_killable_nested(lock, 0) #else -extern void fastcall mutex_lock(struct mutex *lock); -extern int __must_check fastcall mutex_lock_interruptible(struct mutex *lock); -extern int __must_check fastcall mutex_lock_killable(struct mutex *lock); +extern void mutex_lock(struct mutex *lock); +extern int __must_check mutex_lock_interruptible(struct mutex *lock); +extern int __must_check mutex_lock_killable(struct mutex *lock); # define mutex_lock_nested(lock, subclass) mutex_lock(lock) # define mutex_lock_interruptible_nested(lock, subclass) mutex_lock_interruptible(lock) @@ -145,7 +145,7 @@ extern int __must_check fastcall mutex_lock_killable(struct mutex *lock); * NOTE: mutex_trylock() follows the spin_trylock() convention, * not the down_trylock() convention! */ -extern int fastcall mutex_trylock(struct mutex *lock); -extern void fastcall mutex_unlock(struct mutex *lock); +extern int mutex_trylock(struct mutex *lock); +extern void mutex_unlock(struct mutex *lock); #endif diff --git a/include/linux/nbd.h b/include/linux/nbd.h index cc2b47240a8..986572081e1 100644 --- a/include/linux/nbd.h +++ b/include/linux/nbd.h @@ -35,7 +35,6 @@ enum { }; #define nbd_cmd(req) ((req)->cmd[0]) -#define MAX_NBD 128 /* userspace doesn't need the nbd_device structure */ #ifdef __KERNEL__ diff --git a/include/linux/pfkeyv2.h b/include/linux/pfkeyv2.h index 6db69ff5d83..700725ddcaa 100644 --- a/include/linux/pfkeyv2.h +++ b/include/linux/pfkeyv2.h @@ -298,6 +298,7 @@ struct sadb_x_sec_ctx { #define SADB_X_EALG_BLOWFISHCBC 7 #define SADB_EALG_NULL 11 #define SADB_X_EALG_AESCBC 12 +#define SADB_X_EALG_AESCTR 13 #define SADB_X_EALG_AES_CCM_ICV8 14 #define SADB_X_EALG_AES_CCM_ICV12 15 #define SADB_X_EALG_AES_CCM_ICV16 16 diff --git a/include/linux/pid.h b/include/linux/pid.h index e29a900a849..f84d532b5d2 100644 --- a/include/linux/pid.h +++ b/include/linux/pid.h @@ -118,18 +118,17 @@ extern struct pid *find_pid(int nr); */ extern struct pid *find_get_pid(int nr); extern struct pid *find_ge_pid(int nr, struct pid_namespace *); +int next_pidmap(struct pid_namespace *pid_ns, int last); extern struct pid *alloc_pid(struct pid_namespace *ns); extern void FASTCALL(free_pid(struct pid *pid)); -extern void zap_pid_ns_processes(struct pid_namespace *pid_ns); /* * the helpers to get the pid's id seen from different namespaces * * pid_nr() : global id, i.e. the id seen from the init namespace; - * pid_vnr() : virtual id, i.e. the id seen from the namespace this pid - * belongs to. this only makes sence when called in the - * context of the task that belongs to the same namespace; + * pid_vnr() : virtual id, i.e. the id seen from the pid namespace of + * current. * pid_nr_ns() : id seen from the ns specified. * * see also task_xid_nr() etc in include/linux/sched.h @@ -144,14 +143,7 @@ static inline pid_t pid_nr(struct pid *pid) } pid_t pid_nr_ns(struct pid *pid, struct pid_namespace *ns); - -static inline pid_t pid_vnr(struct pid *pid) -{ - pid_t nr = 0; - if (pid) - nr = pid->numbers[pid->level].nr; - return nr; -} +pid_t pid_vnr(struct pid *pid); #define do_each_pid_task(pid, type, task) \ do { \ @@ -160,7 +152,13 @@ static inline pid_t pid_vnr(struct pid *pid) hlist_for_each_entry_rcu((task), pos___, \ &pid->tasks[type], pids[type].node) { + /* + * Both old and new leaders may be attached to + * the same pid in the middle of de_thread(). + */ #define while_each_pid_task(pid, type, task) \ + if (type == PIDTYPE_PID) \ + break; \ } \ } while (0) diff --git a/include/linux/pid_namespace.h b/include/linux/pid_namespace.h index 1689e28483e..fcd61fa2c83 100644 --- a/include/linux/pid_namespace.h +++ b/include/linux/pid_namespace.h @@ -39,6 +39,7 @@ static inline struct pid_namespace *get_pid_ns(struct pid_namespace *ns) extern struct pid_namespace *copy_pid_ns(unsigned long flags, struct pid_namespace *ns); extern void free_pid_ns(struct kref *kref); +extern void zap_pid_ns_processes(struct pid_namespace *pid_ns); static inline void put_pid_ns(struct pid_namespace *ns) { @@ -66,6 +67,11 @@ static inline void put_pid_ns(struct pid_namespace *ns) { } + +static inline void zap_pid_ns_processes(struct pid_namespace *ns) +{ + BUG(); +} #endif /* CONFIG_PID_NS */ static inline struct pid_namespace *task_active_pid_ns(struct task_struct *tsk) diff --git a/include/linux/preempt.h b/include/linux/preempt.h index 484988ed301..23f0c54175c 100644 --- a/include/linux/preempt.h +++ b/include/linux/preempt.h @@ -11,8 +11,8 @@ #include <linux/list.h> #ifdef CONFIG_DEBUG_PREEMPT - extern void fastcall add_preempt_count(int val); - extern void fastcall sub_preempt_count(int val); + extern void add_preempt_count(int val); + extern void sub_preempt_count(int val); #else # define add_preempt_count(val) do { preempt_count() += (val); } while (0) # define sub_preempt_count(val) do { preempt_count() -= (val); } while (0) diff --git a/include/linux/proc_fs.h b/include/linux/proc_fs.h index e4355151683..d6a4f69bdc9 100644 --- a/include/linux/proc_fs.h +++ b/include/linux/proc_fs.h @@ -118,13 +118,17 @@ struct dentry *proc_pid_lookup(struct inode *dir, struct dentry * dentry, struct int proc_pid_readdir(struct file * filp, void * dirent, filldir_t filldir); unsigned long task_vsize(struct mm_struct *); int task_statm(struct mm_struct *, int *, int *, int *, int *); -char *task_mem(struct mm_struct *, char *); +void task_mem(struct seq_file *, struct mm_struct *); +void clear_refs_smap(struct mm_struct *mm); struct proc_dir_entry *de_get(struct proc_dir_entry *de); void de_put(struct proc_dir_entry *de); extern struct proc_dir_entry *create_proc_entry(const char *name, mode_t mode, struct proc_dir_entry *parent); +struct proc_dir_entry *proc_create(const char *name, mode_t mode, + struct proc_dir_entry *parent, + const struct file_operations *proc_fops); extern void remove_proc_entry(const char *name, struct proc_dir_entry *parent); extern struct vfsmount *proc_mnt; @@ -219,7 +223,12 @@ static inline void proc_flush_task(struct task_struct *task) static inline struct proc_dir_entry *create_proc_entry(const char *name, mode_t mode, struct proc_dir_entry *parent) { return NULL; } - +static inline struct proc_dir_entry *proc_create(const char *name, + mode_t mode, struct proc_dir_entry *parent, + const struct file_operations *proc_fops) +{ + return NULL; +} #define remove_proc_entry(name, parent) do {} while (0) static inline struct proc_dir_entry *proc_symlink(const char *name, @@ -262,6 +271,9 @@ extern void kclist_add(struct kcore_list *, void *, size_t); union proc_op { int (*proc_get_link)(struct inode *, struct dentry **, struct vfsmount **); int (*proc_read)(struct task_struct *task, char *page); + int (*proc_show)(struct seq_file *m, + struct pid_namespace *ns, struct pid *pid, + struct task_struct *task); }; struct proc_inode { diff --git a/include/linux/ptrace.h b/include/linux/ptrace.h index 6ab80714a91..ebe0c17039c 100644 --- a/include/linux/ptrace.h +++ b/include/linux/ptrace.h @@ -67,7 +67,6 @@ #define PT_TRACE_EXEC 0x00000080 #define PT_TRACE_VFORK_DONE 0x00000100 #define PT_TRACE_EXIT 0x00000200 -#define PT_ATTACHED 0x00000400 /* parent != real_parent */ #define PT_TRACE_MASK 0x000003f4 diff --git a/include/linux/rcupreempt.h b/include/linux/rcupreempt.h index ece8eb3e415..60c2a033b19 100644 --- a/include/linux/rcupreempt.h +++ b/include/linux/rcupreempt.h @@ -46,8 +46,8 @@ #define rcu_bh_qsctr_inc(cpu) #define call_rcu_bh(head, rcu) call_rcu(head, rcu) -extern void __rcu_read_lock(void); -extern void __rcu_read_unlock(void); +extern void __rcu_read_lock(void) __acquires(RCU); +extern void __rcu_read_unlock(void) __releases(RCU); extern int rcu_pending(int cpu); extern int rcu_needs_cpu(int cpu); diff --git a/include/linux/reiserfs_fs.h b/include/linux/reiserfs_fs.h index 422eab4958a..8e7eff2cd0a 100644 --- a/include/linux/reiserfs_fs.h +++ b/include/linux/reiserfs_fs.h @@ -287,7 +287,7 @@ static inline struct reiserfs_sb_info *REISERFS_SB(const struct super_block *sb) /* Don't trust REISERFS_SB(sb)->s_bmap_nr, it's a u16 * which overflows on large file systems. */ -static inline u32 reiserfs_bmap_count(struct super_block *sb) +static inline __u32 reiserfs_bmap_count(struct super_block *sb) { return (SB_BLOCK_COUNT(sb) - 1) / (sb->s_blocksize * 8) + 1; } diff --git a/include/linux/sched.h b/include/linux/sched.h index 8a4812c1c03..00e14411732 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -460,7 +460,7 @@ struct signal_struct { /* ITIMER_REAL timer for the process */ struct hrtimer real_timer; - struct task_struct *tsk; + struct pid *leader_pid; ktime_t it_real_incr; /* ITIMER_PROF and ITIMER_VIRTUAL timers for the process */ @@ -1332,9 +1332,8 @@ struct pid_namespace; * from various namespaces * * task_xid_nr() : global id, i.e. the id seen from the init namespace; - * task_xid_vnr() : virtual id, i.e. the id seen from the namespace the task - * belongs to. this only makes sence when called in the - * context of the task that belongs to the same namespace; + * task_xid_vnr() : virtual id, i.e. the id seen from the pid namespace of + * current. * task_xid_nr_ns() : id seen from the ns specified; * * set_task_vxid() : assigns a virtual id to a task; @@ -1632,7 +1631,7 @@ extern struct task_struct *find_task_by_vpid(pid_t nr); extern struct task_struct *find_task_by_pid_ns(pid_t nr, struct pid_namespace *ns); -extern void __set_special_pids(pid_t session, pid_t pgrp); +extern void __set_special_pids(struct pid *pid); /* per-UID process charging. */ extern struct user_struct * alloc_uid(struct user_namespace *, uid_t); @@ -1687,11 +1686,9 @@ extern void block_all_signals(int (*notifier)(void *priv), void *priv, extern void unblock_all_signals(void); extern void release_task(struct task_struct * p); extern int send_sig_info(int, struct siginfo *, struct task_struct *); -extern int send_group_sig_info(int, struct siginfo *, struct task_struct *); extern int force_sigsegv(int, struct task_struct *); extern int force_sig_info(int, struct siginfo *, struct task_struct *); extern int __kill_pgrp_info(int sig, struct siginfo *info, struct pid *pgrp); -extern int kill_pgrp_info(int sig, struct siginfo *info, struct pid *pgrp); extern int kill_pid_info(int sig, struct siginfo *info, struct pid *pid); extern int kill_pid_info_as_uid(int, struct siginfo *, struct pid *, uid_t, uid_t, u32); extern int kill_pgrp(struct pid *pid, int sig, int priv); diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index 9963f81fea9..1a0b6cf83ff 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -150,6 +150,10 @@ #define PORT_MCF 78 +/* MN10300 on-chip UART numbers */ +#define PORT_MN10300 80 +#define PORT_MN10300_CTS 81 + #ifdef __KERNEL__ #include <linux/compiler.h> diff --git a/include/linux/shmem_fs.h b/include/linux/shmem_fs.h index f3c51899117..8d5fb36ea04 100644 --- a/include/linux/shmem_fs.h +++ b/include/linux/shmem_fs.h @@ -30,9 +30,12 @@ struct shmem_sb_info { unsigned long free_blocks; /* How many are left for allocation */ unsigned long max_inodes; /* How many inodes are allowed */ unsigned long free_inodes; /* How many are left for allocation */ + spinlock_t stat_lock; /* Serialize shmem_sb_info changes */ + uid_t uid; /* Mount uid for root directory */ + gid_t gid; /* Mount gid for root directory */ + mode_t mode; /* Mount mode for root directory */ int policy; /* Default NUMA memory alloc policy */ nodemask_t policy_nodes; /* nodemask for preferred and bind */ - spinlock_t stat_lock; }; static inline struct shmem_inode_info *SHMEM_I(struct inode *inode) diff --git a/include/linux/signal.h b/include/linux/signal.h index 7e095147656..42d2e0a948f 100644 --- a/include/linux/signal.h +++ b/include/linux/signal.h @@ -241,6 +241,7 @@ extern int show_unhandled_signals; struct pt_regs; extern int get_signal_to_deliver(siginfo_t *info, struct k_sigaction *return_ka, struct pt_regs *regs, void *cookie); +extern void exit_signals(struct task_struct *tsk); extern struct kmem_cache *sighand_cachep; diff --git a/include/linux/spinlock.h b/include/linux/spinlock.h index 124449733c5..576a5f77d3b 100644 --- a/include/linux/spinlock.h +++ b/include/linux/spinlock.h @@ -71,7 +71,7 @@ #define LOCK_SECTION_END \ ".previous\n\t" -#define __lockfunc fastcall __attribute__((section(".spinlock.text"))) +#define __lockfunc __attribute__((section(".spinlock.text"))) /* * Pull the raw_spinlock_t and raw_rwlock_t definitions: diff --git a/include/linux/time.h b/include/linux/time.h index ceaab9fff15..2091a19f165 100644 --- a/include/linux/time.h +++ b/include/linux/time.h @@ -120,7 +120,7 @@ extern void getboottime(struct timespec *ts); extern void monotonic_to_bootbased(struct timespec *ts); extern struct timespec timespec_trunc(struct timespec t, unsigned gran); -extern int timekeeping_is_continuous(void); +extern int timekeeping_valid_for_hres(void); extern void update_wall_time(void); extern void update_xtime_cache(u64 nsec); diff --git a/include/linux/timer.h b/include/linux/timer.h index de0e71359ed..979fefdeb86 100644 --- a/include/linux/timer.h +++ b/include/linux/timer.h @@ -35,8 +35,8 @@ extern struct tvec_base boot_tvec_bases; struct timer_list _name = \ TIMER_INITIALIZER(_function, _expires, _data) -void fastcall init_timer(struct timer_list * timer); -void fastcall init_timer_deferrable(struct timer_list *timer); +void init_timer(struct timer_list *timer); +void init_timer_deferrable(struct timer_list *timer); static inline void setup_timer(struct timer_list * timer, void (*function)(unsigned long), @@ -124,8 +124,6 @@ static inline void timer_stats_timer_clear_start_info(struct timer_list *timer) } #endif -extern void delayed_work_timer_fn(unsigned long __data); - /** * add_timer - start a timer * @timer: the timer to be added diff --git a/include/linux/types.h b/include/linux/types.h index b94c0e4efe2..9dc2346627b 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -53,7 +53,7 @@ typedef __kernel_uid_t uid_t; typedef __kernel_gid_t gid_t; #endif /* __KERNEL__ */ -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +#if defined(__GNUC__) typedef __kernel_loff_t loff_t; #endif @@ -119,7 +119,7 @@ typedef __u8 uint8_t; typedef __u16 uint16_t; typedef __u32 uint32_t; -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +#if defined(__GNUC__) typedef __u64 uint64_t; typedef __u64 u_int64_t; typedef __s64 int64_t; @@ -181,7 +181,7 @@ typedef __u16 __bitwise __le16; typedef __u16 __bitwise __be16; typedef __u32 __bitwise __le32; typedef __u32 __bitwise __be32; -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +#if defined(__GNUC__) typedef __u64 __bitwise __le64; typedef __u64 __bitwise __be64; #endif diff --git a/include/linux/udf_fs.h b/include/linux/udf_fs.h index 36c684e1b11..aa88654eb76 100644 --- a/include/linux/udf_fs.h +++ b/include/linux/udf_fs.h @@ -32,18 +32,15 @@ #define UDF_PREALLOCATE #define UDF_DEFAULT_PREALLOC_BLOCKS 8 -#define UDFFS_DATE "2004/29/09" -#define UDFFS_VERSION "0.9.8.1" - #undef UDFFS_DEBUG #ifdef UDFFS_DEBUG #define udf_debug(f, a...) \ - { \ + do { \ printk (KERN_DEBUG "UDF-fs DEBUG %s:%d:%s: ", \ __FILE__, __LINE__, __FUNCTION__); \ printk (f, ##a); \ - } + } while (0) #else #define udf_debug(f, a...) /**/ #endif diff --git a/include/linux/udf_fs_sb.h b/include/linux/udf_fs_sb.h index 80ae9ef940d..9bc47352b6b 100644 --- a/include/linux/udf_fs_sb.h +++ b/include/linux/udf_fs_sb.h @@ -75,7 +75,7 @@ struct udf_part_map struct udf_sb_info { struct udf_part_map *s_partmaps; - __u8 s_volident[32]; + __u8 s_volume_ident[32]; /* Overall info */ __u16 s_partitions; @@ -84,9 +84,9 @@ struct udf_sb_info /* Sector headers */ __s32 s_session; __u32 s_anchor[4]; - __u32 s_lastblock; + __u32 s_last_block; - struct buffer_head *s_lvidbh; + struct buffer_head *s_lvid_bh; /* Default permissions */ mode_t s_umask; @@ -94,10 +94,10 @@ struct udf_sb_info uid_t s_uid; /* Root Info */ - struct timespec s_recordtime; + struct timespec s_record_time; /* Fileset Info */ - __u16 s_serialnum; + __u16 s_serial_number; /* highest UDF revision we have recorded to this media */ __u16 s_udfrev; @@ -109,7 +109,7 @@ struct udf_sb_info struct nls_table *s_nls_map; /* VAT inode */ - struct inode *s_vat; + struct inode *s_vat_inode; struct mutex s_alloc_mutex; }; diff --git a/include/linux/ufs_fs.h b/include/linux/ufs_fs.h deleted file mode 100644 index 10b854d3561..00000000000 --- a/include/linux/ufs_fs.h +++ /dev/null @@ -1,953 +0,0 @@ -/* - * linux/include/linux/ufs_fs.h - * - * Copyright (C) 1996 - * Adrian Rodriguez (adrian@franklins-tower.rutgers.edu) - * Laboratory for Computer Science Research Computing Facility - * Rutgers, The State University of New Jersey - * - * Clean swab support by Fare <fare@tunes.org> - * just hope no one is using NNUUXXI on __?64 structure elements - * 64-bit clean thanks to Maciej W. Rozycki <macro@ds2.pg.gda.pl> - * - * 4.4BSD (FreeBSD) support added on February 1st 1998 by - * Niels Kristian Bech Jensen <nkbj@image.dk> partially based - * on code by Martin von Loewis <martin@mira.isdn.cs.tu-berlin.de>. - * - * NeXTstep support added on February 5th 1998 by - * Niels Kristian Bech Jensen <nkbj@image.dk>. - * - * Write support by Daniel Pirkl <daniel.pirkl@email.cz> - * - * HP/UX hfs filesystem support added by - * Martin K. Petersen <mkp@mkp.net>, August 1999 - * - * UFS2 (of FreeBSD 5.x) support added by - * Niraj Kumar <niraj17@iitbombay.org> , Jan 2004 - * - */ - -#ifndef __LINUX_UFS_FS_H -#define __LINUX_UFS_FS_H - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/stat.h> -#include <linux/fs.h> - -#ifndef __KERNEL__ -typedef __u64 __fs64; -typedef __u32 __fs32; -typedef __u16 __fs16; -#else -#include <asm/div64.h> -typedef __u64 __bitwise __fs64; -typedef __u32 __bitwise __fs32; -typedef __u16 __bitwise __fs16; -#endif - -#define UFS_BBLOCK 0 -#define UFS_BBSIZE 8192 -#define UFS_SBLOCK 8192 -#define UFS_SBSIZE 8192 - -#define UFS_SECTOR_SIZE 512 -#define UFS_SECTOR_BITS 9 -#define UFS_MAGIC 0x00011954 -#define UFS2_MAGIC 0x19540119 -#define UFS_CIGAM 0x54190100 /* byteswapped MAGIC */ - -/* Copied from FreeBSD */ -/* - * Each disk drive contains some number of filesystems. - * A filesystem consists of a number of cylinder groups. - * Each cylinder group has inodes and data. - * - * A filesystem is described by its super-block, which in turn - * describes the cylinder groups. The super-block is critical - * data and is replicated in each cylinder group to protect against - * catastrophic loss. This is done at `newfs' time and the critical - * super-block data does not change, so the copies need not be - * referenced further unless disaster strikes. - * - * For filesystem fs, the offsets of the various blocks of interest - * are given in the super block as: - * [fs->fs_sblkno] Super-block - * [fs->fs_cblkno] Cylinder group block - * [fs->fs_iblkno] Inode blocks - * [fs->fs_dblkno] Data blocks - * The beginning of cylinder group cg in fs, is given by - * the ``cgbase(fs, cg)'' macro. - * - * Depending on the architecture and the media, the superblock may - * reside in any one of four places. For tiny media where every block - * counts, it is placed at the very front of the partition. Historically, - * UFS1 placed it 8K from the front to leave room for the disk label and - * a small bootstrap. For UFS2 it got moved to 64K from the front to leave - * room for the disk label and a bigger bootstrap, and for really piggy - * systems we check at 256K from the front if the first three fail. In - * all cases the size of the superblock will be SBLOCKSIZE. All values are - * given in byte-offset form, so they do not imply a sector size. The - * SBLOCKSEARCH specifies the order in which the locations should be searched. - */ -#define SBLOCK_FLOPPY 0 -#define SBLOCK_UFS1 8192 -#define SBLOCK_UFS2 65536 -#define SBLOCK_PIGGY 262144 -#define SBLOCKSIZE 8192 -#define SBLOCKSEARCH \ - { SBLOCK_UFS2, SBLOCK_UFS1, SBLOCK_FLOPPY, SBLOCK_PIGGY, -1 } - - -/* HP specific MAGIC values */ - -#define UFS_MAGIC_LFN 0x00095014 /* fs supports filenames > 14 chars */ -#define UFS_CIGAM_LFN 0x14500900 /* srahc 41 < semanelif stroppus sf */ - -#define UFS_MAGIC_SEC 0x00612195 /* B1 security fs */ -#define UFS_CIGAM_SEC 0x95216100 - -#define UFS_MAGIC_FEA 0x00195612 /* fs_featurebits supported */ -#define UFS_CIGAM_FEA 0x12561900 - -#define UFS_MAGIC_4GB 0x05231994 /* fs > 4 GB && fs_featurebits */ -#define UFS_CIGAM_4GB 0x94192305 - -/* Seems somebody at HP goofed here. B1 and lfs are both 0x2 !?! */ -#define UFS_FSF_LFN 0x00000001 /* long file names */ -#define UFS_FSF_B1 0x00000002 /* B1 security */ -#define UFS_FSF_LFS 0x00000002 /* large files */ -#define UFS_FSF_LUID 0x00000004 /* large UIDs */ - -/* End of HP stuff */ - - -#define UFS_BSIZE 8192 -#define UFS_MINBSIZE 4096 -#define UFS_FSIZE 1024 -#define UFS_MAXFRAG (UFS_BSIZE / UFS_FSIZE) - -#define UFS_NDADDR 12 -#define UFS_NINDIR 3 - -#define UFS_IND_BLOCK (UFS_NDADDR + 0) -#define UFS_DIND_BLOCK (UFS_NDADDR + 1) -#define UFS_TIND_BLOCK (UFS_NDADDR + 2) - -#define UFS_NDIR_FRAGMENT (UFS_NDADDR << uspi->s_fpbshift) -#define UFS_IND_FRAGMENT (UFS_IND_BLOCK << uspi->s_fpbshift) -#define UFS_DIND_FRAGMENT (UFS_DIND_BLOCK << uspi->s_fpbshift) -#define UFS_TIND_FRAGMENT (UFS_TIND_BLOCK << uspi->s_fpbshift) - -#define UFS_ROOTINO 2 -#define UFS_FIRST_INO (UFS_ROOTINO + 1) - -#define UFS_USEEFT ((__u16)65535) - -#define UFS_FSOK 0x7c269d38 -#define UFS_FSACTIVE ((__s8)0x00) -#define UFS_FSCLEAN ((__s8)0x01) -#define UFS_FSSTABLE ((__s8)0x02) -#define UFS_FSOSF1 ((__s8)0x03) /* is this correct for DEC OSF/1? */ -#define UFS_FSBAD ((__s8)0xff) - -/* From here to next blank line, s_flags for ufs_sb_info */ -/* directory entry encoding */ -#define UFS_DE_MASK 0x00000010 /* mask for the following */ -#define UFS_DE_OLD 0x00000000 -#define UFS_DE_44BSD 0x00000010 -/* uid encoding */ -#define UFS_UID_MASK 0x00000060 /* mask for the following */ -#define UFS_UID_OLD 0x00000000 -#define UFS_UID_44BSD 0x00000020 -#define UFS_UID_EFT 0x00000040 -/* superblock state encoding */ -#define UFS_ST_MASK 0x00000700 /* mask for the following */ -#define UFS_ST_OLD 0x00000000 -#define UFS_ST_44BSD 0x00000100 -#define UFS_ST_SUN 0x00000200 /* Solaris */ -#define UFS_ST_SUNOS 0x00000300 -#define UFS_ST_SUNx86 0x00000400 /* Solaris x86 */ -/*cylinder group encoding */ -#define UFS_CG_MASK 0x00003000 /* mask for the following */ -#define UFS_CG_OLD 0x00000000 -#define UFS_CG_44BSD 0x00002000 -#define UFS_CG_SUN 0x00001000 -/* filesystem type encoding */ -#define UFS_TYPE_MASK 0x00010000 /* mask for the following */ -#define UFS_TYPE_UFS1 0x00000000 -#define UFS_TYPE_UFS2 0x00010000 - - -/* fs_inodefmt options */ -#define UFS_42INODEFMT -1 -#define UFS_44INODEFMT 2 - -/* - * MINFREE gives the minimum acceptable percentage of file system - * blocks which may be free. If the freelist drops below this level - * only the superuser may continue to allocate blocks. This may - * be set to 0 if no reserve of free blocks is deemed necessary, - * however throughput drops by fifty percent if the file system - * is run at between 95% and 100% full; thus the minimum default - * value of fs_minfree is 5%. However, to get good clustering - * performance, 10% is a better choice. hence we use 10% as our - * default value. With 10% free space, fragmentation is not a - * problem, so we choose to optimize for time. - */ -#define UFS_MINFREE 5 -#define UFS_DEFAULTOPT UFS_OPTTIME - -/* - * Turn file system block numbers into disk block addresses. - * This maps file system blocks to device size blocks. - */ -#define ufs_fsbtodb(uspi, b) ((b) << (uspi)->s_fsbtodb) -#define ufs_dbtofsb(uspi, b) ((b) >> (uspi)->s_fsbtodb) - -/* - * Cylinder group macros to locate things in cylinder groups. - * They calc file system addresses of cylinder group data structures. - */ -#define ufs_cgbase(c) (uspi->s_fpg * (c)) -#define ufs_cgstart(c) ((uspi)->fs_magic == UFS2_MAGIC ? ufs_cgbase(c) : \ - (ufs_cgbase(c) + uspi->s_cgoffset * ((c) & ~uspi->s_cgmask))) -#define ufs_cgsblock(c) (ufs_cgstart(c) + uspi->s_sblkno) /* super blk */ -#define ufs_cgcmin(c) (ufs_cgstart(c) + uspi->s_cblkno) /* cg block */ -#define ufs_cgimin(c) (ufs_cgstart(c) + uspi->s_iblkno) /* inode blk */ -#define ufs_cgdmin(c) (ufs_cgstart(c) + uspi->s_dblkno) /* 1st data */ - -/* - * Macros for handling inode numbers: - * inode number to file system block offset. - * inode number to cylinder group number. - * inode number to file system block address. - */ -#define ufs_inotocg(x) ((x) / uspi->s_ipg) -#define ufs_inotocgoff(x) ((x) % uspi->s_ipg) -#define ufs_inotofsba(x) (((u64)ufs_cgimin(ufs_inotocg(x))) + ufs_inotocgoff(x) / uspi->s_inopf) -#define ufs_inotofsbo(x) ((x) % uspi->s_inopf) - -/* - * Compute the cylinder and rotational position of a cyl block addr. - */ -#define ufs_cbtocylno(bno) \ - ((bno) * uspi->s_nspf / uspi->s_spc) -#define ufs_cbtorpos(bno) \ - ((((bno) * uspi->s_nspf % uspi->s_spc / uspi->s_nsect \ - * uspi->s_trackskew + (bno) * uspi->s_nspf % uspi->s_spc \ - % uspi->s_nsect * uspi->s_interleave) % uspi->s_nsect \ - * uspi->s_nrpos) / uspi->s_npsect) - -/* - * The following macros optimize certain frequently calculated - * quantities by using shifts and masks in place of divisions - * modulos and multiplications. - */ -#define ufs_blkoff(loc) ((loc) & uspi->s_qbmask) -#define ufs_fragoff(loc) ((loc) & uspi->s_qfmask) -#define ufs_lblktosize(blk) ((blk) << uspi->s_bshift) -#define ufs_lblkno(loc) ((loc) >> uspi->s_bshift) -#define ufs_numfrags(loc) ((loc) >> uspi->s_fshift) -#define ufs_blkroundup(size) (((size) + uspi->s_qbmask) & uspi->s_bmask) -#define ufs_fragroundup(size) (((size) + uspi->s_qfmask) & uspi->s_fmask) -#define ufs_fragstoblks(frags) ((frags) >> uspi->s_fpbshift) -#define ufs_blkstofrags(blks) ((blks) << uspi->s_fpbshift) -#define ufs_fragnum(fsb) ((fsb) & uspi->s_fpbmask) -#define ufs_blknum(fsb) ((fsb) & ~uspi->s_fpbmask) - -#define UFS_MAXNAMLEN 255 -#define UFS_MAXMNTLEN 512 -#define UFS2_MAXMNTLEN 468 -#define UFS2_MAXVOLLEN 32 -#define UFS_MAXCSBUFS 31 -#define UFS_LINK_MAX 32000 -/* -#define UFS2_NOCSPTRS ((128 / sizeof(void *)) - 4) -*/ -#define UFS2_NOCSPTRS 28 - -/* - * UFS_DIR_PAD defines the directory entries boundaries - * (must be a multiple of 4) - */ -#define UFS_DIR_PAD 4 -#define UFS_DIR_ROUND (UFS_DIR_PAD - 1) -#define UFS_DIR_REC_LEN(name_len) (((name_len) + 1 + 8 + UFS_DIR_ROUND) & ~UFS_DIR_ROUND) - -struct ufs_timeval { - __fs32 tv_sec; - __fs32 tv_usec; -}; - -struct ufs_dir_entry { - __fs32 d_ino; /* inode number of this entry */ - __fs16 d_reclen; /* length of this entry */ - union { - __fs16 d_namlen; /* actual length of d_name */ - struct { - __u8 d_type; /* file type */ - __u8 d_namlen; /* length of string in d_name */ - } d_44; - } d_u; - __u8 d_name[UFS_MAXNAMLEN + 1]; /* file name */ -}; - -struct ufs_csum { - __fs32 cs_ndir; /* number of directories */ - __fs32 cs_nbfree; /* number of free blocks */ - __fs32 cs_nifree; /* number of free inodes */ - __fs32 cs_nffree; /* number of free frags */ -}; -struct ufs2_csum_total { - __fs64 cs_ndir; /* number of directories */ - __fs64 cs_nbfree; /* number of free blocks */ - __fs64 cs_nifree; /* number of free inodes */ - __fs64 cs_nffree; /* number of free frags */ - __fs64 cs_numclusters; /* number of free clusters */ - __fs64 cs_spare[3]; /* future expansion */ -}; - -struct ufs_csum_core { - __u64 cs_ndir; /* number of directories */ - __u64 cs_nbfree; /* number of free blocks */ - __u64 cs_nifree; /* number of free inodes */ - __u64 cs_nffree; /* number of free frags */ - __u64 cs_numclusters; /* number of free clusters */ -}; - -/* - * File system flags - */ -#define UFS_UNCLEAN 0x01 /* file system not clean at mount (unused) */ -#define UFS_DOSOFTDEP 0x02 /* file system using soft dependencies */ -#define UFS_NEEDSFSCK 0x04 /* needs sync fsck (FreeBSD compat, unused) */ -#define UFS_INDEXDIRS 0x08 /* kernel supports indexed directories */ -#define UFS_ACLS 0x10 /* file system has ACLs enabled */ -#define UFS_MULTILABEL 0x20 /* file system is MAC multi-label */ -#define UFS_FLAGS_UPDATED 0x80 /* flags have been moved to new location */ - -#if 0 -/* - * This is the actual superblock, as it is laid out on the disk. - * Do NOT use this structure, because of sizeof(ufs_super_block) > 512 and - * it may occupy several blocks, use - * struct ufs_super_block_(first,second,third) instead. - */ -struct ufs_super_block { - union { - struct { - __fs32 fs_link; /* UNUSED */ - } fs_42; - struct { - __fs32 fs_state; /* file system state flag */ - } fs_sun; - } fs_u0; - __fs32 fs_rlink; /* UNUSED */ - __fs32 fs_sblkno; /* addr of super-block in filesys */ - __fs32 fs_cblkno; /* offset of cyl-block in filesys */ - __fs32 fs_iblkno; /* offset of inode-blocks in filesys */ - __fs32 fs_dblkno; /* offset of first data after cg */ - __fs32 fs_cgoffset; /* cylinder group offset in cylinder */ - __fs32 fs_cgmask; /* used to calc mod fs_ntrak */ - __fs32 fs_time; /* last time written -- time_t */ - __fs32 fs_size; /* number of blocks in fs */ - __fs32 fs_dsize; /* number of data blocks in fs */ - __fs32 fs_ncg; /* number of cylinder groups */ - __fs32 fs_bsize; /* size of basic blocks in fs */ - __fs32 fs_fsize; /* size of frag blocks in fs */ - __fs32 fs_frag; /* number of frags in a block in fs */ -/* these are configuration parameters */ - __fs32 fs_minfree; /* minimum percentage of free blocks */ - __fs32 fs_rotdelay; /* num of ms for optimal next block */ - __fs32 fs_rps; /* disk revolutions per second */ -/* these fields can be computed from the others */ - __fs32 fs_bmask; /* ``blkoff'' calc of blk offsets */ - __fs32 fs_fmask; /* ``fragoff'' calc of frag offsets */ - __fs32 fs_bshift; /* ``lblkno'' calc of logical blkno */ - __fs32 fs_fshift; /* ``numfrags'' calc number of frags */ -/* these are configuration parameters */ - __fs32 fs_maxcontig; /* max number of contiguous blks */ - __fs32 fs_maxbpg; /* max number of blks per cyl group */ -/* these fields can be computed from the others */ - __fs32 fs_fragshift; /* block to frag shift */ - __fs32 fs_fsbtodb; /* fsbtodb and dbtofsb shift constant */ - __fs32 fs_sbsize; /* actual size of super block */ - __fs32 fs_csmask; /* csum block offset */ - __fs32 fs_csshift; /* csum block number */ - __fs32 fs_nindir; /* value of NINDIR */ - __fs32 fs_inopb; /* value of INOPB */ - __fs32 fs_nspf; /* value of NSPF */ -/* yet another configuration parameter */ - __fs32 fs_optim; /* optimization preference, see below */ -/* these fields are derived from the hardware */ - union { - struct { - __fs32 fs_npsect; /* # sectors/track including spares */ - } fs_sun; - struct { - __fs32 fs_state; /* file system state time stamp */ - } fs_sunx86; - } fs_u1; - __fs32 fs_interleave; /* hardware sector interleave */ - __fs32 fs_trackskew; /* sector 0 skew, per track */ -/* a unique id for this filesystem (currently unused and unmaintained) */ -/* In 4.3 Tahoe this space is used by fs_headswitch and fs_trkseek */ -/* Neither of those fields is used in the Tahoe code right now but */ -/* there could be problems if they are. */ - __fs32 fs_id[2]; /* file system id */ -/* sizes determined by number of cylinder groups and their sizes */ - __fs32 fs_csaddr; /* blk addr of cyl grp summary area */ - __fs32 fs_cssize; /* size of cyl grp summary area */ - __fs32 fs_cgsize; /* cylinder group size */ -/* these fields are derived from the hardware */ - __fs32 fs_ntrak; /* tracks per cylinder */ - __fs32 fs_nsect; /* sectors per track */ - __fs32 fs_spc; /* sectors per cylinder */ -/* this comes from the disk driver partitioning */ - __fs32 fs_ncyl; /* cylinders in file system */ -/* these fields can be computed from the others */ - __fs32 fs_cpg; /* cylinders per group */ - __fs32 fs_ipg; /* inodes per cylinder group */ - __fs32 fs_fpg; /* blocks per group * fs_frag */ -/* this data must be re-computed after crashes */ - struct ufs_csum fs_cstotal; /* cylinder summary information */ -/* these fields are cleared at mount time */ - __s8 fs_fmod; /* super block modified flag */ - __s8 fs_clean; /* file system is clean flag */ - __s8 fs_ronly; /* mounted read-only flag */ - __s8 fs_flags; - union { - struct { - __s8 fs_fsmnt[UFS_MAXMNTLEN];/* name mounted on */ - __fs32 fs_cgrotor; /* last cg searched */ - __fs32 fs_csp[UFS_MAXCSBUFS];/*list of fs_cs info buffers */ - __fs32 fs_maxcluster; - __fs32 fs_cpc; /* cyl per cycle in postbl */ - __fs16 fs_opostbl[16][8]; /* old rotation block list head */ - } fs_u1; - struct { - __s8 fs_fsmnt[UFS2_MAXMNTLEN]; /* name mounted on */ - __u8 fs_volname[UFS2_MAXVOLLEN]; /* volume name */ - __fs64 fs_swuid; /* system-wide uid */ - __fs32 fs_pad; /* due to alignment of fs_swuid */ - __fs32 fs_cgrotor; /* last cg searched */ - __fs32 fs_ocsp[UFS2_NOCSPTRS]; /*list of fs_cs info buffers */ - __fs32 fs_contigdirs;/*# of contiguously allocated dirs */ - __fs32 fs_csp; /* cg summary info buffer for fs_cs */ - __fs32 fs_maxcluster; - __fs32 fs_active;/* used by snapshots to track fs */ - __fs32 fs_old_cpc; /* cyl per cycle in postbl */ - __fs32 fs_maxbsize;/*maximum blocking factor permitted */ - __fs64 fs_sparecon64[17];/*old rotation block list head */ - __fs64 fs_sblockloc; /* byte offset of standard superblock */ - struct ufs2_csum_total fs_cstotal;/*cylinder summary information*/ - struct ufs_timeval fs_time; /* last time written */ - __fs64 fs_size; /* number of blocks in fs */ - __fs64 fs_dsize; /* number of data blocks in fs */ - __fs64 fs_csaddr; /* blk addr of cyl grp summary area */ - __fs64 fs_pendingblocks;/* blocks in process of being freed */ - __fs32 fs_pendinginodes;/*inodes in process of being freed */ - } fs_u2; - } fs_u11; - union { - struct { - __fs32 fs_sparecon[53];/* reserved for future constants */ - __fs32 fs_reclaim; - __fs32 fs_sparecon2[1]; - __fs32 fs_state; /* file system state time stamp */ - __fs32 fs_qbmask[2]; /* ~usb_bmask */ - __fs32 fs_qfmask[2]; /* ~usb_fmask */ - } fs_sun; - struct { - __fs32 fs_sparecon[53];/* reserved for future constants */ - __fs32 fs_reclaim; - __fs32 fs_sparecon2[1]; - __fs32 fs_npsect; /* # sectors/track including spares */ - __fs32 fs_qbmask[2]; /* ~usb_bmask */ - __fs32 fs_qfmask[2]; /* ~usb_fmask */ - } fs_sunx86; - struct { - __fs32 fs_sparecon[50];/* reserved for future constants */ - __fs32 fs_contigsumsize;/* size of cluster summary array */ - __fs32 fs_maxsymlinklen;/* max length of an internal symlink */ - __fs32 fs_inodefmt; /* format of on-disk inodes */ - __fs32 fs_maxfilesize[2]; /* max representable file size */ - __fs32 fs_qbmask[2]; /* ~usb_bmask */ - __fs32 fs_qfmask[2]; /* ~usb_fmask */ - __fs32 fs_state; /* file system state time stamp */ - } fs_44; - } fs_u2; - __fs32 fs_postblformat; /* format of positional layout tables */ - __fs32 fs_nrpos; /* number of rotational positions */ - __fs32 fs_postbloff; /* (__s16) rotation block list head */ - __fs32 fs_rotbloff; /* (__u8) blocks for each rotation */ - __fs32 fs_magic; /* magic number */ - __u8 fs_space[1]; /* list of blocks for each rotation */ -}; -#endif/*struct ufs_super_block*/ - -/* - * Preference for optimization. - */ -#define UFS_OPTTIME 0 /* minimize allocation time */ -#define UFS_OPTSPACE 1 /* minimize disk fragmentation */ - -/* - * Rotational layout table format types - */ -#define UFS_42POSTBLFMT -1 /* 4.2BSD rotational table format */ -#define UFS_DYNAMICPOSTBLFMT 1 /* dynamic rotational table format */ - -/* - * Convert cylinder group to base address of its global summary info. - */ -#define fs_cs(indx) s_csp[(indx)] - -/* - * Cylinder group block for a file system. - * - * Writable fields in the cylinder group are protected by the associated - * super block lock fs->fs_lock. - */ -#define CG_MAGIC 0x090255 -#define ufs_cg_chkmagic(sb, ucg) \ - (fs32_to_cpu((sb), (ucg)->cg_magic) == CG_MAGIC) -/* - * Macros for access to old cylinder group array structures - */ -#define ufs_ocg_blktot(sb, ucg) fs32_to_cpu((sb), ((struct ufs_old_cylinder_group *)(ucg))->cg_btot) -#define ufs_ocg_blks(sb, ucg, cylno) fs32_to_cpu((sb), ((struct ufs_old_cylinder_group *)(ucg))->cg_b[cylno]) -#define ufs_ocg_inosused(sb, ucg) fs32_to_cpu((sb), ((struct ufs_old_cylinder_group *)(ucg))->cg_iused) -#define ufs_ocg_blksfree(sb, ucg) fs32_to_cpu((sb), ((struct ufs_old_cylinder_group *)(ucg))->cg_free) -#define ufs_ocg_chkmagic(sb, ucg) \ - (fs32_to_cpu((sb), ((struct ufs_old_cylinder_group *)(ucg))->cg_magic) == CG_MAGIC) - -/* - * size of this structure is 172 B - */ -struct ufs_cylinder_group { - __fs32 cg_link; /* linked list of cyl groups */ - __fs32 cg_magic; /* magic number */ - __fs32 cg_time; /* time last written */ - __fs32 cg_cgx; /* we are the cgx'th cylinder group */ - __fs16 cg_ncyl; /* number of cyl's this cg */ - __fs16 cg_niblk; /* number of inode blocks this cg */ - __fs32 cg_ndblk; /* number of data blocks this cg */ - struct ufs_csum cg_cs; /* cylinder summary information */ - __fs32 cg_rotor; /* position of last used block */ - __fs32 cg_frotor; /* position of last used frag */ - __fs32 cg_irotor; /* position of last used inode */ - __fs32 cg_frsum[UFS_MAXFRAG]; /* counts of available frags */ - __fs32 cg_btotoff; /* (__u32) block totals per cylinder */ - __fs32 cg_boff; /* (short) free block positions */ - __fs32 cg_iusedoff; /* (char) used inode map */ - __fs32 cg_freeoff; /* (u_char) free block map */ - __fs32 cg_nextfreeoff; /* (u_char) next available space */ - union { - struct { - __fs32 cg_clustersumoff; /* (u_int32) counts of avail clusters */ - __fs32 cg_clusteroff; /* (u_int8) free cluster map */ - __fs32 cg_nclusterblks; /* number of clusters this cg */ - __fs32 cg_sparecon[13]; /* reserved for future use */ - } cg_44; - struct { - __fs32 cg_clustersumoff;/* (u_int32) counts of avail clusters */ - __fs32 cg_clusteroff; /* (u_int8) free cluster map */ - __fs32 cg_nclusterblks;/* number of clusters this cg */ - __fs32 cg_niblk; /* number of inode blocks this cg */ - __fs32 cg_initediblk; /* last initialized inode */ - __fs32 cg_sparecon32[3];/* reserved for future use */ - __fs64 cg_time; /* time last written */ - __fs64 cg_sparecon[3]; /* reserved for future use */ - } cg_u2; - __fs32 cg_sparecon[16]; /* reserved for future use */ - } cg_u; - __u8 cg_space[1]; /* space for cylinder group maps */ -/* actually longer */ -}; - -/* Historic Cylinder group info */ -struct ufs_old_cylinder_group { - __fs32 cg_link; /* linked list of cyl groups */ - __fs32 cg_rlink; /* for incore cyl groups */ - __fs32 cg_time; /* time last written */ - __fs32 cg_cgx; /* we are the cgx'th cylinder group */ - __fs16 cg_ncyl; /* number of cyl's this cg */ - __fs16 cg_niblk; /* number of inode blocks this cg */ - __fs32 cg_ndblk; /* number of data blocks this cg */ - struct ufs_csum cg_cs; /* cylinder summary information */ - __fs32 cg_rotor; /* position of last used block */ - __fs32 cg_frotor; /* position of last used frag */ - __fs32 cg_irotor; /* position of last used inode */ - __fs32 cg_frsum[8]; /* counts of available frags */ - __fs32 cg_btot[32]; /* block totals per cylinder */ - __fs16 cg_b[32][8]; /* positions of free blocks */ - __u8 cg_iused[256]; /* used inode map */ - __fs32 cg_magic; /* magic number */ - __u8 cg_free[1]; /* free block map */ -/* actually longer */ -}; - -/* - * structure of an on-disk inode - */ -struct ufs_inode { - __fs16 ui_mode; /* 0x0 */ - __fs16 ui_nlink; /* 0x2 */ - union { - struct { - __fs16 ui_suid; /* 0x4 */ - __fs16 ui_sgid; /* 0x6 */ - } oldids; - __fs32 ui_inumber; /* 0x4 lsf: inode number */ - __fs32 ui_author; /* 0x4 GNU HURD: author */ - } ui_u1; - __fs64 ui_size; /* 0x8 */ - struct ufs_timeval ui_atime; /* 0x10 access */ - struct ufs_timeval ui_mtime; /* 0x18 modification */ - struct ufs_timeval ui_ctime; /* 0x20 creation */ - union { - struct { - __fs32 ui_db[UFS_NDADDR];/* 0x28 data blocks */ - __fs32 ui_ib[UFS_NINDIR];/* 0x58 indirect blocks */ - } ui_addr; - __u8 ui_symlink[4*(UFS_NDADDR+UFS_NINDIR)];/* 0x28 fast symlink */ - } ui_u2; - __fs32 ui_flags; /* 0x64 immutable, append-only... */ - __fs32 ui_blocks; /* 0x68 blocks in use */ - __fs32 ui_gen; /* 0x6c like ext2 i_version, for NFS support */ - union { - struct { - __fs32 ui_shadow; /* 0x70 shadow inode with security data */ - __fs32 ui_uid; /* 0x74 long EFT version of uid */ - __fs32 ui_gid; /* 0x78 long EFT version of gid */ - __fs32 ui_oeftflag; /* 0x7c reserved */ - } ui_sun; - struct { - __fs32 ui_uid; /* 0x70 File owner */ - __fs32 ui_gid; /* 0x74 File group */ - __fs32 ui_spare[2]; /* 0x78 reserved */ - } ui_44; - struct { - __fs32 ui_uid; /* 0x70 */ - __fs32 ui_gid; /* 0x74 */ - __fs16 ui_modeh; /* 0x78 mode high bits */ - __fs16 ui_spare; /* 0x7A unused */ - __fs32 ui_trans; /* 0x7c filesystem translator */ - } ui_hurd; - } ui_u3; -}; - -#define UFS_NXADDR 2 /* External addresses in inode. */ -struct ufs2_inode { - __fs16 ui_mode; /* 0: IFMT, permissions; see below. */ - __fs16 ui_nlink; /* 2: File link count. */ - __fs32 ui_uid; /* 4: File owner. */ - __fs32 ui_gid; /* 8: File group. */ - __fs32 ui_blksize; /* 12: Inode blocksize. */ - __fs64 ui_size; /* 16: File byte count. */ - __fs64 ui_blocks; /* 24: Bytes actually held. */ - __fs64 ui_atime; /* 32: Last access time. */ - __fs64 ui_mtime; /* 40: Last modified time. */ - __fs64 ui_ctime; /* 48: Last inode change time. */ - __fs64 ui_birthtime; /* 56: Inode creation time. */ - __fs32 ui_mtimensec; /* 64: Last modified time. */ - __fs32 ui_atimensec; /* 68: Last access time. */ - __fs32 ui_ctimensec; /* 72: Last inode change time. */ - __fs32 ui_birthnsec; /* 76: Inode creation time. */ - __fs32 ui_gen; /* 80: Generation number. */ - __fs32 ui_kernflags; /* 84: Kernel flags. */ - __fs32 ui_flags; /* 88: Status flags (chflags). */ - __fs32 ui_extsize; /* 92: External attributes block. */ - __fs64 ui_extb[UFS_NXADDR];/* 96: External attributes block. */ - union { - struct { - __fs64 ui_db[UFS_NDADDR]; /* 112: Direct disk blocks. */ - __fs64 ui_ib[UFS_NINDIR];/* 208: Indirect disk blocks.*/ - } ui_addr; - __u8 ui_symlink[2*4*(UFS_NDADDR+UFS_NINDIR)];/* 0x28 fast symlink */ - } ui_u2; - __fs64 ui_spare[3]; /* 232: Reserved; currently unused */ -}; - - -/* FreeBSD has these in sys/stat.h */ -/* ui_flags that can be set by a file owner */ -#define UFS_UF_SETTABLE 0x0000ffff -#define UFS_UF_NODUMP 0x00000001 /* do not dump */ -#define UFS_UF_IMMUTABLE 0x00000002 /* immutable (can't "change") */ -#define UFS_UF_APPEND 0x00000004 /* append-only */ -#define UFS_UF_OPAQUE 0x00000008 /* directory is opaque (unionfs) */ -#define UFS_UF_NOUNLINK 0x00000010 /* can't be removed or renamed */ -/* ui_flags that only root can set */ -#define UFS_SF_SETTABLE 0xffff0000 -#define UFS_SF_ARCHIVED 0x00010000 /* archived */ -#define UFS_SF_IMMUTABLE 0x00020000 /* immutable (can't "change") */ -#define UFS_SF_APPEND 0x00040000 /* append-only */ -#define UFS_SF_NOUNLINK 0x00100000 /* can't be removed or renamed */ - -/* - * This structure is used for reading disk structures larger - * than the size of fragment. - */ -struct ufs_buffer_head { - __u64 fragment; /* first fragment */ - __u64 count; /* number of fragments */ - struct buffer_head * bh[UFS_MAXFRAG]; /* buffers */ -}; - -struct ufs_cg_private_info { - struct ufs_buffer_head c_ubh; - __u32 c_cgx; /* number of cylidner group */ - __u16 c_ncyl; /* number of cyl's this cg */ - __u16 c_niblk; /* number of inode blocks this cg */ - __u32 c_ndblk; /* number of data blocks this cg */ - __u32 c_rotor; /* position of last used block */ - __u32 c_frotor; /* position of last used frag */ - __u32 c_irotor; /* position of last used inode */ - __u32 c_btotoff; /* (__u32) block totals per cylinder */ - __u32 c_boff; /* (short) free block positions */ - __u32 c_iusedoff; /* (char) used inode map */ - __u32 c_freeoff; /* (u_char) free block map */ - __u32 c_nextfreeoff; /* (u_char) next available space */ - __u32 c_clustersumoff;/* (u_int32) counts of avail clusters */ - __u32 c_clusteroff; /* (u_int8) free cluster map */ - __u32 c_nclusterblks; /* number of clusters this cg */ -}; - - -struct ufs_sb_private_info { - struct ufs_buffer_head s_ubh; /* buffer containing super block */ - struct ufs_csum_core cs_total; - __u32 s_sblkno; /* offset of super-blocks in filesys */ - __u32 s_cblkno; /* offset of cg-block in filesys */ - __u32 s_iblkno; /* offset of inode-blocks in filesys */ - __u32 s_dblkno; /* offset of first data after cg */ - __u32 s_cgoffset; /* cylinder group offset in cylinder */ - __u32 s_cgmask; /* used to calc mod fs_ntrak */ - __u32 s_size; /* number of blocks (fragments) in fs */ - __u32 s_dsize; /* number of data blocks in fs */ - __u64 s_u2_size; /* ufs2: number of blocks (fragments) in fs */ - __u64 s_u2_dsize; /*ufs2: number of data blocks in fs */ - __u32 s_ncg; /* number of cylinder groups */ - __u32 s_bsize; /* size of basic blocks */ - __u32 s_fsize; /* size of fragments */ - __u32 s_fpb; /* fragments per block */ - __u32 s_minfree; /* minimum percentage of free blocks */ - __u32 s_bmask; /* `blkoff'' calc of blk offsets */ - __u32 s_fmask; /* s_fsize mask */ - __u32 s_bshift; /* `lblkno'' calc of logical blkno */ - __u32 s_fshift; /* s_fsize shift */ - __u32 s_fpbshift; /* fragments per block shift */ - __u32 s_fsbtodb; /* fsbtodb and dbtofsb shift constant */ - __u32 s_sbsize; /* actual size of super block */ - __u32 s_csmask; /* csum block offset */ - __u32 s_csshift; /* csum block number */ - __u32 s_nindir; /* value of NINDIR */ - __u32 s_inopb; /* value of INOPB */ - __u32 s_nspf; /* value of NSPF */ - __u32 s_npsect; /* # sectors/track including spares */ - __u32 s_interleave; /* hardware sector interleave */ - __u32 s_trackskew; /* sector 0 skew, per track */ - __u64 s_csaddr; /* blk addr of cyl grp summary area */ - __u32 s_cssize; /* size of cyl grp summary area */ - __u32 s_cgsize; /* cylinder group size */ - __u32 s_ntrak; /* tracks per cylinder */ - __u32 s_nsect; /* sectors per track */ - __u32 s_spc; /* sectors per cylinder */ - __u32 s_ipg; /* inodes per cylinder group */ - __u32 s_fpg; /* fragments per group */ - __u32 s_cpc; /* cyl per cycle in postbl */ - __s32 s_contigsumsize;/* size of cluster summary array, 44bsd */ - __s64 s_qbmask; /* ~usb_bmask */ - __s64 s_qfmask; /* ~usb_fmask */ - __s32 s_postblformat; /* format of positional layout tables */ - __s32 s_nrpos; /* number of rotational positions */ - __s32 s_postbloff; /* (__s16) rotation block list head */ - __s32 s_rotbloff; /* (__u8) blocks for each rotation */ - - __u32 s_fpbmask; /* fragments per block mask */ - __u32 s_apb; /* address per block */ - __u32 s_2apb; /* address per block^2 */ - __u32 s_3apb; /* address per block^3 */ - __u32 s_apbmask; /* address per block mask */ - __u32 s_apbshift; /* address per block shift */ - __u32 s_2apbshift; /* address per block shift * 2 */ - __u32 s_3apbshift; /* address per block shift * 3 */ - __u32 s_nspfshift; /* number of sector per fragment shift */ - __u32 s_nspb; /* number of sector per block */ - __u32 s_inopf; /* inodes per fragment */ - __u32 s_sbbase; /* offset of NeXTstep superblock */ - __u32 s_bpf; /* bits per fragment */ - __u32 s_bpfshift; /* bits per fragment shift*/ - __u32 s_bpfmask; /* bits per fragment mask */ - - __u32 s_maxsymlinklen;/* upper limit on fast symlinks' size */ - __s32 fs_magic; /* filesystem magic */ - unsigned int s_dirblksize; -}; - -/* - * Sizes of this structures are: - * ufs_super_block_first 512 - * ufs_super_block_second 512 - * ufs_super_block_third 356 - */ -struct ufs_super_block_first { - union { - struct { - __fs32 fs_link; /* UNUSED */ - } fs_42; - struct { - __fs32 fs_state; /* file system state flag */ - } fs_sun; - } fs_u0; - __fs32 fs_rlink; - __fs32 fs_sblkno; - __fs32 fs_cblkno; - __fs32 fs_iblkno; - __fs32 fs_dblkno; - __fs32 fs_cgoffset; - __fs32 fs_cgmask; - __fs32 fs_time; - __fs32 fs_size; - __fs32 fs_dsize; - __fs32 fs_ncg; - __fs32 fs_bsize; - __fs32 fs_fsize; - __fs32 fs_frag; - __fs32 fs_minfree; - __fs32 fs_rotdelay; - __fs32 fs_rps; - __fs32 fs_bmask; - __fs32 fs_fmask; - __fs32 fs_bshift; - __fs32 fs_fshift; - __fs32 fs_maxcontig; - __fs32 fs_maxbpg; - __fs32 fs_fragshift; - __fs32 fs_fsbtodb; - __fs32 fs_sbsize; - __fs32 fs_csmask; - __fs32 fs_csshift; - __fs32 fs_nindir; - __fs32 fs_inopb; - __fs32 fs_nspf; - __fs32 fs_optim; - union { - struct { - __fs32 fs_npsect; - } fs_sun; - struct { - __fs32 fs_state; - } fs_sunx86; - } fs_u1; - __fs32 fs_interleave; - __fs32 fs_trackskew; - __fs32 fs_id[2]; - __fs32 fs_csaddr; - __fs32 fs_cssize; - __fs32 fs_cgsize; - __fs32 fs_ntrak; - __fs32 fs_nsect; - __fs32 fs_spc; - __fs32 fs_ncyl; - __fs32 fs_cpg; - __fs32 fs_ipg; - __fs32 fs_fpg; - struct ufs_csum fs_cstotal; - __s8 fs_fmod; - __s8 fs_clean; - __s8 fs_ronly; - __s8 fs_flags; - __s8 fs_fsmnt[UFS_MAXMNTLEN - 212]; - -}; - -struct ufs_super_block_second { - union { - struct { - __s8 fs_fsmnt[212]; - __fs32 fs_cgrotor; - __fs32 fs_csp[UFS_MAXCSBUFS]; - __fs32 fs_maxcluster; - __fs32 fs_cpc; - __fs16 fs_opostbl[82]; - } fs_u1; - struct { - __s8 fs_fsmnt[UFS2_MAXMNTLEN - UFS_MAXMNTLEN + 212]; - __u8 fs_volname[UFS2_MAXVOLLEN]; - __fs64 fs_swuid; - __fs32 fs_pad; - __fs32 fs_cgrotor; - __fs32 fs_ocsp[UFS2_NOCSPTRS]; - __fs32 fs_contigdirs; - __fs32 fs_csp; - __fs32 fs_maxcluster; - __fs32 fs_active; - __fs32 fs_old_cpc; - __fs32 fs_maxbsize; - __fs64 fs_sparecon64[17]; - __fs64 fs_sblockloc; - __fs64 cs_ndir; - __fs64 cs_nbfree; - } fs_u2; - } fs_un; -}; - -struct ufs_super_block_third { - union { - struct { - __fs16 fs_opostbl[46]; - } fs_u1; - struct { - __fs64 cs_nifree; /* number of free inodes */ - __fs64 cs_nffree; /* number of free frags */ - __fs64 cs_numclusters; /* number of free clusters */ - __fs64 cs_spare[3]; /* future expansion */ - struct ufs_timeval fs_time; /* last time written */ - __fs64 fs_size; /* number of blocks in fs */ - __fs64 fs_dsize; /* number of data blocks in fs */ - __fs64 fs_csaddr; /* blk addr of cyl grp summary area */ - __fs64 fs_pendingblocks;/* blocks in process of being freed */ - __fs32 fs_pendinginodes;/*inodes in process of being freed */ - } __attribute__ ((packed)) fs_u2; - } fs_un1; - union { - struct { - __fs32 fs_sparecon[53];/* reserved for future constants */ - __fs32 fs_reclaim; - __fs32 fs_sparecon2[1]; - __fs32 fs_state; /* file system state time stamp */ - __fs32 fs_qbmask[2]; /* ~usb_bmask */ - __fs32 fs_qfmask[2]; /* ~usb_fmask */ - } fs_sun; - struct { - __fs32 fs_sparecon[53];/* reserved for future constants */ - __fs32 fs_reclaim; - __fs32 fs_sparecon2[1]; - __fs32 fs_npsect; /* # sectors/track including spares */ - __fs32 fs_qbmask[2]; /* ~usb_bmask */ - __fs32 fs_qfmask[2]; /* ~usb_fmask */ - } fs_sunx86; - struct { - __fs32 fs_sparecon[50];/* reserved for future constants */ - __fs32 fs_contigsumsize;/* size of cluster summary array */ - __fs32 fs_maxsymlinklen;/* max length of an internal symlink */ - __fs32 fs_inodefmt; /* format of on-disk inodes */ - __fs32 fs_maxfilesize[2]; /* max representable file size */ - __fs32 fs_qbmask[2]; /* ~usb_bmask */ - __fs32 fs_qfmask[2]; /* ~usb_fmask */ - __fs32 fs_state; /* file system state time stamp */ - } fs_44; - } fs_un2; - __fs32 fs_postblformat; - __fs32 fs_nrpos; - __fs32 fs_postbloff; - __fs32 fs_rotbloff; - __fs32 fs_magic; - __u8 fs_space[1]; -}; - -#endif /* __LINUX_UFS_FS_H */ diff --git a/include/linux/utsname.h b/include/linux/utsname.h index 923db99175f..11232676bff 100644 --- a/include/linux/utsname.h +++ b/include/linux/utsname.h @@ -35,6 +35,7 @@ struct new_utsname { #include <linux/sched.h> #include <linux/kref.h> #include <linux/nsproxy.h> +#include <linux/err.h> #include <asm/atomic.h> struct uts_namespace { @@ -43,6 +44,7 @@ struct uts_namespace { }; extern struct uts_namespace init_uts_ns; +#ifdef CONFIG_UTS_NS static inline void get_uts_ns(struct uts_namespace *ns) { kref_get(&ns->kref); @@ -56,6 +58,25 @@ static inline void put_uts_ns(struct uts_namespace *ns) { kref_put(&ns->kref, free_uts_ns); } +#else +static inline void get_uts_ns(struct uts_namespace *ns) +{ +} + +static inline void put_uts_ns(struct uts_namespace *ns) +{ +} + +static inline struct uts_namespace *copy_utsname(unsigned long flags, + struct uts_namespace *ns) +{ + if (flags & CLONE_NEWUTS) + return ERR_PTR(-EINVAL); + + return ns; +} +#endif + static inline struct new_utsname *utsname(void) { return ¤t->nsproxy->uts_ns->name; diff --git a/include/net/ip6_fib.h b/include/net/ip6_fib.h index d8d85b13364..953d6040ff5 100644 --- a/include/net/ip6_fib.h +++ b/include/net/ip6_fib.h @@ -150,19 +150,6 @@ struct rt6_statistics { * */ -#define RTPRI_FIREWALL 8 /* Firewall control information */ -#define RTPRI_FLOW 16 /* Flow based forwarding rules */ -#define RTPRI_KERN_CTL 32 /* Kernel control routes */ - -#define RTPRI_USER_MIN 256 /* Mimimum user priority */ -#define RTPRI_USER_MAX 1024 /* Maximum user priority */ - -#define RTPRI_KERN_DFLT 4096 /* Kernel default routes */ - -#define MAX_FLOW_BACKTRACE 32 - - -typedef void (*f_pnode)(struct fib6_node *fn, void *); struct fib6_table { struct hlist_node tb6_hlist; diff --git a/include/net/ip6_route.h b/include/net/ip6_route.h index faac0eee1ef..f99e4f0f568 100644 --- a/include/net/ip6_route.h +++ b/include/net/ip6_route.h @@ -1,11 +1,9 @@ #ifndef _NET_IP6_ROUTE_H #define _NET_IP6_ROUTE_H -#define IP6_RT_PRIO_FW 16 #define IP6_RT_PRIO_USER 1024 #define IP6_RT_PRIO_ADDRCONF 256 #define IP6_RT_PRIO_KERN 512 -#define IP6_RT_FLOW_MASK 0x00ff struct route_info { __u8 type; diff --git a/include/net/netfilter/nf_conntrack_extend.h b/include/net/netfilter/nf_conntrack_extend.h index 73b5711faf3..49aac6323fb 100644 --- a/include/net/netfilter/nf_conntrack_extend.h +++ b/include/net/netfilter/nf_conntrack_extend.h @@ -67,7 +67,7 @@ struct nf_ct_ext_type void (*destroy)(struct nf_conn *ct); /* Called when realloacted (can be NULL). Contents has already been moved. */ - void (*move)(struct nf_conn *ct, void *old); + void (*move)(void *new, void *old); enum nf_ct_ext_id id; diff --git a/include/net/tipc/tipc_msg.h b/include/net/tipc/tipc_msg.h index fb42eb7a86a..2e159a812f8 100644 --- a/include/net/tipc/tipc_msg.h +++ b/include/net/tipc/tipc_msg.h @@ -130,11 +130,6 @@ static inline u32 msg_type(struct tipc_msg *m) return msg_bits(m, 1, 29, 0x7); } -static inline u32 msg_direct(struct tipc_msg *m) -{ - return (msg_type(m) == TIPC_DIRECT_MSG); -} - static inline u32 msg_named(struct tipc_msg *m) { return (msg_type(m) == TIPC_NAMED_MSG); @@ -207,17 +202,6 @@ static inline u32 msg_nameupper(struct tipc_msg *m) return msg_word(m, 10); } -static inline char *msg_options(struct tipc_msg *m, u32 *len) -{ - u32 pos = msg_bits(m, 1, 16, 0x7); - - if (!pos) - return 0; - pos = (pos * 4) + 28; - *len = msg_hdr_sz(m) - pos; - return (char *)&m->hdr[pos/4]; -} - #endif #endif diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h index cfbd38fe299..701e7b40560 100644 --- a/include/rdma/ib_verbs.h +++ b/include/rdma/ib_verbs.h @@ -95,7 +95,15 @@ enum ib_device_cap_flags { IB_DEVICE_N_NOTIFY_CQ = (1<<14), IB_DEVICE_ZERO_STAG = (1<<15), IB_DEVICE_SEND_W_INV = (1<<16), - IB_DEVICE_MEM_WINDOW = (1<<17) + IB_DEVICE_MEM_WINDOW = (1<<17), + /* + * Devices should set IB_DEVICE_UD_IP_SUM if they support + * insertion of UDP and TCP checksum on outgoing UD IPoIB + * messages and can verify the validity of checksum for + * incoming messages. Setting this flag implies that the + * IPoIB driver may set NETIF_F_IP_CSUM for datagram mode. + */ + IB_DEVICE_UD_IP_CSUM = (1<<18), }; enum ib_atomic_cap { @@ -431,6 +439,7 @@ struct ib_wc { u8 sl; u8 dlid_path_bits; u8 port_num; /* valid only for DR SMPs on switches */ + int csum_ok; }; enum ib_cq_notify_flags { @@ -615,7 +624,8 @@ enum ib_send_flags { IB_SEND_FENCE = 1, IB_SEND_SIGNALED = (1<<1), IB_SEND_SOLICITED = (1<<2), - IB_SEND_INLINE = (1<<3) + IB_SEND_INLINE = (1<<3), + IB_SEND_IP_CSUM = (1<<4) }; struct ib_sge { @@ -890,8 +900,6 @@ struct ib_device { int *pkey_tbl_len; int *gid_tbl_len; - u32 flags; - int num_comp_vectors; struct iw_cm_verbs *iwcm; |