From 8b5f79f9d7ee4f4edb0212886771c977476eb811 Mon Sep 17 00:00:00 2001 From: Vitja Makarov Date: Fri, 29 Feb 2008 12:24:23 +0800 Subject: [Blackfin] arch: initial generic time and clock sources This patch enables Hight-Res Timers and tickless kernel Signed-off-by: Vitja Makarov Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- arch/blackfin/Kconfig | 28 +++++- arch/blackfin/kernel/Makefile | 8 +- arch/blackfin/kernel/process.c | 43 +++++---- arch/blackfin/kernel/time-ts.c | 194 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 253 insertions(+), 20 deletions(-) create mode 100644 arch/blackfin/kernel/time-ts.c diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 2dd1f300a5c..a3cf9d0a528 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -47,10 +47,6 @@ config GENERIC_IRQ_PROBE bool default y -config GENERIC_TIME - bool - default n - config GENERIC_GPIO bool default y @@ -415,6 +411,30 @@ comment "Kernel Timer/Scheduler" source kernel/Kconfig.hz +config GENERIC_TIME + bool "Generic time" + default y + +config GENERIC_CLOCKEVENTS + bool "Generic clock events" + depends on GENERIC_TIME + default y + +config CYCLES_CLOCKSOURCE + bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)" + depends on EXPERIMENTAL + depends on GENERIC_CLOCKEVENTS + depends on !BFIN_SCRATCH_REG_CYCLES + default n + help + If you say Y here, you will enable support for using the 'cycles' + registers as a clock source. Doing so means you will be unable to + safely write to the 'cycles' register during runtime. You will + still be able to read it (such as for performance monitoring), but + writing the registers will most likely crash the kernel. + +source kernel/time/Kconfig + comment "Memory Setup" config MEM_SIZE diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile index 318b9b692a4..6140cd69c78 100644 --- a/arch/blackfin/kernel/Makefile +++ b/arch/blackfin/kernel/Makefile @@ -6,9 +6,15 @@ extra-y := init_task.o vmlinux.lds obj-y := \ entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ - sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o \ + sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \ fixed_code.o reboot.o bfin_gpio.o +ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y) + obj-y += time-ts.o +else + obj-y += time.o +endif + obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_BFIN_DMA_5XX) += bfin_dma_5xx.o diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index 6b8459c6616..6dedb2da8b6 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -32,6 +32,8 @@ #include #include #include +#include +#include #include #include @@ -69,33 +71,44 @@ EXPORT_SYMBOL(pm_power_off); * The idle loop on BFIN */ #ifdef CONFIG_IDLE_L1 -void default_idle(void)__attribute__((l1_text)); +static void default_idle(void)__attribute__((l1_text)); void cpu_idle(void)__attribute__((l1_text)); #endif -void default_idle(void) +/* + * This is our default idle handler. We need to disable + * interrupts here to ensure we don't miss a wakeup call. + */ +static void default_idle(void) { - while (!need_resched()) { - local_irq_disable(); - if (likely(!need_resched())) - idle_with_irq_disabled(); - local_irq_enable(); - } -} + local_irq_disable(); + if (!need_resched()) + idle_with_irq_disabled(); -void (*idle)(void) = default_idle; + local_irq_enable(); +} /* - * The idle thread. There's no useful work to be - * done, so just try to conserve power and have a - * low exit latency (ie sit in a loop waiting for - * somebody to say that they'd like to reschedule) + * The idle thread. We try to conserve power, while trying to keep + * overall latency low. The architecture specific idle is passed + * a value to indicate the level of "idleness" of the system. */ void cpu_idle(void) { /* endless idle loop with no priority at all */ while (1) { - idle(); + void (*idle)(void) = pm_idle; + +#ifdef CONFIG_HOTPLUG_CPU + if (cpu_is_offline(smp_processor_id())) + cpu_die(); +#endif + if (!idle) + idle = default_idle; + tick_nohz_stop_sched_tick(); + while (!need_resched()) + idle(); + tick_nohz_restart_sched_tick(); preempt_enable_no_resched(); schedule(); preempt_disable(); diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c new file mode 100644 index 00000000000..3aad6d71072 --- /dev/null +++ b/arch/blackfin/kernel/time-ts.c @@ -0,0 +1,194 @@ +/* + * linux/arch/kernel/time-ts.c + * + * Based on arm clockevents implementation and old bfin time tick. + * + * Copyright(C) 2008, GeoTechnologies, Vitja Makarov + * + * This code is licenced under the GPL version 2. For details see + * kernel-base/COPYING. + */ +#include +#include +#include +#include +#include +#include +#include + +#include + +#ifdef CONFIG_CYCLES_CLOCKSOURCE + +static unsigned long cyc2ns_scale; +#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ + +static inline void set_cyc2ns_scale(unsigned long cpu_khz) +{ + cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR) / cpu_khz; +} + +static inline unsigned long long cycles_2_ns(cycle_t cyc) +{ + return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR; +} + +static cycle_t read_cycles(void) +{ + unsigned long tmp, tmp2; + asm("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2)); + return tmp | ((cycle_t)tmp2 << 32); +} + +unsigned long long sched_clock(void) +{ + return cycles_2_ns(read_cycles()); +} + +static struct clocksource clocksource_bfin = { + .name = "bfin_cycles", + .rating = 350, + .read = read_cycles, + .mask = CLOCKSOURCE_MASK(64), + .shift = 22, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int __init bfin_clocksource_init(void) +{ + set_cyc2ns_scale(get_cclk() / 1000); + + clocksource_bfin.mult = clocksource_hz2mult(get_cclk(), clocksource_bfin.shift); + + if (clocksource_register(&clocksource_bfin)) + panic("failed to register clocksource"); + + return 0; +} + +#else +# define bfin_clocksource_init() +#endif + +static int bfin_timer_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + bfin_write_TCOUNT(cycles); + CSYNC(); + return 0; +} + +static void bfin_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: { + unsigned long tcount = ((get_cclk() / (HZ * 1)) - 1); + bfin_write_TCNTL(TMPWR); + CSYNC(); + bfin_write_TPERIOD(tcount); + bfin_write_TCOUNT(tcount); + bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD); + CSYNC(); + break; + } + case CLOCK_EVT_MODE_ONESHOT: + bfin_write_TCOUNT(0); + bfin_write_TCNTL(TMPWR | TMREN); + CSYNC(); + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + bfin_write_TCNTL(0); + CSYNC(); + break; + case CLOCK_EVT_MODE_RESUME: + break; + } +} + +static void __init bfin_timer_init(void) +{ + /* power up the timer, but don't enable it just yet */ + bfin_write_TCNTL(TMPWR); + CSYNC(); + + /* + * the TSCALE prescaler counter. + */ + bfin_write_TSCALE(0); + bfin_write_TPERIOD(0); + bfin_write_TCOUNT(0); + + /* now enable the timer */ + CSYNC(); +} + +/* + * timer_interrupt() needs to keep up the real-time clock, + * as well as call the "do_timer()" routine every clocktick + */ +#ifdef CONFIG_CORE_TIMER_IRQ_L1 +__attribute__((l1_text)) +#endif +irqreturn_t timer_interrupt(int irq, void *dev_id); + +static struct clock_event_device clockevent_bfin = { + .name = "bfin_core_timer", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .cpumask = CPU_MASK_CPU0, + .set_next_event = bfin_timer_set_next_event, + .set_mode = bfin_timer_set_mode, +}; + +static struct irqaction bfin_timer_irq = { + .name = "Blackfin Core Timer", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = timer_interrupt, + .dev_id = &clockevent_bfin, +}; + +irqreturn_t timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + evt->event_handler(evt); + return IRQ_HANDLED; +} + +static int __init bfin_clockevent_init(void) +{ + setup_irq(IRQ_CORETMR, &bfin_timer_irq); + bfin_timer_init(); + + clockevent_bfin.mult = div_sc(get_cclk(), NSEC_PER_SEC, clockevent_bfin.shift); + clockevent_bfin.max_delta_ns = clockevent_delta2ns(-1, &clockevent_bfin); + clockevent_bfin.min_delta_ns = clockevent_delta2ns(100, &clockevent_bfin); + clockevents_register_device(&clockevent_bfin); + + return 0; +} + +void __init time_init(void) +{ + time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */ + +#ifdef CONFIG_RTC_DRV_BFIN + /* [#2663] hack to filter junk RTC values that would cause + * userspace to have to deal with time values greater than + * 2^31 seconds (which uClibc cannot cope with yet) + */ + if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) { + printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n"); + bfin_write_RTC_STAT(0); + } +#endif + + /* Initialize xtime. From now on, xtime is updated with timer interrupts */ + xtime.tv_sec = secs_since_1970; + xtime.tv_nsec = 0; + set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec); + + bfin_clocksource_init(); + bfin_clockevent_init(); +} -- cgit v1.2.3 From b4e2d18f73e16846acb91993da1769e9fd23462f Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 29 Feb 2008 12:14:25 +0800 Subject: [Blackfin] arch: add board bluetechnix kernel defconfigs to kernel Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/configs/CM-BF533_defconfig | 912 +++++++++++++++++++++++++++ arch/blackfin/configs/CM-BF537E_defconfig | 940 ++++++++++++++++++++++++++++ arch/blackfin/configs/CM-BF537U_defconfig | 940 ++++++++++++++++++++++++++++ arch/blackfin/configs/CM-BF561_defconfig | 986 ++++++++++++++++++++++++++++++ 4 files changed, 3778 insertions(+) create mode 100644 arch/blackfin/configs/CM-BF533_defconfig create mode 100644 arch/blackfin/configs/CM-BF537E_defconfig create mode 100644 arch/blackfin/configs/CM-BF537U_defconfig create mode 100644 arch/blackfin/configs/CM-BF561_defconfig diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig new file mode 100644 index 00000000000..1babdd92080 --- /dev/null +++ b/arch/blackfin/configs/CM-BF533_defconfig @@ -0,0 +1,912 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.16 +# +# CONFIG_MMU is not set +# CONFIG_FPU is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +CONFIG_BLACKFIN=y +CONFIG_ZONE_DMA=y +CONFIG_SEMAPHORE_SLEEPERS=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_GPIO=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_UID16 is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# Blackfin Processor Options +# + +# +# Processor and Board Settings +# +# CONFIG_BF522 is not set +# CONFIG_BF523 is not set +# CONFIG_BF524 is not set +# CONFIG_BF525 is not set +# CONFIG_BF526 is not set +# CONFIG_BF527 is not set +# CONFIG_BF531 is not set +# CONFIG_BF532 is not set +CONFIG_BF533=y +# CONFIG_BF534 is not set +# CONFIG_BF536 is not set +# CONFIG_BF537 is not set +# CONFIG_BF542 is not set +# CONFIG_BF544 is not set +# CONFIG_BF547 is not set +# CONFIG_BF548 is not set +# CONFIG_BF549 is not set +# CONFIG_BF561 is not set +# CONFIG_BF_REV_0_0 is not set +# CONFIG_BF_REV_0_1 is not set +# CONFIG_BF_REV_0_2 is not set +CONFIG_BF_REV_0_3=y +# CONFIG_BF_REV_0_4 is not set +# CONFIG_BF_REV_0_5 is not set +# CONFIG_BF_REV_ANY is not set +# CONFIG_BF_REV_NONE is not set +CONFIG_BF53x=y +CONFIG_BFIN_SINGLE_CORE=y +CONFIG_MEM_MT48LC16M16A2TG_75=y +# CONFIG_BFIN533_EZKIT is not set +# CONFIG_BFIN533_STAMP is not set +CONFIG_BFIN533_BLUETECHNIX_CM=y +# CONFIG_H8606_HVSISTEMAS is not set +# CONFIG_GENERIC_BF533_BOARD is not set + +# +# BF533/2/1 Specific Configuration +# + +# +# Interrupt Priority Assignment +# + +# +# Priority +# +CONFIG_UART_ERROR=7 +CONFIG_SPORT0_ERROR=7 +CONFIG_SPI_ERROR=7 +CONFIG_SPORT1_ERROR=7 +CONFIG_PPI_ERROR=7 +CONFIG_DMA_ERROR=7 +CONFIG_PLLWAKE_ERROR=7 +CONFIG_RTC_ERROR=8 +CONFIG_DMA0_PPI=8 +CONFIG_DMA1_SPORT0RX=9 +CONFIG_DMA2_SPORT0TX=9 +CONFIG_DMA3_SPORT1RX=9 +CONFIG_DMA4_SPORT1TX=9 +CONFIG_DMA5_SPI=10 +CONFIG_DMA6_UARTRX=10 +CONFIG_DMA7_UARTTX=10 +CONFIG_TIMER0=11 +CONFIG_TIMER1=11 +CONFIG_TIMER2=11 +CONFIG_PFA=12 +CONFIG_PFB=12 +CONFIG_MEMDMA0=13 +CONFIG_MEMDMA1=13 +CONFIG_WDTIMER=13 + +# +# Board customizations +# +# CONFIG_CMDLINE_BOOL is not set + +# +# Clock/PLL Setup +# +CONFIG_CLKIN_HZ=25000000 +# CONFIG_BFIN_KERNEL_CLOCK is not set +CONFIG_MAX_VCO_HZ=750000000 +CONFIG_MIN_VCO_HZ=50000000 +CONFIG_MAX_SCLK_HZ=133333333 +CONFIG_MIN_SCLK_HZ=27000000 + +# +# Kernel Timer/Scheduler +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 + +# +# Memory Setup +# +CONFIG_MEM_SIZE=32 +CONFIG_MEM_ADD_WIDTH=9 +CONFIG_BOOT_LOAD=0x1000 +CONFIG_BFIN_SCRATCH_REG_RETN=y +# CONFIG_BFIN_SCRATCH_REG_RETE is not set +# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set + +# +# Blackfin Kernel Optimizations +# + +# +# Memory Optimizations +# +CONFIG_I_ENTRY_L1=y +CONFIG_EXCPT_IRQ_SYSC_L1=y +CONFIG_DO_IRQ_L1=y +CONFIG_CORE_TIMER_IRQ_L1=y +CONFIG_IDLE_L1=y +CONFIG_SCHEDULE_L1=y +CONFIG_ARITHMETIC_OPS_L1=y +CONFIG_ACCESS_OK_L1=y +CONFIG_MEMSET_L1=y +CONFIG_MEMCPY_L1=y +CONFIG_SYS_BFIN_SPINLOCK_L1=y +CONFIG_IP_CHECKSUM_L1=y +CONFIG_CACHELINE_ALIGNED_L1=y +CONFIG_SYSCALL_TAB_L1=y +CONFIG_CPLB_SWITCH_TAB_L1=y +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LARGE_ALLOCS=y +# CONFIG_BFIN_GPTIMERS is not set +CONFIG_BFIN_DMA_5XX=y +# CONFIG_DMA_UNCACHED_2M is not set +CONFIG_DMA_UNCACHED_1M=y +# CONFIG_DMA_UNCACHED_NONE is not set + +# +# Cache Support +# +CONFIG_BFIN_ICACHE=y +CONFIG_BFIN_DCACHE=y +# CONFIG_BFIN_DCACHE_BANKA is not set +# CONFIG_BFIN_ICACHE_LOCK is not set +CONFIG_BFIN_WB=y +# CONFIG_BFIN_WT is not set +CONFIG_L1_MAX_PIECE=16 +# CONFIG_MPU is not set + +# +# Asynchonous Memory Configuration +# + +# +# EBIU_AMGCTL Global Control +# +CONFIG_C_AMCKEN=y +CONFIG_C_CDPRIO=y +# CONFIG_C_AMBEN is not set +# CONFIG_C_AMBEN_B0 is not set +# CONFIG_C_AMBEN_B0_B1 is not set +# CONFIG_C_AMBEN_B0_B1_B2 is not set +CONFIG_C_AMBEN_ALL=y + +# +# EBIU_AMBCTL Control +# +CONFIG_BANK_0=0x7BB0 +CONFIG_BANK_1=0x7BB0 +CONFIG_BANK_2=0x7BB0 +CONFIG_BANK_3=0xFFC3 + +# +# Bus options (PCI, PCMCIA, EISA, MCA, ISA) +# +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# + +# +# Executable file formats +# +CONFIG_BINFMT_ELF_FDPIC=y +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_BINFMT_SHARED_FLAT=y +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +# CONFIG_PM_WAKEUP_BY_GPIO is not set + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETLABEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_UCLINUX=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# Misc devices +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_SMC91X=y +# CONFIG_SMSC911X is not set +# CONFIG_DM9000 is not set +CONFIG_NETDEV_1000=y +# CONFIG_AX88180 is not set +CONFIG_NETDEV_10000=y + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PFLAGS is not set +# CONFIG_BF5xx_PPIFCD is not set +# CONFIG_BFIN_SIMPLE_TIMER is not set +# CONFIG_BF5xx_PPI is not set +CONFIG_BFIN_SPORT=y +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_BFIN=y +CONFIG_SERIAL_BFIN_CONSOLE=y +CONFIG_SERIAL_BFIN_DMA=y +# CONFIG_SERIAL_BFIN_PIO is not set +CONFIG_SERIAL_BFIN_UART0=y +# CONFIG_BFIN_UART0_CTSRTS is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_BFIN_SPORT is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# CAN, the car bus and industrial fieldbus +# +# CONFIG_CAN4LINUX is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set + +# +# Enable Host or Gadget support to see Inventra options +# + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# InfiniBand support +# + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock +# +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# PBX support +# +# CONFIG_PBX is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MMRS is not set +CONFIG_DEBUG_HUNT_FOR_ZERO=y +CONFIG_DEBUG_BFIN_HWTRACE_ON=y +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y +# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set +# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 +# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set +# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set +# CONFIG_EARLY_PRINTK is not set +CONFIG_CPLB_INFO=y +CONFIG_ACCESS_CHECK=y + +# +# Security options +# +# CONFIG_KEYS is not set +CONFIG_SECURITY=y +# CONFIG_SECURITY_NETWORK is not set +CONFIG_SECURITY_CAPABILITIES=y + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig new file mode 100644 index 00000000000..1befb66e4ee --- /dev/null +++ b/arch/blackfin/configs/CM-BF537E_defconfig @@ -0,0 +1,940 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.16 +# +# CONFIG_MMU is not set +# CONFIG_FPU is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +CONFIG_BLACKFIN=y +CONFIG_ZONE_DMA=y +CONFIG_SEMAPHORE_SLEEPERS=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_GPIO=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_UID16 is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# Blackfin Processor Options +# + +# +# Processor and Board Settings +# +# CONFIG_BF522 is not set +# CONFIG_BF523 is not set +# CONFIG_BF524 is not set +# CONFIG_BF525 is not set +# CONFIG_BF526 is not set +# CONFIG_BF527 is not set +# CONFIG_BF531 is not set +# CONFIG_BF532 is not set +# CONFIG_BF533 is not set +# CONFIG_BF534 is not set +# CONFIG_BF536 is not set +CONFIG_BF537=y +# CONFIG_BF542 is not set +# CONFIG_BF544 is not set +# CONFIG_BF547 is not set +# CONFIG_BF548 is not set +# CONFIG_BF549 is not set +# CONFIG_BF561 is not set +# CONFIG_BF_REV_0_0 is not set +# CONFIG_BF_REV_0_1 is not set +CONFIG_BF_REV_0_2=y +# CONFIG_BF_REV_0_3 is not set +# CONFIG_BF_REV_0_4 is not set +# CONFIG_BF_REV_0_5 is not set +# CONFIG_BF_REV_ANY is not set +# CONFIG_BF_REV_NONE is not set +CONFIG_BF53x=y +CONFIG_BFIN_SINGLE_CORE=y +CONFIG_MEM_MT48LC16M16A2TG_75=y +CONFIG_IRQ_PLL_WAKEUP=7 +CONFIG_IRQ_RTC=8 +CONFIG_IRQ_PPI=8 +CONFIG_IRQ_SPORT0_RX=9 +CONFIG_IRQ_SPORT0_TX=9 +CONFIG_IRQ_SPORT1_RX=9 +CONFIG_IRQ_SPORT1_TX=9 +CONFIG_IRQ_TWI=10 +CONFIG_IRQ_SPI=10 +CONFIG_IRQ_UART0_RX=10 +CONFIG_IRQ_UART0_TX=10 +CONFIG_IRQ_UART1_RX=10 +CONFIG_IRQ_UART1_TX=10 +CONFIG_IRQ_MAC_RX=11 +CONFIG_IRQ_MAC_TX=11 +CONFIG_IRQ_TMR0=12 +CONFIG_IRQ_TMR1=12 +CONFIG_IRQ_TMR2=12 +CONFIG_IRQ_TMR3=12 +CONFIG_IRQ_TMR4=12 +CONFIG_IRQ_TMR5=12 +CONFIG_IRQ_TMR6=12 +CONFIG_IRQ_TMR7=12 +CONFIG_IRQ_PORTG_INTB=12 +CONFIG_IRQ_MEM_DMA0=13 +CONFIG_IRQ_MEM_DMA1=13 +CONFIG_IRQ_WATCH=13 +# CONFIG_BFIN537_STAMP is not set +CONFIG_BFIN537_BLUETECHNIX_CM=y +# CONFIG_PNAV10 is not set +# CONFIG_CAMSIG_MINOTAUR is not set +# CONFIG_GENERIC_BF537_BOARD is not set + +# +# BF537 Specific Configuration +# + +# +# Interrupt Priority Assignment +# + +# +# Priority +# +CONFIG_IRQ_DMA_ERROR=7 +CONFIG_IRQ_ERROR=7 +CONFIG_IRQ_CAN_RX=11 +CONFIG_IRQ_CAN_TX=11 +CONFIG_IRQ_PROG_INTA=12 + +# +# Board customizations +# +# CONFIG_CMDLINE_BOOL is not set + +# +# Clock/PLL Setup +# +CONFIG_CLKIN_HZ=25000000 +# CONFIG_BFIN_KERNEL_CLOCK is not set +CONFIG_MAX_VCO_HZ=600000000 +CONFIG_MIN_VCO_HZ=50000000 +CONFIG_MAX_SCLK_HZ=133333333 +CONFIG_MIN_SCLK_HZ=27000000 + +# +# Kernel Timer/Scheduler +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 + +# +# Memory Setup +# +CONFIG_MEM_SIZE=32 +CONFIG_MEM_ADD_WIDTH=9 +CONFIG_BOOT_LOAD=0x1000 +CONFIG_BFIN_SCRATCH_REG_RETN=y +# CONFIG_BFIN_SCRATCH_REG_RETE is not set +# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set + +# +# Blackfin Kernel Optimizations +# + +# +# Memory Optimizations +# +CONFIG_I_ENTRY_L1=y +CONFIG_EXCPT_IRQ_SYSC_L1=y +CONFIG_DO_IRQ_L1=y +CONFIG_CORE_TIMER_IRQ_L1=y +CONFIG_IDLE_L1=y +CONFIG_SCHEDULE_L1=y +CONFIG_ARITHMETIC_OPS_L1=y +CONFIG_ACCESS_OK_L1=y +CONFIG_MEMSET_L1=y +CONFIG_MEMCPY_L1=y +CONFIG_SYS_BFIN_SPINLOCK_L1=y +CONFIG_IP_CHECKSUM_L1=y +CONFIG_CACHELINE_ALIGNED_L1=y +CONFIG_SYSCALL_TAB_L1=y +CONFIG_CPLB_SWITCH_TAB_L1=y +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LARGE_ALLOCS=y +# CONFIG_BFIN_GPTIMERS is not set +CONFIG_BFIN_DMA_5XX=y +# CONFIG_DMA_UNCACHED_2M is not set +CONFIG_DMA_UNCACHED_1M=y +# CONFIG_DMA_UNCACHED_NONE is not set + +# +# Cache Support +# +CONFIG_BFIN_ICACHE=y +CONFIG_BFIN_DCACHE=y +# CONFIG_BFIN_DCACHE_BANKA is not set +# CONFIG_BFIN_ICACHE_LOCK is not set +CONFIG_BFIN_WB=y +# CONFIG_BFIN_WT is not set +CONFIG_L1_MAX_PIECE=16 +# CONFIG_MPU is not set + +# +# Asynchonous Memory Configuration +# + +# +# EBIU_AMGCTL Global Control +# +CONFIG_C_AMCKEN=y +CONFIG_C_CDPRIO=y +# CONFIG_C_AMBEN is not set +# CONFIG_C_AMBEN_B0 is not set +# CONFIG_C_AMBEN_B0_B1 is not set +# CONFIG_C_AMBEN_B0_B1_B2 is not set +CONFIG_C_AMBEN_ALL=y + +# +# EBIU_AMBCTL Control +# +CONFIG_BANK_0=0x7BB0 +CONFIG_BANK_1=0x7BB0 +CONFIG_BANK_2=0x7BB0 +CONFIG_BANK_3=0xFFC3 + +# +# Bus options (PCI, PCMCIA, EISA, MCA, ISA) +# +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# + +# +# Executable file formats +# +CONFIG_BINFMT_ELF_FDPIC=y +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_BINFMT_SHARED_FLAT=y +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +# CONFIG_PM_WAKEUP_BY_GPIO is not set + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETLABEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_UCLINUX=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# Misc devices +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_FIXED_PHY is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_SMC91X is not set +CONFIG_BFIN_MAC=y +CONFIG_BFIN_MAC_USE_L1=y +CONFIG_BFIN_TX_DESC_NUM=10 +CONFIG_BFIN_RX_DESC_NUM=20 +# CONFIG_BFIN_MAC_RMII is not set +# CONFIG_SMSC911X is not set +# CONFIG_DM9000 is not set +CONFIG_NETDEV_1000=y +# CONFIG_AX88180 is not set +CONFIG_NETDEV_10000=y + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PFLAGS is not set +# CONFIG_BF5xx_PPIFCD is not set +# CONFIG_BFIN_SIMPLE_TIMER is not set +# CONFIG_BF5xx_PPI is not set +CONFIG_BFIN_SPORT=y +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_BFIN=y +CONFIG_SERIAL_BFIN_CONSOLE=y +CONFIG_SERIAL_BFIN_DMA=y +# CONFIG_SERIAL_BFIN_PIO is not set +CONFIG_SERIAL_BFIN_UART0=y +# CONFIG_BFIN_UART0_CTSRTS is not set +CONFIG_SERIAL_BFIN_UART1=y +# CONFIG_BFIN_UART1_CTSRTS is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_BFIN_SPORT is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# CAN, the car bus and industrial fieldbus +# +# CONFIG_CAN4LINUX is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set + +# +# Enable Host or Gadget support to see Inventra options +# + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# InfiniBand support +# + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock +# +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# PBX support +# +# CONFIG_PBX is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MMRS is not set +# CONFIG_DEBUG_HUNT_FOR_ZERO is not set +CONFIG_DEBUG_BFIN_HWTRACE_ON=y +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y +# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set +# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 +# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set +# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set +# CONFIG_EARLY_PRINTK is not set +CONFIG_CPLB_INFO=y +CONFIG_ACCESS_CHECK=y + +# +# Security options +# +# CONFIG_KEYS is not set +CONFIG_SECURITY=y +# CONFIG_SECURITY_NETWORK is not set +CONFIG_SECURITY_CAPABILITIES=y + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig new file mode 100644 index 00000000000..37108e85af0 --- /dev/null +++ b/arch/blackfin/configs/CM-BF537U_defconfig @@ -0,0 +1,940 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.16 +# +# CONFIG_MMU is not set +# CONFIG_FPU is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +CONFIG_BLACKFIN=y +CONFIG_ZONE_DMA=y +CONFIG_SEMAPHORE_SLEEPERS=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_GPIO=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_UID16 is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# Blackfin Processor Options +# + +# +# Processor and Board Settings +# +# CONFIG_BF522 is not set +# CONFIG_BF523 is not set +# CONFIG_BF524 is not set +# CONFIG_BF525 is not set +# CONFIG_BF526 is not set +# CONFIG_BF527 is not set +# CONFIG_BF531 is not set +# CONFIG_BF532 is not set +# CONFIG_BF533 is not set +# CONFIG_BF534 is not set +# CONFIG_BF536 is not set +CONFIG_BF537=y +# CONFIG_BF542 is not set +# CONFIG_BF544 is not set +# CONFIG_BF547 is not set +# CONFIG_BF548 is not set +# CONFIG_BF549 is not set +# CONFIG_BF561 is not set +# CONFIG_BF_REV_0_0 is not set +# CONFIG_BF_REV_0_1 is not set +CONFIG_BF_REV_0_2=y +# CONFIG_BF_REV_0_3 is not set +# CONFIG_BF_REV_0_4 is not set +# CONFIG_BF_REV_0_5 is not set +# CONFIG_BF_REV_ANY is not set +# CONFIG_BF_REV_NONE is not set +CONFIG_BF53x=y +CONFIG_BFIN_SINGLE_CORE=y +CONFIG_MEM_MT48LC16M16A2TG_75=y +CONFIG_IRQ_PLL_WAKEUP=7 +CONFIG_IRQ_RTC=8 +CONFIG_IRQ_PPI=8 +CONFIG_IRQ_SPORT0_RX=9 +CONFIG_IRQ_SPORT0_TX=9 +CONFIG_IRQ_SPORT1_RX=9 +CONFIG_IRQ_SPORT1_TX=9 +CONFIG_IRQ_TWI=10 +CONFIG_IRQ_SPI=10 +CONFIG_IRQ_UART0_RX=10 +CONFIG_IRQ_UART0_TX=10 +CONFIG_IRQ_UART1_RX=10 +CONFIG_IRQ_UART1_TX=10 +CONFIG_IRQ_MAC_RX=11 +CONFIG_IRQ_MAC_TX=11 +CONFIG_IRQ_TMR0=12 +CONFIG_IRQ_TMR1=12 +CONFIG_IRQ_TMR2=12 +CONFIG_IRQ_TMR3=12 +CONFIG_IRQ_TMR4=12 +CONFIG_IRQ_TMR5=12 +CONFIG_IRQ_TMR6=12 +CONFIG_IRQ_TMR7=12 +CONFIG_IRQ_PORTG_INTB=12 +CONFIG_IRQ_MEM_DMA0=13 +CONFIG_IRQ_MEM_DMA1=13 +CONFIG_IRQ_WATCH=13 +# CONFIG_BFIN537_STAMP is not set +CONFIG_BFIN537_BLUETECHNIX_CM=y +# CONFIG_PNAV10 is not set +# CONFIG_CAMSIG_MINOTAUR is not set +# CONFIG_GENERIC_BF537_BOARD is not set + +# +# BF537 Specific Configuration +# + +# +# Interrupt Priority Assignment +# + +# +# Priority +# +CONFIG_IRQ_DMA_ERROR=7 +CONFIG_IRQ_ERROR=7 +CONFIG_IRQ_CAN_RX=11 +CONFIG_IRQ_CAN_TX=11 +CONFIG_IRQ_PROG_INTA=12 + +# +# Board customizations +# +# CONFIG_CMDLINE_BOOL is not set + +# +# Clock/PLL Setup +# +CONFIG_CLKIN_HZ=30000000 +# CONFIG_BFIN_KERNEL_CLOCK is not set +CONFIG_MAX_VCO_HZ=600000000 +CONFIG_MIN_VCO_HZ=50000000 +CONFIG_MAX_SCLK_HZ=133333333 +CONFIG_MIN_SCLK_HZ=27000000 + +# +# Kernel Timer/Scheduler +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 + +# +# Memory Setup +# +CONFIG_MEM_SIZE=32 +CONFIG_MEM_ADD_WIDTH=9 +CONFIG_BOOT_LOAD=0x1000 +CONFIG_BFIN_SCRATCH_REG_RETN=y +# CONFIG_BFIN_SCRATCH_REG_RETE is not set +# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set + +# +# Blackfin Kernel Optimizations +# + +# +# Memory Optimizations +# +CONFIG_I_ENTRY_L1=y +CONFIG_EXCPT_IRQ_SYSC_L1=y +CONFIG_DO_IRQ_L1=y +CONFIG_CORE_TIMER_IRQ_L1=y +CONFIG_IDLE_L1=y +CONFIG_SCHEDULE_L1=y +CONFIG_ARITHMETIC_OPS_L1=y +CONFIG_ACCESS_OK_L1=y +CONFIG_MEMSET_L1=y +CONFIG_MEMCPY_L1=y +CONFIG_SYS_BFIN_SPINLOCK_L1=y +CONFIG_IP_CHECKSUM_L1=y +CONFIG_CACHELINE_ALIGNED_L1=y +CONFIG_SYSCALL_TAB_L1=y +CONFIG_CPLB_SWITCH_TAB_L1=y +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LARGE_ALLOCS=y +# CONFIG_BFIN_GPTIMERS is not set +CONFIG_BFIN_DMA_5XX=y +# CONFIG_DMA_UNCACHED_2M is not set +CONFIG_DMA_UNCACHED_1M=y +# CONFIG_DMA_UNCACHED_NONE is not set + +# +# Cache Support +# +CONFIG_BFIN_ICACHE=y +CONFIG_BFIN_DCACHE=y +# CONFIG_BFIN_DCACHE_BANKA is not set +# CONFIG_BFIN_ICACHE_LOCK is not set +CONFIG_BFIN_WB=y +# CONFIG_BFIN_WT is not set +CONFIG_L1_MAX_PIECE=16 +# CONFIG_MPU is not set + +# +# Asynchonous Memory Configuration +# + +# +# EBIU_AMGCTL Global Control +# +CONFIG_C_AMCKEN=y +CONFIG_C_CDPRIO=y +# CONFIG_C_AMBEN is not set +# CONFIG_C_AMBEN_B0 is not set +# CONFIG_C_AMBEN_B0_B1 is not set +# CONFIG_C_AMBEN_B0_B1_B2 is not set +CONFIG_C_AMBEN_ALL=y + +# +# EBIU_AMBCTL Control +# +CONFIG_BANK_0=0x7BB0 +CONFIG_BANK_1=0x7BB0 +CONFIG_BANK_2=0xFFC3 +CONFIG_BANK_3=0xFFC3 + +# +# Bus options (PCI, PCMCIA, EISA, MCA, ISA) +# +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# + +# +# Executable file formats +# +CONFIG_BINFMT_ELF_FDPIC=y +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_BINFMT_SHARED_FLAT=y +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +# CONFIG_PM_WAKEUP_BY_GPIO is not set + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETLABEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_UCLINUX=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# Misc devices +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_SMC91X=y +# CONFIG_BFIN_MAC is not set +# CONFIG_SMSC911X is not set +# CONFIG_DM9000 is not set +CONFIG_NETDEV_1000=y +# CONFIG_AX88180 is not set +CONFIG_NETDEV_10000=y + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PFLAGS is not set +# CONFIG_BF5xx_PPIFCD is not set +# CONFIG_BFIN_SIMPLE_TIMER is not set +# CONFIG_BF5xx_PPI is not set +CONFIG_BFIN_SPORT=y +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_BFIN=y +CONFIG_SERIAL_BFIN_CONSOLE=y +CONFIG_SERIAL_BFIN_DMA=y +# CONFIG_SERIAL_BFIN_PIO is not set +CONFIG_SERIAL_BFIN_UART0=y +# CONFIG_BFIN_UART0_CTSRTS is not set +CONFIG_SERIAL_BFIN_UART1=y +# CONFIG_BFIN_UART1_CTSRTS is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_BFIN_SPORT is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# CAN, the car bus and industrial fieldbus +# +# CONFIG_CAN4LINUX is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +CONFIG_USB_GADGET_NET2272=y +CONFIG_USB_NET2272=y +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# InfiniBand support +# + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock +# +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# PBX support +# +# CONFIG_PBX is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MMRS is not set +# CONFIG_DEBUG_HUNT_FOR_ZERO is not set +CONFIG_DEBUG_BFIN_HWTRACE_ON=y +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y +# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set +# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 +# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set +# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set +# CONFIG_EARLY_PRINTK is not set +CONFIG_CPLB_INFO=y +CONFIG_ACCESS_CHECK=y + +# +# Security options +# +# CONFIG_KEYS is not set +CONFIG_SECURITY=y +# CONFIG_SECURITY_NETWORK is not set +CONFIG_SECURITY_CAPABILITIES=y + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig new file mode 100644 index 00000000000..56b313a2d58 --- /dev/null +++ b/arch/blackfin/configs/CM-BF561_defconfig @@ -0,0 +1,986 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.16 +# +# CONFIG_MMU is not set +# CONFIG_FPU is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +CONFIG_BLACKFIN=y +CONFIG_ZONE_DMA=y +CONFIG_SEMAPHORE_SLEEPERS=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_GPIO=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_UID16 is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# Blackfin Processor Options +# + +# +# Processor and Board Settings +# +# CONFIG_BF522 is not set +# CONFIG_BF523 is not set +# CONFIG_BF524 is not set +# CONFIG_BF525 is not set +# CONFIG_BF526 is not set +# CONFIG_BF527 is not set +# CONFIG_BF531 is not set +# CONFIG_BF532 is not set +# CONFIG_BF533 is not set +# CONFIG_BF534 is not set +# CONFIG_BF536 is not set +# CONFIG_BF537 is not set +# CONFIG_BF542 is not set +# CONFIG_BF544 is not set +# CONFIG_BF547 is not set +# CONFIG_BF548 is not set +# CONFIG_BF549 is not set +CONFIG_BF561=y +# CONFIG_BF_REV_0_0 is not set +# CONFIG_BF_REV_0_1 is not set +# CONFIG_BF_REV_0_2 is not set +CONFIG_BF_REV_0_3=y +# CONFIG_BF_REV_0_4 is not set +# CONFIG_BF_REV_0_5 is not set +# CONFIG_BF_REV_ANY is not set +# CONFIG_BF_REV_NONE is not set +CONFIG_BFIN_DUAL_CORE=y +CONFIG_MEM_MT48LC8M32B2B5_7=y +CONFIG_IRQ_PLL_WAKEUP=7 +CONFIG_IRQ_SPORT0_ERROR=7 +CONFIG_IRQ_SPORT1_ERROR=7 +CONFIG_IRQ_SPI_ERROR=7 +# CONFIG_BFIN561_EZKIT is not set +# CONFIG_BFIN561_TEPLA is not set +CONFIG_BFIN561_BLUETECHNIX_CM=y +# CONFIG_GENERIC_BF561_BOARD is not set + +# +# BF561 Specific Configuration +# + +# +# Core B Support +# + +# +# Core B Support +# +CONFIG_BF561_COREB=y +# CONFIG_BF561_COREB_RESET is not set + +# +# Interrupt Priority Assignment +# + +# +# Priority +# +CONFIG_IRQ_DMA1_ERROR=7 +CONFIG_IRQ_DMA2_ERROR=7 +CONFIG_IRQ_IMDMA_ERROR=7 +CONFIG_IRQ_PPI0_ERROR=7 +CONFIG_IRQ_PPI1_ERROR=7 +CONFIG_IRQ_UART_ERROR=7 +CONFIG_IRQ_RESERVED_ERROR=7 +CONFIG_IRQ_DMA1_0=8 +CONFIG_IRQ_DMA1_1=8 +CONFIG_IRQ_DMA1_2=8 +CONFIG_IRQ_DMA1_3=8 +CONFIG_IRQ_DMA1_4=8 +CONFIG_IRQ_DMA1_5=8 +CONFIG_IRQ_DMA1_6=8 +CONFIG_IRQ_DMA1_7=8 +CONFIG_IRQ_DMA1_8=8 +CONFIG_IRQ_DMA1_9=8 +CONFIG_IRQ_DMA1_10=8 +CONFIG_IRQ_DMA1_11=8 +CONFIG_IRQ_DMA2_0=9 +CONFIG_IRQ_DMA2_1=9 +CONFIG_IRQ_DMA2_2=9 +CONFIG_IRQ_DMA2_3=9 +CONFIG_IRQ_DMA2_4=9 +CONFIG_IRQ_DMA2_5=9 +CONFIG_IRQ_DMA2_6=9 +CONFIG_IRQ_DMA2_7=9 +CONFIG_IRQ_DMA2_8=9 +CONFIG_IRQ_DMA2_9=9 +CONFIG_IRQ_DMA2_10=9 +CONFIG_IRQ_DMA2_11=9 +CONFIG_IRQ_TIMER0=10 +CONFIG_IRQ_TIMER1=10 +CONFIG_IRQ_TIMER2=10 +CONFIG_IRQ_TIMER3=10 +CONFIG_IRQ_TIMER4=10 +CONFIG_IRQ_TIMER5=10 +CONFIG_IRQ_TIMER6=10 +CONFIG_IRQ_TIMER7=10 +CONFIG_IRQ_TIMER8=10 +CONFIG_IRQ_TIMER9=10 +CONFIG_IRQ_TIMER10=10 +CONFIG_IRQ_TIMER11=10 +CONFIG_IRQ_PROG0_INTA=11 +CONFIG_IRQ_PROG0_INTB=11 +CONFIG_IRQ_PROG1_INTA=11 +CONFIG_IRQ_PROG1_INTB=11 +CONFIG_IRQ_PROG2_INTA=11 +CONFIG_IRQ_PROG2_INTB=11 +CONFIG_IRQ_DMA1_WRRD0=8 +CONFIG_IRQ_DMA1_WRRD1=8 +CONFIG_IRQ_DMA2_WRRD0=9 +CONFIG_IRQ_DMA2_WRRD1=9 +CONFIG_IRQ_IMDMA_WRRD0=12 +CONFIG_IRQ_IMDMA_WRRD1=12 +CONFIG_IRQ_WDTIMER=13 + +# +# Board customizations +# +# CONFIG_CMDLINE_BOOL is not set + +# +# Clock/PLL Setup +# +CONFIG_CLKIN_HZ=25000000 +# CONFIG_BFIN_KERNEL_CLOCK is not set +CONFIG_MAX_VCO_HZ=600000000 +CONFIG_MIN_VCO_HZ=50000000 +CONFIG_MAX_SCLK_HZ=133333333 +CONFIG_MIN_SCLK_HZ=27000000 + +# +# Kernel Timer/Scheduler +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 + +# +# Memory Setup +# +CONFIG_MEM_SIZE=32 +CONFIG_MEM_ADD_WIDTH=9 +CONFIG_BOOT_LOAD=0x1000 +CONFIG_BFIN_SCRATCH_REG_RETN=y +# CONFIG_BFIN_SCRATCH_REG_RETE is not set +# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set + +# +# Blackfin Kernel Optimizations +# + +# +# Memory Optimizations +# +CONFIG_I_ENTRY_L1=y +CONFIG_EXCPT_IRQ_SYSC_L1=y +CONFIG_DO_IRQ_L1=y +CONFIG_CORE_TIMER_IRQ_L1=y +CONFIG_IDLE_L1=y +CONFIG_SCHEDULE_L1=y +CONFIG_ARITHMETIC_OPS_L1=y +CONFIG_ACCESS_OK_L1=y +CONFIG_MEMSET_L1=y +CONFIG_MEMCPY_L1=y +CONFIG_SYS_BFIN_SPINLOCK_L1=y +CONFIG_IP_CHECKSUM_L1=y +CONFIG_CACHELINE_ALIGNED_L1=y +CONFIG_SYSCALL_TAB_L1=y +CONFIG_CPLB_SWITCH_TAB_L1=y +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LARGE_ALLOCS=y +# CONFIG_BFIN_GPTIMERS is not set +CONFIG_BFIN_DMA_5XX=y +# CONFIG_DMA_UNCACHED_2M is not set +CONFIG_DMA_UNCACHED_1M=y +# CONFIG_DMA_UNCACHED_NONE is not set + +# +# Cache Support +# +CONFIG_BFIN_ICACHE=y +CONFIG_BFIN_DCACHE=y +# CONFIG_BFIN_DCACHE_BANKA is not set +# CONFIG_BFIN_ICACHE_LOCK is not set +CONFIG_BFIN_WB=y +# CONFIG_BFIN_WT is not set +CONFIG_L1_MAX_PIECE=16 +# CONFIG_MPU is not set + +# +# Asynchonous Memory Configuration +# + +# +# EBIU_AMGCTL Global Control +# +CONFIG_C_AMCKEN=y +CONFIG_C_CDPRIO=y +CONFIG_C_B0PEN=y +CONFIG_C_B1PEN=y +CONFIG_C_B2PEN=y +# CONFIG_C_B3PEN is not set +# CONFIG_C_AMBEN is not set +# CONFIG_C_AMBEN_B0 is not set +# CONFIG_C_AMBEN_B0_B1 is not set +# CONFIG_C_AMBEN_B0_B1_B2 is not set +CONFIG_C_AMBEN_ALL=y + +# +# EBIU_AMBCTL Control +# +CONFIG_BANK_0=0x7BB0 +CONFIG_BANK_1=0x7BB0 +CONFIG_BANK_2=0x7BB0 +CONFIG_BANK_3=0xFFC3 + +# +# Bus options (PCI, PCMCIA, EISA, MCA, ISA) +# +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# + +# +# Executable file formats +# +CONFIG_BINFMT_ELF_FDPIC=y +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_BINFMT_SHARED_FLAT=y +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +# CONFIG_PM_WAKEUP_BY_GPIO is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETLABEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_UCLINUX=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# Misc devices +# +CONFIG_IDE=m +CONFIG_IDE_MAX_HWIFS=4 +CONFIG_BLK_DEV_IDE=m + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=m +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=m +CONFIG_IDE_BFIN=y +CONFIG_BFIN_IDE_ADDRESS_MAPPING_MODE0=y +# CONFIG_BFIN_IDE_ADDRESS_MAPPING_MODE1 is not set +CONFIG_BFIN_IDE_BASE=0x2400C000 +CONFIG_BFIN_IDE_ALT=0x2400D018 +CONFIG_BFIN_IDE_IRQ_PFX=46 +CONFIG_BFIN_IDE_GAP=4 +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +# CONFIG_IDE_ARM is not set +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_SMC91X=y +# CONFIG_SMSC911X is not set +# CONFIG_DM9000 is not set +CONFIG_NETDEV_1000=y +# CONFIG_AX88180 is not set +CONFIG_NETDEV_10000=y + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PFLAGS is not set +# CONFIG_BF5xx_PPIFCD is not set +# CONFIG_BFIN_SIMPLE_TIMER is not set +# CONFIG_BF5xx_PPI is not set +# CONFIG_BFIN_SPORT is not set +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_BFIN=y +CONFIG_SERIAL_BFIN_CONSOLE=y +CONFIG_SERIAL_BFIN_DMA=y +# CONFIG_SERIAL_BFIN_PIO is not set +CONFIG_SERIAL_BFIN_UART0=y +# CONFIG_BFIN_UART0_CTSRTS is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_BFIN_SPORT is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# CAN, the car bus and industrial fieldbus +# +# CONFIG_CAN4LINUX is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set + +# +# Enable Host or Gadget support to see Inventra options +# + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# InfiniBand support +# + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock +# +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# PBX support +# +# CONFIG_PBX is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MMRS is not set +CONFIG_DEBUG_HUNT_FOR_ZERO=y +CONFIG_DEBUG_BFIN_HWTRACE_ON=y +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y +# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set +# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 +# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set +# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set +# CONFIG_EARLY_PRINTK is not set +# CONFIG_DUAL_CORE_TEST_MODULE is not set +CONFIG_CPLB_INFO=y +CONFIG_ACCESS_CHECK=y + +# +# Security options +# +# CONFIG_KEYS is not set +CONFIG_SECURITY=y +# CONFIG_SECURITY_NETWORK is not set +CONFIG_SECURITY_CAPABILITIES=y + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y -- cgit v1.2.3 From 1307a65130963b061fbaca308b228a0f693a4495 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 29 Feb 2008 12:26:41 +0800 Subject: [Blackfin] arch: turn generic time on by default Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/configs/BF527-EZKIT_defconfig | 2 +- arch/blackfin/configs/BF533-EZKIT_defconfig | 2 +- arch/blackfin/configs/BF533-STAMP_defconfig | 2 +- arch/blackfin/configs/BF537-STAMP_defconfig | 2 +- arch/blackfin/configs/BF548-EZKIT_defconfig | 2 +- arch/blackfin/configs/BF561-EZKIT_defconfig | 2 +- arch/blackfin/configs/CM-BF533_defconfig | 2 +- arch/blackfin/configs/CM-BF537E_defconfig | 2 +- arch/blackfin/configs/CM-BF537U_defconfig | 2 +- arch/blackfin/configs/CM-BF561_defconfig | 2 +- arch/blackfin/configs/H8606_defconfig | 2 +- arch/blackfin/configs/PNAV-10_defconfig | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig index ae320dcfede..a50bf5fa99c 100644 --- a/arch/blackfin/configs/BF527-EZKIT_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT_defconfig @@ -13,7 +13,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig index 9621caa60b5..29019961de2 100644 --- a/arch/blackfin/configs/BF533-EZKIT_defconfig +++ b/arch/blackfin/configs/BF533-EZKIT_defconfig @@ -13,7 +13,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig index b51e76ce7f4..080f7ab8c9a 100644 --- a/arch/blackfin/configs/BF533-STAMP_defconfig +++ b/arch/blackfin/configs/BF533-STAMP_defconfig @@ -13,7 +13,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig index d45fa535dad..b9b87497c84 100644 --- a/arch/blackfin/configs/BF537-STAMP_defconfig +++ b/arch/blackfin/configs/BF537-STAMP_defconfig @@ -13,7 +13,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig index c9707f7665a..06c0180b98d 100644 --- a/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/arch/blackfin/configs/BF548-EZKIT_defconfig @@ -13,7 +13,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig index 4d8a6333130..073b32fe973 100644 --- a/arch/blackfin/configs/BF561-EZKIT_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT_defconfig @@ -13,7 +13,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig index 1babdd92080..fdfdee31801 100644 --- a/arch/blackfin/configs/CM-BF533_defconfig +++ b/arch/blackfin/configs/CM-BF533_defconfig @@ -13,7 +13,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig index 1befb66e4ee..36a7244eefc 100644 --- a/arch/blackfin/configs/CM-BF537E_defconfig +++ b/arch/blackfin/configs/CM-BF537E_defconfig @@ -13,7 +13,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig index 37108e85af0..3bb7ed3fd79 100644 --- a/arch/blackfin/configs/CM-BF537U_defconfig +++ b/arch/blackfin/configs/CM-BF537U_defconfig @@ -13,7 +13,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig index 56b313a2d58..7157bf4a1c5 100644 --- a/arch/blackfin/configs/CM-BF561_defconfig +++ b/arch/blackfin/configs/CM-BF561_defconfig @@ -13,7 +13,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig index 18cbb8c3c37..7e648a7a38d 100644 --- a/arch/blackfin/configs/H8606_defconfig +++ b/arch/blackfin/configs/H8606_defconfig @@ -13,7 +13,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig index 25709f504d8..19e8f051ad1 100644 --- a/arch/blackfin/configs/PNAV-10_defconfig +++ b/arch/blackfin/configs/PNAV-10_defconfig @@ -13,7 +13,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -- cgit v1.2.3 From 0ddeeca25ce33686262459e2387f57bd09574e47 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 7 Mar 2008 02:37:41 +0800 Subject: [Blackfin] arch: add missing __user marking to ss_sp member of signalstack and a few userspace system functions Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/process.c | 20 +++++++++++--------- arch/blackfin/kernel/ptrace.c | 7 ++++--- arch/blackfin/kernel/signal.c | 4 ++-- arch/blackfin/kernel/sys_bfin.c | 2 +- arch/blackfin/kernel/traps.c | 2 +- include/asm-blackfin/signal.h | 2 +- 6 files changed, 20 insertions(+), 17 deletions(-) diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index 6dedb2da8b6..fb94cbeafad 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -202,7 +202,7 @@ copy_thread(int nr, unsigned long clone_flags, * sys_execve() executes a new program. */ -asmlinkage int sys_execve(char *name, char **argv, char **envp) +asmlinkage int sys_execve(char __user *name, char __user * __user *argv, char __user * __user *envp) { int error; char *filename; @@ -245,23 +245,25 @@ unsigned long get_wchan(struct task_struct *p) void finish_atomic_sections (struct pt_regs *regs) { + int __user *up0 = (int __user *)®s->p0; + if (regs->pc < ATOMIC_SEQS_START || regs->pc >= ATOMIC_SEQS_END) return; switch (regs->pc) { case ATOMIC_XCHG32 + 2: - put_user(regs->r1, (int *)regs->p0); + put_user(regs->r1, up0); regs->pc += 2; break; case ATOMIC_CAS32 + 2: case ATOMIC_CAS32 + 4: if (regs->r0 == regs->r1) - put_user(regs->r2, (int *)regs->p0); + put_user(regs->r2, up0); regs->pc = ATOMIC_CAS32 + 8; break; case ATOMIC_CAS32 + 6: - put_user(regs->r2, (int *)regs->p0); + put_user(regs->r2, up0); regs->pc += 2; break; @@ -269,7 +271,7 @@ void finish_atomic_sections (struct pt_regs *regs) regs->r0 = regs->r1 + regs->r0; /* fall through */ case ATOMIC_ADD32 + 4: - put_user(regs->r0, (int *)regs->p0); + put_user(regs->r0, up0); regs->pc = ATOMIC_ADD32 + 6; break; @@ -277,7 +279,7 @@ void finish_atomic_sections (struct pt_regs *regs) regs->r0 = regs->r1 - regs->r0; /* fall through */ case ATOMIC_SUB32 + 4: - put_user(regs->r0, (int *)regs->p0); + put_user(regs->r0, up0); regs->pc = ATOMIC_SUB32 + 6; break; @@ -285,7 +287,7 @@ void finish_atomic_sections (struct pt_regs *regs) regs->r0 = regs->r1 | regs->r0; /* fall through */ case ATOMIC_IOR32 + 4: - put_user(regs->r0, (int *)regs->p0); + put_user(regs->r0, up0); regs->pc = ATOMIC_IOR32 + 6; break; @@ -293,7 +295,7 @@ void finish_atomic_sections (struct pt_regs *regs) regs->r0 = regs->r1 & regs->r0; /* fall through */ case ATOMIC_AND32 + 4: - put_user(regs->r0, (int *)regs->p0); + put_user(regs->r0, up0); regs->pc = ATOMIC_AND32 + 6; break; @@ -301,7 +303,7 @@ void finish_atomic_sections (struct pt_regs *regs) regs->r0 = regs->r1 ^ regs->r0; /* fall through */ case ATOMIC_XOR32 + 4: - put_user(regs->r0, (int *)regs->p0); + put_user(regs->r0, up0); regs->pc = ATOMIC_XOR32 + 6; break; } diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c index 85caf9b711a..b4f062c172c 100644 --- a/arch/blackfin/kernel/ptrace.c +++ b/arch/blackfin/kernel/ptrace.c @@ -193,6 +193,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) { int ret; int add = 0; + unsigned long __user *datap = (unsigned long __user *)data; switch (request) { /* when I and D space are separate, these will need to be fixed. */ @@ -229,7 +230,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) pr_debug("ptrace: copied size %d [0x%08lx]\n", copied, tmp); if (copied != sizeof(tmp)) break; - ret = put_user(tmp, (unsigned long *)data); + ret = put_user(tmp, datap); break; } @@ -263,7 +264,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) } else { tmp = get_reg(child, addr); } - ret = put_user(tmp, (unsigned long *)data); + ret = put_user(tmp, datap); break; } @@ -389,7 +390,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) { /* Get all gp regs from the child. */ - ret = ptrace_getregs(child, (void __user *)data); + ret = ptrace_getregs(child, datap); break; } diff --git a/arch/blackfin/kernel/signal.c b/arch/blackfin/kernel/signal.c index 5564c9588aa..71cfcd28b39 100644 --- a/arch/blackfin/kernel/signal.c +++ b/arch/blackfin/kernel/signal.c @@ -55,13 +55,13 @@ struct rt_sigframe { struct ucontext uc; }; -asmlinkage int sys_sigaltstack(const stack_t * uss, stack_t * uoss) +asmlinkage int sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss) { return do_sigaltstack(uss, uoss, rdusp()); } static inline int -rt_restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc, int *pr0) +rt_restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, int *pr0) { unsigned long usp = 0; int err = 0; diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c index abcd14817d0..efb7b25a263 100644 --- a/arch/blackfin/kernel/sys_bfin.c +++ b/arch/blackfin/kernel/sys_bfin.c @@ -49,7 +49,7 @@ * sys_pipe() is the normal C calling standard for creating * a pipe. It's not the way unix traditionally does this, though. */ -asmlinkage int sys_pipe(unsigned long *fildes) +asmlinkage int sys_pipe(unsigned long __user *fildes) { int fd[2]; int error; diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 56a67ab698c..e8e8f735c23 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -506,7 +506,7 @@ asmlinkage void trap_c(struct pt_regs *fp) info.si_signo = sig; info.si_errno = 0; - info.si_addr = (void *)fp->pc; + info.si_addr = (void __user *)fp->pc; force_sig_info(sig, &info, current); trace_buffer_restore(j); diff --git a/include/asm-blackfin/signal.h b/include/asm-blackfin/signal.h index 0250429b736..87951d25145 100644 --- a/include/asm-blackfin/signal.h +++ b/include/asm-blackfin/signal.h @@ -143,7 +143,7 @@ struct sigaction { #endif /* __KERNEL__ */ typedef struct sigaltstack { - void *ss_sp; + void __user *ss_sp; int ss_flags; size_t ss_size; } stack_t; -- cgit v1.2.3 From f692940101bbcef3717f40df9fd3c52f497c8589 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 7 Mar 2008 02:43:48 +0800 Subject: [Blackfin] arch: declare CHECKFLAGS to make sparse output more readable Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/Makefile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile index 75eba2ca788..3cbe16caad4 100644 --- a/arch/blackfin/Makefile +++ b/arch/blackfin/Makefile @@ -72,6 +72,11 @@ rev-$(CONFIG_BF_REV_ANY) := any KBUILD_CFLAGS += -mcpu=$(cpu-y)-$(rev-y) KBUILD_AFLAGS += -mcpu=$(cpu-y)-$(rev-y) +# - we utilize the silicon rev from the toolchain, so move it over to the checkflags +# - the l1_text attribute is Blackfin specific, so fake it out as used to kill warnings +CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }') +CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -Dl1_text=__used__ + head-y := arch/$(ARCH)/mach-$(MACHINE)/head.o arch/$(ARCH)/kernel/init_task.o core-y += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/ arch/$(ARCH)/mach-common/ -- cgit v1.2.3 From 56ce835b608343b22e1e46e5bb913b87c162486e Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 26 Mar 2008 06:00:18 +0800 Subject: [Blackfin] arch: add twi resources to CM_BF537 board as reported by Servaes Joordens Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf537/boards/cm_bf537.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c index f7c1f964f13..b575b23fe69 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c @@ -325,6 +325,28 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static struct resource bfin_twi0_resource[] = { + [0] = { + .start = TWI0_REGBASE, + .end = TWI0_REGBASE, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TWI, + .end = IRQ_TWI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device i2c_bfin_twi_device = { + .name = "i2c-bfin-twi", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_twi0_resource), + .resource = bfin_twi0_resource, +}; +#endif + #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) static struct platform_device bfin_sport0_uart_device = { .name = "bfin-sport-uart", @@ -393,6 +415,10 @@ static struct platform_device *cm_bf537_devices[] __initdata = { &bfin_uart_device, #endif +#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) + &i2c_bfin_twi_device, +#endif + #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) &bfin_sport0_uart_device, &bfin_sport1_uart_device, -- cgit v1.2.3 From 9df7a8f62268a05e3bc8be2b2f8f95c522fd9ccc Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Wed, 26 Mar 2008 06:39:15 +0800 Subject: [Blackfin] arch: remove NOTES from linker script Since r3658 | vapier | 2007-09-12 16:26:11 +0200 (Wed, 12 Sep 2007) | 1 line add more common defines for output sections we've had a new line, NOTES, in our linker script, which causes upstream binutils to complain about "missing phdr". Currently the only other arch that uses NOTES is i386, and the patch which added it also added PHDRS { text PT_LOAD FLAGS(5); /* R_E */ data PT_LOAD FLAGS(7); /* RWE */ note PT_NOTE FLAGS(0); /* ___ */ } and a few other modifications to use ":text" and ":data" to the linker script. It seems that we don't need NOTES at all, so just remove it. Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu --- arch/blackfin/kernel/vmlinux.lds.S | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S index cb01a9de268..7a1200328ac 100644 --- a/arch/blackfin/kernel/vmlinux.lds.S +++ b/arch/blackfin/kernel/vmlinux.lds.S @@ -223,8 +223,6 @@ SECTIONS DWARF_DEBUG - NOTES - /DISCARD/ : { EXIT_TEXT -- cgit v1.2.3 From 2e8d7965e69a4879f9331d35b13ce234a3df4a04 Mon Sep 17 00:00:00 2001 From: Yi Li Date: Wed, 26 Mar 2008 07:08:12 +0800 Subject: [Blackfin] arch: add code to initialize globals declared in linux/bootmem.h: max_pfn, max_low_pfn, min_low_pfn. Signed-off-by: Yi Li Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 52 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 45 insertions(+), 7 deletions(-) diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 2255c289a71..a871d835824 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -547,11 +547,38 @@ static __init void memory_setup(void) ); } +/* + * Find the lowest, highest page frame number we have available + */ +void __init find_min_max_pfn(void) +{ + int i; + + max_pfn = 0; + min_low_pfn = memory_end; + + for (i = 0; i < bfin_memmap.nr_map; i++) { + unsigned long start, end; + /* RAM? */ + if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM) + continue; + start = PFN_UP(bfin_memmap.map[i].addr); + end = PFN_DOWN(bfin_memmap.map[i].addr + + bfin_memmap.map[i].size); + if (start >= end) + continue; + if (end > max_pfn) + max_pfn = end; + if (start < min_low_pfn) + min_low_pfn = start; + } +} + static __init void setup_bootmem_allocator(void) { int bootmap_size; int i; - unsigned long min_pfn, max_pfn; + unsigned long start_pfn, end_pfn; unsigned long curr_pfn, last_pfn, size; /* mark memory between memory_start and memory_end usable */ @@ -561,8 +588,19 @@ static __init void setup_bootmem_allocator(void) sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map); print_memory_map("boot memmap"); - min_pfn = PAGE_OFFSET >> PAGE_SHIFT; - max_pfn = memory_end >> PAGE_SHIFT; + /* intialize globals in linux/bootmem.h */ + find_min_max_pfn(); + /* pfn of the last usable page frame */ + if (max_pfn > memory_end >> PAGE_SHIFT) + max_pfn = memory_end >> PAGE_SHIFT; + /* pfn of last page frame directly mapped by kernel */ + max_low_pfn = max_pfn; + /* pfn of the first usable page frame after kernel image*/ + if (min_low_pfn < memory_start >> PAGE_SHIFT) + min_low_pfn = memory_start >> PAGE_SHIFT; + + start_pfn = PAGE_OFFSET >> PAGE_SHIFT; + end_pfn = memory_end >> PAGE_SHIFT; /* * give all the memory to the bootmap allocator, tell it to put the @@ -570,7 +608,7 @@ static __init void setup_bootmem_allocator(void) */ bootmap_size = init_bootmem_node(NODE_DATA(0), memory_start >> PAGE_SHIFT, /* map goes here */ - min_pfn, max_pfn); + start_pfn, end_pfn); /* register the memmap regions with the bootmem allocator */ for (i = 0; i < bfin_memmap.nr_map; i++) { @@ -583,7 +621,7 @@ static __init void setup_bootmem_allocator(void) * We are rounding up the start address of usable memory: */ curr_pfn = PFN_UP(bfin_memmap.map[i].addr); - if (curr_pfn >= max_pfn) + if (curr_pfn >= end_pfn) continue; /* * ... and at the end of the usable range downwards: @@ -591,8 +629,8 @@ static __init void setup_bootmem_allocator(void) last_pfn = PFN_DOWN(bfin_memmap.map[i].addr + bfin_memmap.map[i].size); - if (last_pfn > max_pfn) - last_pfn = max_pfn; + if (last_pfn > end_pfn) + last_pfn = end_pfn; /* * .. finally, did all the rounding and playing -- cgit v1.2.3 From 793dc27b51b2ffff95b72408e2ef44e0995c185b Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 26 Mar 2008 08:09:12 +0800 Subject: [Blackfin] arch: conditionally enable flash resources since it requests the async memory bank Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf533/boards/stamp.c | 5 +++++ arch/blackfin/mach-bf537/boards/stamp.c | 5 +++++ arch/blackfin/mach-bf548/boards/ezkit.c | 5 +++++ arch/blackfin/mach-bf561/boards/ezkit.c | 5 +++++ 4 files changed, 20 insertions(+) diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index b2ac4816ae6..ecf449b322d 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c @@ -109,6 +109,7 @@ static struct platform_device net2272_bfin_device = { }; #endif +#if defined(CONFIG_MTD_BF5xx) || defined(CONFIG_MTD_BF5xx_MODULE) static struct mtd_partition stamp_partitions[] = { { .name = "Bootloader", @@ -152,6 +153,7 @@ static struct platform_device stamp_flash_device = { .num_resources = ARRAY_SIZE(stamp_flash_resource), .resource = stamp_flash_resource, }; +#endif #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) /* all SPI peripherals info goes here */ @@ -515,7 +517,10 @@ static struct platform_device *stamp_devices[] __initdata = { #endif &bfin_gpios_device, + +#if defined(CONFIG_MTD_BF5xx) || defined(CONFIG_MTD_BF5xx_MODULE) &stamp_flash_device, +#endif }; static int __init stamp_init(void) diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index ea83148993d..09828a0e999 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -353,6 +353,7 @@ static struct platform_device net2272_bfin_device = { }; #endif +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) static struct mtd_partition stamp_partitions[] = { { .name = "Bootloader", @@ -395,6 +396,7 @@ static struct platform_device stamp_flash_device = { .num_resources = 1, .resource = &stamp_flash_resource, }; +#endif #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) /* all SPI peripherals info goes here */ @@ -818,7 +820,10 @@ static struct platform_device *stamp_devices[] __initdata = { #endif &bfin_gpios_device, + +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) &stamp_flash_device, +#endif }; static int __init stamp_init(void) diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 40846aa034c..dc3c0156f37 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -330,6 +330,7 @@ static struct platform_device bf54x_sdh_device = { }; #endif +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) static struct mtd_partition ezkit_partitions[] = { { .name = "Bootloader", @@ -367,6 +368,7 @@ static struct platform_device ezkit_flash_device = { .num_resources = 1, .resource = &ezkit_flash_resource, }; +#endif #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) /* all SPI peripherals info goes here */ @@ -661,7 +663,10 @@ static struct platform_device *ezkit_devices[] __initdata = { #endif &bfin_gpios_device, + +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) &ezkit_flash_device, +#endif }; static int __init ezkit_init(void) diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index d357f648d96..79a55b42e96 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -220,6 +220,7 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) static struct mtd_partition ezkit_partitions[] = { { .name = "Bootloader", @@ -257,6 +258,7 @@ static struct platform_device ezkit_flash_device = { .num_resources = 1, .resource = &ezkit_flash_resource, }; +#endif #ifdef CONFIG_SPI_BFIN #if defined(CONFIG_SND_BLACKFIN_AD1836) \ @@ -460,7 +462,10 @@ static struct platform_device *ezkit_devices[] __initdata = { #endif &bfin_gpios_device, + +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) &ezkit_flash_device, +#endif }; static int __init ezkit_init(void) -- cgit v1.2.3 From f85c4abdbc24ede9978073375bee12980cf852b2 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 26 Mar 2008 08:34:23 +0800 Subject: [Blackfin] arch: dump the stack before printing out an error otherwise the stack dump is useless as it shows us tracing through printk Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/bfin_gpio.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index 08788f7bbfb..a09dc48050b 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -821,10 +821,10 @@ int peripheral_request(unsigned short per, const char *label) local_irq_save(flags); if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) { + dump_stack(); printk(KERN_ERR "%s: Peripheral %d is already reserved as GPIO by %s !\n", __FUNCTION__, ident, get_label(ident)); - dump_stack(); local_irq_restore(flags); return -EBUSY; } @@ -848,10 +848,10 @@ int peripheral_request(unsigned short per, const char *label) if (cmp_label(ident, label) == 0) goto anyway; + dump_stack(); printk(KERN_ERR "%s: Peripheral %d function %d is already reserved by %s !\n", __FUNCTION__, ident, P_FUNCT2MUX(per), get_label(ident)); - dump_stack(); local_irq_restore(flags); return -EBUSY; } @@ -891,10 +891,10 @@ int peripheral_request(unsigned short per, const char *label) if (!check_gpio(ident)) { if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) { + dump_stack(); printk(KERN_ERR "%s: Peripheral %d is already reserved as GPIO by %s !\n", __FUNCTION__, ident, get_label(ident)); - dump_stack(); local_irq_restore(flags); return -EBUSY; } @@ -918,12 +918,12 @@ int peripheral_request(unsigned short per, const char *label) if (cmp_label(ident, label) == 0) goto anyway; + dump_stack(); printk(KERN_ERR "%s: Peripheral %d function %d is already" " reserved by %s !\n", __FUNCTION__, ident, P_FUNCT2MUX(per), get_label(ident)); - dump_stack(); local_irq_restore(flags); return -EBUSY; } @@ -1046,17 +1046,17 @@ int gpio_request(unsigned gpio, const char *label) } if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { + dump_stack(); printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n", gpio, get_label(gpio)); - dump_stack(); local_irq_restore(flags); return -EBUSY; } if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { + dump_stack(); printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", gpio, get_label(gpio)); - dump_stack(); local_irq_restore(flags); return -EBUSY; } @@ -1082,8 +1082,8 @@ void gpio_free(unsigned gpio) local_irq_save(flags); if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { - gpio_error(gpio); dump_stack(); + gpio_error(gpio); local_irq_restore(flags); return; } -- cgit v1.2.3 From d171c23327e2d596ac27d3df4322fc6430b45aa2 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 26 Mar 2008 08:35:46 +0800 Subject: [Blackfin] arch: fix up gpio code style -- no functional changes Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/bfin_gpio.c | 86 ++++++++++++++++++---------------------- 1 file changed, 39 insertions(+), 47 deletions(-) diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index a09dc48050b..b54dad505f8 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -348,11 +348,10 @@ static void portmux_setup(unsigned short per, unsigned short function) offset = port_mux_lut[y].offset; muxreg = bfin_read_PORT_MUX(); - if (offset != 1) { + if (offset != 1) muxreg &= ~(1 << offset); - } else { + else muxreg &= ~(3 << 1); - } muxreg |= (function << offset); bfin_write_PORT_MUX(muxreg); @@ -424,11 +423,9 @@ static void default_gpio(unsigned gpio) static int __init bfin_gpio_init(void) { - printk(KERN_INFO "Blackfin GPIO Controller\n"); return 0; - } arch_initcall(bfin_gpio_init); @@ -833,20 +830,20 @@ int peripheral_request(unsigned short per, const char *label) u16 funct = get_portmux(ident); - /* - * Pin functions like AMC address strobes my - * be requested and used by several drivers - */ + /* + * Pin functions like AMC address strobes my + * be requested and used by several drivers + */ if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) { - /* - * Allow that the identical pin function can - * be requested from the same driver twice - */ + /* + * Allow that the identical pin function can + * be requested from the same driver twice + */ - if (cmp_label(ident, label) == 0) - goto anyway; + if (cmp_label(ident, label) == 0) + goto anyway; dump_stack(); printk(KERN_ERR @@ -857,7 +854,7 @@ int peripheral_request(unsigned short per, const char *label) } } -anyway: + anyway: reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident); portmux_setup(ident, P_FUNCT2MUX(per)); @@ -890,33 +887,33 @@ int peripheral_request(unsigned short per, const char *label) if (!check_gpio(ident)) { - if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) { - dump_stack(); - printk(KERN_ERR - "%s: Peripheral %d is already reserved as GPIO by %s !\n", - __FUNCTION__, ident, get_label(ident)); - local_irq_restore(flags); - return -EBUSY; - } + if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) { + dump_stack(); + printk(KERN_ERR + "%s: Peripheral %d is already reserved as GPIO by %s !\n", + __FUNCTION__, ident, get_label(ident)); + local_irq_restore(flags); + return -EBUSY; + } } if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) { - /* - * Pin functions like AMC address strobes my - * be requested and used by several drivers - */ + /* + * Pin functions like AMC address strobes my + * be requested and used by several drivers + */ - if (!(per & P_MAYSHARE)) { + if (!(per & P_MAYSHARE)) { - /* - * Allow that the identical pin function can - * be requested from the same driver twice - */ + /* + * Allow that the identical pin function can + * be requested from the same driver twice + */ - if (cmp_label(ident, label) == 0) - goto anyway; + if (cmp_label(ident, label) == 0) + goto anyway; dump_stack(); printk(KERN_ERR @@ -930,7 +927,7 @@ int peripheral_request(unsigned short per, const char *label) } -anyway: + anyway: portmux_setup(per, P_FUNCT2MUX(per)); port_setup(ident, PERIPHERAL_USAGE); @@ -954,10 +951,10 @@ int peripheral_request_list(unsigned short per[], const char *label) ret = peripheral_request(per[cnt], label); if (ret < 0) { - for ( ; cnt > 0; cnt--) { + for ( ; cnt > 0; cnt--) peripheral_free(per[cnt - 1]); - } - return ret; + + return ret; } } @@ -981,15 +978,13 @@ void peripheral_free(unsigned short per) local_irq_save(flags); - if (unlikely(!(reserved_peri_map[gpio_bank(ident)] - & gpio_bit(ident)))) { + if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) { local_irq_restore(flags); return; } - if (!(per & P_MAYSHARE)) { + if (!(per & P_MAYSHARE)) port_setup(ident, GPIO_USAGE); - } reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident); @@ -1002,11 +997,8 @@ EXPORT_SYMBOL(peripheral_free); void peripheral_free_list(unsigned short per[]) { u16 cnt; - - for (cnt = 0; per[cnt] != 0; cnt++) { + for (cnt = 0; per[cnt] != 0; cnt++) peripheral_free(per[cnt]); - } - } EXPORT_SYMBOL(peripheral_free_list); -- cgit v1.2.3 From 81d9c7f27dd679df6d03df53eba4fd12caafdb47 Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Wed, 26 Mar 2008 10:02:13 +0800 Subject: [Blackfin] arch: add i2c board info struct and move to new-style i2c interface Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf533/boards/stamp.c | 32 +++++++++++++++++++++++++++++++ arch/blackfin/mach-bf537/boards/stamp.c | 33 ++++++++++++++++++++++++++++++++ arch/blackfin/mach-bf548/boards/ezkit.c | 34 +++++++++++++++++++++++++++++++++ 3 files changed, 99 insertions(+) diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index ecf449b322d..32b37afc6e6 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c @@ -40,6 +40,7 @@ #endif #include #include +#include #include #include #include @@ -474,6 +475,31 @@ static struct platform_device i2c_gpio_device = { }; #endif +#ifdef CONFIG_I2C_BOARDINFO +static struct i2c_board_info __initdata bfin_i2c_board_info[] = { +#if defined(CONFIG_JOYSTICK_AD7142) || defined(CONFIG_JOYSTICK_AD7142_MODULE) + { + I2C_BOARD_INFO("ad7142_joystick", 0x2C), + .type = "ad7142_joystick", + .irq = 39, + }, +#endif +#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) + { + I2C_BOARD_INFO("pcf8574_lcd", 0x22), + .type = "pcf8574_lcd", + }, +#endif +#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE) + { + I2C_BOARD_INFO("pcf8574_keypad", 0x27), + .type = "pcf8574_keypad", + .irq = 39, + }, +#endif +}; +#endif + static struct platform_device *stamp_devices[] __initdata = { #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) &rtc_device, @@ -528,6 +554,12 @@ static int __init stamp_init(void) int ret; printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + +#ifdef CONFIG_I2C_BOARDINFO + i2c_register_board_info(0, bfin_i2c_board_info, + ARRAY_SIZE(bfin_i2c_board_info)); +#endif + ret = platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); if (ret < 0) return ret; diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index 09828a0e999..f81a9b8a640 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include #include @@ -700,6 +701,31 @@ static struct platform_device i2c_bfin_twi_device = { }; #endif +#ifdef CONFIG_I2C_BOARDINFO +static struct i2c_board_info __initdata bfin_i2c_board_info[] = { +#if defined(CONFIG_JOYSTICK_AD7142) || defined(CONFIG_JOYSTICK_AD7142_MODULE) + { + I2C_BOARD_INFO("ad7142_joystick", 0x2C), + .type = "ad7142_joystick", + .irq = 55, + }, +#endif +#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) + { + I2C_BOARD_INFO("pcf8574_lcd", 0x22), + .type = "pcf8574_lcd", + }, +#endif +#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE) + { + I2C_BOARD_INFO("pcf8574_keypad", 0x27), + .type = "pcf8574_keypad", + .irq = 72, + }, +#endif +}; +#endif + #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) static struct platform_device bfin_sport0_uart_device = { .name = "bfin-sport-uart", @@ -829,6 +855,12 @@ static struct platform_device *stamp_devices[] __initdata = { static int __init stamp_init(void) { printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + +#ifdef CONFIG_I2C_BOARDINFO + i2c_register_board_info(0, bfin_i2c_board_info, + ARRAY_SIZE(bfin_i2c_board_info)); +#endif + platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) spi_register_board_info(bfin_spi_board_info, @@ -838,6 +870,7 @@ static int __init stamp_init(void) #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; #endif + return 0; } diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index dc3c0156f37..04c0c8df6e9 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) #include @@ -573,6 +574,29 @@ static struct platform_device i2c_bfin_twi1_device = { #endif #endif +#ifdef CONFIG_I2C_BOARDINFO +static struct i2c_board_info __initdata bfin_i2c_board_info0[] = { +}; + +#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ +static struct i2c_board_info __initdata bfin_i2c_board_info1[] = { +#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) + { + I2C_BOARD_INFO("pcf8574_lcd", 0x22), + .type = "pcf8574_lcd", + }, +#endif +#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE) + { + I2C_BOARD_INFO("pcf8574_keypad", 0x27), + .type = "pcf8574_keypad", + .irq = 212, + }, +#endif +}; +#endif +#endif + #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) #include @@ -672,6 +696,16 @@ static struct platform_device *ezkit_devices[] __initdata = { static int __init ezkit_init(void) { printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + +#ifdef CONFIG_I2C_BOARDINFO + i2c_register_board_info(0, bfin_i2c_board_info0, + ARRAY_SIZE(bfin_i2c_board_info0)); +#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ + i2c_register_board_info(1, bfin_i2c_board_info1, + ARRAY_SIZE(bfin_i2c_board_info1)); +#endif +#endif + platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices)); #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) -- cgit v1.2.3 From 9a62ca40fd793742f92565104c6b44319af8c282 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Wed, 26 Mar 2008 09:15:58 +0800 Subject: [Blackfin] arch: fix bug - when we crash, current is not valid Sometimes when we crash, current is not valid, (has been written over), so the existing code causes a invalid read during exception context - which is a unrecoverable double fault. This fixes this. Signed-off-by: Robin Getz Signed-off-by: Bryan Wu --- arch/blackfin/kernel/traps.c | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index e8e8f735c23..7557d0dce21 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -655,21 +655,30 @@ void dump_bfin_process(struct pt_regs *fp) else if (context & 0x8000) printk(KERN_NOTICE "Kernel process context\n"); - if (current->pid && current->mm) { + /* Because we are crashing, and pointers could be bad, we check things + * pretty closely before we use them + */ + if (!((unsigned long)current & 0x3) && current->pid) { printk(KERN_NOTICE "CURRENT PROCESS:\n"); - printk(KERN_NOTICE "COMM=%s PID=%d\n", - current->comm, current->pid); - - printk(KERN_NOTICE "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n" - KERN_NOTICE "BSS = 0x%p-0x%p USER-STACK = 0x%p\n" - KERN_NOTICE "\n", - (void *)current->mm->start_code, - (void *)current->mm->end_code, - (void *)current->mm->start_data, - (void *)current->mm->end_data, - (void *)current->mm->end_data, - (void *)current->mm->brk, - (void *)current->mm->start_stack); + if (current->comm >= (char *)FIXED_CODE_START) + printk(KERN_NOTICE "COMM=%s PID=%d\n", + current->comm, current->pid); + else + printk(KERN_NOTICE "COMM= invalid\n"); + + if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START) + printk(KERN_NOTICE "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n" + KERN_NOTICE " BSS = 0x%p-0x%p USER-STACK = 0x%p\n" + KERN_NOTICE "\n", + (void *)current->mm->start_code, + (void *)current->mm->end_code, + (void *)current->mm->start_data, + (void *)current->mm->end_data, + (void *)current->mm->end_data, + (void *)current->mm->brk, + (void *)current->mm->start_stack); + else + printk(KERN_NOTICE "invalid mm\n"); } else printk(KERN_NOTICE "\n" KERN_NOTICE "No Valid process in current context\n"); -- cgit v1.2.3 From 904656cda10ce985e6bc8b16488b58236eaec8e2 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Wed, 26 Mar 2008 09:17:43 +0800 Subject: [Blackfin] arch: fix bug - grab locks when not atomic grab locks when not atomic - this fixes the issues sometimes seen when using magic sysrq. Signed-off-by: Robin Getz Signed-off-by: Bryan Wu --- arch/blackfin/kernel/traps.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 7557d0dce21..de249d6fdd9 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -75,7 +75,7 @@ static void decode_address(char *buf, unsigned long address) struct task_struct *p; struct mm_struct *mm; unsigned long flags, offset; - unsigned int in_exception = bfin_read_IPEND() & 0x10; + unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic(); #ifdef CONFIG_KALLSYMS unsigned long symsize; @@ -117,7 +117,7 @@ static void decode_address(char *buf, unsigned long address) */ write_lock_irqsave(&tasklist_lock, flags); for_each_process(p) { - mm = (in_exception ? p->mm : get_task_mm(p)); + mm = (in_atomic ? p->mm : get_task_mm(p)); if (!mm) continue; @@ -146,14 +146,14 @@ static void decode_address(char *buf, unsigned long address) sprintf(buf, "<0x%p> [ %s + 0x%lx ]", (void *)address, name, offset); - if (!in_exception) + if (!in_atomic) mmput(mm); goto done; } vml = vml->next; } - if (!in_exception) + if (!in_atomic) mmput(mm); } -- cgit v1.2.3 From b594272c5e2837b6856b93520303c5981c852327 Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Thu, 27 Mar 2008 07:25:21 +0800 Subject: [Blackfin] arch: remove TWI I2C register accessing helper macros, because we moved to use i2c new-style interface Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf527/cdefBF52x_base.h | 33 ----------------------- include/asm-blackfin/mach-bf537/cdefBF534.h | 34 +----------------------- include/asm-blackfin/mach-bf548/cdefBF544.h | 33 ----------------------- include/asm-blackfin/mach-bf548/cdefBF547.h | 33 ----------------------- include/asm-blackfin/mach-bf548/cdefBF548.h | 33 ----------------------- include/asm-blackfin/mach-bf548/cdefBF549.h | 33 ----------------------- include/asm-blackfin/mach-bf548/cdefBF54x_base.h | 33 ----------------------- 7 files changed, 1 insertion(+), 231 deletions(-) diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h index 3f4de5d9d4c..50e14e7da3e 100644 --- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h +++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h @@ -873,39 +873,6 @@ /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) -#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val) -#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) -#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val) -#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) -#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val) -#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val) -#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val) -#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) -#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val) -#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) -#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val) -#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val) -#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) -#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val) -#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) -#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val) -#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val) -#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) -#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val) -#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val) -#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) -#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val) -#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) -#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val) -#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) -#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val) - /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ #define bfin_read_PORTGIO() bfin_read16(PORTGIO) diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h index 78227bc855d..048d26a61fd 100644 --- a/include/asm-blackfin/mach-bf537/cdefBF534.h +++ b/include/asm-blackfin/mach-bf537/cdefBF534.h @@ -858,39 +858,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) -#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val) -#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) -#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL,val) -#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) -#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL,val) -#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT,val) -#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR,val) -#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) -#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL,val) -#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) -#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT,val) -#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR,val) -#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) -#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT,val) -#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) -#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK,val) -#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL,val) -#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) -#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT,val) -#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8,val) -#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) -#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16,val) -#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) -#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8,val) -#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) -#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16,val) +/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ #define bfin_read_PORTGIO() bfin_read16(PORTGIO) diff --git a/include/asm-blackfin/mach-bf548/cdefBF544.h b/include/asm-blackfin/mach-bf548/cdefBF544.h index 7a2d177c8dc..ea9b4ab496f 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF544.h +++ b/include/asm-blackfin/mach-bf548/cdefBF544.h @@ -113,39 +113,6 @@ /* Two Wire Interface Registers (TWI1) */ -#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) -#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) -#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) -#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) -#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) -#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) -#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL) -#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val) -#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) -#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) -#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) -#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) -#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL) -#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val) -#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) -#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) -#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) -#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) -#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) -#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) - /* CAN Controller 1 Config 1 Registers */ #define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) diff --git a/include/asm-blackfin/mach-bf548/cdefBF547.h b/include/asm-blackfin/mach-bf548/cdefBF547.h index d0a200b08ab..ba716277c00 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF547.h +++ b/include/asm-blackfin/mach-bf548/cdefBF547.h @@ -185,39 +185,6 @@ /* Two Wire Interface Registers (TWI1) */ -#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) -#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) -#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) -#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) -#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) -#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) -#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL) -#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val) -#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) -#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) -#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) -#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) -#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL) -#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val) -#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) -#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) -#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) -#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) -#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) -#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) - /* SPI2 Registers */ #define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) diff --git a/include/asm-blackfin/mach-bf548/cdefBF548.h b/include/asm-blackfin/mach-bf548/cdefBF548.h index 674be0216bf..ae971ebff6a 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF548.h +++ b/include/asm-blackfin/mach-bf548/cdefBF548.h @@ -185,39 +185,6 @@ /* Two Wire Interface Registers (TWI1) */ -#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) -#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) -#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) -#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) -#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) -#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) -#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL) -#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val) -#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) -#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) -#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) -#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) -#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL) -#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val) -#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) -#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) -#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) -#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) -#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) -#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) - /* SPI2 Registers */ #define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) diff --git a/include/asm-blackfin/mach-bf548/cdefBF549.h b/include/asm-blackfin/mach-bf548/cdefBF549.h index 2ab5b7c0082..38eafe71913 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF549.h +++ b/include/asm-blackfin/mach-bf548/cdefBF549.h @@ -185,39 +185,6 @@ /* Two Wire Interface Registers (TWI1) */ -#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) -#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) -#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) -#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) -#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) -#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) -#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL) -#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val) -#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) -#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) -#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) -#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) -#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL) -#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val) -#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) -#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) -#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) -#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) -#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) -#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) - /* SPI2 Registers */ #define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index 19ddcd83c71..d8d2f1f127d 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -211,39 +211,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* Two Wire Interface Registers (TWI0) */ -#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) -#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) -#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL) -#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val) -#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) -#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) -#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define bfin_read_TWI0_MASTER_CTRL() bfin_read16(TWI0_MASTER_CTRL) -#define bfin_write_TWI0_MASTER_CTRL(val) bfin_write16(TWI0_MASTER_CTRL, val) -#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) -#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) -#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) -#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) -#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define bfin_read_TWI0_FIFO_CTRL() bfin_read16(TWI0_FIFO_CTRL) -#define bfin_write_TWI0_FIFO_CTRL(val) bfin_write16(TWI0_FIFO_CTRL, val) -#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) -#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) -#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) -#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) -#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) -#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) - /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ /* SPORT1 Registers */ -- cgit v1.2.3 From dbfe44f02b6855efb5a596e942ec2fd96d592f60 Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Wed, 23 Apr 2008 07:11:55 +0800 Subject: [Blackfin] arch: fix up - CONFIG_BLKFIN_WT was renamed CONFIG_BFIN_WT while the MPU code was out-of-tree. Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu --- arch/blackfin/kernel/cplb-mpu/cplbinit.c | 2 +- arch/blackfin/kernel/cplb-mpu/cplbmgr.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c index dc6e8a7a8bd..7310e5fc639 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c @@ -49,7 +49,7 @@ void __init generate_cpl_tables(void) #ifdef CONFIG_BFIN_DCACHE d_cache = CPLB_L1_CHBL; -#ifdef CONFIG_BLKFIN_WT +#ifdef CONFIG_BFIN_WT d_cache |= CPLB_L1_AOW | CPLB_WT; #endif #endif diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index c426a22f990..0a30d625607 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c @@ -149,7 +149,7 @@ static noinline int dcplb_miss(void) d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; #ifdef CONFIG_BFIN_DCACHE d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; -#ifdef CONFIG_BLKFIN_WT +#ifdef CONFIG_BFIN_WT d_data |= CPLB_L1_AOW | CPLB_WT; #endif #endif @@ -319,7 +319,7 @@ void set_mask_dcplbs(unsigned long *masks) d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; #ifdef CONFIG_BFIN_DCACHE d_data |= CPLB_L1_CHBL; -#ifdef CONFIG_BLKFIN_WT +#ifdef CONFIG_BFIN_WT d_data |= CPLB_L1_AOW | CPLB_WT; #endif #endif -- cgit v1.2.3 From 2a0c4fdb6602ea066380aaf71ff7bb2f61ffeee8 Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Wed, 23 Apr 2008 07:17:34 +0800 Subject: [Blackfin] arch: fix bug - when using trace buffer with CONFIG_MPU enabled. There were a couple of problems with the way the trace buffer state is saved/restored in assembly. The DEBUG_HWTRACE_SAVE/RESTORE macros save a value to the stack, which is not immediately obvious; the CPLB exception code needed changes to load the correct value of the stack pointer. The other problem is that the SAVE/RESTORE macros weren't pushing and popping the value downwards on the stack, but rather moving it _upwards_, which is of course completely broken. We also need to make sure there's a matching DEBUG_HWTRACE_RESTORE in the error case of the CPLB handler. Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu --- arch/blackfin/mach-common/entry.S | 7 ++++++- include/asm-blackfin/trace.h | 4 ++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index cee54cebbc6..a504c65d999 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -121,10 +121,14 @@ ENTRY(_ex_icplb_miss) (R7:6,P5:4) = [sp++]; ASTAT = [sp++]; SAVE_ALL_SYS - DEBUG_HWTRACE_SAVE(p5, r7) #ifdef CONFIG_MPU + /* We must load R1 here, _before_ DEBUG_HWTRACE_SAVE, since that + * will change the stack pointer. */ R0 = SEQSTAT; R1 = SP; +#endif + DEBUG_HWTRACE_SAVE(p5, r7) +#ifdef CONFIG_MPU sp += -12; call _cplb_hdr; sp += 12; @@ -191,6 +195,7 @@ ENTRY(_bfin_return_from_exception) ENDPROC(_bfin_return_from_exception) ENTRY(_handle_bad_cplb) + DEBUG_HWTRACE_RESTORE(p5, r7) /* To get here, we just tried and failed to change a CPLB * so, handle things in trap_c (C code), by lowering to * IRQ5, just like we normally do. Since this is not a diff --git a/include/asm-blackfin/trace.h b/include/asm-blackfin/trace.h index ef18afbc210..312b596b973 100644 --- a/include/asm-blackfin/trace.h +++ b/include/asm-blackfin/trace.h @@ -62,14 +62,14 @@ extern unsigned long software_trace_buff[]; preg.L = LO(TBUFCTL); \ preg.H = HI(TBUFCTL); \ dreg = [preg]; \ - [sp++] = dreg; \ + [--sp] = dreg; \ dreg = 0x1; \ [preg] = dreg; #define trace_buffer_restore(preg, dreg) \ preg.L = LO(TBUFCTL); \ preg.H = HI(TBUFCTL); \ - dreg = [sp--]; \ + dreg = [sp++]; \ [preg] = dreg; #else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ -- cgit v1.2.3 From b4bb68f7d049e923a812903133e7e3747dfe0fce Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Wed, 23 Apr 2008 07:26:23 +0800 Subject: [Blackfin] arch: fix bug - Make the MPU code aware of the async banks and the uncached DMA area. Bug: CONFIG_MPU doesn't seem to handle access to ASYNC/IO Memory well http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3912 Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu --- arch/blackfin/kernel/cplb-mpu/cplbmgr.c | 46 +++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index 0a30d625607..6f1c053903c 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c @@ -143,30 +143,39 @@ static noinline int dcplb_miss(void) unsigned long d_data; nr_dcplb_miss++; - if (addr >= _ramend) - return CPLB_PROT_VIOL; d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; #ifdef CONFIG_BFIN_DCACHE - d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; + if (addr < _ramend - DMA_UNCACHED_REGION) { + d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; #ifdef CONFIG_BFIN_WT - d_data |= CPLB_L1_AOW | CPLB_WT; -#endif + d_data |= CPLB_L1_AOW | CPLB_WT; #endif - mask = current_rwx_mask; - if (mask) { - int page = addr >> PAGE_SHIFT; - int offs = page >> 5; - int bit = 1 << (page & 31); - - if (mask[offs] & bit) - d_data |= CPLB_USER_RD; - - mask += page_mask_nelts; - if (mask[offs] & bit) - d_data |= CPLB_USER_WR; } +#endif + if (addr >= _ramend) { + if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE + && (status & FAULT_USERSUPV)) { + addr &= ~0x3fffff; + d_data &= ~PAGE_SIZE_4KB; + d_data |= PAGE_SIZE_4MB; + } else + return CPLB_PROT_VIOL; + } else { + mask = current_rwx_mask; + if (mask) { + int page = addr >> PAGE_SHIFT; + int offs = page >> 5; + int bit = 1 << (page & 31); + + if (mask[offs] & bit) + d_data |= CPLB_USER_RD; + mask += page_mask_nelts; + if (mask[offs] & bit) + d_data |= CPLB_USER_WR; + } + } idx = evict_one_dcplb(); addr &= PAGE_MASK; @@ -280,8 +289,7 @@ int cplb_hdr(int seqstat, struct pt_regs *regs) case 0x26: return dcplb_miss(); default: - return 1; - panic_cplb_error(seqstat, regs); + return 1; } } -- cgit v1.2.3 From 9fcdc78c5ebaba0970d006dd72376a815aee1efa Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Wed, 23 Apr 2008 07:41:52 +0800 Subject: [Blackfin] arch: Add dma_map_page and dma_unmap_page stub for MMC SPI compiling Signed-off-by: Bryan Wu --- include/asm-blackfin/dma-mapping.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/include/asm-blackfin/dma-mapping.h b/include/asm-blackfin/dma-mapping.h index 282fabccf6a..1a13c2fc366 100644 --- a/include/asm-blackfin/dma-mapping.h +++ b/include/asm-blackfin/dma-mapping.h @@ -27,6 +27,14 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr, extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, enum dma_data_direction direction); +static inline dma_addr_t +dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction dir) +{ + return dma_map_single(dev, page_address(page) + offset, size, dir); +} + /* * Unmap a single streaming mode DMA translation. The dma_addr and size * must match what was provided for in a previous pci_map_single call. All @@ -38,6 +46,13 @@ extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, enum dma_data_direction direction); +static inline void +dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, + enum dma_data_direction dir) +{ + dma_unmap_single(dev, dma_addr, size, dir); +} + /* * Map a set of buffers described by scatterlist in streaming * mode for DMA. This is the scather-gather version of the -- cgit v1.2.3 From 6a42a91019cb8744435e903f0693bd0e424061f8 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 23 Apr 2008 08:01:31 +0800 Subject: [Blackfin] arch: update reboot code to match latest info (really just copy from u-boot) Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/reboot.c | 69 +++++++++++++++++++++++++------------------ 1 file changed, 40 insertions(+), 29 deletions(-) diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c index 483f93dfc1b..367e2dc0988 100644 --- a/arch/blackfin/kernel/reboot.c +++ b/arch/blackfin/kernel/reboot.c @@ -11,45 +11,56 @@ #include #include -#if defined(BF537_FAMILY) || defined(BF533_FAMILY) || defined(BF527_FAMILY) -#define SYSCR_VAL 0x0 -#elif defined(BF561_FAMILY) -#define SYSCR_VAL 0x20 -#elif defined(BF548_FAMILY) -#define SYSCR_VAL 0x10 -#endif - -/* - * Delay min 5 SCLK cycles using worst case CCLK/SCLK ratio (15) - */ -#define SWRST_DELAY (5 * 15) - -/* A system soft reset makes external memory unusable - * so force this function into L1. +/* A system soft reset makes external memory unusable so force + * this function into L1. We use the compiler ssync here rather + * than SSYNC() because it's safe (no interrupts and such) and + * we save some L1. We do not need to force sanity in the SYSCR + * register as the BMODE selection bit is cleared by the soft + * reset while the Core B bit (on dual core parts) is cleared by + * the core reset. */ __attribute__((l1_text)) void bfin_reset(void) { - /* force BMODE and disable Core B (as needed) */ - bfin_write_SYSCR(SYSCR_VAL); - - /* we use asm ssync here because it's save and we save some L1 */ - asm("ssync;"); + /* Wait for completion of "system" events such as cache line + * line fills so that we avoid infinite stalls later on as + * much as possible. This code is in L1, so it won't trigger + * any such event after this point in time. + */ + __builtin_bfin_ssync(); while (1) { - /* initiate system soft reset with magic 0x7 */ + /* Initiate System software reset. */ bfin_write_SWRST(0x7); - /* Wait for System reset to actually reset, needs to be 5 SCLKs, */ - /* Assume CCLK / SCLK ratio is worst case (15), and use 5*15 */ - - asm("LSETUP(.Lfoo,.Lfoo) LC0 = %0\n .Lfoo: NOP;\n" - : : "a" (SWRST_DELAY) : "LC0", "LT0", "LB0"); + /* Due to the way reset is handled in the hardware, we need + * to delay for 7 SCLKS. The only reliable way to do this is + * to calculate the CCLK/SCLK ratio and multiply 7. For now, + * we'll assume worse case which is a 1:15 ratio. + */ + asm( + "LSETUP (1f, 1f) LC0 = %0\n" + "1: nop;" + : + : "a" (15 * 7) + : "LC0", "LB0", "LT0" + ); - /* clear system soft reset */ + /* Clear System software reset */ bfin_write_SWRST(0); - asm("ssync;"); - /* issue core reset */ + + /* Wait for the SWRST write to complete. Cannot rely on SSYNC + * though as the System state is all reset now. + */ + asm( + "LSETUP (1f, 1f) LC1 = %0\n" + "1: nop;" + : + : "a" (15 * 1) + : "LC1", "LB1", "LT1" + ); + + /* Issue core reset */ asm("raise 1"); } } -- cgit v1.2.3 From 618835a0e33a822d18b391a5e9dd821c8fb34b06 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 23 Apr 2008 08:07:05 +0800 Subject: [Blackfin] arch: MEM_ADD_WIDTH only gets used when reprogramming clocks, so dont bother exposing it in the menu normally Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/Kconfig | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index a3cf9d0a528..add87a5f64e 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -303,6 +303,18 @@ config BFIN_KERNEL_CLOCK are also not changed, and the Bootloader does 100% of the hardware configuration. +config MEM_ADD_WIDTH + int "Memory Address Width" + depends on BFIN_KERNEL_CLOCK + depends on (!BF54x) + default 9 if BFIN533_EZKIT + default 9 if BFIN561_EZKIT + default 9 if H8606_HVSISTEMAS + default 10 if BFIN527_EZKIT + default 10 if BFIN537_STAMP + default 11 if BFIN533_STAMP + default 10 if PNAV10 + config PLL_BYPASS bool "Bypass PLL" depends on BFIN_KERNEL_CLOCK @@ -448,18 +460,6 @@ config MEM_SIZE default 64 if PNAV10 default 32 if H8606_HVSISTEMAS -config MEM_ADD_WIDTH - int "SDRAM Memory Address Width" - depends on (!BF54x) - default 9 if BFIN533_EZKIT - default 9 if BFIN561_EZKIT - default 9 if H8606_HVSISTEMAS - default 10 if BFIN527_EZKIT - default 10 if BFIN537_STAMP - default 11 if BFIN533_STAMP - default 10 if PNAV10 - - choice prompt "DDR SDRAM Chip Type" depends on BFIN548_EZKIT -- cgit v1.2.3 From 53eabf046b2837647f186f0cba085ce7a43bd7ce Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 23 Apr 2008 08:09:45 +0800 Subject: [Blackfin] arch: replace implied numbers with real values replace implied numbers with real values so that strace is able to calculate things automatically ... the numbers are frozen in our ABI, so having them based off other __NR_xxx values really doesnt matter -- no functional changes Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/unistd.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h index c18a399f6e3..42955d0c439 100644 --- a/include/asm-blackfin/unistd.h +++ b/include/asm-blackfin/unistd.h @@ -265,14 +265,14 @@ /* 258 __NR_remap_file_pages */ #define __NR_set_tid_address 259 #define __NR_timer_create 260 -#define __NR_timer_settime (__NR_timer_create+1) -#define __NR_timer_gettime (__NR_timer_create+2) -#define __NR_timer_getoverrun (__NR_timer_create+3) -#define __NR_timer_delete (__NR_timer_create+4) -#define __NR_clock_settime (__NR_timer_create+5) -#define __NR_clock_gettime (__NR_timer_create+6) -#define __NR_clock_getres (__NR_timer_create+7) -#define __NR_clock_nanosleep (__NR_timer_create+8) +#define __NR_timer_settime 261 +#define __NR_timer_gettime 262 +#define __NR_timer_getoverrun 263 +#define __NR_timer_delete 264 +#define __NR_clock_settime 265 +#define __NR_clock_gettime 266 +#define __NR_clock_getres 267 +#define __NR_clock_nanosleep 268 #define __NR_statfs64 269 #define __NR_fstatfs64 270 #define __NR_tgkill 271 @@ -283,11 +283,11 @@ /* 276 __NR_get_mempolicy */ /* 277 __NR_set_mempolicy */ #define __NR_mq_open 278 -#define __NR_mq_unlink (__NR_mq_open+1) -#define __NR_mq_timedsend (__NR_mq_open+2) -#define __NR_mq_timedreceive (__NR_mq_open+3) -#define __NR_mq_notify (__NR_mq_open+4) -#define __NR_mq_getsetattr (__NR_mq_open+5) +#define __NR_mq_unlink 279 +#define __NR_mq_timedsend 280 +#define __NR_mq_timedreceive 281 +#define __NR_mq_notify 282 +#define __NR_mq_getsetattr 283 #define __NR_kexec_load 284 #define __NR_waitid 285 #define __NR_add_key 286 -- cgit v1.2.3 From 0e184c6b4feba9640c85811a7929d18f4491ddb0 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 23 Apr 2008 08:23:51 +0800 Subject: [Blackfin] arch: relocate MAX_SWITCH_{D,I}_CPLBS from the header to the file where it actually gets used. relocate MAX_SWITCH_{D,I}_CPLBS from the header to the file where it actually gets used. this way when we change CONFIG_MEM_SIZE in our kconfig, we only rebuild one or two files rather than a whole bunch that implicitly include cplb.h. this will also remove the ability to clear the swapcount on the fly, but i really dont think that functionality is important. ultimate goal is for CONFIG_MEM_SIZE to go away and calculate this value on the fly based on what u-boot programmed for us. Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/cplb-nompu/cplbinfo.c | 11 ----------- arch/blackfin/kernel/cplb-nompu/cplbinit.c | 23 +++++++++++++++++++++++ include/asm-blackfin/cplb.h | 26 -------------------------- 3 files changed, 23 insertions(+), 37 deletions(-) diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinfo.c b/arch/blackfin/kernel/cplb-nompu/cplbinfo.c index a4f0b428a34..f7f2eb0b7fe 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinfo.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinfo.c @@ -174,16 +174,6 @@ static int cplbinfo_read_proc(char *page, char **start, off_t off, return len; } -static int cplbinfo_write_proc(struct file *file, const char __user *buffer, - unsigned long count, void *data) -{ - printk(KERN_INFO "Reset the CPLB swap in/out counts.\n"); - memset(ipdt_swapcount_table, 0, MAX_SWITCH_I_CPLBS * sizeof(unsigned long)); - memset(dpdt_swapcount_table, 0, MAX_SWITCH_D_CPLBS * sizeof(unsigned long)); - - return count; -} - static int __init cplbinfo_init(void) { struct proc_dir_entry *entry; @@ -193,7 +183,6 @@ static int __init cplbinfo_init(void) return -ENOMEM; entry->read_proc = cplbinfo_read_proc; - entry->write_proc = cplbinfo_write_proc; entry->data = NULL; return 0; diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index 6320bc45fbb..dd46b666fd4 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -26,6 +26,29 @@ #include #include +/* +* Number of required data CPLB switchtable entries +* MEMSIZE / 4 (we mostly install 4M page size CPLBs +* approx 16 for smaller 1MB page size CPLBs for allignment purposes +* 1 for L1 Data Memory +* possibly 1 for L2 Data Memory +* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO +* 1 for ASYNC Memory +*/ +#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \ + + ASYNC_MEMORY_CPLB_COVERAGE) * 2) + +/* +* Number of required instruction CPLB switchtable entries +* MEMSIZE / 4 (we mostly install 4M page size CPLBs +* approx 12 for smaller 1MB page size CPLBs for allignment purposes +* 1 for L1 Instruction Memory +* possibly 1 for L2 Instruction Memory +* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO +*/ +#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2) + + u_long icplb_table[MAX_CPLBS + 1]; u_long dcplb_table[MAX_CPLBS + 1]; diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index 654375c2b74..5b0da9a69b6 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -74,32 +74,6 @@ #define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) -/* -* Number of required data CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 16 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Data Memory -* possibly 1 for L2 Data Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -* 1 for ASYNC Memory -*/ - - -#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \ - + ASYNC_MEMORY_CPLB_COVERAGE) * 2) - -/* -* Number of required instruction CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 12 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Instruction Memory -* possibly 1 for L2 Instruction Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -*/ - -#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2) - - #define CPLB_ENABLE_ICACHE_P 0 #define CPLB_ENABLE_DCACHE_P 1 #define CPLB_ENABLE_DCACHE2_P 2 -- cgit v1.2.3 From 25bb23bfd061075955ca68b6a336c542d56263b3 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 23 Apr 2008 08:27:06 +0800 Subject: [Blackfin] arch: fix some obvious typos -- some of which prevent SDH building for the BF542 Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/cdefBF542.h | 12 ++++++------ include/asm-blackfin/mach-bf548/cdefBF549.h | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/asm-blackfin/mach-bf548/cdefBF542.h b/include/asm-blackfin/mach-bf548/cdefBF542.h index 308b33ab531..60b9f77576f 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF542.h +++ b/include/asm-blackfin/mach-bf548/cdefBF542.h @@ -123,12 +123,12 @@ #define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) #define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) #define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) -#define bfin_read_SDH_DATA_CNT() fin_read16(SDH_DATA_CNT) +#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) #define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) #define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) #define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) -#define bfin_read_SDH_STATUS_CLR() fin_read16(SDH_STATUS_CLR) -#define bfin_write_SDH_STATUS_CLR(val) fin_write16(SDH_STATUS_CLR, val) +#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) +#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) #define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) #define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) #define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) @@ -184,8 +184,8 @@ #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) #define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define bfin_read_USB_TESTMODE() fin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) fin_write16(USB_TESTMODE, val) +#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) +#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) #define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) #define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) #define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) @@ -244,7 +244,7 @@ #define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) #define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) fin_write16(USB_OTG_VBUS_IRQ, val) +#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) #define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) diff --git a/include/asm-blackfin/mach-bf548/cdefBF549.h b/include/asm-blackfin/mach-bf548/cdefBF549.h index 38eafe71913..92d07d96199 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF549.h +++ b/include/asm-blackfin/mach-bf548/cdefBF549.h @@ -1740,7 +1740,7 @@ #define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) #define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) #define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) -#define bfin_write_USB_DMA5COUNTLOW(val) fin_write16(USB_DMA5COUNTLOW, val) +#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) #define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) #define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) -- cgit v1.2.3 From 37167e6411f15fc8d8da8acabfd7cdd17668ffad Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Fri, 25 Apr 2008 03:06:10 +0800 Subject: [Blackfin] arch: Fix bug - Properly calculate DDR clock. Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/mem_init.h | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h index befc2903d5a..ab0b863eee6 100644 --- a/include/asm-blackfin/mach-bf548/mem_init.h +++ b/include/asm-blackfin/mach-bf548/mem_init.h @@ -29,16 +29,19 @@ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1) +#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000) +#define DDR_CLK_HZ(x) (1000*1000*1000/x) #if (CONFIG_MEM_MT46V32M16_6T) #define DDR_SIZE DEVSZ_512 #define DDR_WIDTH DEVWD_16 +#define DDR_MAX_tCK 13 #define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60)) #define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42)) #define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) #define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72)) -#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800)) +#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) #define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) #define DDR_tWTR DDR_TWTR(1) @@ -49,12 +52,13 @@ #if (CONFIG_MEM_MT46V32M16_5B) #define DDR_SIZE DEVSZ_512 #define DDR_WIDTH DEVWD_16 +#define DDR_MAX_tCK 13 #define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55)) #define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40)) #define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) #define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70)) -#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800)) +#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) #define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) #define DDR_tWTR DDR_TWTR(2) @@ -65,6 +69,7 @@ #if (CONFIG_MEM_GENERIC_BOARD) #define DDR_SIZE DEVSZ_512 #define DDR_WIDTH DEVWD_16 +#define DDR_MAX_tCK 13 #define DDR_tRCD DDR_TRCD(3) #define DDR_tWTR DDR_TWTR(2) @@ -77,14 +82,15 @@ #define DDR_tREFI DDR_TREFI(1288) #endif -#if (CONFIG_SCLK_HZ <= 133333333) -#define DDR_CL CL_2 -#elif (CONFIG_SCLK_HZ <= 166666666) -#define DDR_CL CL_2_5 +#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK)) +# error "CONFIG_SCLK_HZ is too small (133333333 Hz)." #endif + #define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI) #define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \ | DDR_tMRD | DDR_tWR | DDR_tRCD) -- cgit v1.2.3 From a8a46a269e05190d18e4e36f51477d59bd0b29f6 Mon Sep 17 00:00:00 2001 From: Meihui Fan Date: Wed, 23 Apr 2008 08:50:53 +0800 Subject: [Blackfin] arch: fix obvious bfin_write typos Signed-off-by: Meihui Fan Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/cdefBF54x_base.h | 348 +++++++++++------------ 1 file changed, 174 insertions(+), 174 deletions(-) diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index d8d2f1f127d..33c67500717 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -290,7 +290,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) #define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) #define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD) -#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD) +#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val) #define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) #define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) #define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) @@ -359,23 +359,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 0 Registers */ #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR) +#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR) +#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY) +#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY) +#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR) +#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR) +#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) @@ -388,23 +388,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 1 Registers */ #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR) +#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR) +#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY) +#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY) +#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR) +#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR) +#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) @@ -417,23 +417,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 2 Registers */ #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR) +#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR) +#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY) +#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY) +#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR) +#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR) +#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) @@ -446,23 +446,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 3 Registers */ #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR) +#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR) +#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY) +#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY) +#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR) +#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR) +#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) @@ -475,23 +475,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 4 Registers */ #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR) +#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR) +#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY) +#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY) +#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR) +#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR) +#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) @@ -504,23 +504,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 5 Registers */ #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR) +#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR) +#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY) +#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY) +#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR) +#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR) +#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) @@ -533,23 +533,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 6 Registers */ #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR) +#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR) +#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY) +#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY) +#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR) +#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR) +#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) @@ -562,23 +562,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 7 Registers */ #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR) +#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR) +#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY) +#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY) +#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR) +#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR) +#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) @@ -591,23 +591,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 8 Registers */ #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR) +#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) #define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR) +#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY) +#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY) +#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) #define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR) +#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) #define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR) +#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) @@ -620,23 +620,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 9 Registers */ #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR) +#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) #define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR) +#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY) +#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY) +#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) #define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR) +#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) #define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR) +#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) @@ -649,23 +649,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 10 Registers */ #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR) +#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) #define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR) +#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY) +#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY) +#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) #define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR) +#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) #define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR) +#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) @@ -678,23 +678,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 11 Registers */ #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR) +#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) #define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR) +#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY) +#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY) +#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) #define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR) +#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) #define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR) +#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) @@ -707,7 +707,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* MDMA Stream 0 Registers */ #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) @@ -770,11 +770,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY) +#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY) +#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) @@ -796,11 +796,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY) +#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY) +#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) @@ -1213,23 +1213,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 12 Registers */ #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR) -#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR) +#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val) #define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR) -#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR) +#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val) #define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) #define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) #define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) #define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) #define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) -#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY) +#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) #define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) #define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) #define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) -#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY) +#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) #define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR) -#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR) +#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val) #define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR) -#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR) +#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val) #define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) @@ -1242,23 +1242,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 13 Registers */ #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR) -#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR) +#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val) #define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR) -#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR) +#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val) #define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) #define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) #define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) #define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) #define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) -#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY) +#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) #define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) #define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) #define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) -#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY) +#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) #define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR) -#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR) +#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val) #define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR) -#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR) +#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val) #define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) @@ -1271,23 +1271,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 14 Registers */ #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR) -#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR) +#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val) #define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR) -#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR) +#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val) #define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) #define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) #define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) #define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) #define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) -#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY) +#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) #define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) #define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) #define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) -#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY) +#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) #define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR) -#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR) +#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val) #define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR) -#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR) +#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val) #define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) @@ -1300,23 +1300,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 15 Registers */ #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR) -#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR) +#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val) #define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR) -#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR) +#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val) #define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) #define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) #define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) #define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) #define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) -#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY) +#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) #define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) #define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) #define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) -#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY) +#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) #define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR) -#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR) +#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val) #define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR) -#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR) +#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val) #define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) @@ -1329,23 +1329,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 16 Registers */ #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR) -#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR) +#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val) #define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR) -#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR) +#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val) #define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) #define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) #define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) #define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) #define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) -#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY) +#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) #define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) #define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) #define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) -#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY) +#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) #define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR) -#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR) +#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val) #define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR) -#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR) +#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val) #define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) @@ -1358,23 +1358,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 17 Registers */ #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR) -#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR) +#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val) #define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR) -#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR) +#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val) #define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) #define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) #define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) #define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) #define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) -#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY) +#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) #define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) #define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) #define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) -#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY) +#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) #define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR) -#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR) +#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val) #define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR) -#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR) +#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val) #define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) @@ -1387,23 +1387,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 18 Registers */ #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR) -#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR) +#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val) #define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR) -#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR) +#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val) #define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) #define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) #define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) #define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) #define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) -#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY) +#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) #define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) #define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) #define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) -#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY) +#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) #define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR) -#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR) +#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val) #define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR) -#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR) +#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val) #define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) @@ -1416,23 +1416,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 19 Registers */ #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR) -#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR) +#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val) #define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR) -#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR) +#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val) #define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) #define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) #define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) #define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) #define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) -#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY) +#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) #define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) #define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) #define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) -#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY) +#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) #define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR) -#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR) +#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val) #define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR) -#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR) +#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val) #define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) @@ -1445,23 +1445,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 20 Registers */ #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR) -#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR) +#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val) #define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR) -#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR) +#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val) #define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) #define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) #define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) #define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) #define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) -#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY) +#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) #define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) #define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) #define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) -#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY) +#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) #define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR) -#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR) +#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val) #define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR) -#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR) +#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val) #define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) #define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) @@ -1474,23 +1474,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 21 Registers */ #define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR) -#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR) +#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val) #define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR) -#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR) +#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val) #define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) #define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) #define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) #define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) #define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) -#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY) +#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) #define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) #define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) #define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) -#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY) +#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) #define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR) -#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR) +#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val) #define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR) -#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR) +#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val) #define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) #define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) @@ -1503,23 +1503,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 22 Registers */ #define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR) -#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR) +#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val) #define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR) -#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR) +#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val) #define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) #define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) #define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) #define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) #define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) -#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY) +#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) #define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) #define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) #define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) -#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY) +#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) #define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR) -#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR) +#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val) #define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR) -#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR) +#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val) #define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) #define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) @@ -1532,23 +1532,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 23 Registers */ #define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR) -#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR) +#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val) #define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR) -#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR) +#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val) #define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) #define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) #define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) #define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) #define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) -#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY) +#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) #define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) #define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) #define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) -#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY) +#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) #define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR) -#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR) +#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val) #define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR) -#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR) +#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val) #define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) #define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) @@ -1561,23 +1561,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* MDMA Stream 2 Registers */ #define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR) -#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR) +#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val) #define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR) -#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR) +#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val) #define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) #define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) #define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) -#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY) +#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) #define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) #define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) -#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY) +#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) #define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR) -#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR) +#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val) #define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR) -#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR) +#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val) #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) #define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) @@ -1587,23 +1587,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) #define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR) -#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR) +#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val) #define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR) -#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR) +#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val) #define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) #define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) #define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) -#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY) +#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) #define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) #define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) -#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY) +#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) #define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR) -#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR) +#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val) #define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR) -#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR) +#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val) #define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) #define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) @@ -1616,23 +1616,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* MDMA Stream 3 Registers */ #define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR) -#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR) +#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val) #define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR) -#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR) +#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val) #define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) #define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) #define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) -#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY) +#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) #define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) #define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) -#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY) +#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) #define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR) -#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR) +#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val) #define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR) -#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR) +#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val) #define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) #define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) @@ -1642,23 +1642,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) #define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR) -#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR) +#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val) #define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR) -#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR) +#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val) #define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) #define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) #define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) -#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY) +#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) #define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) #define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) -#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY) +#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) #define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR) -#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR) +#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val) #define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR) -#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR) +#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val) #define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) #define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) -- cgit v1.2.3 From 6eceb0d4da10df9301e27bcec7a9b927e5047251 Mon Sep 17 00:00:00 2001 From: Meihui Fan Date: Wed, 23 Apr 2008 08:53:15 +0800 Subject: [Blackfin] arch: add support for the rest of the gptimers on the BF54x Signed-off-by: Meihui Fan Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/gptimers.c | 24 ++++--- include/asm-blackfin/gptimers.h | 150 +++++++++++++++++----------------------- 2 files changed, 81 insertions(+), 93 deletions(-) diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c index 1904d8b5332..e698554895a 100644 --- a/arch/blackfin/kernel/gptimers.c +++ b/arch/blackfin/kernel/gptimers.c @@ -52,12 +52,14 @@ static volatile GPTIMER_timer_regs *const timer_regs[MAX_BLACKFIN_GPTIMERS] = (GPTIMER_timer_regs *)TIMER5_CONFIG, (GPTIMER_timer_regs *)TIMER6_CONFIG, (GPTIMER_timer_regs *)TIMER7_CONFIG, -#endif -#if (MAX_BLACKFIN_GPTIMERS > 8) +# if (MAX_BLACKFIN_GPTIMERS > 8) (GPTIMER_timer_regs *)TIMER8_CONFIG, (GPTIMER_timer_regs *)TIMER9_CONFIG, (GPTIMER_timer_regs *)TIMER10_CONFIG, +# if (MAX_BLACKFIN_GPTIMERS > 11) (GPTIMER_timer_regs *)TIMER11_CONFIG, +# endif +# endif #endif }; @@ -80,12 +82,14 @@ static uint32_t const trun_mask[MAX_BLACKFIN_GPTIMERS] = TIMER_STATUS_TRUN5, TIMER_STATUS_TRUN6, TIMER_STATUS_TRUN7, -#endif -#if (MAX_BLACKFIN_GPTIMERS > 8) +# if (MAX_BLACKFIN_GPTIMERS > 8) TIMER_STATUS_TRUN8, TIMER_STATUS_TRUN9, TIMER_STATUS_TRUN10, +# if (MAX_BLACKFIN_GPTIMERS > 11) TIMER_STATUS_TRUN11, +# endif +# endif #endif }; @@ -100,12 +104,14 @@ static uint32_t const tovf_mask[MAX_BLACKFIN_GPTIMERS] = TIMER_STATUS_TOVF5, TIMER_STATUS_TOVF6, TIMER_STATUS_TOVF7, -#endif -#if (MAX_BLACKFIN_GPTIMERS > 8) +# if (MAX_BLACKFIN_GPTIMERS > 8) TIMER_STATUS_TOVF8, TIMER_STATUS_TOVF9, TIMER_STATUS_TOVF10, +# if (MAX_BLACKFIN_GPTIMERS > 11) TIMER_STATUS_TOVF11, +# endif +# endif #endif }; @@ -120,12 +126,14 @@ static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] = TIMER_STATUS_TIMIL5, TIMER_STATUS_TIMIL6, TIMER_STATUS_TIMIL7, -#endif -#if (MAX_BLACKFIN_GPTIMERS > 8) +# if (MAX_BLACKFIN_GPTIMERS > 8) TIMER_STATUS_TIMIL8, TIMER_STATUS_TIMIL9, TIMER_STATUS_TIMIL10, +# if (MAX_BLACKFIN_GPTIMERS > 11) TIMER_STATUS_TIMIL11, +# endif +# endif #endif }; diff --git a/include/asm-blackfin/gptimers.h b/include/asm-blackfin/gptimers.h index 4f318f1fd2d..0520d2aac8f 100644 --- a/include/asm-blackfin/gptimers.h +++ b/include/asm-blackfin/gptimers.h @@ -21,6 +21,18 @@ # define MAX_BLACKFIN_GPTIMERS 8 # define TIMER0_GROUP_REG TIMER_ENABLE #endif +/* + * BF54x: 11 timers (BF542: 8 timers): + */ +#if defined(BF548_FAMILY) +# ifdef CONFIG_BF542 +# define MAX_BLACKFIN_GPTIMERS 8 +# else +# define MAX_BLACKFIN_GPTIMERS 11 +# define TIMER8_GROUP_REG TIMER_ENABLE1 +# endif +# define TIMER0_GROUP_REG TIMER_ENABLE0 +#endif /* * BF561: 12 timers: */ @@ -44,40 +56,28 @@ #define TIMER0bit 0x0001 /* 0001b */ #define TIMER1bit 0x0002 /* 0010b */ #define TIMER2bit 0x0004 /* 0100b */ - -#if (MAX_BLACKFIN_GPTIMERS > 3) -# define TIMER3bit 0x0008 -# define TIMER4bit 0x0010 -# define TIMER5bit 0x0020 -# define TIMER6bit 0x0040 -# define TIMER7bit 0x0080 -#endif - -#if (MAX_BLACKFIN_GPTIMERS > 8) -# define TIMER8bit 0x0100 -# define TIMER9bit 0x0200 -# define TIMER10bit 0x0400 -# define TIMER11bit 0x0800 -#endif +#define TIMER3bit 0x0008 +#define TIMER4bit 0x0010 +#define TIMER5bit 0x0020 +#define TIMER6bit 0x0040 +#define TIMER7bit 0x0080 +#define TIMER8bit 0x0100 +#define TIMER9bit 0x0200 +#define TIMER10bit 0x0400 +#define TIMER11bit 0x0800 #define TIMER0_id 0 #define TIMER1_id 1 #define TIMER2_id 2 - -#if (MAX_BLACKFIN_GPTIMERS > 3) -# define TIMER3_id 3 -# define TIMER4_id 4 -# define TIMER5_id 5 -# define TIMER6_id 6 -# define TIMER7_id 7 -#endif - -#if (MAX_BLACKFIN_GPTIMERS > 8) -# define TIMER8_id 8 -# define TIMER9_id 9 -# define TIMER10_id 10 -# define TIMER11_id 11 -#endif +#define TIMER3_id 3 +#define TIMER4_id 4 +#define TIMER5_id 5 +#define TIMER6_id 6 +#define TIMER7_id 7 +#define TIMER8_id 8 +#define TIMER9_id 9 +#define TIMER10_id 10 +#define TIMER11_id 11 /* associated timers for ppi framesync: */ @@ -124,45 +124,31 @@ /* * Timer Status Register Bits */ -#define TIMER_STATUS_TIMIL0 0x0001 -#define TIMER_STATUS_TIMIL1 0x0002 -#define TIMER_STATUS_TIMIL2 0x0004 -#if (MAX_BLACKFIN_GPTIMERS > 3) -# define TIMER_STATUS_TIMIL3 0x00000008 -# define TIMER_STATUS_TIMIL4 0x00010000 -# define TIMER_STATUS_TIMIL5 0x00020000 -# define TIMER_STATUS_TIMIL6 0x00040000 -# define TIMER_STATUS_TIMIL7 0x00080000 -# if (MAX_BLACKFIN_GPTIMERS > 8) -# define TIMER_STATUS_TIMIL8 0x0001 -# define TIMER_STATUS_TIMIL9 0x0002 -# define TIMER_STATUS_TIMIL10 0x0004 -# define TIMER_STATUS_TIMIL11 0x0008 -# endif -# define TIMER_STATUS_INTR 0x000F000F -#else -# define TIMER_STATUS_INTR 0x0007 /* any timer interrupt */ -#endif - -#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */ -#define TIMER_STATUS_TOVF1 0x0020 -#define TIMER_STATUS_TOVF2 0x0040 -#if (MAX_BLACKFIN_GPTIMERS > 3) -# define TIMER_STATUS_TOVF3 0x00000080 -# define TIMER_STATUS_TOVF4 0x00100000 -# define TIMER_STATUS_TOVF5 0x00200000 -# define TIMER_STATUS_TOVF6 0x00400000 -# define TIMER_STATUS_TOVF7 0x00800000 -# if (MAX_BLACKFIN_GPTIMERS > 8) -# define TIMER_STATUS_TOVF8 0x0010 -# define TIMER_STATUS_TOVF9 0x0020 -# define TIMER_STATUS_TOVF10 0x0040 -# define TIMER_STATUS_TOVF11 0x0080 -# endif -# define TIMER_STATUS_OFLOW 0x00F000F0 -#else -# define TIMER_STATUS_OFLOW 0x0070 /* any timer overflow */ -#endif +#define TIMER_STATUS_TIMIL0 0x0001 +#define TIMER_STATUS_TIMIL1 0x0002 +#define TIMER_STATUS_TIMIL2 0x0004 +#define TIMER_STATUS_TIMIL3 0x00000008 +#define TIMER_STATUS_TIMIL4 0x00010000 +#define TIMER_STATUS_TIMIL5 0x00020000 +#define TIMER_STATUS_TIMIL6 0x00040000 +#define TIMER_STATUS_TIMIL7 0x00080000 +#define TIMER_STATUS_TIMIL8 0x0001 +#define TIMER_STATUS_TIMIL9 0x0002 +#define TIMER_STATUS_TIMIL10 0x0004 +#define TIMER_STATUS_TIMIL11 0x0008 + +#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */ +#define TIMER_STATUS_TOVF1 0x0020 +#define TIMER_STATUS_TOVF2 0x0040 +#define TIMER_STATUS_TOVF3 0x00000080 +#define TIMER_STATUS_TOVF4 0x00100000 +#define TIMER_STATUS_TOVF5 0x00200000 +#define TIMER_STATUS_TOVF6 0x00400000 +#define TIMER_STATUS_TOVF7 0x00800000 +#define TIMER_STATUS_TOVF8 0x0010 +#define TIMER_STATUS_TOVF9 0x0020 +#define TIMER_STATUS_TOVF10 0x0040 +#define TIMER_STATUS_TOVF11 0x0080 /* * Timer Slave Enable Status : write 1 to clear @@ -170,22 +156,16 @@ #define TIMER_STATUS_TRUN0 0x1000 #define TIMER_STATUS_TRUN1 0x2000 #define TIMER_STATUS_TRUN2 0x4000 -#if (MAX_BLACKFIN_GPTIMERS > 3) -# define TIMER_STATUS_TRUN3 0x00008000 -# define TIMER_STATUS_TRUN4 0x10000000 -# define TIMER_STATUS_TRUN5 0x20000000 -# define TIMER_STATUS_TRUN6 0x40000000 -# define TIMER_STATUS_TRUN7 0x80000000 -# define TIMER_STATUS_TRUN 0xF000F000 -# if (MAX_BLACKFIN_GPTIMERS > 8) -# define TIMER_STATUS_TRUN8 0x1000 -# define TIMER_STATUS_TRUN9 0x2000 -# define TIMER_STATUS_TRUN10 0x4000 -# define TIMER_STATUS_TRUN11 0x8000 -# endif -#else -# define TIMER_STATUS_TRUN 0x7000 -#endif +#define TIMER_STATUS_TRUN3 0x00008000 +#define TIMER_STATUS_TRUN4 0x10000000 +#define TIMER_STATUS_TRUN5 0x20000000 +#define TIMER_STATUS_TRUN6 0x40000000 +#define TIMER_STATUS_TRUN7 0x80000000 +#define TIMER_STATUS_TRUN 0xF000F000 +#define TIMER_STATUS_TRUN8 0x1000 +#define TIMER_STATUS_TRUN9 0x2000 +#define TIMER_STATUS_TRUN10 0x4000 +#define TIMER_STATUS_TRUN11 0x8000 /* The actual gptimer API */ -- cgit v1.2.3 From c5b50df8f071f0f28cbac3909929149acab6c170 Mon Sep 17 00:00:00 2001 From: Meihui Fan Date: Wed, 23 Apr 2008 08:55:26 +0800 Subject: [Blackfin] arch: fix bug - make sure we check the right L1 length Signed-off-by: Meihui Fan Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/mm/blackfin_sram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/blackfin/mm/blackfin_sram.c b/arch/blackfin/mm/blackfin_sram.c index e41f0e8ecac..3246f91c7ba 100644 --- a/arch/blackfin/mm/blackfin_sram.c +++ b/arch/blackfin/mm/blackfin_sram.c @@ -401,7 +401,7 @@ EXPORT_SYMBOL(l1_data_sram_free); void *l1_inst_sram_alloc(size_t size) { -#if L1_DATA_A_LENGTH != 0 +#if L1_CODE_LENGTH != 0 unsigned flags; void *addr; -- cgit v1.2.3 From 6b13483ba2c9c90fc34c79b44be418b56b6a756c Mon Sep 17 00:00:00 2001 From: Meihui Fan Date: Wed, 23 Apr 2008 09:07:25 +0800 Subject: [Blackfin] arch: remove unused/incorrect definition Signed-off-by: Meihui Fan Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/bfin-global.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h index 5dba3a73559..08474eb28bb 100644 --- a/include/asm-blackfin/bfin-global.h +++ b/include/asm-blackfin/bfin-global.h @@ -125,7 +125,6 @@ extern unsigned long table_start, table_end; extern unsigned long bfin_sic_iwr[]; extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ extern struct file_operations dpmc_fops; -extern char _start; extern unsigned long _ramstart, _ramend, _rambase; extern unsigned long memory_start, memory_end, physical_mem_end; extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[], -- cgit v1.2.3 From b85d858b40a28107ee50ca9e89f57c0e35c251c6 Mon Sep 17 00:00:00 2001 From: Harvey Harrison Date: Wed, 23 Apr 2008 09:39:01 +0800 Subject: [Blackfin] arch: __FUNCTION__ is gcc-specific, use __func__ Signed-off-by: Harvey Harrison Cc: Mike Frysinger Signed-off-by: Bryan Wu Signed-off-by: Andrew Morton Signed-off-by: Bryan Wu --- arch/blackfin/kernel/bfin_gpio.c | 8 ++++---- arch/blackfin/kernel/dma-mapping.c | 4 ++-- arch/blackfin/mach-bf527/boards/ezkit.c | 4 ++-- arch/blackfin/mach-bf533/boards/H8606.c | 2 +- arch/blackfin/mach-bf533/boards/cm_bf533.c | 2 +- arch/blackfin/mach-bf533/boards/ezkit.c | 2 +- arch/blackfin/mach-bf533/boards/generic_board.c | 2 +- arch/blackfin/mach-bf533/boards/stamp.c | 2 +- arch/blackfin/mach-bf537/boards/cm_bf537.c | 2 +- arch/blackfin/mach-bf537/boards/generic_board.c | 4 ++-- arch/blackfin/mach-bf537/boards/minotaur.c | 2 +- arch/blackfin/mach-bf537/boards/pnav10.c | 2 +- arch/blackfin/mach-bf537/boards/stamp.c | 4 ++-- arch/blackfin/mach-bf548/boards/ezkit.c | 2 +- arch/blackfin/mach-bf561/boards/cm_bf561.c | 2 +- arch/blackfin/mach-bf561/boards/ezkit.c | 2 +- arch/blackfin/mach-bf561/boards/generic_board.c | 2 +- arch/blackfin/mach-bf561/boards/tepla.c | 2 +- arch/blackfin/mach-common/ints-priority.c | 2 +- arch/blackfin/oprofile/common.c | 2 +- arch/blackfin/oprofile/op_model_bf533.c | 2 +- include/asm-blackfin/uaccess.h | 4 ++-- 22 files changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index b54dad505f8..7e8ceea9b5d 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -821,7 +821,7 @@ int peripheral_request(unsigned short per, const char *label) dump_stack(); printk(KERN_ERR "%s: Peripheral %d is already reserved as GPIO by %s !\n", - __FUNCTION__, ident, get_label(ident)); + __func__, ident, get_label(ident)); local_irq_restore(flags); return -EBUSY; } @@ -848,7 +848,7 @@ int peripheral_request(unsigned short per, const char *label) dump_stack(); printk(KERN_ERR "%s: Peripheral %d function %d is already reserved by %s !\n", - __FUNCTION__, ident, P_FUNCT2MUX(per), get_label(ident)); + __func__, ident, P_FUNCT2MUX(per), get_label(ident)); local_irq_restore(flags); return -EBUSY; } @@ -891,7 +891,7 @@ int peripheral_request(unsigned short per, const char *label) dump_stack(); printk(KERN_ERR "%s: Peripheral %d is already reserved as GPIO by %s !\n", - __FUNCTION__, ident, get_label(ident)); + __func__, ident, get_label(ident)); local_irq_restore(flags); return -EBUSY; } @@ -919,7 +919,7 @@ int peripheral_request(unsigned short per, const char *label) printk(KERN_ERR "%s: Peripheral %d function %d is already" " reserved by %s !\n", - __FUNCTION__, ident, P_FUNCT2MUX(per), + __func__, ident, P_FUNCT2MUX(per), get_label(ident)); local_irq_restore(flags); return -EBUSY; diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c index d6b61d56b65..2f62a9f4058 100644 --- a/arch/blackfin/kernel/dma-mapping.c +++ b/arch/blackfin/kernel/dma-mapping.c @@ -59,7 +59,7 @@ void dma_alloc_init(unsigned long start, unsigned long end) memset((void *)dma_base, 0, DMA_UNCACHED_REGION); dma_initialized = 1; - printk(KERN_INFO "%s: dma_page @ 0x%p - %d pages at 0x%08lx\n", __FUNCTION__, + printk(KERN_INFO "%s: dma_page @ 0x%p - %d pages at 0x%08lx\n", __func__, dma_page, dma_pages, dma_base); } @@ -100,7 +100,7 @@ static void __free_dma_pages(unsigned long addr, unsigned int pages) int i; if ((page + pages) > dma_pages) { - printk(KERN_ERR "%s: freeing outside range.\n", __FUNCTION__); + printk(KERN_ERR "%s: freeing outside range.\n", __func__); BUG(); } diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index cf4bc0d8335..1452391fe95 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -94,7 +94,7 @@ int __init bfin_isp1761_init(void) { unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices); - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); return platform_add_devices(bfin_isp1761_devices, num_devices); @@ -896,7 +896,7 @@ static struct platform_device *stamp_devices[] __initdata = { static int __init stamp_init(void) { - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) spi_register_board_info(bfin_spi_board_info, diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c index 97378b0a975..39c3dd3d595 100644 --- a/arch/blackfin/mach-bf533/boards/H8606.c +++ b/arch/blackfin/mach-bf533/boards/H8606.c @@ -411,7 +411,7 @@ static struct platform_device *h8606_devices[] __initdata = { static int __init H8606_init(void) { printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n"); - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); platform_add_devices(h8606_devices, ARRAY_SIZE(h8606_devices)); #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c index 886f260d935..7e7b7c9a5c8 100644 --- a/arch/blackfin/mach-bf533/boards/cm_bf533.c +++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c @@ -355,7 +355,7 @@ static struct platform_device *cm_bf533_devices[] __initdata = { static int __init cm_bf533_init(void) { - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices)); #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c index 241b5a20a36..35c1efdf8e1 100644 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ b/arch/blackfin/mach-bf533/boards/ezkit.c @@ -369,7 +369,7 @@ static struct platform_device *ezkit_devices[] __initdata = { static int __init ezkit_init(void) { - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices)); #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); diff --git a/arch/blackfin/mach-bf533/boards/generic_board.c b/arch/blackfin/mach-bf533/boards/generic_board.c index e359a0d6467..82b1f6a60e3 100644 --- a/arch/blackfin/mach-bf533/boards/generic_board.c +++ b/arch/blackfin/mach-bf533/boards/generic_board.c @@ -84,7 +84,7 @@ static struct platform_device *generic_board_devices[] __initdata = { static int __init generic_board_init(void) { - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); return platform_add_devices(generic_board_devices, ARRAY_SIZE(generic_board_devices)); } diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index 32b37afc6e6..3a727d3676e 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c @@ -553,7 +553,7 @@ static int __init stamp_init(void) { int ret; - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); #ifdef CONFIG_I2C_BOARDINFO i2c_register_board_info(0, bfin_i2c_board_info, diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c index b575b23fe69..199fde69b96 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c @@ -451,7 +451,7 @@ static struct platform_device *cm_bf537_devices[] __initdata = { static int __init cm_bf537_init(void) { - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices)); #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c index c95395ba7bf..b3d78ea755c 100644 --- a/arch/blackfin/mach-bf537/boards/generic_board.c +++ b/arch/blackfin/mach-bf537/boards/generic_board.c @@ -90,7 +90,7 @@ int __init bfin_isp1761_init(void) { unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices); - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); return platform_add_devices(bfin_isp1761_devices, num_devices); @@ -690,7 +690,7 @@ static struct platform_device *stamp_devices[] __initdata = { static int __init stamp_init(void) { - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) spi_register_board_info(bfin_spi_board_info, diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c index d71e0be3392..815ad404588 100644 --- a/arch/blackfin/mach-bf537/boards/minotaur.c +++ b/arch/blackfin/mach-bf537/boards/minotaur.c @@ -297,7 +297,7 @@ static struct platform_device *minotaur_devices[] __initdata = { static int __init minotaur_init(void) { - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices)); #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) spi_register_board_info(bfin_spi_board_info, diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index 509a8a236fd..0b3e22b1b68 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c @@ -497,7 +497,7 @@ static struct platform_device *stamp_devices[] __initdata = { static int __init stamp_init(void) { - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) spi_register_board_info(bfin_spi_board_info, diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index f81a9b8a640..e95478252c8 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -91,7 +91,7 @@ int __init bfin_isp1761_init(void) { unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices); - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); return platform_add_devices(bfin_isp1761_devices, num_devices); @@ -854,7 +854,7 @@ static struct platform_device *stamp_devices[] __initdata = { static int __init stamp_init(void) { - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); #ifdef CONFIG_I2C_BOARDINFO i2c_register_board_info(0, bfin_i2c_board_info, diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 04c0c8df6e9..acbfb0fc028 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -695,7 +695,7 @@ static struct platform_device *ezkit_devices[] __initdata = { static int __init ezkit_init(void) { - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); #ifdef CONFIG_I2C_BOARDINFO i2c_register_board_info(0, bfin_i2c_board_info0, diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c index bf9e738a7c6..4a3e0853f2a 100644 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c @@ -349,7 +349,7 @@ static struct platform_device *cm_bf561_devices[] __initdata = { static int __init cm_bf561_init(void) { - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); platform_add_devices(cm_bf561_devices, ARRAY_SIZE(cm_bf561_devices)); #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 79a55b42e96..984d654cc8d 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -78,7 +78,7 @@ int __init bfin_isp1761_init(void) { unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices); - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); return platform_add_devices(bfin_isp1761_devices, num_devices); diff --git a/arch/blackfin/mach-bf561/boards/generic_board.c b/arch/blackfin/mach-bf561/boards/generic_board.c index fc80c5d059f..2faa0072d61 100644 --- a/arch/blackfin/mach-bf561/boards/generic_board.c +++ b/arch/blackfin/mach-bf561/boards/generic_board.c @@ -70,7 +70,7 @@ static struct platform_device *generic_board_devices[] __initdata = { static int __init generic_board_init(void) { - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); return platform_add_devices(generic_board_devices, ARRAY_SIZE(generic_board_devices)); } diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c index ec6a2207c20..c9174b39f98 100644 --- a/arch/blackfin/mach-bf561/boards/tepla.c +++ b/arch/blackfin/mach-bf561/boards/tepla.c @@ -50,7 +50,7 @@ static struct platform_device *tepla_devices[] __initdata = { static int __init tepla_init(void) { - printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + printk(KERN_INFO "%s(): registering device resources\n", __func__); return platform_add_devices(tepla_devices, ARRAY_SIZE(tepla_devices)); } diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 225ef14af75..a2a11717bf6 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -316,7 +316,7 @@ static void bfin_demux_error_irq(unsigned int int_err_irq, printk(KERN_ERR "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR" " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", - __FUNCTION__, __FILE__, __LINE__); + __func__, __FILE__, __LINE__); } #endif /* BF537_GENERIC_ERROR_INT_DEMUX */ diff --git a/arch/blackfin/oprofile/common.c b/arch/blackfin/oprofile/common.c index cb8b8d5af34..0f6d303a889 100644 --- a/arch/blackfin/oprofile/common.c +++ b/arch/blackfin/oprofile/common.c @@ -75,7 +75,7 @@ static int op_bfin_start(void) { int ret = -EBUSY; - printk(KERN_INFO "KSDBG:in %s\n", __FUNCTION__); + printk(KERN_INFO "KSDBG:in %s\n", __func__); mutex_lock(&pfmon_lock); if (!pfmon_enabled) { ret = model->start(ctr); diff --git a/arch/blackfin/oprofile/op_model_bf533.c b/arch/blackfin/oprofile/op_model_bf533.c index 872dffe3362..d1c698bb9ee 100644 --- a/arch/blackfin/oprofile/op_model_bf533.c +++ b/arch/blackfin/oprofile/op_model_bf533.c @@ -125,7 +125,7 @@ int pm_overflow_handler(int irq, struct pt_regs *regs) unsigned int pc, pfctl; unsigned int count[2]; - pr_debug("get interrupt in %s\n", __FUNCTION__); + pr_debug("get interrupt in %s\n", __func__); if (oprofile_running == 0) { pr_debug("error: entering interrupt when oprofile is stopped.\n\r"); return -1; diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h index 22a410b8003..d928b809905 100644 --- a/include/asm-blackfin/uaccess.h +++ b/include/asm-blackfin/uaccess.h @@ -133,7 +133,7 @@ static inline int bad_user_access_length(void) } #define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\ - __FILE__, __LINE__, __FUNCTION__),\ + __FILE__, __LINE__, __func__),\ bad_user_access_length(), (-EFAULT)) /* @@ -177,7 +177,7 @@ static inline int bad_user_access_length(void) default: \ x = 0; \ printk(KERN_INFO "get_user_bad: %s:%d %s\n", \ - __FILE__, __LINE__, __FUNCTION__); \ + __FILE__, __LINE__, __func__); \ _err = __get_user_bad(); \ break; \ } \ -- cgit v1.2.3 From 1bee1a660ab42b33cbd39275de3dfdec3c62cee6 Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Thu, 24 Apr 2008 05:02:04 +0800 Subject: [Blackfin] arch: boards and machines defconfig updates Signed-off-by: Bryan Wu --- arch/blackfin/configs/BF527-EZKIT_defconfig | 6 +- arch/blackfin/configs/BF533-EZKIT_defconfig | 2 +- arch/blackfin/configs/BF533-STAMP_defconfig | 2 +- arch/blackfin/configs/BF537-STAMP_defconfig | 2 +- arch/blackfin/configs/BF548-EZKIT_defconfig | 6 +- arch/blackfin/configs/BF561-EZKIT_defconfig | 2 +- arch/blackfin/configs/CM-BF533_defconfig | 2 +- arch/blackfin/configs/CM-BF537E_defconfig | 2 +- arch/blackfin/configs/CM-BF537U_defconfig | 2 +- arch/blackfin/configs/CM-BF548_defconfig | 1373 +++++++++++++++++++++++++++ arch/blackfin/configs/CM-BF561_defconfig | 240 ++--- arch/blackfin/configs/H8606_defconfig | 2 +- arch/blackfin/configs/PNAV-10_defconfig | 2 +- arch/blackfin/configs/SRV1_defconfig | 1290 +++++++++++++++++++++++++ 14 files changed, 2743 insertions(+), 190 deletions(-) create mode 100644 arch/blackfin/configs/CM-BF548_defconfig create mode 100644 arch/blackfin/configs/SRV1_defconfig diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig index a50bf5fa99c..64876dfc2e5 100644 --- a/arch/blackfin/configs/BF527-EZKIT_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT_defconfig @@ -250,7 +250,7 @@ CONFIG_HZ=250 # # Memory Setup # -CONFIG_MEM_SIZE=64 +CONFIG_MAX_MEM_SIZE=512 CONFIG_MEM_ADD_WIDTH=10 CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y @@ -720,8 +720,8 @@ CONFIG_BFIN_OTP=y # CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_SERIAL_BFIN_DMA is not set -CONFIG_SERIAL_BFIN_PIO=y +CONFIG_SERIAL_BFIN_DMA=y +# CONFIG_SERIAL_BFIN_PIO is not set # CONFIG_SERIAL_BFIN_UART0 is not set CONFIG_SERIAL_BFIN_UART1=y # CONFIG_BFIN_UART1_CTSRTS is not set diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig index 29019961de2..8d817ba0194 100644 --- a/arch/blackfin/configs/BF533-EZKIT_defconfig +++ b/arch/blackfin/configs/BF533-EZKIT_defconfig @@ -212,7 +212,7 @@ CONFIG_HZ=250 # # Memory Setup # -CONFIG_MEM_SIZE=32 +CONFIG_MAX_MEM_SIZE=512 CONFIG_MEM_ADD_WIDTH=9 CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig index 080f7ab8c9a..20d598d17bd 100644 --- a/arch/blackfin/configs/BF533-STAMP_defconfig +++ b/arch/blackfin/configs/BF533-STAMP_defconfig @@ -212,7 +212,7 @@ CONFIG_HZ=250 # # Memory Setup # -CONFIG_MEM_SIZE=128 +CONFIG_MAX_MEM_SIZE=512 CONFIG_MEM_ADD_WIDTH=11 CONFIG_ENET_FLASH_PIN=0 CONFIG_BOOT_LOAD=0x1000 diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig index b9b87497c84..b5189c8ba26 100644 --- a/arch/blackfin/configs/BF537-STAMP_defconfig +++ b/arch/blackfin/configs/BF537-STAMP_defconfig @@ -220,7 +220,7 @@ CONFIG_HZ=250 # # Memory Setup # -CONFIG_MEM_SIZE=64 +CONFIG_MAX_MEM_SIZE=512 CONFIG_MEM_ADD_WIDTH=10 CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig index 06c0180b98d..5bfdfb287d1 100644 --- a/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/arch/blackfin/configs/BF548-EZKIT_defconfig @@ -285,7 +285,7 @@ CONFIG_HZ=250 # # Memory Setup # -CONFIG_MEM_SIZE=64 +CONFIG_MAX_MEM_SIZE=512 # CONFIG_MEM_MT46V32M16_6T is not set CONFIG_MEM_MT46V32M16_5B=y CONFIG_BOOT_LOAD=0x1000 @@ -813,8 +813,8 @@ CONFIG_HW_CONSOLE=y # CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_SERIAL_BFIN_DMA is not set -CONFIG_SERIAL_BFIN_PIO=y +CONFIG_SERIAL_BFIN_DMA=y +# CONFIG_SERIAL_BFIN_PIO is not set # CONFIG_SERIAL_BFIN_UART0 is not set CONFIG_SERIAL_BFIN_UART1=y # CONFIG_BFIN_UART1_CTSRTS is not set diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig index 073b32fe973..b4a20c89081 100644 --- a/arch/blackfin/configs/BF561-EZKIT_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT_defconfig @@ -256,7 +256,7 @@ CONFIG_HZ=250 # # Memory Setup # -CONFIG_MEM_SIZE=64 +CONFIG_MAX_MEM_SIZE=512 CONFIG_MEM_ADD_WIDTH=9 CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig index fdfdee31801..560890fe0d3 100644 --- a/arch/blackfin/configs/CM-BF533_defconfig +++ b/arch/blackfin/configs/CM-BF533_defconfig @@ -210,7 +210,7 @@ CONFIG_HZ=250 # # Memory Setup # -CONFIG_MEM_SIZE=32 +CONFIG_MAX_MEM_SIZE=32 CONFIG_MEM_ADD_WIDTH=9 CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig index 36a7244eefc..9f66d2de100 100644 --- a/arch/blackfin/configs/CM-BF537E_defconfig +++ b/arch/blackfin/configs/CM-BF537E_defconfig @@ -218,7 +218,7 @@ CONFIG_HZ=250 # # Memory Setup # -CONFIG_MEM_SIZE=32 +CONFIG_MAX_MEM_SIZE=32 CONFIG_MEM_ADD_WIDTH=9 CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig index 3bb7ed3fd79..2694d06c5bd 100644 --- a/arch/blackfin/configs/CM-BF537U_defconfig +++ b/arch/blackfin/configs/CM-BF537U_defconfig @@ -218,7 +218,7 @@ CONFIG_HZ=250 # # Memory Setup # -CONFIG_MEM_SIZE=32 +CONFIG_MAX_MEM_SIZE=32 CONFIG_MEM_ADD_WIDTH=9 CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig new file mode 100644 index 00000000000..90207251c53 --- /dev/null +++ b/arch/blackfin/configs/CM-BF548_defconfig @@ -0,0 +1,1373 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.24.4 +# +# CONFIG_MMU is not set +# CONFIG_FPU is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +CONFIG_BLACKFIN=y +CONFIG_ZONE_DMA=y +CONFIG_SEMAPHORE_SLEEPERS=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_GPIO=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set + +# +# Blackfin Processor Options +# + +# +# Processor and Board Settings +# +# CONFIG_BF522 is not set +# CONFIG_BF523 is not set +# CONFIG_BF524 is not set +# CONFIG_BF525 is not set +# CONFIG_BF526 is not set +# CONFIG_BF527 is not set +# CONFIG_BF531 is not set +# CONFIG_BF532 is not set +# CONFIG_BF533 is not set +# CONFIG_BF534 is not set +# CONFIG_BF536 is not set +# CONFIG_BF537 is not set +# CONFIG_BF542 is not set +# CONFIG_BF544 is not set +# CONFIG_BF547 is not set +CONFIG_BF548=y +# CONFIG_BF549 is not set +# CONFIG_BF561 is not set +CONFIG_BF_REV_0_0=y +# CONFIG_BF_REV_0_1 is not set +# CONFIG_BF_REV_0_2 is not set +# CONFIG_BF_REV_0_3 is not set +# CONFIG_BF_REV_0_4 is not set +# CONFIG_BF_REV_0_5 is not set +# CONFIG_BF_REV_ANY is not set +# CONFIG_BF_REV_NONE is not set +CONFIG_BF54x=y +CONFIG_IRQ_PLL_WAKEUP=7 +CONFIG_IRQ_RTC=8 +CONFIG_IRQ_SPORT0_RX=9 +CONFIG_IRQ_SPORT0_TX=9 +CONFIG_IRQ_SPORT1_RX=9 +CONFIG_IRQ_SPORT1_TX=9 +CONFIG_IRQ_UART0_RX=10 +CONFIG_IRQ_UART0_TX=10 +CONFIG_IRQ_UART1_RX=10 +CONFIG_IRQ_UART1_TX=10 +CONFIG_IRQ_CNT=8 +CONFIG_IRQ_USB_INT0=11 +CONFIG_IRQ_USB_INT1=11 +CONFIG_IRQ_USB_INT2=11 +CONFIG_IRQ_USB_DMA=11 +CONFIG_IRQ_TIMER0=11 +CONFIG_IRQ_TIMER1=11 +CONFIG_IRQ_TIMER2=11 +CONFIG_IRQ_TIMER3=11 +CONFIG_IRQ_TIMER4=11 +CONFIG_IRQ_TIMER5=11 +CONFIG_IRQ_TIMER6=11 +CONFIG_IRQ_TIMER7=11 +CONFIG_IRQ_TIMER8=11 +CONFIG_IRQ_TIMER9=11 +CONFIG_IRQ_TIMER10=11 +# CONFIG_BFIN548_EZKIT is not set +CONFIG_BFIN548_BLUETECHNIX_CM=y + +# +# BF548 Specific Configuration +# +# CONFIG_DEB_DMA_URGENT is not set + +# +# Interrupt Priority Assignment +# + +# +# Priority +# +CONFIG_IRQ_DMAC0_ERR=7 +CONFIG_IRQ_EPPI0_ERR=7 +CONFIG_IRQ_SPORT0_ERR=7 +CONFIG_IRQ_SPORT1_ERR=7 +CONFIG_IRQ_SPI0_ERR=7 +CONFIG_IRQ_UART0_ERR=7 +CONFIG_IRQ_EPPI0=8 +CONFIG_IRQ_SPI0=10 +CONFIG_IRQ_PINT0=12 +CONFIG_IRQ_PINT1=12 +CONFIG_IRQ_MDMAS0=13 +CONFIG_IRQ_MDMAS1=13 +CONFIG_IRQ_WATCHDOG=13 +CONFIG_IRQ_DMAC1_ERR=7 +CONFIG_IRQ_SPORT2_ERR=7 +CONFIG_IRQ_SPORT3_ERR=7 +CONFIG_IRQ_MXVR_DATA=7 +CONFIG_IRQ_SPI1_ERR=7 +CONFIG_IRQ_SPI2_ERR=7 +CONFIG_IRQ_UART1_ERR=7 +CONFIG_IRQ_UART2_ERR=7 +CONFIG_IRQ_CAN0_ERR=7 +CONFIG_IRQ_SPORT2_RX=9 +CONFIG_IRQ_SPORT2_TX=9 +CONFIG_IRQ_SPORT3_RX=9 +CONFIG_IRQ_SPORT3_TX=9 +CONFIG_IRQ_EPPI1=9 +CONFIG_IRQ_EPPI2=9 +CONFIG_IRQ_SPI1=10 +CONFIG_IRQ_SPI2=10 +CONFIG_IRQ_ATAPI_RX=10 +CONFIG_IRQ_ATAPI_TX=10 +CONFIG_IRQ_TWI0=11 +CONFIG_IRQ_TWI1=11 +CONFIG_IRQ_CAN0_RX=11 +CONFIG_IRQ_CAN0_TX=11 +CONFIG_IRQ_MDMAS2=13 +CONFIG_IRQ_MDMAS3=13 +CONFIG_IRQ_MXVR_ERR=11 +CONFIG_IRQ_MXVR_MSG=11 +CONFIG_IRQ_MXVR_PKT=11 +CONFIG_IRQ_EPPI1_ERR=7 +CONFIG_IRQ_EPPI2_ERR=7 +CONFIG_IRQ_UART3_ERR=7 +CONFIG_IRQ_HOST_ERR=7 +CONFIG_IRQ_PIXC_ERR=7 +CONFIG_IRQ_NFC_ERR=7 +CONFIG_IRQ_ATAPI_ERR=7 +CONFIG_IRQ_CAN1_ERR=7 +CONFIG_IRQ_HS_DMA_ERR=7 +CONFIG_IRQ_PIXC_IN0=8 +CONFIG_IRQ_PIXC_IN1=8 +CONFIG_IRQ_PIXC_OUT=8 +CONFIG_IRQ_SDH=8 +CONFIG_IRQ_KEY=8 +CONFIG_IRQ_CAN1_RX=11 +CONFIG_IRQ_CAN1_TX=11 +CONFIG_IRQ_SDH_MASK0=11 +CONFIG_IRQ_SDH_MASK1=11 +CONFIG_IRQ_OTPSEC=11 +CONFIG_IRQ_PINT2=11 +CONFIG_IRQ_PINT3=11 + +# +# Pin Interrupt to Port Assignment +# + +# +# Assignment +# +CONFIG_PINTx_REASSIGN=y +CONFIG_PINT0_ASSIGN=0x00000101 +CONFIG_PINT1_ASSIGN=0x01010000 +CONFIG_PINT2_ASSIGN=0x07000101 +CONFIG_PINT3_ASSIGN=0x02020303 + +# +# Board customizations +# +# CONFIG_CMDLINE_BOOL is not set + +# +# Clock/PLL Setup +# +CONFIG_CLKIN_HZ=25000000 +# CONFIG_BFIN_KERNEL_CLOCK is not set +CONFIG_MAX_VCO_HZ=600000000 +CONFIG_MIN_VCO_HZ=50000000 +CONFIG_MAX_SCLK_HZ=133333333 +CONFIG_MIN_SCLK_HZ=27000000 + +# +# Kernel Timer/Scheduler +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +# CONFIG_GENERIC_TIME is not set +# CONFIG_TICK_ONESHOT is not set + +# +# Memory Setup +# +CONFIG_MAX_MEM_SIZE=64 +# CONFIG_MEM_MT46V32M16_6T is not set +CONFIG_MEM_MT46V32M16_5B=y +CONFIG_BOOT_LOAD=0x1000 +CONFIG_BFIN_SCRATCH_REG_RETN=y +# CONFIG_BFIN_SCRATCH_REG_RETE is not set +# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set + +# +# Blackfin Kernel Optimizations +# + +# +# Memory Optimizations +# +CONFIG_I_ENTRY_L1=y +CONFIG_EXCPT_IRQ_SYSC_L1=y +CONFIG_DO_IRQ_L1=y +CONFIG_CORE_TIMER_IRQ_L1=y +CONFIG_IDLE_L1=y +# CONFIG_SCHEDULE_L1 is not set +CONFIG_ARITHMETIC_OPS_L1=y +CONFIG_ACCESS_OK_L1=y +# CONFIG_MEMSET_L1 is not set +# CONFIG_MEMCPY_L1 is not set +# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set +# CONFIG_IP_CHECKSUM_L1 is not set +CONFIG_CACHELINE_ALIGNED_L1=y +# CONFIG_SYSCALL_TAB_L1 is not set +# CONFIG_CPLB_SWITCH_TAB_L1 is not set +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_VIRT_TO_BUS=y +# CONFIG_BFIN_GPTIMERS is not set +CONFIG_BFIN_DMA_5XX=y +# CONFIG_DMA_UNCACHED_2M is not set +CONFIG_DMA_UNCACHED_1M=y +# CONFIG_DMA_UNCACHED_NONE is not set + +# +# Cache Support +# +CONFIG_BFIN_ICACHE=y +CONFIG_BFIN_DCACHE=y +# CONFIG_BFIN_DCACHE_BANKA is not set +# CONFIG_BFIN_ICACHE_LOCK is not set +# CONFIG_BFIN_WB is not set +CONFIG_BFIN_WT=y +CONFIG_L1_MAX_PIECE=16 +# CONFIG_MPU is not set + +# +# Asynchonous Memory Configuration +# + +# +# EBIU_AMGCTL Global Control +# +CONFIG_C_AMCKEN=y +# CONFIG_C_CDPRIO is not set +# CONFIG_C_AMBEN is not set +# CONFIG_C_AMBEN_B0 is not set +# CONFIG_C_AMBEN_B0_B1 is not set +# CONFIG_C_AMBEN_B0_B1_B2 is not set +CONFIG_C_AMBEN_ALL=y + +# +# EBIU_AMBCTL Control +# +CONFIG_BANK_0=0x7BB0 +CONFIG_BANK_1=0x5554 +CONFIG_BANK_2=0x7BB0 +CONFIG_BANK_3=0x99B3 +CONFIG_EBIU_MBSCTLVAL=0x0 +CONFIG_EBIU_MODEVAL=0x1 +CONFIG_EBIU_FCTLVAL=0x6 + +# +# Bus options (PCI, PCMCIA, EISA, MCA, ISA) +# +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF_FDPIC=y +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +# CONFIG_BINFMT_SHARED_FLAT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_SUSPEND_UP_POSSIBLE=y +# CONFIG_PM_WAKEUP_BY_GPIO is not set + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETLABEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x20000000 +CONFIG_MTD_PHYSMAP_LEN=0x800000 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_UCLINUX is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_SMC91X is not set +CONFIG_SMSC911X=y +# CONFIG_DM9000 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_BFIN is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PPIFCD is not set +# CONFIG_BFIN_SIMPLE_TIMER is not set +# CONFIG_BF5xx_PPI is not set +CONFIG_BFIN_OTP=y +# CONFIG_BFIN_OTP_WRITE_ENABLE is not set +# CONFIG_BFIN_SPORT is not set +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_TWI_LCD is not set +# CONFIG_SIMPLE_GPIO is not set +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_BFIN=y +CONFIG_SERIAL_BFIN_CONSOLE=y +# CONFIG_SERIAL_BFIN_DMA is not set +CONFIG_SERIAL_BFIN_PIO=y +# CONFIG_SERIAL_BFIN_UART0 is not set +CONFIG_SERIAL_BFIN_UART1=y +# CONFIG_BFIN_UART1_CTSRTS is not set +# CONFIG_SERIAL_BFIN_UART2 is not set +# CONFIG_SERIAL_BFIN_UART3 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_BFIN_SPORT is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set + +# +# CAN, the car bus and industrial fieldbus +# +# CONFIG_CAN4LINUX is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +CONFIG_I2C_BLACKFIN_TWI=y +CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_AD5252 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCF8575 is not set +# CONFIG_SENSORS_PCA9543 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BFIN=y +# CONFIG_SPI_BITBANG is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_BFIN_WDT=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_SOC=y + +# +# Blackfin BF54x, BF525 and BF527 high speed USB support +# +CONFIG_USB_MUSB_HOST=y +# CONFIG_USB_MUSB_PERIPHERAL is not set +# CONFIG_USB_MUSB_OTG is not set +CONFIG_USB_MUSB_HDRC_HCD=y +# CONFIG_MUSB_PIO_ONLY is not set +# CONFIG_USB_INVENTRA_DMA is not set +# CONFIG_USB_TI_CPPI_DMA is not set +CONFIG_USB_MUSB_LOGLEVEL=0 + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set + +# +# MMC/SD Host Controller Drivers +# +CONFIG_SDH_BFIN=y +# CONFIG_MMC_SPI is not set +# CONFIG_SPI_MMC is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_BFIN=y + +# +# Userspace I/O +# +# CONFIG_UIO is not set + +# +# PBX support +# +# CONFIG_PBX is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_YAFFS_FS=m +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set +CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10 +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_NFSD_TCP=y +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +CONFIG_SMB_NLS_DEFAULT=y +CONFIG_SMB_NLS_REMOTE="cp437" +CONFIG_CIFS=y +# CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_XATTR is not set +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_EXPERIMENTAL is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set +CONFIG_INSTRUMENTATION=y +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_SAMPLES is not set +# CONFIG_DEBUG_MMRS is not set +CONFIG_DEBUG_HUNT_FOR_ZERO=y +CONFIG_DEBUG_BFIN_HWTRACE_ON=y +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y +# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set +# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 +# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set +# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set +# CONFIG_EARLY_PRINTK is not set +CONFIG_CPLB_INFO=y +CONFIG_ACCESS_CHECK=y + +# +# Security options +# +# CONFIG_KEYS is not set +CONFIG_SECURITY=y +# CONFIG_SECURITY_NETWORK is not set +# CONFIG_SECURITY_CAPABILITIES is not set +# CONFIG_SECURITY_ROOTPLUG is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig index 7157bf4a1c5..daf00906c1e 100644 --- a/arch/blackfin/configs/CM-BF561_defconfig +++ b/arch/blackfin/configs/CM-BF561_defconfig @@ -1,6 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.22.16 +# Linux kernel version: 2.6.24.4 +# Tue Apr 1 10:50:11 2008 # # CONFIG_MMU is not set # CONFIG_FPU is not set @@ -13,34 +14,33 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y # CONFIG_RELAY is not set # CONFIG_BLK_DEV_INITRD is not set @@ -67,27 +67,21 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 - -# -# Loadable module support -# CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_KMOD=y - -# -# Block layer -# CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set # # IO Schedulers @@ -250,12 +244,18 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +# CONFIG_CYCLES_CLOCKSOURCE is not set +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # # Memory Setup # -CONFIG_MEM_SIZE=32 -CONFIG_MEM_ADD_WIDTH=9 +CONFIG_MAX_MEM_SIZE=32 CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y # CONFIG_BFIN_SCRATCH_REG_RETE is not set @@ -292,9 +292,11 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 +CONFIG_VIRT_TO_BUS=y CONFIG_LARGE_ALLOCS=y # CONFIG_BFIN_GPTIMERS is not set CONFIG_BFIN_DMA_5XX=y @@ -347,10 +349,6 @@ CONFIG_BANK_3=0xFFC3 # CONFIG_PCI is not set # CONFIG_ARCH_SUPPORTS_MSI is not set -# -# PCCARD (PCMCIA/CardBus) support -# - # # Executable file formats # @@ -364,6 +362,7 @@ CONFIG_BINFMT_SHARED_FLAT=y # Power management options # # CONFIG_PM is not set +CONFIG_SUSPEND_UP_POSSIBLE=y # CONFIG_PM_WAKEUP_BY_GPIO is not set # @@ -399,6 +398,7 @@ CONFIG_SYN_COOKIES=y CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set @@ -425,10 +425,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# # CONFIG_NET_SCHED is not set # @@ -448,6 +444,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -459,10 +456,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set @@ -482,6 +475,7 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -530,20 +524,8 @@ CONFIG_MTD_UCLINUX=y # UBI - Unsorted block images # # CONFIG_MTD_UBI is not set - -# -# Parallel port support -# # CONFIG_PARPORT is not set - -# -# Plug and Play support -# -# CONFIG_PNPACPI is not set - -# -# Block devices -# +CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set @@ -553,73 +535,40 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set - -# -# Misc devices -# -CONFIG_IDE=m -CONFIG_IDE_MAX_HWIFS=4 -CONFIG_BLK_DEV_IDE=m - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=m -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_IDE_TASK_IOCTL is not set -CONFIG_IDE_PROC_FS=y - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=m -CONFIG_IDE_BFIN=y -CONFIG_BFIN_IDE_ADDRESS_MAPPING_MODE0=y +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IDE is not set +# CONFIG_BFIN_IDE_ADDRESS_MAPPING_MODE0 is not set # CONFIG_BFIN_IDE_ADDRESS_MAPPING_MODE1 is not set -CONFIG_BFIN_IDE_BASE=0x2400C000 -CONFIG_BFIN_IDE_ALT=0x2400D018 -CONFIG_BFIN_IDE_IRQ_PFX=46 -CONFIG_BFIN_IDE_GAP=4 -# CONFIG_IDEPCI_PCIBUS_ORDER is not set -# CONFIG_IDE_ARM is not set -# CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_BLK_DEV_HD is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set # CONFIG_SCSI_NETLINK is not set # CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# # CONFIG_MD is not set - -# -# Network device support -# CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_VETH is not set # CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# CONFIG_NET_ETHERNET=y CONFIG_MII=y CONFIG_SMC91X=y # CONFIG_SMSC911X is not set # CONFIG_DM9000 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set CONFIG_NETDEV_1000=y # CONFIG_AX88180 is not set CONFIG_NETDEV_10000=y @@ -636,15 +585,7 @@ CONFIG_NETDEV_10000=y # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set - -# -# Telephony Support -# # CONFIG_PHONE is not set # @@ -663,12 +604,12 @@ CONFIG_NETDEV_10000=y # # CONFIG_AD9960 is not set # CONFIG_SPI_ADC_BF533 is not set -# CONFIG_BF5xx_PFLAGS is not set # CONFIG_BF5xx_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set # CONFIG_BF5xx_PPI is not set # CONFIG_BFIN_SPORT is not set # CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_SIMPLE_GPIO is not set # CONFIG_VT is not set # CONFIG_SERIAL_NONSTANDARD is not set @@ -697,20 +638,11 @@ CONFIG_LEGACY_PTY_COUNT=256 # CAN, the car bus and industrial fieldbus # # CONFIG_CAN4LINUX is not set - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set -# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set # CONFIG_GEN_RTC is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# # CONFIG_TCG_TPM is not set # CONFIG_I2C is not set @@ -719,21 +651,28 @@ CONFIG_LEGACY_PTY_COUNT=256 # # CONFIG_SPI is not set # CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# # CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ABITUGURU is not set # CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set # # Multifunction device drivers @@ -750,23 +689,21 @@ CONFIG_DAB=y # # Graphics support # +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set -# CONFIG_VGASTATE is not set -# CONFIG_FB is not set # # Sound # # CONFIG_SOUND is not set - -# -# USB support -# +CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_USB_ARCH_HAS_OHCI is not set # CONFIG_USB_ARCH_HAS_EHCI is not set @@ -785,45 +722,13 @@ CONFIG_USB_ARCH_HAS_HCD=y # # CONFIG_USB_GADGET is not set # CONFIG_MMC is not set - -# -# LED devices -# # CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# # CONFIG_RTC_CLASS is not set # -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices +# Userspace I/O # +# CONFIG_UIO is not set # # PBX support @@ -877,7 +782,6 @@ CONFIG_PROC_SYSCTL=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set # @@ -898,10 +802,7 @@ CONFIG_RAMFS=y # CONFIG_QNX4FS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y # CONFIG_NFS_FS is not set # CONFIG_NFSD is not set # CONFIG_SMB_FS is not set @@ -909,33 +810,23 @@ CONFIG_RAMFS=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# # CONFIG_NLS is not set - -# -# Distributed Lock Manager -# # CONFIG_DLM is not set - -# -# Profiling support -# +CONFIG_INSTRUMENTATION=y # CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set # # Kernel hacking # # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set @@ -943,6 +834,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set # CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_SAMPLES is not set # CONFIG_DEBUG_MMRS is not set CONFIG_DEBUG_HUNT_FOR_ZERO=y CONFIG_DEBUG_BFIN_HWTRACE_ON=y @@ -964,10 +856,7 @@ CONFIG_ACCESS_CHECK=y CONFIG_SECURITY=y # CONFIG_SECURITY_NETWORK is not set CONFIG_SECURITY_CAPABILITIES=y - -# -# Cryptographic options -# +# CONFIG_SECURITY_FILE_CAPABILITIES is not set # CONFIG_CRYPTO is not set # @@ -978,6 +867,7 @@ CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_PLIST=y diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig index 7e648a7a38d..679c7483ea7 100644 --- a/arch/blackfin/configs/H8606_defconfig +++ b/arch/blackfin/configs/H8606_defconfig @@ -207,7 +207,7 @@ CONFIG_HZ=250 # # Memory Setup # -CONFIG_MEM_SIZE=32 +CONFIG_MAX_MEM_SIZE=32 CONFIG_MEM_ADD_WIDTH=9 CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig index 19e8f051ad1..87622ad9df4 100644 --- a/arch/blackfin/configs/PNAV-10_defconfig +++ b/arch/blackfin/configs/PNAV-10_defconfig @@ -214,7 +214,7 @@ CONFIG_HZ=250 # # Memory Setup # -CONFIG_MEM_SIZE=64 +CONFIG_MAX_MEM_SIZE=64 CONFIG_MEM_ADD_WIDTH=10 CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig new file mode 100644 index 00000000000..951ea041257 --- /dev/null +++ b/arch/blackfin/configs/SRV1_defconfig @@ -0,0 +1,1290 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.10 +# Fri Nov 2 20:50:23 2007 +# +# CONFIG_MMU is not set +# CONFIG_FPU is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +CONFIG_BLACKFIN=y +CONFIG_ZONE_DMA=y +CONFIG_BFIN=y +CONFIG_SEMAPHORE_SLEEPERS=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_GPIO=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_IRQCHIP_DEMUX_GPIO=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set + +# +# Blackfin Processor Options +# + +# +# Processor and Board Settings +# +# CONFIG_BF522 is not set +# CONFIG_BF525 is not set +# CONFIG_BF527 is not set +# CONFIG_BF531 is not set +# CONFIG_BF532 is not set +# CONFIG_BF533 is not set +# CONFIG_BF534 is not set +# CONFIG_BF536 is not set +CONFIG_BF537=y +# CONFIG_BF542 is not set +# CONFIG_BF544 is not set +# CONFIG_BF548 is not set +# CONFIG_BF549 is not set +# CONFIG_BF561 is not set +# CONFIG_BF_REV_0_0 is not set +# CONFIG_BF_REV_0_1 is not set +CONFIG_BF_REV_0_2=y +# CONFIG_BF_REV_0_3 is not set +# CONFIG_BF_REV_0_4 is not set +# CONFIG_BF_REV_0_5 is not set +# CONFIG_BF_REV_ANY is not set +# CONFIG_BF_REV_NONE is not set +CONFIG_BF53x=y +CONFIG_BFIN_SINGLE_CORE=y +# CONFIG_BFIN527_EZKIT is not set +# CONFIG_BFIN533_EZKIT is not set +# CONFIG_BFIN533_STAMP is not set +# CONFIG_BFIN537_STAMP is not set +# CONFIG_CAMSIG_MINOTAUR is not set +# CONFIG_BFIN533_BLUETECHNIX_CM is not set +# CONFIG_BFIN537_BLUETECHNIX_CM is not set +# CONFIG_BFIN548_EZKIT is not set +# CONFIG_BFIN561_BLUETECHNIX_CM is not set +# CONFIG_BFIN561_EZKIT is not set +# CONFIG_BFIN561_TEPLA is not set +# CONFIG_PNAV10 is not set +# CONFIG_VISTASCAN is not set +# CONFIG_BFIN533_SR3K is not set +CONFIG_GENERIC_BOARD=y +CONFIG_MEM_GENERIC_BOARD=y +CONFIG_IRQ_PLL_WAKEUP=7 +CONFIG_IRQ_RTC=8 +CONFIG_IRQ_PPI=8 +CONFIG_IRQ_SPORT0_RX=9 +CONFIG_IRQ_SPORT0_TX=9 +CONFIG_IRQ_SPORT1_RX=9 +CONFIG_IRQ_SPORT1_TX=9 +CONFIG_IRQ_TWI=10 +CONFIG_IRQ_SPI=10 +CONFIG_IRQ_UART0_RX=10 +CONFIG_IRQ_UART0_TX=10 +CONFIG_IRQ_UART1_RX=10 +CONFIG_IRQ_UART1_TX=10 +CONFIG_IRQ_MAC_RX=11 +CONFIG_IRQ_MAC_TX=11 +CONFIG_IRQ_TMR0=12 +CONFIG_IRQ_TMR1=12 +CONFIG_IRQ_TMR2=12 +CONFIG_IRQ_TMR3=12 +CONFIG_IRQ_TMR4=12 +CONFIG_IRQ_TMR5=12 +CONFIG_IRQ_TMR6=12 +CONFIG_IRQ_TMR7=12 +CONFIG_IRQ_PORTG_INTB=12 +CONFIG_IRQ_MEM_DMA0=13 +CONFIG_IRQ_MEM_DMA1=13 +CONFIG_IRQ_WATCH=13 + +# +# BF537 Specific Configuration +# + +# +# Interrupt Priority Assignment +# + +# +# Priority +# +CONFIG_IRQ_DMA_ERROR=7 +CONFIG_IRQ_ERROR=7 +CONFIG_IRQ_CAN_RX=11 +CONFIG_IRQ_CAN_TX=11 +CONFIG_IRQ_PROG_INTA=12 + +# +# Board customizations +# +# CONFIG_CMDLINE_BOOL is not set + +# +# Clock/PLL Setup +# +CONFIG_CLKIN_HZ=22118400 +# CONFIG_BFIN_KERNEL_CLOCK is not set +CONFIG_MAX_VCO_HZ=600000000 +CONFIG_MIN_VCO_HZ=50000000 +CONFIG_MAX_SCLK_HZ=133000000 +CONFIG_MIN_SCLK_HZ=27000000 + +# +# Kernel Timer/Scheduler +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 + +# +# Memory Setup +# +CONFIG_MAX_MEM_SIZE=32 +CONFIG_MEM_ADD_WIDTH=9 +CONFIG_BOOT_LOAD=0x400000 +CONFIG_BFIN_SCRATCH_REG_RETN=y +# CONFIG_BFIN_SCRATCH_REG_RETE is not set +# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set + +# +# Blackfin Kernel Optimizations +# + +# +# Memory Optimizations +# +CONFIG_I_ENTRY_L1=y +CONFIG_EXCPT_IRQ_SYSC_L1=y +CONFIG_DO_IRQ_L1=y +CONFIG_CORE_TIMER_IRQ_L1=y +CONFIG_IDLE_L1=y +CONFIG_SCHEDULE_L1=y +CONFIG_ARITHMETIC_OPS_L1=y +CONFIG_ACCESS_OK_L1=y +CONFIG_MEMSET_L1=y +CONFIG_MEMCPY_L1=y +CONFIG_SYS_BFIN_SPINLOCK_L1=y +# CONFIG_IP_CHECKSUM_L1 is not set +CONFIG_CACHELINE_ALIGNED_L1=y +# CONFIG_SYSCALL_TAB_L1 is not set +# CONFIG_CPLB_SWITCH_TAB_L1 is not set +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LARGE_ALLOCS=y +CONFIG_BFIN_DMA_5XX=y +CONFIG_DMA_UNCACHED_2M=y +# CONFIG_DMA_UNCACHED_1M is not set +# CONFIG_DMA_UNCACHED_NONE is not set + +# +# Cache Support +# +CONFIG_BFIN_ICACHE=y +CONFIG_BFIN_DCACHE=y +# CONFIG_BFIN_DCACHE_BANKA is not set +# CONFIG_BFIN_ICACHE_LOCK is not set +# CONFIG_BFIN_WB is not set +CONFIG_BFIN_WT=y +CONFIG_L1_MAX_PIECE=16 + +# +# Asynchonous Memory Configuration +# + +# +# EBIU_AMGCTL Global Control +# +CONFIG_C_AMCKEN=y +CONFIG_C_CDPRIO=y +# CONFIG_C_AMBEN is not set +# CONFIG_C_AMBEN_B0 is not set +# CONFIG_C_AMBEN_B0_B1 is not set +# CONFIG_C_AMBEN_B0_B1_B2 is not set +CONFIG_C_AMBEN_ALL=y + +# +# EBIU_AMBCTL Control +# +CONFIG_BANK_0=0x7BB0 +CONFIG_BANK_1=0x7BB0 +CONFIG_BANK_2=0x7BB0 +CONFIG_BANK_3=0x99B3 + +# +# Bus options (PCI, PCMCIA, EISA, MCA, ISA) +# +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF_FDPIC=y +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +# CONFIG_BINFMT_SHARED_FLAT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_LEGACY is not set +# CONFIG_PM_DEBUG is not set +# CONFIG_PM_SYSFS_DEPRECATED is not set +CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y +# CONFIG_PM_WAKEUP_BY_GPIO is not set +# CONFIG_PM_WAKEUP_GPIO_API is not set +CONFIG_PM_WAKEUP_SIC_IWR=0x80000000 + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETLABEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +CONFIG_IRDA=m + +# +# IrDA protocols +# +CONFIG_IRLAN=m +CONFIG_IRCOMM=m +# CONFIG_IRDA_ULTRA is not set + +# +# IrDA options +# +CONFIG_IRDA_CACHE_LAST_LSAP=y +# CONFIG_IRDA_FAST_RR is not set +# CONFIG_IRDA_DEBUG is not set + +# +# Infrared-port device drivers +# + +# +# SIR device drivers +# +CONFIG_IRTTY_SIR=m + +# +# Dongle support +# +# CONFIG_DONGLE is not set + +# +# Old SIR device drivers +# +# CONFIG_IRPORT_SIR is not set + +# +# Old Serial dongle support +# + +# +# FIR device drivers +# +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=m +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_GEN_PROBE=m +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_MW320D=m +CONFIG_MTD_RAM=y +CONFIG_MTD_ROM=m +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_BF5xx=m +CONFIG_BFIN_FLASH_SIZE=0x400000 +CONFIG_EBIU_FLASH_BASE=0x20000000 +CONFIG_MTD_UCLINUX=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=m +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_BFIN=m +CONFIG_BFIN_NAND_BASE=0x20212000 +CONFIG_BFIN_NAND_CLE=2 +CONFIG_BFIN_NAND_ALE=1 +CONFIG_BFIN_NAND_READY=3 +CONFIG_MTD_NAND_IDS=m +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# Misc devices +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# Ethernet (10 or 100Mbit) +# +# CONFIG_NET_ETHERNET is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +CONFIG_INPUT_UINPUT=y +# CONFIG_BF53X_PFBUTTONS is not set +# CONFIG_TWI_KEYPAD is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +CONFIG_BF5xx_PFLAGS=y +# CONFIG_BF5xx_PFLAGS_PROC is not set +# CONFIG_BF5xx_PPIFCD is not set +# CONFIG_BF5xx_TIMERS is not set +# CONFIG_BF5xx_PPI is not set +# CONFIG_BFIN_SPORT is not set +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_TWI_LCD is not set +# CONFIG_AD5304 is not set +# CONFIG_BF5xx_TEA5764 is not set +# CONFIG_BF5xx_FBDMA is not set +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_BFIN=y +CONFIG_SERIAL_BFIN_CONSOLE=y +CONFIG_SERIAL_BFIN_DMA=y +# CONFIG_SERIAL_BFIN_PIO is not set +CONFIG_SERIAL_BFIN_UART0=y +# CONFIG_BFIN_UART0_CTSRTS is not set +# CONFIG_SERIAL_BFIN_UART1 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_BFIN_SPORT is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set + +# +# CAN, the car bus and industrial fieldbus +# +# CONFIG_CAN4LINUX is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_BFIN_WDT=y +CONFIG_HW_RANDOM=m +# CONFIG_GEN_RTC is not set +CONFIG_BLACKFIN_DPMC=y +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_BLACKFIN_GPIO is not set +CONFIG_I2C_BLACKFIN_TWI=y +CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_SENSORS_AD5252 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCF8575 is not set +# CONFIG_SENSORS_PCA9543 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BFIN=y +# CONFIG_SPI_BITBANG is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_AT25=m +# CONFIG_SPI_SPIDEV is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +CONFIG_HWMON=m +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_FSCPOS is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +CONFIG_VIDEO_DEV=y +# CONFIG_VIDEO_V4L1 is not set +CONFIG_VIDEO_V4L1_COMPAT=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set + +# +# Encoders/decoders and other helper chips +# + +# +# Audio decoders +# +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_TVP5150 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_CX25840 is not set + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_VIDEO_PPI_GENERIC is not set +CONFIG_VIDEO_BLACKFIN_CAM=m +# CONFIG_VIDEO_BLACKFIN_MT9M001 is not set + +# +# CMOS Camera Sensor Selection +# +# CONFIG_MT9V022 is not set +# CONFIG_MT9M001 is not set +# CONFIG_VS6524 is not set +# CONFIG_VS6624 is not set +CONFIG_OV9655=y +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# HID Devices +# +# CONFIG_HID is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set + +# +# Enable Host or Gadget support to see Inventra options +# + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# InfiniBand support +# + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock +# +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# PBX support +# +# CONFIG_PBX is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_YAFFS_FS=m +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set +CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10 +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=m +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_FRAME_POINTER is not set +# CONFIG_FORCED_INLINING is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_DEBUG_MMRS is not set +# CONFIG_DEBUG_HWERR is not set +CONFIG_DEBUG_HUNT_FOR_ZERO=y +CONFIG_DEBUG_BFIN_HWTRACE_ON=y +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y +# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set +# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 +# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set +# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set +# CONFIG_EARLY_PRINTK is not set +CONFIG_CPLB_INFO=y +CONFIG_ACCESS_CHECK=y + +# +# Security options +# +# CONFIG_KEYS is not set +CONFIG_SECURITY=y +# CONFIG_SECURITY_NETWORK is not set +CONFIG_SECURITY_CAPABILITIES=y + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y -- cgit v1.2.3 From 2973951c96723433d80f43a450ba932e8b267d89 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 23 Apr 2008 10:14:14 +0800 Subject: [Blackfin] arch: we no longer use BFIN_{SINGLE,DUAL}_CORE in our source Signed-off-by: Bryan Wu --- arch/blackfin/Kconfig | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index add87a5f64e..87c9a7e1e82 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -220,16 +220,6 @@ config BF54x depends on (BF542 || BF544 || BF547 || BF548 || BF549) default y -config BFIN_DUAL_CORE - bool - depends on (BF561) - default y - -config BFIN_SINGLE_CORE - bool - depends on !BFIN_DUAL_CORE - default y - config MEM_GENERIC_BOARD bool depends on GENERIC_BOARD -- cgit v1.2.3 From 7b8aa36e568178ea801fcb42a5c55de0361a6892 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 23 Apr 2008 10:19:59 +0800 Subject: [Blackfin] arch: LARGE_ALLOCS was dropped along the way ... bring Blackfin in line Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/Kconfig | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 87c9a7e1e82..369050d9f9f 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -671,14 +671,6 @@ endchoice source "mm/Kconfig" -config LARGE_ALLOCS - bool "Allow allocating large blocks (> 1MB) of memory" - help - Allow the slab memory allocator to keep chains for very large - memory sizes - upto 32MB. You may need this if your system has - a lot of RAM, and you need to able to allocate very large - contiguous chunks. If unsure, say N. - config BFIN_GPTIMERS tristate "Enable Blackfin General Purpose Timers API" default n -- cgit v1.2.3 From 5af29f595813cce3c125d01d2500be483732ef4f Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Apr 2008 02:37:27 +0800 Subject: [Blackfin] arch: finish removing remnants of old BF537_PORT_H option of Blackfin EMAC driver Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu Acked-by: Jeff Garzik --- arch/blackfin/mach-bf537/head.S | 12 ------------ drivers/net/Kconfig | 2 +- 2 files changed, 1 insertion(+), 13 deletions(-) diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index 3014fe8dd15..ac85fdfbfd0 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S @@ -180,18 +180,6 @@ ENTRY(__start) SSYNC; #endif -#ifdef CONFIG_BF537_PORT_H - p0.h = hi(PORTH_FER); - p0.l = lo(PORTH_FER); - R0.L = W[P0]; /* Read */ - SSYNC; - R0 = 0x0000; - W[P0] = R0.L; /* Write */ - SSYNC; - W[P0] = R0.L; /* Disable peripheral function of PORTH */ - SSYNC; -#endif - /* Initialise UART - when booting from u-boot, the UART is not disabled * so if we dont initalize here, our serial console gets hosed */ p0.h = hi(UART_LCR); diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 2399a3796f6..015e1632597 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -827,7 +827,7 @@ config ULTRA32 config BFIN_MAC tristate "Blackfin 527/536/537 on-chip mac support" - depends on NET_ETHERNET && (BF527 || BF537 || BF536) && (!BF537_PORT_H) + depends on NET_ETHERNET && (BF527 || BF537 || BF536) select CRC32 select MII select PHYLIB -- cgit v1.2.3 From 697a9d65aa799940da1c9145944c6b9bd0f442c5 Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Thu, 24 Apr 2008 02:51:36 +0800 Subject: [Blackfin] arch: a rather old performance improvement for the signal handling code This is a rather old performance improvement for the signal handling code, which was originally only committed on the 2007R1 branch as a workaround for what we suspected to be a hardware bug. There's no point in constructing a sigreturn stub on the stack and flushing caches; we can just make signal handlers return to a known location in the fixed code area. Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu --- arch/blackfin/kernel/signal.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/arch/blackfin/kernel/signal.c b/arch/blackfin/kernel/signal.c index 71cfcd28b39..d1fa24401dc 100644 --- a/arch/blackfin/kernel/signal.c +++ b/arch/blackfin/kernel/signal.c @@ -38,6 +38,7 @@ #include #include +#include #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) @@ -50,6 +51,8 @@ struct rt_sigframe { int sig; struct siginfo *pinfo; void *puc; + /* This is no longer needed by the kernel, but unfortunately userspace + * code expects it to be there. */ char retcode[8]; struct siginfo info; struct ucontext uc; @@ -159,11 +162,6 @@ static inline int rt_setup_sigcontext(struct sigcontext *sc, struct pt_regs *reg return err; } -static inline void push_cache(unsigned long vaddr, unsigned int len) -{ - flush_icache_range(vaddr, vaddr + len); -} - static inline void *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) { @@ -209,19 +207,9 @@ setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t * info, err |= rt_setup_sigcontext(&frame->uc.uc_mcontext, regs); err |= copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); - /* Set up to return from userspace. */ - err |= __put_user(0x28, &(frame->retcode[0])); - err |= __put_user(0xe1, &(frame->retcode[1])); - err |= __put_user(0xad, &(frame->retcode[2])); - err |= __put_user(0x00, &(frame->retcode[3])); - err |= __put_user(0xa0, &(frame->retcode[4])); - err |= __put_user(0x00, &(frame->retcode[5])); - if (err) goto give_sigsegv; - push_cache((unsigned long)&frame->retcode, sizeof(frame->retcode)); - /* Set up registers for signal handler */ wrusp((unsigned long)frame); if (get_personality & FDPIC_FUNCPTRS) { @@ -231,7 +219,7 @@ setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t * info, __get_user(regs->p3, &funcptr->GOT); } else regs->pc = (unsigned long)ka->sa.sa_handler; - regs->rets = (unsigned long)(frame->retcode); + regs->rets = SIGRETURN_STUB; regs->r0 = frame->sig; regs->r1 = (unsigned long)(&frame->info); -- cgit v1.2.3 From d56daae9bec92ae4b0c115db787a0fcc4c17b381 Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Thu, 24 Apr 2008 02:56:36 +0800 Subject: [Blackfin] arch: fix bug - a crash on bootup with CONFIG_MPU on the BF548 The function flush_switched_dcplbs was clearing the CPLB entries covering the process permission bitmasks. This means that the sequence flush_switched_dcplbs (); set_mask_dcplbs(mm->context.page_rwx_mask); has a problem: if kernel code (such as an interrupt) causes a CPLB miss before set_mask_dcplbs completes, the CPLB handler function causes a double fault, with an instantaneous reboot. This bug fix is dedicated to Michael Hennerich, the only person in the world capable of providing working JTAG hardware. Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu --- arch/blackfin/kernel/cplb-mpu/cplbmgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index 6f1c053903c..f23bba5c6e6 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c @@ -307,7 +307,7 @@ void flush_switched_cplbs(void) enable_icplb(); disable_dcplb(); - for (i = first_mask_dcplb; i < MAX_CPLBS; i++) { + for (i = first_switched_dcplb; i < MAX_CPLBS; i++) { dcplb_tbl[i].data = 0; bfin_write32(DCPLB_DATA0 + i * 4, 0); } -- cgit v1.2.3 From 1ebc723cf04b55e7aeeec2e758293575d29a9c2b Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Thu, 24 Apr 2008 02:58:26 +0800 Subject: [Blackfin] arch: support the reserved memory region in the MPU code Pointed-out-by: Mike Frysinger Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu --- arch/blackfin/kernel/cplb-mpu/cplbmgr.c | 64 +++++++++++++++++++++------------ 1 file changed, 41 insertions(+), 23 deletions(-) diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index f23bba5c6e6..3377cbf28fb 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c @@ -146,14 +146,16 @@ static noinline int dcplb_miss(void) d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; #ifdef CONFIG_BFIN_DCACHE - if (addr < _ramend - DMA_UNCACHED_REGION) { + if (addr < _ramend - DMA_UNCACHED_REGION || + (reserved_mem_dcache_on && addr >= _ramend && + addr < physical_mem_end)) { d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; #ifdef CONFIG_BFIN_WT d_data |= CPLB_L1_AOW | CPLB_WT; #endif } #endif - if (addr >= _ramend) { + if (addr >= physical_mem_end) { if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && (status & FAULT_USERSUPV)) { addr &= ~0x3fffff; @@ -161,6 +163,8 @@ static noinline int dcplb_miss(void) d_data |= PAGE_SIZE_4MB; } else return CPLB_PROT_VIOL; + } else if (addr >= _ramend) { + d_data |= CPLB_USER_RD | CPLB_USER_WR; } else { mask = current_rwx_mask; if (mask) { @@ -198,12 +202,14 @@ static noinline int icplb_miss(void) unsigned long i_data; nr_icplb_miss++; - if (status & FAULT_USERSUPV) - nr_icplb_supv_miss++; - if (addr >= _ramend) + /* If inside the uncached DMA region, fault. */ + if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend) return CPLB_PROT_VIOL; + if (status & FAULT_USERSUPV) + nr_icplb_supv_miss++; + /* * First, try to find a CPLB that matches this address. If we * find one, then the fact that we're in the miss handler means @@ -220,30 +226,42 @@ static noinline int icplb_miss(void) } i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB; -#ifdef CONFIG_BFIN_ICACHE - i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; -#endif +#ifdef CONFIG_BFIN_ICACHE /* - * Two cases to distinguish - a supervisor access must necessarily - * be for a module page; we grant it unconditionally (could do better - * here in the future). Otherwise, check the x bitmap of the current - * process. + * Normal RAM, and possibly the reserved memory area, are + * cacheable. */ - if (!(status & FAULT_USERSUPV)) { - unsigned long *mask = current_rwx_mask; - - if (mask) { - int page = addr >> PAGE_SHIFT; - int offs = page >> 5; - int bit = 1 << (page & 31); + if (addr < _ramend || + (addr < physical_mem_end && reserved_mem_icache_on)) + i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; +#endif - mask += 2 * page_mask_nelts; - if (mask[offs] & bit) - i_data |= CPLB_USER_RD; + if (addr >= physical_mem_end) { + return CPLB_PROT_VIOL; + } else if (addr >= _ramend) { + i_data |= CPLB_USER_RD; + } else { + /* + * Two cases to distinguish - a supervisor access must + * necessarily be for a module page; we grant it + * unconditionally (could do better here in the future). + * Otherwise, check the x bitmap of the current process. + */ + if (!(status & FAULT_USERSUPV)) { + unsigned long *mask = current_rwx_mask; + + if (mask) { + int page = addr >> PAGE_SHIFT; + int offs = page >> 5; + int bit = 1 << (page & 31); + + mask += 2 * page_mask_nelts; + if (mask[offs] & bit) + i_data |= CPLB_USER_RD; + } } } - idx = evict_one_icplb(); addr &= PAGE_MASK; icplb_tbl[idx].addr = addr; -- cgit v1.2.3 From d5adb029efad3c51db376d620319abe65d1efc21 Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Thu, 24 Apr 2008 03:06:15 +0800 Subject: [Blackfin] arch: This allows XIP to work with FD-PIC. Previously, init failed to do anything meaningful; it turns out that the reason is that FD-PIC has a readonly data section which can be located in the XIP filesystem, and various address checks in the kernel reject such addresses for syscall arguments. Hence, init's execve ("/bin/sh", ...) failed with error code EFAULT. There's room for improvement here: in case people want to have filesystems on flash rather than in main memory, _access_ok should be modified to allow this. This bug fix is also dedicated to Michael Hennerich. Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu --- arch/blackfin/kernel/process.c | 6 ++++++ include/asm-blackfin/processor.h | 5 +++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index fb94cbeafad..be9fdd00d7c 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -324,6 +324,12 @@ int _access_ok(unsigned long addr, unsigned long size) return 1; if (addr >= memory_mtd_end && (addr + size) <= physical_mem_end) return 1; + +#ifdef CONFIG_ROMFS_MTD_FS + /* For XIP, allow user space to use pointers within the ROMFS. */ + if (addr >= memory_mtd_start && (addr + size) <= memory_mtd_end) + return 1; +#endif #else if (addr >= memory_start && (addr + size) <= physical_mem_end) return 1; diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h index 1033e5c7601..1c004072461 100644 --- a/include/asm-blackfin/processor.h +++ b/include/asm-blackfin/processor.h @@ -26,9 +26,10 @@ static inline void wrusp(unsigned long usp) /* * User space process size: 1st byte beyond user address space. + * Fairly meaningless on nommu. Parts of user programs can be scattered + * in a lot of places, so just disable this by setting it to 0xFFFFFFFF. */ -extern unsigned long memory_end; -#define TASK_SIZE (memory_end) +#define TASK_SIZE 0xFFFFFFFF #ifdef __KERNEL__ #define STACK_TOP TASK_SIZE -- cgit v1.2.3 From db68254f0639a357309f02cf8707490265fa7a31 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 24 Apr 2008 03:18:59 +0800 Subject: [Blackfin] arch: Apply Bluetechnix vendor patch Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- arch/blackfin/Kconfig | 7 +- arch/blackfin/mach-bf548/boards/Kconfig | 6 + arch/blackfin/mach-bf548/boards/Makefile | 1 + arch/blackfin/mach-bf548/boards/cm_bf548.c | 620 +++++++++++++++++++++++++++++ 4 files changed, 631 insertions(+), 3 deletions(-) create mode 100644 arch/blackfin/mach-bf548/boards/cm_bf548.c diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 369050d9f9f..d1590c7ed75 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -323,7 +323,7 @@ config VCO_MULT range 1 64 default "22" if BFIN533_EZKIT default "45" if BFIN533_STAMP - default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT) + default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM) default "22" if BFIN533_BLUETECHNIX_CM default "20" if BFIN537_BLUETECHNIX_CM default "20" if BFIN561_BLUETECHNIX_CM @@ -360,7 +360,7 @@ config SCLK_DIV range 1 15 default 5 if BFIN533_EZKIT default 5 if BFIN533_STAMP - default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT) + default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM) default 5 if BFIN533_BLUETECHNIX_CM default 4 if BFIN537_BLUETECHNIX_CM default 4 if BFIN561_BLUETECHNIX_CM @@ -449,10 +449,11 @@ config MEM_SIZE default 128 if BFIN533_STAMP default 64 if PNAV10 default 32 if H8606_HVSISTEMAS + default 64 if BFIN548_BLUETECHNIX_CM choice prompt "DDR SDRAM Chip Type" - depends on BFIN548_EZKIT + depends on (BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM) default MEM_MT46V32M16_5B config MEM_MT46V32M16_6T diff --git a/arch/blackfin/mach-bf548/boards/Kconfig b/arch/blackfin/mach-bf548/boards/Kconfig index 05712906403..d38e5267185 100644 --- a/arch/blackfin/mach-bf548/boards/Kconfig +++ b/arch/blackfin/mach-bf548/boards/Kconfig @@ -8,5 +8,11 @@ config BFIN548_EZKIT bool "BF548-EZKIT" help BFIN548-EZKIT board support. + +config BFIN548_BLUETECHNIX_CM + bool "Bluetechnix CM-BF548" + depends on (BF548) + help + CM-BF548 support for DEV-Board. endchoice diff --git a/arch/blackfin/mach-bf548/boards/Makefile b/arch/blackfin/mach-bf548/boards/Makefile index a444cc73957..eed161dd784 100644 --- a/arch/blackfin/mach-bf548/boards/Makefile +++ b/arch/blackfin/mach-bf548/boards/Makefile @@ -3,3 +3,4 @@ # obj-$(CONFIG_BFIN548_EZKIT) += ezkit.o led.o +obj-$(CONFIG_BFIN548_BLUETECHNIX_CM) += cm_bf548.o diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c new file mode 100644 index 00000000000..1aa3c1b86bc --- /dev/null +++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c @@ -0,0 +1,620 @@ +/* + * File: arch/blackfin/mach-bf548/boards/cm_bf548.c + * Based on: arch/blackfin/mach-bf537/boards/ezkit.c + * Author: Aidan Williams + * + * Created: + * Description: + * + * Modified: + * Copyright 2005 National ICT Australia (NICTA) + * Copyright 2004-2008 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Name the Board for the /proc/cpuinfo + */ +const char bfin_board_name[] = "Bluetechnix CM-BF548"; + +/* + * Driver needs to know address, irq and flag pin. + */ + +#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) + +#include + +static struct bfin_bf54xfb_mach_info bf54x_lq043_data = { + .width = 480, + .height = 272, + .xres = {480, 480, 480}, + .yres = {272, 272, 272}, + .bpp = {24, 24, 24}, + .disp = GPIO_PE3, +}; + +static struct resource bf54x_lq043_resources[] = { + { + .start = IRQ_EPPI0_ERR, + .end = IRQ_EPPI0_ERR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bf54x_lq043_device = { + .name = "bf54x-lq043", + .id = -1, + .num_resources = ARRAY_SIZE(bf54x_lq043_resources), + .resource = bf54x_lq043_resources, + .dev = { + .platform_data = &bf54x_lq043_data, + }, +}; +#endif + +#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE) +static unsigned int bf548_keymap[] = { + KEYVAL(0, 0, KEY_ENTER), + KEYVAL(0, 1, KEY_HELP), + KEYVAL(0, 2, KEY_0), + KEYVAL(0, 3, KEY_BACKSPACE), + KEYVAL(1, 0, KEY_TAB), + KEYVAL(1, 1, KEY_9), + KEYVAL(1, 2, KEY_8), + KEYVAL(1, 3, KEY_7), + KEYVAL(2, 0, KEY_DOWN), + KEYVAL(2, 1, KEY_6), + KEYVAL(2, 2, KEY_5), + KEYVAL(2, 3, KEY_4), + KEYVAL(3, 0, KEY_UP), + KEYVAL(3, 1, KEY_3), + KEYVAL(3, 2, KEY_2), + KEYVAL(3, 3, KEY_1), +}; + +static struct bfin_kpad_platform_data bf54x_kpad_data = { + .rows = 4, + .cols = 4, + .keymap = bf548_keymap, + .keymapsize = ARRAY_SIZE(bf548_keymap), + .repeat = 0, + .debounce_time = 5000, /* ns (5ms) */ + .coldrive_time = 1000, /* ns (1ms) */ + .keyup_test_interval = 50, /* ms (50ms) */ +}; + +static struct resource bf54x_kpad_resources[] = { + { + .start = IRQ_KEY, + .end = IRQ_KEY, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bf54x_kpad_device = { + .name = "bf54x-keys", + .id = -1, + .num_resources = ARRAY_SIZE(bf54x_kpad_resources), + .resource = bf54x_kpad_resources, + .dev = { + .platform_data = &bf54x_kpad_data, + }, +}; +#endif + +#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +static struct platform_device rtc_device = { + .name = "rtc-bfin", + .id = -1, +}; +#endif + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) +static struct resource bfin_uart_resources[] = { +#ifdef CONFIG_SERIAL_BFIN_UART0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + { + .start = 0xFFC02000, + .end = 0xFFC020FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART2 + { + .start = 0xFFC02100, + .end = 0xFFC021FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART3 + { + .start = 0xFFC03100, + .end = 0xFFC031FF, + }, +#endif +}; + +static struct platform_device bfin_uart_device = { + .name = "bfin-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_uart_resources), + .resource = bfin_uart_resources, +}; +#endif + +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) +static struct resource smsc911x_resources[] = { + { + .name = "smsc911x-memory", + .start = 0x24000000, + .end = 0x24000000 + 0xFF, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_PE6, + .end = IRQ_PE6, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, + }, +}; +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = 0, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, +}; +#endif + +#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) +static struct resource musb_resources[] = { + [0] = { + .start = 0xFFC03C00, + .end = 0xFFC040FF, + .flags = IORESOURCE_MEM, + }, + [1] = { /* general IRQ */ + .start = IRQ_USB_INT0, + .end = IRQ_USB_INT0, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, + [2] = { /* DMA IRQ */ + .start = IRQ_USB_DMA, + .end = IRQ_USB_DMA, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct musb_hdrc_platform_data musb_plat = { +#if defined(CONFIG_USB_MUSB_OTG) + .mode = MUSB_OTG, +#elif defined(CONFIG_USB_MUSB_HDRC_HCD) + .mode = MUSB_HOST, +#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) + .mode = MUSB_PERIPHERAL, +#endif + .multipoint = 0, +}; + +static u64 musb_dmamask = ~(u32)0; + +static struct platform_device musb_device = { + .name = "musb_hdrc", + .id = 0, + .dev = { + .dma_mask = &musb_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &musb_plat, + }, + .num_resources = ARRAY_SIZE(musb_resources), + .resource = musb_resources, +}; +#endif + +#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) +static struct resource bfin_atapi_resources[] = { + { + .start = 0xFFC03800, + .end = 0xFFC0386F, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_ATAPI_ERR, + .end = IRQ_ATAPI_ERR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_atapi_device = { + .name = "pata-bf54x", + .id = -1, + .num_resources = ARRAY_SIZE(bfin_atapi_resources), + .resource = bfin_atapi_resources, +}; +#endif + +#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) +static struct mtd_partition partition_info[] = { + { + .name = "Linux Kernel", + .offset = 0, + .size = 4 * SIZE_1M, + }, + { + .name = "File System", + .offset = 4 * SIZE_1M, + .size = (256 - 4) * SIZE_1M, + }, +}; + +static struct bf5xx_nand_platform bf5xx_nand_platform = { + .page_size = NFC_PG_SIZE_256, + .data_width = NFC_NWIDTH_8, + .partitions = partition_info, + .nr_partitions = ARRAY_SIZE(partition_info), + .rd_dly = 3, + .wr_dly = 3, +}; + +static struct resource bf5xx_nand_resources[] = { + { + .start = 0xFFC03B00, + .end = 0xFFC03B4F, + .flags = IORESOURCE_MEM, + }, + { + .start = CH_NFC, + .end = CH_NFC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bf5xx_nand_device = { + .name = "bf5xx-nand", + .id = 0, + .num_resources = ARRAY_SIZE(bf5xx_nand_resources), + .resource = bf5xx_nand_resources, + .dev = { + .platform_data = &bf5xx_nand_platform, + }, +}; +#endif + +#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) +static struct platform_device bf54x_sdh_device = { + .name = "bfin-sdh", + .id = 0, +}; +#endif + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +/* all SPI peripherals info goes here */ +#if defined(CONFIG_MTD_M25P80) \ + || defined(CONFIG_MTD_M25P80_MODULE) +/* SPI flash chip (m25p16) */ +static struct mtd_partition bfin_spi_flash_partitions[] = { + { + .name = "bootloader", + .size = 0x00040000, + .offset = 0, + .mask_flags = MTD_CAP_ROM + }, { + .name = "linux kernel", + .size = 0x1c0000, + .offset = 0x40000 + } +}; + +static struct flash_platform_data bfin_spi_flash_data = { + .name = "m25p80", + .parts = bfin_spi_flash_partitions, + .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), + .type = "m25p16", +}; + +static struct bfin5xx_spi_chip spi_flash_chip_info = { + .enable_dma = 0, /* use dma transfer with this chip*/ + .bits_per_word = 8, + .cs_change_per_word = 0, +}; +#endif + +#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) +static struct bfin5xx_spi_chip spi_ad7877_chip_info = { + .cs_change_per_word = 0, + .enable_dma = 0, + .bits_per_word = 16, +}; + +static const struct ad7877_platform_data bfin_ad7877_ts_info = { + .model = 7877, + .vref_delay_usecs = 50, /* internal, no capacitor */ + .x_plate_ohms = 419, + .y_plate_ohms = 486, + .pressure_max = 1000, + .pressure_min = 0, + .stopacq_polarity = 1, + .first_conversion_delay = 3, + .acquisition_time = 1, + .averaging = 1, + .pen_down_acc_interval = 1, +}; +#endif + +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) +static struct bfin5xx_spi_chip spidev_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; +#endif + +static struct spi_board_info bf54x_spi_board_info[] __initdata = { +#if defined(CONFIG_MTD_M25P80) \ + || defined(CONFIG_MTD_M25P80_MODULE) + { + /* the modalias must be the same as spi device driver name */ + .modalias = "m25p80", /* Name of spi_driver for this device */ + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, /* Framework bus number */ + .chip_select = 1, /* SPI_SSEL1*/ + .platform_data = &bfin_spi_flash_data, + .controller_data = &spi_flash_chip_info, + .mode = SPI_MODE_3, + }, +#endif +#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) +{ + .modalias = "ad7877", + .platform_data = &bfin_ad7877_ts_info, + .irq = IRQ_PJ11, + .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 2, + .controller_data = &spi_ad7877_chip_info, +}, +#endif +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) + { + .modalias = "spidev", + .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, + .controller_data = &spidev_chip_info, + }, +#endif +}; + +/* SPI (0) */ +static struct resource bfin_spi0_resource[] = { + [0] = { + .start = SPI0_REGBASE, + .end = SPI0_REGBASE + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = CH_SPI0, + .end = CH_SPI0, + .flags = IORESOURCE_IRQ, + } +}; + +/* SPI (1) */ +static struct resource bfin_spi1_resource[] = { + [0] = { + .start = SPI1_REGBASE, + .end = SPI1_REGBASE + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = CH_SPI1, + .end = CH_SPI1, + .flags = IORESOURCE_IRQ, + } +}; + +/* SPI controller data */ +static struct bfin5xx_spi_master bf54x_spi_master_info0 = { + .num_chipselect = 8, + .enable_dma = 1, /* master has the ability to do dma transfer */ + .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, +}; + +static struct platform_device bf54x_spi_master0 = { + .name = "bfin-spi", + .id = 0, /* Bus number */ + .num_resources = ARRAY_SIZE(bfin_spi0_resource), + .resource = bfin_spi0_resource, + .dev = { + .platform_data = &bf54x_spi_master_info0, /* Passed to driver */ + }, +}; + +static struct bfin5xx_spi_master bf54x_spi_master_info1 = { + .num_chipselect = 8, + .enable_dma = 1, /* master has the ability to do dma transfer */ + .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, +}; + +static struct platform_device bf54x_spi_master1 = { + .name = "bfin-spi", + .id = 1, /* Bus number */ + .num_resources = ARRAY_SIZE(bfin_spi1_resource), + .resource = bfin_spi1_resource, + .dev = { + .platform_data = &bf54x_spi_master_info1, /* Passed to driver */ + }, +}; +#endif /* spi master and devices */ + +#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static struct resource bfin_twi0_resource[] = { + [0] = { + .start = TWI0_REGBASE, + .end = TWI0_REGBASE + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TWI0, + .end = IRQ_TWI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device i2c_bfin_twi0_device = { + .name = "i2c-bfin-twi", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_twi0_resource), + .resource = bfin_twi0_resource, +}; + +#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ +static struct resource bfin_twi1_resource[] = { + [0] = { + .start = TWI1_REGBASE, + .end = TWI1_REGBASE + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TWI1, + .end = IRQ_TWI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device i2c_bfin_twi1_device = { + .name = "i2c-bfin-twi", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_twi1_resource), + .resource = bfin_twi1_resource, +}; +#endif +#endif + +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +#include + +static struct gpio_keys_button bfin_gpio_keys_table[] = { + {BTN_0, GPIO_PH7, 1, "gpio-keys: BTN0"}, +}; + +static struct gpio_keys_platform_data bfin_gpio_keys_data = { + .buttons = bfin_gpio_keys_table, + .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), +}; + +static struct platform_device bfin_device_gpiokeys = { + .name = "gpio-keys", + .dev = { + .platform_data = &bfin_gpio_keys_data, + }, +}; +#endif + +static struct platform_device *cm_bf548_devices[] __initdata = { +#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) + &rtc_device, +#endif + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) + &bfin_uart_device, +#endif + +#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) + &bf54x_lq043_device, +#endif + +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) + &smsc911x_device, +#endif + +#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) + &musb_device, +#endif + +#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) + &bfin_atapi_device, +#endif + +#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) + &bf5xx_nand_device, +#endif + +#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) + &bf54x_sdh_device, +#endif + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) + &bf54x_spi_master0, + &bf54x_spi_master1, +#endif + +#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE) + &bf54x_kpad_device, +#endif + +#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +/* &i2c_bfin_twi0_device, */ +#if !defined(CONFIG_BF542) + &i2c_bfin_twi1_device, +#endif +#endif + +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) + &bfin_device_gpiokeys, +#endif +}; + +static int __init cm_bf548_init(void) +{ + printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + platform_add_devices(cm_bf548_devices, ARRAY_SIZE(cm_bf548_devices)); + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) + spi_register_board_info(bf54x_spi_board_info, + ARRAY_SIZE(bf54x_spi_board_info)); +#endif + + return 0; +} + +arch_initcall(cm_bf548_init); -- cgit v1.2.3 From 6ed839423073251b513664fdadb180634aed704b Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Thu, 24 Apr 2008 04:43:14 +0800 Subject: [Blackfin] arch: Resolve the clash issue of UART defines between blackfin headers and include/linux/serial_reg. Signed-off-by: Graf Yang Cc: Robin Getz Signed-off-by: Bryan Wu --- arch/blackfin/kernel/bfin_gpio.c | 16 ++++++++-------- arch/blackfin/mach-bf533/head.S | 16 ++++++++-------- arch/blackfin/mach-bf537/head.S | 16 ++++++++-------- arch/blackfin/mach-bf561/head.S | 16 ++++++++-------- include/asm-blackfin/mach-bf533/defBF532.h | 29 +++++++++++++++++------------ include/asm-blackfin/mach-bf537/blackfin.h | 24 +++++++++++------------- include/asm-blackfin/mach-bf548/blackfin.h | 23 ++++++++++++----------- include/asm-blackfin/mach-bf561/defBF561.h | 29 +++++++++++++++++------------ 8 files changed, 89 insertions(+), 80 deletions(-) diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index 7e8ceea9b5d..72477c252a9 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -95,14 +95,14 @@ enum { AWA_data_clear = SYSCR, AWA_data_set = SYSCR, AWA_toggle = SYSCR, - AWA_maska = UART_SCR, - AWA_maska_clear = UART_SCR, - AWA_maska_set = UART_SCR, - AWA_maska_toggle = UART_SCR, - AWA_maskb = UART_GCTL, - AWA_maskb_clear = UART_GCTL, - AWA_maskb_set = UART_GCTL, - AWA_maskb_toggle = UART_GCTL, + AWA_maska = BFIN_UART_SCR, + AWA_maska_clear = BFIN_UART_SCR, + AWA_maska_set = BFIN_UART_SCR, + AWA_maska_toggle = BFIN_UART_SCR, + AWA_maskb = BFIN_UART_GCTL, + AWA_maskb_clear = BFIN_UART_GCTL, + AWA_maskb_set = BFIN_UART_GCTL, + AWA_maskb_toggle = BFIN_UART_GCTL, AWA_dir = SPORT1_STAT, AWA_polar = SPORT1_STAT, AWA_edge = SPORT1_STAT, diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S index 1ded945a6fa..d9ba2b11e01 100644 --- a/arch/blackfin/mach-bf533/head.S +++ b/arch/blackfin/mach-bf533/head.S @@ -151,26 +151,26 @@ ENTRY(__start) /* Initialise UART - when booting from u-boot, the UART is not disabled * so if we dont initalize here, our serial console gets hosed */ - p0.h = hi(UART_LCR); - p0.l = lo(UART_LCR); + p0.h = hi(BFIN_UART_LCR); + p0.l = lo(BFIN_UART_LCR); r0 = 0x0(Z); w[p0] = r0.L; /* To enable DLL writes */ ssync; - p0.h = hi(UART_DLL); - p0.l = lo(UART_DLL); + p0.h = hi(BFIN_UART_DLL); + p0.l = lo(BFIN_UART_DLL); r0 = 0x0(Z); w[p0] = r0.L; ssync; - p0.h = hi(UART_DLH); - p0.l = lo(UART_DLH); + p0.h = hi(BFIN_UART_DLH); + p0.l = lo(BFIN_UART_DLH); r0 = 0x00(Z); w[p0] = r0.L; ssync; - p0.h = hi(UART_GCTL); - p0.l = lo(UART_GCTL); + p0.h = hi(BFIN_UART_GCTL); + p0.l = lo(BFIN_UART_GCTL); r0 = 0x0(Z); w[p0] = r0.L; /* To enable UART clock */ ssync; diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index ac85fdfbfd0..9e9fac9c634 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S @@ -182,26 +182,26 @@ ENTRY(__start) /* Initialise UART - when booting from u-boot, the UART is not disabled * so if we dont initalize here, our serial console gets hosed */ - p0.h = hi(UART_LCR); - p0.l = lo(UART_LCR); + p0.h = hi(BFIN_UART_LCR); + p0.l = lo(BFIN_UART_LCR); r0 = 0x0(Z); w[p0] = r0.L; /* To enable DLL writes */ ssync; - p0.h = hi(UART_DLL); - p0.l = lo(UART_DLL); + p0.h = hi(BFIN_UART_DLL); + p0.l = lo(BFIN_UART_DLL); r0 = 0x0(Z); w[p0] = r0.L; ssync; - p0.h = hi(UART_DLH); - p0.l = lo(UART_DLH); + p0.h = hi(BFIN_UART_DLH); + p0.l = lo(BFIN_UART_DLH); r0 = 0x00(Z); w[p0] = r0.L; ssync; - p0.h = hi(UART_GCTL); - p0.l = lo(UART_GCTL); + p0.h = hi(BFIN_UART_GCTL); + p0.l = lo(BFIN_UART_GCTL); r0 = 0x0(Z); w[p0] = r0.L; /* To enable UART clock */ ssync; diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S index 96a3d456fb6..279e2e812a2 100644 --- a/arch/blackfin/mach-bf561/head.S +++ b/arch/blackfin/mach-bf561/head.S @@ -139,26 +139,26 @@ ENTRY(__start) /* Initialise UART - when booting from u-boot, the UART is not disabled * so if we dont initalize here, our serial console gets hosed */ - p0.h = hi(UART_LCR); - p0.l = lo(UART_LCR); + p0.h = hi(BFIN_UART_LCR); + p0.l = lo(BFIN_UART_LCR); r0 = 0x0(Z); w[p0] = r0.L; /* To enable DLL writes */ ssync; - p0.h = hi(UART_DLL); - p0.l = lo(UART_DLL); + p0.h = hi(BFIN_UART_DLL); + p0.l = lo(BFIN_UART_DLL); r0 = 0x0(Z); w[p0] = r0.L; ssync; - p0.h = hi(UART_DLH); - p0.l = lo(UART_DLH); + p0.h = hi(BFIN_UART_DLH); + p0.l = lo(BFIN_UART_DLH); r0 = 0x00(Z); w[p0] = r0.L; ssync; - p0.h = hi(UART_GCTL); - p0.l = lo(UART_GCTL); + p0.h = hi(BFIN_UART_GCTL); + p0.l = lo(BFIN_UART_GCTL); r0 = 0x0(Z); w[p0] = r0.L; /* To enable UART clock */ ssync; diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h index 37134aaf995..17e1548cec0 100644 --- a/include/asm-blackfin/mach-bf533/defBF532.h +++ b/include/asm-blackfin/mach-bf533/defBF532.h @@ -88,20 +88,25 @@ #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ /* UART Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART_THR 0xFFC00400 /* Transmit Holding register */ -#define UART_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART_LCR 0xFFC0040C /* Line Control Register */ -#define UART_MCR 0xFFC00410 /* Modem Control Register */ -#define UART_LSR 0xFFC00414 /* Line Status Register */ + +/* + * Because include/linux/serial_reg.h have defined UART_*, + * So we define blackfin uart regs to BFIN_UART_*. + */ +#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */ +#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */ +#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */ +#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */ +#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */ +#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */ #if 0 -#define UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */ +#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */ #endif -#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART_GCTL 0xFFC00424 /* Global Control Register */ +#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */ +#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ #define SPI0_REGBASE 0xFFC00500 diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h index 53fcfa3408d..4f10ee0ae10 100644 --- a/include/asm-blackfin/mach-bf537/blackfin.h +++ b/include/asm-blackfin/mach-bf537/blackfin.h @@ -82,8 +82,6 @@ #define STATUS_P1 0x02 #define STATUS_P0 0x01 -/* UART 0*/ - /* DMA Channnel */ #define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX() #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val) @@ -106,37 +104,37 @@ /* MMR Registers*/ #define bfin_read_UART_THR() bfin_read_UART0_THR() #define bfin_write_UART_THR(val) bfin_write_UART0_THR(val) -#define UART_THR UART0_THR +#define BFIN_UART_THR UART0_THR #define bfin_read_UART_RBR() bfin_read_UART0_RBR() #define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val) -#define UART_RBR UART0_RBR +#define BFIN_UART_RBR UART0_RBR #define bfin_read_UART_DLL() bfin_read_UART0_DLL() #define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val) -#define UART_DLL UART0_DLL +#define BFIN_UART_DLL UART0_DLL #define bfin_read_UART_IER() bfin_read_UART0_IER() #define bfin_write_UART_IER(val) bfin_write_UART0_IER(val) -#define UART_IER UART0_IER +#define BFIN_UART_IER UART0_IER #define bfin_read_UART_DLH() bfin_read_UART0_DLH() #define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val) -#define UART_DLH UART0_DLH +#define BFIN_UART_DLH UART0_DLH #define bfin_read_UART_IIR() bfin_read_UART0_IIR() #define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val) -#define UART_IIR UART0_IIR +#define BFIN_UART_IIR UART0_IIR #define bfin_read_UART_LCR() bfin_read_UART0_LCR() #define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val) -#define UART_LCR UART0_LCR +#define BFIN_UART_LCR UART0_LCR #define bfin_read_UART_MCR() bfin_read_UART0_MCR() #define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val) -#define UART_MCR UART0_MCR +#define BFIN_UART_MCR UART0_MCR #define bfin_read_UART_LSR() bfin_read_UART0_LSR() #define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val) -#define UART_LSR UART0_LSR +#define BFIN_UART_LSR UART0_LSR #define bfin_read_UART_SCR() bfin_read_UART0_SCR() #define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val) -#define UART_SCR UART0_SCR +#define BFIN_UART_SCR UART0_SCR #define bfin_read_UART_GCTL() bfin_read_UART0_GCTL() #define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) -#define UART_GCTL UART0_GCTL +#define BFIN_UART_GCTL UART0_GCTL /* DPMC*/ #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h index 3bd67da8605..b8509c16ecd 100644 --- a/include/asm-blackfin/mach-bf548/blackfin.h +++ b/include/asm-blackfin/mach-bf548/blackfin.h @@ -153,17 +153,18 @@ #define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) #define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() #define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) -#define UART_THR UART1_THR -#define UART_RBR UART1_RBR -#define UART_DLL UART1_DLL -#define UART_IER UART1_IER -#define UART_DLH UART1_DLH -#define UART_IIR UART1_IIR -#define UART_LCR UART1_LCR -#define UART_MCR UART1_MCR -#define UART_LSR UART1_LSR -#define UART_SCR UART1_SCR -#define UART_GCTL UART1_GCTL + +#define BFIN_UART_THR UART1_THR +#define BFIN_UART_RBR UART1_RBR +#define BFIN_UART_DLL UART1_DLL +#define BFIN_UART_IER UART1_IER +#define BFIN_UART_DLH UART1_DLH +#define BFIN_UART_IIR UART1_IIR +#define BFIN_UART_LCR UART1_LCR +#define BFIN_UART_MCR UART1_MCR +#define BFIN_UART_LSR UART1_LSR +#define BFIN_UART_SCR UART1_SCR +#define BFIN_UART_GCTL UART1_GCTL /* PLL_DIV Masks */ #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h index c3c0eb13c81..bee30230187 100644 --- a/include/asm-blackfin/mach-bf561/defBF561.h +++ b/include/asm-blackfin/mach-bf561/defBF561.h @@ -110,18 +110,23 @@ #define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */ /* UART Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART_THR 0xFFC00400 /* Transmit Holding register */ -#define UART_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART_LCR 0xFFC0040C /* Line Control Register */ -#define UART_MCR 0xFFC00410 /* Modem Control Register */ -#define UART_LSR 0xFFC00414 /* Line Status Register */ -#define UART_MSR 0xFFC00418 /* Modem Status Register */ -#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART_GCTL 0xFFC00424 /* Global Control Register */ + +/* + * Because include/linux/serial_reg.h have defined UART_*, + * So we define blackfin uart regs to BFIN_UART0_*. + */ +#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */ +#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */ +#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */ +#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */ +#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */ +#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */ +#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */ +#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */ +#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ #define SPI0_REGBASE 0xFFC00500 -- cgit v1.2.3 From f950f605b9cd0e4bb53b902d2b2edbbb3e6079fc Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Thu, 24 Apr 2008 03:34:13 +0800 Subject: [Blackfin] arch: USB header files are now located under linux/usb/. Signed-off-by: Peter Korsgaard Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf537/boards/minotaur.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c index 815ad404588..4ea7173915e 100644 --- a/arch/blackfin/mach-bf537/boards/minotaur.c +++ b/arch/blackfin/mach-bf537/boards/minotaur.c @@ -8,12 +8,12 @@ #include #include #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) -#include +#include #endif #include #include #include -#include +#include #include #include #include -- cgit v1.2.3 From 5d1617b247aa63698618215a9f39ecf905d55779 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Apr 2008 05:03:26 +0800 Subject: [Blackfin] arch: merge ip0x-specific board changes Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/Kconfig | 5 +- arch/blackfin/configs/IP0X_defconfig | 1252 ++++++++++++++++++++++++++++ arch/blackfin/mach-bf533/boards/Kconfig | 6 + arch/blackfin/mach-bf533/boards/Makefile | 1 + arch/blackfin/mach-bf533/boards/ip0x.c | 279 +++++++ include/asm-blackfin/mach-bf533/mem_init.h | 10 +- 6 files changed, 1551 insertions(+), 2 deletions(-) create mode 100644 arch/blackfin/configs/IP0X_defconfig create mode 100644 arch/blackfin/mach-bf533/boards/ip0x.c diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index d1590c7ed75..308bbe291d8 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -249,7 +249,7 @@ config MEM_MT48LC8M32B2B5_7 config MEM_MT48LC32M16A2TG_75 bool - depends on (BFIN527_EZKIT) + depends on (BFIN527_EZKIT || BFIN532_IP0X) default y source "arch/blackfin/mach-bf527/Kconfig" @@ -281,6 +281,7 @@ config CLKIN_HZ default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS) default "30000000" if BFIN561_EZKIT default "24576000" if PNAV10 + default "10000000" if BFIN532_IP0X help The frequency of CLKIN crystal oscillator on the board in Hz. @@ -304,6 +305,7 @@ config MEM_ADD_WIDTH default 10 if BFIN537_STAMP default 11 if BFIN533_STAMP default 10 if PNAV10 + default 10 if BFIN532_IP0X config PLL_BYPASS bool "Bypass PLL" @@ -450,6 +452,7 @@ config MEM_SIZE default 64 if PNAV10 default 32 if H8606_HVSISTEMAS default 64 if BFIN548_BLUETECHNIX_CM + default 64 if BFIN532_IP0X choice prompt "DDR SDRAM Chip Type" diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig new file mode 100644 index 00000000000..5f6ff04a86c --- /dev/null +++ b/arch/blackfin/configs/IP0X_defconfig @@ -0,0 +1,1252 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# +# CONFIG_MMU is not set +# CONFIG_FPU is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +CONFIG_BLACKFIN=y +CONFIG_ZONE_DMA=y +CONFIG_SEMAPHORE_SLEEPERS=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_GENERIC_TIME is not set +CONFIG_GENERIC_GPIO=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# Blackfin Processor Options +# + +# +# Processor and Board Settings +# +# CONFIG_BF522 is not set +# CONFIG_BF523 is not set +# CONFIG_BF524 is not set +# CONFIG_BF525 is not set +# CONFIG_BF526 is not set +# CONFIG_BF527 is not set +# CONFIG_BF531 is not set +CONFIG_BF532=y +# CONFIG_BF533 is not set +# CONFIG_BF534 is not set +# CONFIG_BF536 is not set +# CONFIG_BF537 is not set +# CONFIG_BF542 is not set +# CONFIG_BF544 is not set +# CONFIG_BF547 is not set +# CONFIG_BF548 is not set +# CONFIG_BF549 is not set +# CONFIG_BF561 is not set +# CONFIG_BF_REV_0_0 is not set +# CONFIG_BF_REV_0_1 is not set +# CONFIG_BF_REV_0_2 is not set +# CONFIG_BF_REV_0_3 is not set +# CONFIG_BF_REV_0_4 is not set +CONFIG_BF_REV_0_5=y +# CONFIG_BF_REV_ANY is not set +# CONFIG_BF_REV_NONE is not set +CONFIG_BF53x=y +CONFIG_BFIN_SINGLE_CORE=y +CONFIG_MEM_MT48LC32M16A2TG_75=y +# CONFIG_BFIN533_EZKIT is not set +# CONFIG_BFIN533_STAMP is not set +# CONFIG_BFIN533_BLUETECHNIX_CM is not set +# CONFIG_H8606_HVSISTEMAS is not set +CONFIG_BFIN532_IP0X=y +# CONFIG_GENERIC_BF533_BOARD is not set + +# +# BF533/2/1 Specific Configuration +# + +# +# Interrupt Priority Assignment +# + +# +# Priority +# +CONFIG_UART_ERROR=7 +CONFIG_SPORT0_ERROR=7 +CONFIG_SPI_ERROR=7 +CONFIG_SPORT1_ERROR=7 +CONFIG_PPI_ERROR=7 +CONFIG_DMA_ERROR=7 +CONFIG_PLLWAKE_ERROR=7 +CONFIG_RTC_ERROR=8 +CONFIG_DMA0_PPI=8 +CONFIG_DMA1_SPORT0RX=9 +CONFIG_DMA2_SPORT0TX=9 +CONFIG_DMA3_SPORT1RX=9 +CONFIG_DMA4_SPORT1TX=9 +CONFIG_DMA5_SPI=10 +CONFIG_DMA6_UARTRX=10 +CONFIG_DMA7_UARTTX=10 +CONFIG_TIMER0=11 +CONFIG_TIMER1=11 +CONFIG_TIMER2=11 +CONFIG_PFA=12 +CONFIG_PFB=12 +CONFIG_MEMDMA0=13 +CONFIG_MEMDMA1=13 +CONFIG_WDTIMER=13 + +# +# Board customizations +# +# CONFIG_CMDLINE_BOOL is not set + +# +# Clock/PLL Setup +# +CONFIG_CLKIN_HZ=10000000 +# CONFIG_BFIN_KERNEL_CLOCK is not set +CONFIG_MAX_VCO_HZ=400000000 +CONFIG_MIN_VCO_HZ=50000000 +CONFIG_MAX_SCLK_HZ=133333333 +CONFIG_MIN_SCLK_HZ=27000000 + +# +# Kernel Timer/Scheduler +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 + +# +# Memory Setup +# +CONFIG_MEM_SIZE=64 +CONFIG_MEM_ADD_WIDTH=10 + +# +# Hardware addresses +# +CONFIG_IP0X_NET1=0x20100000 +CONFIG_IP0X_NET2=0x20200000 +CONFIG_IP0X_USB=0x20300000 +CONFIG_BOOT_LOAD=0x1000 +CONFIG_BFIN_SCRATCH_REG_RETN=y +# CONFIG_BFIN_SCRATCH_REG_RETE is not set +# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set + +# +# Blackfin Kernel Optimizations +# + +# +# Memory Optimizations +# +CONFIG_I_ENTRY_L1=y +CONFIG_EXCPT_IRQ_SYSC_L1=y +CONFIG_DO_IRQ_L1=y +CONFIG_CORE_TIMER_IRQ_L1=y +CONFIG_IDLE_L1=y +CONFIG_SCHEDULE_L1=y +CONFIG_ARITHMETIC_OPS_L1=y +CONFIG_ACCESS_OK_L1=y +CONFIG_MEMSET_L1=y +CONFIG_MEMCPY_L1=y +CONFIG_SYS_BFIN_SPINLOCK_L1=y +# CONFIG_IP_CHECKSUM_L1 is not set +CONFIG_CACHELINE_ALIGNED_L1=y +# CONFIG_SYSCALL_TAB_L1 is not set +# CONFIG_CPLB_SWITCH_TAB_L1 is not set +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LARGE_ALLOCS=y +# CONFIG_BFIN_GPTIMERS is not set +CONFIG_BFIN_DMA_5XX=y +# CONFIG_DMA_UNCACHED_2M is not set +CONFIG_DMA_UNCACHED_1M=y +# CONFIG_DMA_UNCACHED_NONE is not set + +# +# Cache Support +# +# CONFIG_BFIN_ICACHE is not set +# CONFIG_BFIN_DCACHE is not set +# CONFIG_BFIN_ICACHE_LOCK is not set +CONFIG_L1_MAX_PIECE=16 +# CONFIG_MPU is not set + +# +# Asynchonous Memory Configuration +# + +# +# EBIU_AMGCTL Global Control +# +CONFIG_C_AMCKEN=y +CONFIG_C_CDPRIO=y +# CONFIG_C_AMBEN is not set +# CONFIG_C_AMBEN_B0 is not set +# CONFIG_C_AMBEN_B0_B1 is not set +# CONFIG_C_AMBEN_B0_B1_B2 is not set +CONFIG_C_AMBEN_ALL=y + +# +# EBIU_AMBCTL Control +# +CONFIG_BANK_0=0xffc2 +CONFIG_BANK_1=0xffc2 +CONFIG_BANK_2=0xffc2 +CONFIG_BANK_3=0xffc2 + +# +# Bus options (PCI, PCMCIA, EISA, MCA, ISA) +# +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# + +# +# Executable file formats +# +CONFIG_BINFMT_ELF_FDPIC=y +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +# CONFIG_BINFMT_SHARED_FLAT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_LEGACY is not set +# CONFIG_PM_DEBUG is not set +# CONFIG_PM_SYSFS_DEPRECATED is not set +CONFIG_PM_BFIN_SLEEP_DEEPER=y +# CONFIG_PM_BFIN_SLEEP is not set +# CONFIG_PM_WAKEUP_BY_GPIO is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETLABEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +# CONFIG_NF_CONNTRACK_ENABLED is not set +# CONFIG_NF_CONNTRACK is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +CONFIG_NETFILTER_XT_MATCH_MAC=y +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_IPRANGE=y +CONFIG_IP_NF_MATCH_TOS=y +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_TOS=y +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_UCLINUX=y +CONFIG_MTD_PLATRAM=y + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_BFIN=y +CONFIG_BFIN_NAND_BASE=0x20000000 +CONFIG_BFIN_NAND_SIZE=0x10000000 +CONFIG_BFIN_NAND_CLE=2 +CONFIG_BFIN_NAND_ALE=1 +CONFIG_BFIN_NAND_READY=10 +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# Misc devices +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set + +# +# SCSI low-level drivers +# +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_SMC91X is not set +# CONFIG_SMSC911X is not set +CONFIG_DM9000=y +CONFIG_NETDEV_1000=y +# CONFIG_AX88180 is not set +CONFIG_NETDEV_10000=y + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PFLAGS is not set +# CONFIG_BF5xx_PPIFCD is not set +# CONFIG_BFIN_SIMPLE_TIMER is not set +# CONFIG_BF5xx_PPI is not set +CONFIG_BFIN_SPORT=y +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_AD5304 is not set +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_BFIN=y +CONFIG_SERIAL_BFIN_CONSOLE=y +CONFIG_SERIAL_BFIN_DMA=y +# CONFIG_SERIAL_BFIN_PIO is not set +CONFIG_SERIAL_BFIN_UART0=y +# CONFIG_BFIN_UART0_CTSRTS is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_BFIN_SPORT is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set + +# +# CAN, the car bus and industrial fieldbus +# +# CONFIG_CAN4LINUX is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_BFIN_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_HW_RANDOM=y +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set + +# +# SPI support +# +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BFIN=y +# CONFIG_SPI_BITBANG is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +# CONFIG_SPI_SPIDEV is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +CONFIG_USB_OTG_WHITELIST=y +# CONFIG_USB_OTG_BLACKLIST_HUB is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_ISP1362_HCD=y +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +CONFIG_MMC=m +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=m + +# +# MMC/SD Host Controller Drivers +# +CONFIG_SPI_MMC=m +CONFIG_SPI_MMC_FRAMEWORK_DRIVER=y +# CONFIG_SPI_MMC_BFIN_PIO_SPI is not set +CONFIG_SPI_MMC_CS_CHAN=5 +CONFIG_SPI_MMC_MAX_HZ=20000000 +# CONFIG_SPI_MMC_CARD_DETECT is not set +# CONFIG_SPI_MMC_DEBUG_MODE is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# InfiniBand support +# + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_BFIN=y + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# PBX support +# +# CONFIG_PBX is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set +CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10 +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MMRS is not set +CONFIG_DEBUG_HUNT_FOR_ZERO=y +CONFIG_DEBUG_BFIN_HWTRACE_ON=y +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y +# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set +# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 +# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set +# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set +# CONFIG_EARLY_PRINTK is not set +CONFIG_CPLB_INFO=y +CONFIG_ACCESS_CHECK=y + +# +# Security options +# +# CONFIG_KEYS is not set +CONFIG_SECURITY=y +# CONFIG_SECURITY_NETWORK is not set +CONFIG_SECURITY_CAPABILITIES=m +# CONFIG_SECURITY_ROOTPLUG is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/blackfin/mach-bf533/boards/Kconfig b/arch/blackfin/mach-bf533/boards/Kconfig index 751de5110af..840059241fb 100644 --- a/arch/blackfin/mach-bf533/boards/Kconfig +++ b/arch/blackfin/mach-bf533/boards/Kconfig @@ -26,6 +26,12 @@ config H8606_HVSISTEMAS help HV Sistemas H8606 board support. +config BFIN532_IP0X + bool "IP04/IP08 IP-PBX" + depends on (BF532) + help + Core support for IP04/IP04 open hardware IP-PBX. + config GENERIC_BF533_BOARD bool "Generic" help diff --git a/arch/blackfin/mach-bf533/boards/Makefile b/arch/blackfin/mach-bf533/boards/Makefile index 54f57fb9791..b7a1a1d79bd 100644 --- a/arch/blackfin/mach-bf533/boards/Makefile +++ b/arch/blackfin/mach-bf533/boards/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_GENERIC_BF533_BOARD) += generic_board.o obj-$(CONFIG_BFIN533_STAMP) += stamp.o +obj-$(CONFIG_BFIN532_IP0X) += ip0x.o obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o obj-$(CONFIG_BFIN533_BLUETECHNIX_CM) += cm_bf533.o obj-$(CONFIG_H8606_HVSISTEMAS) += H8606.o diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c new file mode 100644 index 00000000000..4af61474a99 --- /dev/null +++ b/arch/blackfin/mach-bf533/boards/ip0x.c @@ -0,0 +1,279 @@ +/* + * File: arch/blackfin/mach-bf533/ip0x.c + * Based on: arch/blackfin/mach-bf533/bf1.c + * Based on: arch/blackfin/mach-bf533/stamp.c + * Author: Ivan Danov + * Modified for IP0X David Rowe + * + * Created: 2007 + * Description: Board info file for the IP04/IP08 boards, which + * are derived from the BlackfinOne V2.0 boards. + * + * Modified: + * COpyright 2007 David Rowe + * Copyright 2006 Intratrade Ltd. + * Copyright 2005 National ICT Australia (NICTA) + * Copyright 2004-2006 Analog Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#include +#endif +#include +#include + +/* + * Name the Board for the /proc/cpuinfo + */ +const char bfin_board_name[] = "IP04/IP08"; + +/* + * Driver needs to know address, irq and flag pin. + */ +#if defined(CONFIG_BFIN532_IP0X) +#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) + +#include + +static struct resource dm9000_resource1[] = { + { + .start = 0x20100000, + .end = 0x20100000 + 1, + .flags = IORESOURCE_MEM + },{ + .start = 0x20100000 + 2, + .end = 0x20100000 + 3, + .flags = IORESOURCE_MEM + },{ + .start = IRQ_PF15, + .end = IRQ_PF15, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE + } +}; + +static struct resource dm9000_resource2[] = { + { + .start = 0x20200000, + .end = 0x20200000 + 1, + .flags = IORESOURCE_MEM + },{ + .start = 0x20200000 + 2, + .end = 0x20200000 + 3, + .flags = IORESOURCE_MEM + },{ + .start = IRQ_PF14, + .end = IRQ_PF14, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE + } +}; + +/* +* for the moment we limit ourselves to 16bit IO until some +* better IO routines can be written and tested +*/ +static struct dm9000_plat_data dm9000_platdata1 = { + .flags = DM9000_PLATF_16BITONLY, +}; + +static struct platform_device dm9000_device1 = { + .name = "dm9000", + .id = 0, + .num_resources = ARRAY_SIZE(dm9000_resource1), + .resource = dm9000_resource1, + .dev = { + .platform_data = &dm9000_platdata1, + } +}; + +static struct dm9000_plat_data dm9000_platdata2 = { + .flags = DM9000_PLATF_16BITONLY, +}; + +static struct platform_device dm9000_device2 = { + .name = "dm9000", + .id = 1, + .num_resources = ARRAY_SIZE(dm9000_resource2), + .resource = dm9000_resource2, + .dev = { + .platform_data = &dm9000_platdata2, + } +}; + +#endif +#endif + + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +/* all SPI peripherals info goes here */ + +#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) +static struct bfin5xx_spi_chip spi_mmc_chip_info = { +/* + * CPOL (Clock Polarity) + * 0 - Active high SCK + * 1 - Active low SCK + * CPHA (Clock Phase) Selects transfer format and operation mode + * 0 - SCLK toggles from middle of the first data bit, slave select + * pins controlled by hardware. + * 1 - SCLK toggles from beginning of first data bit, slave select + * pins controller by user software. + * .ctl_reg = 0x1c00, * CPOL=1,CPHA=1,Sandisk 1G work + * NO NO .ctl_reg = 0x1800, * CPOL=1,CPHA=0 + * NO NO .ctl_reg = 0x1400, * CPOL=0,CPHA=1 + */ + .ctl_reg = 0x1000, /* CPOL=0,CPHA=0,Sandisk 1G work */ + .enable_dma = 0, /* if 1 - block!!! */ + .bits_per_word = 8, + .cs_change_per_word = 0, +}; +#endif + +/* Notice: for blackfin, the speed_hz is the value of register + * SPI_BAUD, not the real baudrate */ +static struct spi_board_info bfin_spi_board_info[] __initdata = { +#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) + { + .modalias = "spi_mmc", + .max_speed_hz = 2, + .bus_num = 1, + .chip_select = CONFIG_SPI_MMC_CS_CHAN, + .platform_data = NULL, + .controller_data = &spi_mmc_chip_info, + }, +#endif +}; + +/* SPI controller data */ +static struct bfin5xx_spi_master spi_bfin_master_info = { + .num_chipselect = 8, + .enable_dma = 1, /* master has the ability to do dma transfer */ +}; + +static struct platform_device spi_bfin_master_device = { + .name = "bfin-spi-master", + .id = 1, /* Bus number */ + .dev = { + .platform_data = &spi_bfin_master_info, /* Passed to driver */ + }, +}; +#endif /* spi master and devices */ + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) +static struct resource bfin_uart_resources[] = { + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device bfin_uart_device = { + .name = "bfin-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_uart_resources), + .resource = bfin_uart_resources, +}; +#endif + +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +static struct resource isp1362_hcd_resources[] = { + { + .start = 0x20300000, + .end = 0x20300000 + 1, + .flags = IORESOURCE_MEM, + },{ + .start = 0x20300000 + 2, + .end = 0x20300000 + 3, + .flags = IORESOURCE_MEM, + },{ + .start = IRQ_PF11, + .end = IRQ_PF11, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct isp1362_platform_data isp1362_priv = { + .sel15Kres = 1, + .clknotstop = 0, + .oc_enable = 0, /* external OC */ + .int_act_high = 0, + .int_edge_triggered = 0, + .remote_wakeup_connected = 0, + .no_power_switching = 1, + .power_switching_mode = 0, +}; + +static struct platform_device isp1362_hcd_device = { + .name = "isp1362-hcd", + .id = 0, + .dev = { + .platform_data = &isp1362_priv, + }, + .num_resources = ARRAY_SIZE(isp1362_hcd_resources), + .resource = isp1362_hcd_resources, +}; +#endif + + +static struct platform_device *ip0x_devices[] __initdata = { +#if defined(CONFIG_BFIN532_IP0X) +#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) + &dm9000_device1, + &dm9000_device2, +#endif +#endif + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) + &spi_bfin_master_device, +#endif + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) + &bfin_uart_device, +#endif +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) + &isp1362_hcd_device, +#endif +}; + +static int __init ip0x_init(void) +{ + int i; + + printk(KERN_INFO "%s(): registering device resources\n", __func__); + platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices)); + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) + for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); ++i) { + int j = 1 << bfin_spi_board_info[i].chip_select; + /* set spi cs to 1 */ + bfin_write_FIO_DIR(bfin_read_FIO_DIR() | j); + bfin_write_FIO_FLAG_S(j); + } + spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); +#endif + + return 0; +} + +arch_initcall(ip0x_init); diff --git a/include/asm-blackfin/mach-bf533/mem_init.h b/include/asm-blackfin/mach-bf533/mem_init.h index 1620dae5254..f8f31901fca 100644 --- a/include/asm-blackfin/mach-bf533/mem_init.h +++ b/include/asm-blackfin/mach-bf533/mem_init.h @@ -29,7 +29,8 @@ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD) +#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \ + CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD) #if (CONFIG_SCLK_HZ > 119402985) #define SDRAM_tRP TRP_2 #define SDRAM_tRP_num 2 @@ -118,6 +119,13 @@ #define SDRAM_CL CL_3 #endif +#if (CONFIG_MEM_MT48LC32M16A2TG_75) + /*SDRAM INFORMATION: */ +#define SDRAM_Tref 64 /* Refresh period in milliseconds */ +#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ +#define SDRAM_CL CL_3 +#endif + #if (CONFIG_MEM_GENERIC_BOARD) /*SDRAM INFORMATION: Modify this for your board */ #define SDRAM_Tref 64 /* Refresh period in milliseconds */ -- cgit v1.2.3 From 681793711abca2b45f210a553962e2c4884b5587 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Apr 2008 05:04:24 +0800 Subject: [Blackfin] arch: declare list of peripherals as const since we dont modify the incoming array Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/bfin_gpio.c | 4 ++-- include/asm-blackfin/portmux.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index 72477c252a9..fcb2f6cf430 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -941,7 +941,7 @@ int peripheral_request(unsigned short per, const char *label) EXPORT_SYMBOL(peripheral_request); #endif -int peripheral_request_list(unsigned short per[], const char *label) +int peripheral_request_list(const unsigned short per[], const char *label) { u16 cnt; int ret; @@ -994,7 +994,7 @@ void peripheral_free(unsigned short per) } EXPORT_SYMBOL(peripheral_free); -void peripheral_free_list(unsigned short per[]) +void peripheral_free_list(const unsigned short per[]) { u16 cnt; for (cnt = 0; per[cnt] != 0; cnt++) diff --git a/include/asm-blackfin/portmux.h b/include/asm-blackfin/portmux.h index 0d3f650d2d9..0807b286cd9 100644 --- a/include/asm-blackfin/portmux.h +++ b/include/asm-blackfin/portmux.h @@ -17,8 +17,8 @@ int peripheral_request(unsigned short per, const char *label); void peripheral_free(unsigned short per); -int peripheral_request_list(unsigned short per[], const char *label); -void peripheral_free_list(unsigned short per[]); +int peripheral_request_list(const unsigned short per[], const char *label); +void peripheral_free_list(const unsigned short per[]); #include #include -- cgit v1.2.3 From 8b6eb473c5f8f9906d8c514a8f352dac275b0f3e Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Apr 2008 05:09:06 +0800 Subject: [Blackfin] arch: remove duplicated prototypes for internal cplb structures from the global blackfin header remove duplicated prototypes for internal cplb structures from the global blackfin header as nothing else should be accessing these Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/cplb-nompu/cplbinfo.c | 4 +--- include/asm-blackfin/bfin-global.h | 9 --------- 2 files changed, 1 insertion(+), 12 deletions(-) diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinfo.c b/arch/blackfin/kernel/cplb-nompu/cplbinfo.c index f7f2eb0b7fe..1e74f0b9799 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinfo.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinfo.c @@ -33,9 +33,7 @@ #include #include -#include -#include -#include +#include #include #define CPLB_I 1 diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h index 08474eb28bb..716df7c8592 100644 --- a/include/asm-blackfin/bfin-global.h +++ b/include/asm-blackfin/bfin-global.h @@ -112,15 +112,6 @@ extern void init_leds(void); extern const char bfin_board_name[]; extern unsigned long wall_jiffies; -extern unsigned long ipdt_table[]; -extern unsigned long dpdt_table[]; -extern unsigned long icplb_table[]; -extern unsigned long dcplb_table[]; - -extern unsigned long ipdt_swapcount_table[]; -extern unsigned long dpdt_swapcount_table[]; - -extern unsigned long table_start, table_end; extern unsigned long bfin_sic_iwr[]; extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ -- cgit v1.2.3 From 3132b58679261ee0edfda3a846539bb1b0750705 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Apr 2008 05:12:09 +0800 Subject: [Blackfin] arch: theres no need to declare ram{end,start,base} in the head.S files theres no need to declare ram{end,start,base} in the head.S files when declaring them with the other memory related variables in setup.c is so much simpler/nicer Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 1 + arch/blackfin/mach-bf527/head.S | 18 ------------------ arch/blackfin/mach-bf533/head.S | 18 ------------------ arch/blackfin/mach-bf537/head.S | 18 ------------------ arch/blackfin/mach-bf548/head.S | 18 ------------------ arch/blackfin/mach-bf561/head.S | 18 ------------------ 6 files changed, 1 insertion(+), 90 deletions(-) diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index a871d835824..3f10aa4465f 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -35,6 +35,7 @@ u16 _bfin_swrst; EXPORT_SYMBOL(_bfin_swrst); unsigned long memory_start, memory_end, physical_mem_end; +unsigned long _rambase, _ramstart, _ramend; unsigned long reserved_mem_dcache_on; unsigned long reserved_mem_icache_on; EXPORT_SYMBOL(memory_start); diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S index cdb00a08496..57bdb3ba2fe 100644 --- a/arch/blackfin/mach-bf527/head.S +++ b/arch/blackfin/mach-bf527/head.S @@ -37,9 +37,6 @@ #include #endif -.global __rambase -.global __ramstart -.global __ramend .extern ___bss_stop .extern ___bss_start .extern _bf53x_relocate_l1_mem @@ -439,18 +436,3 @@ ENTRY(_start_dma_code) RTS; ENDPROC(_start_dma_code) #endif /* CONFIG_BFIN_KERNEL_CLOCK */ - -.data - -/* - * Set up the usable of RAM stuff. Size of RAM is determined then - * an initial stack set up at the end. - */ - -.align 4 -__rambase: -.long 0 -__ramstart: -.long 0 -__ramend: -.long 0 diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S index d9ba2b11e01..1295deac00a 100644 --- a/arch/blackfin/mach-bf533/head.S +++ b/arch/blackfin/mach-bf533/head.S @@ -36,9 +36,6 @@ #include #endif -.global __rambase -.global __ramstart -.global __ramend .extern ___bss_stop .extern ___bss_start .extern _bf53x_relocate_l1_mem @@ -431,18 +428,3 @@ ENTRY(_start_dma_code) RTS; ENDPROC(_start_dma_code) #endif /* CONFIG_BFIN_KERNEL_CLOCK */ - -.data - -/* - * Set up the usable of RAM stuff. Size of RAM is determined then - * an initial stack set up at the end. - */ - -.align 4 -__rambase: -.long 0 -__ramstart: -.long 0 -__ramend: -.long 0 diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index 9e9fac9c634..48cd58a410a 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S @@ -37,9 +37,6 @@ #include #endif -.global __rambase -.global __ramstart -.global __ramend .extern ___bss_stop .extern ___bss_start .extern _bf53x_relocate_l1_mem @@ -471,18 +468,3 @@ ENTRY(_start_dma_code) RTS; ENDPROC(_start_dma_code) #endif /* CONFIG_BFIN_KERNEL_CLOCK */ - -.data - -/* - * Set up the usable of RAM stuff. Size of RAM is determined then - * an initial stack set up at the end. - */ - -.align 4 -__rambase: -.long 0 -__ramstart: -.long 0 -__ramend: -.long 0 diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S index 46222a75321..f7191141a3c 100644 --- a/arch/blackfin/mach-bf548/head.S +++ b/arch/blackfin/mach-bf548/head.S @@ -36,9 +36,6 @@ #include #endif -.global __rambase -.global __ramstart -.global __ramend .extern ___bss_stop .extern ___bss_start .extern _bf53x_relocate_l1_mem @@ -456,18 +453,3 @@ ENTRY(_start_dma_code) RTS; ENDPROC(_start_dma_code) #endif /* CONFIG_BFIN_KERNEL_CLOCK */ - -.data - -/* - * Set up the usable of RAM stuff. Size of RAM is determined then - * an initial stack set up at the end. - */ - -.align 4 -__rambase: -.long 0 -__ramstart: -.long 0 -__ramend: -.long 0 diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S index 279e2e812a2..5b8bd40851d 100644 --- a/arch/blackfin/mach-bf561/head.S +++ b/arch/blackfin/mach-bf561/head.S @@ -37,9 +37,6 @@ #include #endif -.global __rambase -.global __ramstart -.global __ramend .extern ___bss_stop .extern ___bss_start .extern _bf53x_relocate_l1_mem @@ -411,18 +408,3 @@ ENTRY(_start_dma_code) RTS; ENDPROC(_start_dma_code) #endif /* CONFIG_BFIN_KERNEL_CLOCK */ - -.data - -/* - * Set up the usable of RAM stuff. Size of RAM is determined then - * an initial stack set up at the end. - */ - -.align 4 -__rambase: -.long 0 -__ramstart: -.long 0 -__ramend: -.long 0 -- cgit v1.2.3 From 8cab0288c6376b9c00155b0802cbe84118d1ba89 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Apr 2008 05:13:10 +0800 Subject: [Blackfin] arch: add boot messages to quickly distinguish between MPU/NOMPU settings Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/cplb-mpu/cplbinit.c | 2 ++ arch/blackfin/kernel/cplb-nompu/cplbinit.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c index 7310e5fc639..48060105346 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c @@ -43,6 +43,8 @@ void __init generate_cpl_tables(void) unsigned long d_data, i_data; unsigned long d_cache = 0, i_cache = 0; + printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n"); + #ifdef CONFIG_BFIN_ICACHE i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; #endif diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index dd46b666fd4..f271f39d565 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -318,6 +318,8 @@ void __init generate_cpl_tables(void) struct cplb_tab *t_d = NULL; struct s_cplb cplb; + printk(KERN_INFO "NOMPU: setting up cplb tables for global access\n"); + cplb.init_i.size = MAX_CPLBS; cplb.init_d.size = MAX_CPLBS; cplb.switch_i.size = MAX_SWITCH_I_CPLBS; -- cgit v1.2.3 From 764cb81cdc0620711d2cef5d06e9ef03c9d84184 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Apr 2008 05:07:29 +0800 Subject: [Blackfin] arch: actually implement get_cycles function Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/time-ts.c | 5 ++--- include/asm-blackfin/timex.h | 17 +++++++++++------ 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c index 3aad6d71072..1ce8cb1e498 100644 --- a/arch/blackfin/kernel/time-ts.c +++ b/arch/blackfin/kernel/time-ts.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -35,9 +36,7 @@ static inline unsigned long long cycles_2_ns(cycle_t cyc) static cycle_t read_cycles(void) { - unsigned long tmp, tmp2; - asm("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2)); - return tmp | ((cycle_t)tmp2 << 32); + return get_cycles(); } unsigned long long sched_clock(void) diff --git a/include/asm-blackfin/timex.h b/include/asm-blackfin/timex.h index 828590117f5..22b0806161b 100644 --- a/include/asm-blackfin/timex.h +++ b/include/asm-blackfin/timex.h @@ -1,18 +1,23 @@ -/* blackfin architecture timex specifications: Lineo Inc. 2001 +/* + * asm-blackfin/timex.h: cpu cycles! * - * Based on: include/asm-m68knommu/timex.h + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. */ -#ifndef _ASMBLACKFIN_TIMEX_H -#define _ASMBLACKFIN_TIMEX_H +#ifndef _ASM_BLACKFIN_TIMEX_H +#define _ASM_BLACKFIN_TIMEX_H #define CLOCK_TICK_RATE 1000000 /* Underlying HZ */ -typedef unsigned long cycles_t; +typedef unsigned long long cycles_t; static inline cycles_t get_cycles(void) { - return 0; + unsigned long tmp, tmp2; + __asm__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2)); + return tmp | ((cycles_t)tmp2 << 32); } #endif -- cgit v1.2.3 From 37fa24212e68e11aee54d4c0d0becb8fc63555c6 Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Thu, 24 Apr 2008 05:19:02 +0800 Subject: [Blackfin] arch: Allow AD1836A board to be connected, either to SPORT2 or SPORT3. Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf548/boards/ezkit.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index acbfb0fc028..073bfdd56aa 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -403,6 +403,14 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { }; #endif +#if defined(CONFIG_SND_BLACKFIN_AD1836) \ + || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) +static struct bfin5xx_spi_chip ad1836_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 16, +}; +#endif + #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) static struct bfin5xx_spi_chip spi_ad7877_chip_info = { .cs_change_per_word = 0, @@ -446,6 +454,16 @@ static struct spi_board_info bf54x_spi_board_info[] __initdata = { .mode = SPI_MODE_3, }, #endif +#if defined(CONFIG_SND_BLACKFIN_AD1836) \ + || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) + { + .modalias = "ad1836-spi", + .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 1, + .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .controller_data = &ad1836_spi_chip_info, + }, +#endif #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) { .modalias = "ad7877", -- cgit v1.2.3 From ac86a9785384843e8359c45a042cc4f87953d4c8 Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Thu, 24 Apr 2008 05:23:31 +0800 Subject: [Blackfin] arch: Consistently export base_addr for all Blackfin variants. Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf527/dma.c | 3 +++ arch/blackfin/mach-bf533/dma.c | 3 +++ arch/blackfin/mach-bf537/dma.c | 3 +++ arch/blackfin/mach-bf548/dma.c | 2 +- arch/blackfin/mach-bf561/dma.c | 3 +++ 5 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c index 522de24cc39..0a82b154c08 100644 --- a/arch/blackfin/mach-bf527/dma.c +++ b/arch/blackfin/mach-bf527/dma.c @@ -26,6 +26,8 @@ * to the Free Software Foundation, Inc., * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include + #include #include @@ -47,6 +49,7 @@ struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, }; +EXPORT_SYMBOL(base_addr); int channel2irq(unsigned int channel) { diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c index 6c909cf4f7b..8d80efce396 100644 --- a/arch/blackfin/mach-bf533/dma.c +++ b/arch/blackfin/mach-bf533/dma.c @@ -26,6 +26,8 @@ * to the Free Software Foundation, Inc., * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include + #include #include @@ -43,6 +45,7 @@ struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, }; +EXPORT_SYMBOL(base_addr); int channel2irq(unsigned int channel) { diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c index 706cb97b026..992b19f400e 100644 --- a/arch/blackfin/mach-bf537/dma.c +++ b/arch/blackfin/mach-bf537/dma.c @@ -26,6 +26,8 @@ * to the Free Software Foundation, Inc., * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include + #include #include @@ -47,6 +49,7 @@ struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, }; +EXPORT_SYMBOL(base_addr); int channel2irq(unsigned int channel) { diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c index f5479298bb7..e78a8833149 100644 --- a/arch/blackfin/mach-bf548/dma.c +++ b/arch/blackfin/mach-bf548/dma.c @@ -32,7 +32,7 @@ #include #include - struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { +struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) DMA0_NEXT_DESC_PTR, (struct dma_register *) DMA1_NEXT_DESC_PTR, (struct dma_register *) DMA2_NEXT_DESC_PTR, diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c index 89c65bb0bed..9863ae4fb8a 100644 --- a/arch/blackfin/mach-bf561/dma.c +++ b/arch/blackfin/mach-bf561/dma.c @@ -26,6 +26,8 @@ * to the Free Software Foundation, Inc., * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include + #include #include @@ -67,6 +69,7 @@ struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR, (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR, }; +EXPORT_SYMBOL(base_addr); int channel2irq(unsigned int channel) { -- cgit v1.2.3 From 7795566495ff90c541a4654d3c903ab277abadfd Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Thu, 24 Apr 2008 05:31:18 +0800 Subject: [Blackfin] arch: Give the DMA base registers a more descriptive name The DMA base registers are available in a global named "base_addr" for every Blackfin variant. Give this a more descriptive name, and remove duplicate tables from some drivers. Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu --- arch/blackfin/kernel/bfin_dma_5xx.c | 2 +- arch/blackfin/mach-bf527/dma.c | 4 ++-- arch/blackfin/mach-bf533/dma.c | 4 ++-- arch/blackfin/mach-bf537/dma.c | 4 ++-- arch/blackfin/mach-bf548/dma.c | 4 ++-- arch/blackfin/mach-bf561/dma.c | 4 ++-- include/asm-blackfin/dma.h | 3 +++ include/asm-blackfin/mach-bf527/dma.h | 3 --- include/asm-blackfin/mach-bf533/dma.h | 3 --- include/asm-blackfin/mach-bf537/dma.h | 3 --- include/asm-blackfin/mach-bf548/dma.h | 2 -- include/asm-blackfin/mach-bf561/dma.h | 3 --- 12 files changed, 14 insertions(+), 25 deletions(-) diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c index 8fd5d22cec3..18fc8a83594 100644 --- a/arch/blackfin/kernel/bfin_dma_5xx.c +++ b/arch/blackfin/kernel/bfin_dma_5xx.c @@ -67,7 +67,7 @@ static int __init blackfin_dma_init(void) for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++) { dma_ch[i].chan_status = DMA_CHANNEL_FREE; - dma_ch[i].regs = base_addr[i]; + dma_ch[i].regs = dma_io_base_addr[i]; mutex_init(&(dma_ch[i].dmalock)); } /* Mark MEMDMA Channel 0 as requested since we're using it internally */ diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c index 0a82b154c08..dfd080cda78 100644 --- a/arch/blackfin/mach-bf527/dma.c +++ b/arch/blackfin/mach-bf527/dma.c @@ -31,7 +31,7 @@ #include #include -struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { +struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) DMA0_NEXT_DESC_PTR, (struct dma_register *) DMA1_NEXT_DESC_PTR, (struct dma_register *) DMA2_NEXT_DESC_PTR, @@ -49,7 +49,7 @@ struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, }; -EXPORT_SYMBOL(base_addr); +EXPORT_SYMBOL(dma_io_base_addr); int channel2irq(unsigned int channel) { diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c index 8d80efce396..28655c1cb7d 100644 --- a/arch/blackfin/mach-bf533/dma.c +++ b/arch/blackfin/mach-bf533/dma.c @@ -31,7 +31,7 @@ #include #include -struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { +struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) DMA0_NEXT_DESC_PTR, (struct dma_register *) DMA1_NEXT_DESC_PTR, (struct dma_register *) DMA2_NEXT_DESC_PTR, @@ -45,7 +45,7 @@ struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, }; -EXPORT_SYMBOL(base_addr); +EXPORT_SYMBOL(dma_io_base_addr); int channel2irq(unsigned int channel) { diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c index 992b19f400e..4edb363ff99 100644 --- a/arch/blackfin/mach-bf537/dma.c +++ b/arch/blackfin/mach-bf537/dma.c @@ -31,7 +31,7 @@ #include #include -struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { +struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) DMA0_NEXT_DESC_PTR, (struct dma_register *) DMA1_NEXT_DESC_PTR, (struct dma_register *) DMA2_NEXT_DESC_PTR, @@ -49,7 +49,7 @@ struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, }; -EXPORT_SYMBOL(base_addr); +EXPORT_SYMBOL(dma_io_base_addr); int channel2irq(unsigned int channel) { diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c index e78a8833149..74730eb8ae1 100644 --- a/arch/blackfin/mach-bf548/dma.c +++ b/arch/blackfin/mach-bf548/dma.c @@ -32,7 +32,7 @@ #include #include -struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { +struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) DMA0_NEXT_DESC_PTR, (struct dma_register *) DMA1_NEXT_DESC_PTR, (struct dma_register *) DMA2_NEXT_DESC_PTR, @@ -66,7 +66,7 @@ struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) MDMA_D3_NEXT_DESC_PTR, (struct dma_register *) MDMA_S3_NEXT_DESC_PTR, }; -EXPORT_SYMBOL(base_addr); +EXPORT_SYMBOL(dma_io_base_addr); int channel2irq(unsigned int channel) { diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c index 9863ae4fb8a..24415eb8269 100644 --- a/arch/blackfin/mach-bf561/dma.c +++ b/arch/blackfin/mach-bf561/dma.c @@ -31,7 +31,7 @@ #include #include -struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { +struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) DMA1_0_NEXT_DESC_PTR, (struct dma_register *) DMA1_1_NEXT_DESC_PTR, (struct dma_register *) DMA1_2_NEXT_DESC_PTR, @@ -69,7 +69,7 @@ struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR, (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR, }; -EXPORT_SYMBOL(base_addr); +EXPORT_SYMBOL(dma_io_base_addr); int channel2irq(unsigned int channel) { diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h index 16d493574ba..c0d5259e315 100644 --- a/include/asm-blackfin/dma.h +++ b/include/asm-blackfin/dma.h @@ -191,4 +191,7 @@ void clear_dma_irqstat(unsigned int channel); void *dma_memcpy(void *dest, const void *src, size_t count); void *safe_dma_memcpy(void *dest, const void *src, size_t count); +extern int channel2irq(unsigned int channel); +extern struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL]; + #endif diff --git a/include/asm-blackfin/mach-bf527/dma.h b/include/asm-blackfin/mach-bf527/dma.h index 2dfee12864f..49dd693223e 100644 --- a/include/asm-blackfin/mach-bf527/dma.h +++ b/include/asm-blackfin/mach-bf527/dma.h @@ -59,7 +59,4 @@ #define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */ #endif -extern int channel2irq(unsigned int channel); -extern struct dma_register *base_addr[]; - #endif diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h index 16c672c01d8..bd9d5e94307 100644 --- a/include/asm-blackfin/mach-bf533/dma.h +++ b/include/asm-blackfin/mach-bf533/dma.h @@ -51,7 +51,4 @@ #define CH_MEM_STREAM1_DEST 10 /* TX */ #define CH_MEM_STREAM1_SRC 11 /* RX */ -extern int channel2irq(unsigned int channel); -extern struct dma_register *base_addr[]; - #endif diff --git a/include/asm-blackfin/mach-bf537/dma.h b/include/asm-blackfin/mach-bf537/dma.h index 021991984e6..7a964040870 100644 --- a/include/asm-blackfin/mach-bf537/dma.h +++ b/include/asm-blackfin/mach-bf537/dma.h @@ -52,7 +52,4 @@ #define CH_MEM_STREAM1_DEST 14 /* TX */ #define CH_MEM_STREAM1_SRC 15 /* RX */ -extern int channel2irq(unsigned int channel); -extern struct dma_register *base_addr[]; - #endif diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h index 46ff31f20ae..36a2ef7e784 100644 --- a/include/asm-blackfin/mach-bf548/dma.h +++ b/include/asm-blackfin/mach-bf548/dma.h @@ -73,6 +73,4 @@ #define MAX_BLACKFIN_DMA_CHANNEL 32 -extern int channel2irq(unsigned int channel); -extern struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL]; #endif diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h index 766334b7d8a..21d982003e7 100644 --- a/include/asm-blackfin/mach-bf561/dma.h +++ b/include/asm-blackfin/mach-bf561/dma.h @@ -32,7 +32,4 @@ #define CH_IMEM_STREAM1_SRC 34 #define CH_IMEM_STREAM1_DEST 35 -extern int channel2irq(unsigned int channel); -extern struct dma_register *base_addr[]; - #endif -- cgit v1.2.3 From 4e354b54991fd7d589c8e5753eea58a1afcae30a Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Apr 2008 05:44:32 +0800 Subject: [Blackfin] arch: cplb-mpu code clean up - allow bootrom to be readable from supervisor mode - delete unused local variable "addr" - punt unused local defines of cplbinfo.c Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/cplb-mpu/cplbinfo.c | 8 -------- arch/blackfin/kernel/cplb-mpu/cplbmgr.c | 6 +++++- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinfo.c b/arch/blackfin/kernel/cplb-mpu/cplbinfo.c index bd072299f7f..822beefa3a4 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbinfo.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbinfo.c @@ -39,14 +39,6 @@ #include #include -#define CPLB_I 1 -#define CPLB_D 2 - -#define SYNC_SYS SSYNC() -#define SYNC_CORE CSYNC() - -#define CPLB_BIT_PAGESIZE 0x30000 - static char page_size_string_table[][4] = { "1K", "4K", "1M", "4M" }; static char *cplb_print_entry(char *buf, struct cplb_entry *tbl, int switched) diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index 3377cbf28fb..3b165bbe90f 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c @@ -161,6 +161,11 @@ static noinline int dcplb_miss(void) addr &= ~0x3fffff; d_data &= ~PAGE_SIZE_4KB; d_data |= PAGE_SIZE_4MB; + } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH + && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) { + addr &= ~(1 * 1024 * 1024 - 1); + d_data &= ~PAGE_SIZE_4KB; + d_data |= PAGE_SIZE_1MB | CPLB_USER_RD; } else return CPLB_PROT_VIOL; } else if (addr >= _ramend) { @@ -277,7 +282,6 @@ static noinline int icplb_miss(void) static noinline int dcplb_protection_fault(void) { - unsigned long addr = bfin_read_DCPLB_FAULT_ADDR(); int status = bfin_read_DCPLB_STATUS(); nr_dcplb_prot++; -- cgit v1.2.3 From 16428a4fa99d273fe27aaee7a847a9cfd5466fda Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Apr 2008 05:56:07 +0800 Subject: [Blackfin] arch: make the mask explicit rather than writing a negative number in hex Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/mach-common/lock.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S index 28b87fe9ce3..30b887e67dd 100644 --- a/arch/blackfin/mach-common/lock.S +++ b/arch/blackfin/mach-common/lock.S @@ -174,7 +174,7 @@ ENTRY(_cache_lock) CLI R3; R7 = [P1]; - R2 = 0xFFFFFF87 (X); + R2 = ~(0x78) (X); /* mask out ILOC */ R7 = R7 & R2; R0 = R0 << 3; R7 = R0 | R7; -- cgit v1.2.3 From 253bcf4f9b6dde1cfa169bc29655cf177d6a903b Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Thu, 24 Apr 2008 05:57:13 +0800 Subject: [Blackfin] arch: Add a little bit more runtime info for MPU Signed-off-by: Robin Getz Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 3f10aa4465f..fafaccb321f 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -898,12 +898,17 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n" "cpu family\t: 0x%x\n" - "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK)\n" + "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n" "stepping\t: %d\n", 0, vendor, (bfin_read_CHIPID() & CHIPID_FAMILY), cpu, cclk/1000000, sclk/1000000, +#ifdef CONFIG_MPU + "mpu on", +#else + "mpu off", +#endif revid); seq_printf(m, "cpu MHz\t\t: %lu.%03lu/%lu.%03lu\n", @@ -1012,7 +1017,6 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "No Ways are locked\n"); } #endif - seq_printf(m, "board name\t: %s\n", bfin_board_name); seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); -- cgit v1.2.3 From b85b82d980526d683dc3b39f2ac1f447fa84a105 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 24 Apr 2008 06:13:37 +0800 Subject: [Blackfin] arch: fix bug - Section data_l1_cacheline_aligned should be defined in link script of kernel http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3978 Section data_l1_cacheline_aligned should be defined in link script of kernel, when L1 data sram bank A is not available. In bf536 with all data cache is enabled, there is no L1 data sram. Current link script won't define section data_l1.cacheline_aligned in this case. But, if user select put cacheline_aligned data into l1 sram in kernel menuconfig, these data will be dropped and access to these data will trigger data CPLB exception. Do panic in l1 relocation code as well. Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 6 +++--- arch/blackfin/kernel/vmlinux.lds.S | 5 +++++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index fafaccb321f..c494495af40 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -107,7 +107,7 @@ void __init bf53x_relocate_l1_mem(void) l1_code_length = _etext_l1 - _stext_l1; if (l1_code_length > L1_CODE_LENGTH) - l1_code_length = L1_CODE_LENGTH; + panic("L1 Instruction SRAM Overflow\n"); /* cannot complain as printk is not available as yet. * But we can continue booting and complain later! */ @@ -117,14 +117,14 @@ void __init bf53x_relocate_l1_mem(void) l1_data_a_length = _ebss_l1 - _sdata_l1; if (l1_data_a_length > L1_DATA_A_LENGTH) - l1_data_a_length = L1_DATA_A_LENGTH; + panic("L1 Data SRAM Bank A Overflow\n"); /* Copy _sdata_l1 to _ebss_l1 to L1 data bank A SRAM */ dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length); l1_data_b_length = _ebss_b_l1 - _sdata_b_l1; if (l1_data_b_length > L1_DATA_B_LENGTH) - l1_data_b_length = L1_DATA_B_LENGTH; + panic("L1 Data SRAM Bank B Overflow\n"); /* Copy _sdata_b_l1 to _ebss_b_l1 to L1 data bank B SRAM */ dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length + diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S index 7a1200328ac..288dfdbfb61 100644 --- a/arch/blackfin/kernel/vmlinux.lds.S +++ b/arch/blackfin/kernel/vmlinux.lds.S @@ -83,6 +83,11 @@ SECTIONS . = ALIGN(32); *(.data.cacheline_aligned) +#if !L1_DATA_A_LENGTH + . = ALIGN(32); + *(.data_l1.cacheline_aligned) +#endif + DATA_DATA *(.data.*) CONSTRUCTORS -- cgit v1.2.3 From 9f8e895d6cc2f871bca6df2ad6791671de2adeae Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Apr 2008 06:20:11 +0800 Subject: [Blackfin] arch: now that we can panic() early, dont need the delayed L1 overflow check Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index c494495af40..c2f3e73ba25 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -129,7 +129,6 @@ void __init bf53x_relocate_l1_mem(void) /* Copy _sdata_b_l1 to _ebss_b_l1 to L1 data bank B SRAM */ dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length + l1_data_a_length, l1_data_b_length); - } /* add_memory_region to memmap */ @@ -652,7 +651,7 @@ static __init void setup_bootmem_allocator(void) void __init setup_arch(char **cmdline_p) { - unsigned long l1_length, sclk, cclk; + unsigned long sclk, cclk; #ifdef CONFIG_DUMMY_CONSOLE conswitchp = &dummy_con; @@ -751,15 +750,6 @@ void __init setup_arch(char **cmdline_p) paging_init(); - /* check the size of the l1 area */ - l1_length = _etext_l1 - _stext_l1; - if (l1_length > L1_CODE_LENGTH) - panic("L1 code memory overflow\n"); - - l1_length = _ebss_l1 - _sdata_l1; - if (l1_length > L1_DATA_A_LENGTH) - panic("L1 data memory overflow\n"); - /* Copy atomic sequences to their fixed location, and sanity check that these locations are the ones that we advertise to userspace. */ memcpy((void *)FIXED_CODE_START, &fixed_code_start, -- cgit v1.2.3 From bc6e0fa1596ff0c2cc0de0d000270050b6ba43bf Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Apr 2008 06:21:25 +0800 Subject: [Blackfin] arch: use the same style for missing L1 sections Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/vmlinux.lds.S | 47 ++++++++++++++++---------------------- 1 file changed, 20 insertions(+), 27 deletions(-) diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S index 288dfdbfb61..3ecc64cab3b 100644 --- a/arch/blackfin/kernel/vmlinux.lds.S +++ b/arch/blackfin/kernel/vmlinux.lds.S @@ -56,6 +56,10 @@ SECTIONS *(.text.*) *(.fixup) +#if !L1_CODE_LENGTH + *(.l1.text) +#endif + . = ALIGN(16); ___start___ex_table = .; *(__ex_table) @@ -73,6 +77,12 @@ SECTIONS ___bss_start = .; *(.bss .bss.*) *(COMMON) +#if !L1_DATA_A_LENGTH + *(.l1.bss) +#endif +#if !L1_DATA_B_LENGTH + *(.l1.bss.B) +#endif ___bss_stop = .; } @@ -86,6 +96,10 @@ SECTIONS #if !L1_DATA_A_LENGTH . = ALIGN(32); *(.data_l1.cacheline_aligned) + *(.l1.data) +#endif +#if !L1_DATA_B_LENGTH + *(.l1.data.B) #endif DATA_DATA @@ -152,64 +166,43 @@ SECTIONS __l1_lma_start = .; -#if L1_CODE_LENGTH -# define LDS_L1_CODE *(.l1.text) -#else -# define LDS_L1_CODE -#endif .text_l1 L1_CODE_START : AT(LOADADDR(.init.ramfs) + SIZEOF(.init.ramfs)) { . = ALIGN(4); __stext_l1 = .; - LDS_L1_CODE + *(.l1.text) . = ALIGN(4); __etext_l1 = .; } -#if L1_DATA_A_LENGTH -# define LDS_L1_A_DATA *(.l1.data) -# define LDS_L1_A_BSS *(.l1.bss) -# define LDS_L1_A_CACHE *(.data_l1.cacheline_aligned) -#else -# define LDS_L1_A_DATA -# define LDS_L1_A_BSS -# define LDS_L1_A_CACHE -#endif .data_l1 L1_DATA_A_START : AT(LOADADDR(.text_l1) + SIZEOF(.text_l1)) { . = ALIGN(4); __sdata_l1 = .; - LDS_L1_A_DATA + *(.l1.data) __edata_l1 = .; . = ALIGN(4); __sbss_l1 = .; - LDS_L1_A_BSS + *(.l1.bss) . = ALIGN(32); - LDS_L1_A_CACHE + *(.data_l1.cacheline_aligned) . = ALIGN(4); __ebss_l1 = .; } -#if L1_DATA_B_LENGTH -# define LDS_L1_B_DATA *(.l1.data.B) -# define LDS_L1_B_BSS *(.l1.bss.B) -#else -# define LDS_L1_B_DATA -# define LDS_L1_B_BSS -#endif .data_b_l1 L1_DATA_B_START : AT(LOADADDR(.data_l1) + SIZEOF(.data_l1)) { . = ALIGN(4); __sdata_b_l1 = .; - LDS_L1_B_DATA + *(.l1.data.B) __edata_b_l1 = .; . = ALIGN(4); __sbss_b_l1 = .; - LDS_L1_B_BSS + *(.l1.bss.B) . = ALIGN(4); __ebss_b_l1 = .; -- cgit v1.2.3 From ac76d889b5e1f829f71a1527a00dc8048c2c2660 Mon Sep 17 00:00:00 2001 From: Grace Pan Date: Thu, 24 Apr 2008 06:33:56 +0800 Subject: [Blackfin] arch: Adjust the u-boot and kernel image partition size in mtd device. Signed-off-by: Grace Pan Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf527/boards/ezkit.c | 2 +- arch/blackfin/mach-bf548/boards/ezkit.c | 2 +- arch/blackfin/mach-bf561/boards/ezkit.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index 1452391fe95..be20f79a7fe 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -416,7 +416,7 @@ static struct platform_device net2272_bfin_device = { static struct mtd_partition bfin_spi_flash_partitions[] = { { .name = "bootloader", - .size = 0x00020000, + .size = 0x00040000, .offset = 0, .mask_flags = MTD_CAP_ROM }, { diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 073bfdd56aa..548820d25eb 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -339,7 +339,7 @@ static struct mtd_partition ezkit_partitions[] = { .offset = 0, }, { .name = "Kernel", - .size = 0xE0000, + .size = 0x1C0000, .offset = MTDPART_OFS_APPEND, }, { .name = "RootFS", diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 984d654cc8d..8eb79e526ad 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -228,7 +228,7 @@ static struct mtd_partition ezkit_partitions[] = { .offset = 0, }, { .name = "Kernel", - .size = 0xE0000, + .size = 0x1C0000, .offset = MTDPART_OFS_APPEND, }, { .name = "RootFS", -- cgit v1.2.3 From 4bea8b20fded93871c872bb4a0d7c23345318184 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Apr 2008 07:23:36 +0800 Subject: [Blackfin] arch: add implicit icplb for the bootrom so we can use the utility functions in the kernel Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/cplb-mpu/cplbmgr.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index 3b165bbe90f..44bbfe26ce4 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c @@ -165,7 +165,7 @@ static noinline int dcplb_miss(void) && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) { addr &= ~(1 * 1024 * 1024 - 1); d_data &= ~PAGE_SIZE_4KB; - d_data |= PAGE_SIZE_1MB | CPLB_USER_RD; + d_data |= PAGE_SIZE_1MB; } else return CPLB_PROT_VIOL; } else if (addr >= _ramend) { @@ -243,7 +243,13 @@ static noinline int icplb_miss(void) #endif if (addr >= physical_mem_end) { - return CPLB_PROT_VIOL; + if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH + && (status & FAULT_USERSUPV)) { + addr &= ~(1 * 1024 * 1024 - 1); + i_data &= ~PAGE_SIZE_4KB; + i_data |= PAGE_SIZE_1MB; + } else + return CPLB_PROT_VIOL; } else if (addr >= _ramend) { i_data |= CPLB_USER_RD; } else { -- cgit v1.2.3 From a81501af19830ff43688781edad7e9c0cbd668af Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 24 Apr 2008 07:32:41 +0800 Subject: [Blackfin] arch: Prevent potential Core Hang situation If the new value written to the PLL_CTL or VR_CTL register is the same as the previous value, the PLL wake-up will occur immediately (PLL is already locked), but the core and system clock will be bypassed for the PLL_LOCKCNT duration. For this interval, code will execute at the CLKIN rate instead of at the expected CCLK rate. Software should guard against this condition by comparing the current value to the new value before writing the new value. Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf527/cdefBF52x_base.h | 57 +++++++++++++++++++++++- include/asm-blackfin/mach-bf533/cdefBF532.h | 31 +++++++++++-- include/asm-blackfin/mach-bf537/cdefBF534.h | 31 +++++++++++-- include/asm-blackfin/mach-bf548/cdefBF54x_base.h | 37 +++++++++++++-- include/asm-blackfin/mach-bf561/cdefBF561.h | 34 ++++++++++++-- 5 files changed, 172 insertions(+), 18 deletions(-) diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h index 50e14e7da3e..9dbdbec8ea1 100644 --- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h +++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h @@ -29,18 +29,71 @@ */ #ifndef _CDEF_BF52X_H +#define _CDEF_BF52X_H + +#include +#include #include "defBF52x_base.h" +/* Include core specific register pointer definitions */ +#include + /* ==== begin from cdefBF534.h ==== */ /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1; + + if (val == bfin_read_PLL_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + local_irq_restore(flags); +} #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) +/* Writing to VR_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_VR_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1; + + if (val == bfin_read_VR_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + + bfin_write16(VR_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + local_irq_restore(flags); +} #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h index c803e14b529..154655452d4 100644 --- a/include/asm-blackfin/mach-bf533/cdefBF532.h +++ b/include/asm-blackfin/mach-bf533/cdefBF532.h @@ -43,7 +43,27 @@ /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr; + + if (val == bfin_read_PLL_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr = bfin_read32(SIC_IWR); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR, IWR_ENABLE(0)); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR, iwr); + local_irq_restore(flags); +} #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) @@ -57,6 +77,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) { unsigned long flags, iwr; + if (val == bfin_read_VR_CTL()) + return; + + local_irq_save(flags); /* Enable the PLL Wakeup bit in SIC IWR */ iwr = bfin_read32(SIC_IWR); /* Only allow PPL Wakeup) */ @@ -64,11 +88,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write16(VR_CTL, val); SSYNC(); - - local_irq_save(flags); asm("IDLE;"); - local_irq_restore(flags); + bfin_write32(SIC_IWR, iwr); + local_irq_restore(flags); } /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h index 048d26a61fd..82de526f809 100644 --- a/include/asm-blackfin/mach-bf537/cdefBF534.h +++ b/include/asm-blackfin/mach-bf537/cdefBF534.h @@ -44,7 +44,27 @@ /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr; + + if (val == bfin_read_PLL_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr = bfin_read32(SIC_IWR); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR, IWR_ENABLE(0)); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR, iwr); + local_irq_restore(flags); +} #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) @@ -53,6 +73,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) { unsigned long flags, iwr; + if (val == bfin_read_VR_CTL()) + return; + + local_irq_save(flags); /* Enable the PLL Wakeup bit in SIC IWR */ iwr = bfin_read32(SIC_IWR); /* Only allow PPL Wakeup) */ @@ -60,11 +84,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write16(VR_CTL, val); SSYNC(); - - local_irq_save(flags); asm("IDLE;"); - local_irq_restore(flags); + bfin_write32(SIC_IWR, iwr); + local_irq_restore(flags); } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index 33c67500717..57ac8cb9b1f 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -43,7 +43,33 @@ /* PLL Registers */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1, iwr2; + + if (val == bfin_read_PLL_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + iwr2 = bfin_read32(SIC_IWR2); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + bfin_write32(SIC_IWR2, 0); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + bfin_write32(SIC_IWR2, iwr2); + local_irq_restore(flags); +} #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) @@ -52,6 +78,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) { unsigned long flags, iwr0, iwr1, iwr2; + if (val == bfin_read_VR_CTL()) + return; + + local_irq_save(flags); /* Enable the PLL Wakeup bit in SIC IWR */ iwr0 = bfin_read32(SIC_IWR0); iwr1 = bfin_read32(SIC_IWR1); @@ -63,13 +93,12 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write16(VR_CTL, val); SSYNC(); - - local_irq_save(flags); asm("IDLE;"); - local_irq_restore(flags); + bfin_write32(SIC_IWR0, iwr0); bfin_write32(SIC_IWR1, iwr1); bfin_write32(SIC_IWR2, iwr2); + local_irq_restore(flags); } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h index 1bc8d2f89cc..b07ffccd66d 100644 --- a/include/asm-blackfin/mach-bf561/cdefBF561.h +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h @@ -47,7 +47,30 @@ /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1; + + if (val == bfin_read_PLL_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SICA_IWR0); + iwr1 = bfin_read32(SICA_IWR1); + /* Only allow PPL Wakeup) */ + bfin_write32(SICA_IWR0, IWR_ENABLE(0)); + bfin_write32(SICA_IWR1, 0); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SICA_IWR0, iwr0); + bfin_write32(SICA_IWR1, iwr1); + local_irq_restore(flags); +} #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) @@ -56,6 +79,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) { unsigned long flags, iwr0, iwr1; + if (val == bfin_read_VR_CTL()) + return; + + local_irq_save(flags); /* Enable the PLL Wakeup bit in SIC IWR */ iwr0 = bfin_read32(SICA_IWR0); iwr1 = bfin_read32(SICA_IWR1); @@ -65,12 +92,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write16(VR_CTL, val); SSYNC(); - - local_irq_save(flags); asm("IDLE;"); - local_irq_restore(flags); + bfin_write32(SICA_IWR0, iwr0); bfin_write32(SICA_IWR1, iwr1); + local_irq_restore(flags); } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) -- cgit v1.2.3 From a086ee2268abcfcbf80a114f4602e5b26aa80bf0 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 25 Apr 2008 02:04:05 +0800 Subject: [Blackfin] arch: detect the memory available in the system on the fly by default detect the memory available in the system on the fly by default rather than forcing people to set this manually in the kconfig Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/Kconfig | 26 ++++++++--------- arch/blackfin/kernel/cplb-nompu/cplbinit.c | 10 +++++-- arch/blackfin/kernel/setup.c | 45 +++++++++++++++++++++++++++++- arch/blackfin/mach-common/arch_checks.c | 3 +- 4 files changed, 67 insertions(+), 17 deletions(-) diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 308bbe291d8..75bceee9b9a 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -294,6 +294,11 @@ config BFIN_KERNEL_CLOCK are also not changed, and the Bootloader does 100% of the hardware configuration. +config MEM_SIZE + int "SDRAM Memory Size in MBytes" + depends on BFIN_KERNEL_CLOCK + default 64 + config MEM_ADD_WIDTH int "Memory Address Width" depends on BFIN_KERNEL_CLOCK @@ -373,6 +378,14 @@ config SCLK_DIV This can be between 1 and 15 System Clock = (PLL frequency) / (this setting) +config MAX_MEM_SIZE + int "Max SDRAM Memory Size in MBytes" + depends on !BFIN_KERNEL_CLOCK && !MPU + default 512 + help + This is the max memory size that the kernel will create CPLB + tables for. Your system will not be able to handle any more. + # # Max & Min Speeds for various Chips # @@ -441,19 +454,6 @@ source kernel/time/Kconfig comment "Memory Setup" -config MEM_SIZE - int "SDRAM Memory Size in MBytes" - default 32 if BFIN533_EZKIT - default 64 if BFIN527_EZKIT - default 64 if BFIN537_STAMP - default 64 if BFIN548_EZKIT - default 64 if BFIN561_EZKIT - default 128 if BFIN533_STAMP - default 64 if PNAV10 - default 32 if H8606_HVSISTEMAS - default 64 if BFIN548_BLUETECHNIX_CM - default 64 if BFIN532_IP0X - choice prompt "DDR SDRAM Chip Type" depends on (BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM) diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index f271f39d565..917325bfbd8 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -26,6 +26,12 @@ #include #include +#ifdef CONFIG_MAX_MEM_SIZE +# define CPLB_MEM CONFIG_MAX_MEM_SIZE +#else +# define CPLB_MEM CONFIG_MEM_SIZE +#endif + /* * Number of required data CPLB switchtable entries * MEMSIZE / 4 (we mostly install 4M page size CPLBs @@ -35,7 +41,7 @@ * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO * 1 for ASYNC Memory */ -#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \ +#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \ + ASYNC_MEMORY_CPLB_COVERAGE) * 2) /* @@ -46,7 +52,7 @@ * possibly 1 for L2 Instruction Memory * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO */ -#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2) +#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2) u_long icplb_table[MAX_CPLBS + 1]; diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index c2f3e73ba25..d6668328be7 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -649,6 +649,49 @@ static __init void setup_bootmem_allocator(void) BOOTMEM_DEFAULT); } +#define EBSZ_TO_MEG(ebsz) \ +({ \ + int meg = 0; \ + switch (ebsz & 0xf) { \ + case 0x1: meg = 16; break; \ + case 0x3: meg = 32; break; \ + case 0x5: meg = 64; break; \ + case 0x7: meg = 128; break; \ + case 0x9: meg = 256; break; \ + case 0xb: meg = 512; break; \ + } \ + meg; \ +}) +static inline int __init get_mem_size(void) +{ +#ifdef CONFIG_MEM_SIZE + return CONFIG_MEM_SIZE; +#else +# if defined(EBIU_SDBCTL) +# if defined(BF561_FAMILY) + int ret = 0; + u32 sdbctl = bfin_read_EBIU_SDBCTL(); + ret += EBSZ_TO_MEG(sdbctl >> 0); + ret += EBSZ_TO_MEG(sdbctl >> 8); + ret += EBSZ_TO_MEG(sdbctl >> 16); + ret += EBSZ_TO_MEG(sdbctl >> 24); + return ret; +# else + return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL()); +# endif +# elif defined(EBIU_DDRCTL1) + switch (bfin_read_EBIU_DDRCTL1() & 0xc0000) { + case DEVSZ_64: return 64; + case DEVSZ_128: return 128; + case DEVSZ_256: return 256; + case DEVSZ_512: return 512; + default: return 0; + } +# endif +#endif + BUG(); +} + void __init setup_arch(char **cmdline_p) { unsigned long sclk, cclk; @@ -669,7 +712,7 @@ void __init setup_arch(char **cmdline_p) /* setup memory defaults from the user config */ physical_mem_end = 0; - _ramend = CONFIG_MEM_SIZE * 1024 * 1024; + _ramend = get_mem_size() * 1024 * 1024; memset(&bfin_memmap, 0, sizeof(bfin_memmap)); diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c index 2f6ce397780..caaab49e9cf 100644 --- a/arch/blackfin/mach-common/arch_checks.c +++ b/arch/blackfin/mach-common/arch_checks.c @@ -54,7 +54,8 @@ #endif /* CONFIG_BFIN_KERNEL_CLOCK */ +#ifdef CONFIG_MEM_SIZE #if (CONFIG_MEM_SIZE % 4) #error "SDRAM mem size must be multible of 4MB" #endif - +#endif -- cgit v1.2.3 From affee2b2613ada262eecea354b6c60696ca5d482 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 24 Apr 2008 08:10:10 +0800 Subject: [Blackfin] arch: Allow concurrent use of GPIO and GPIO IRQ The irq setup code no longer calls gpio request and free. This patch also changes the default gpio_free behavior on Blackfin. A freed GPIO keeps it's last state, and is not defaulted back to an input. This is also what all other architectures do. Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- arch/blackfin/kernel/bfin_gpio.c | 45 ++++++++++---------------- arch/blackfin/mach-common/ints-priority.c | 52 ++++++++----------------------- 2 files changed, 30 insertions(+), 67 deletions(-) diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index fcb2f6cf430..7e8eaf4a31b 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -395,32 +395,6 @@ inline void portmux_setup(unsigned short portno, unsigned short function) # define portmux_setup(...) do { } while (0) #endif -#ifndef BF548_FAMILY -static void default_gpio(unsigned gpio) -{ - unsigned short bank, bitmask; - unsigned long flags; - - bank = gpio_bank(gpio); - bitmask = gpio_bit(gpio); - - local_irq_save(flags); - - gpio_bankb[bank]->maska_clear = bitmask; - gpio_bankb[bank]->maskb_clear = bitmask; - SSYNC(); - gpio_bankb[bank]->inen &= ~bitmask; - gpio_bankb[bank]->dir &= ~bitmask; - gpio_bankb[bank]->polar &= ~bitmask; - gpio_bankb[bank]->both &= ~bitmask; - gpio_bankb[bank]->edge &= ~bitmask; - AWA_DUMMY_READ(edge); - local_irq_restore(flags); -} -#else -# define default_gpio(...) do { } while (0) -#endif - static int __init bfin_gpio_init(void) { printk(KERN_INFO "Blackfin GPIO Controller\n"); @@ -1080,8 +1054,6 @@ void gpio_free(unsigned gpio) return; } - default_gpio(gpio); - reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); set_label(gpio, "free"); @@ -1144,6 +1116,18 @@ int gpio_get_value(unsigned gpio) } EXPORT_SYMBOL(gpio_get_value); +void bfin_gpio_irq_prepare(unsigned gpio) +{ + unsigned long flags; + + port_setup(gpio, GPIO_USAGE); + + local_irq_save(flags); + gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio); + gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio); + local_irq_restore(flags); +} + #else int gpio_direction_input(unsigned gpio) @@ -1210,6 +1194,11 @@ void bfin_gpio_reset_spi0_ssel1(void) udelay(1); } +void bfin_gpio_irq_prepare(unsigned gpio) +{ + port_setup(gpio, GPIO_USAGE); +} + #endif /*BF548_FAMILY */ #if defined(CONFIG_PROC_FS) diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index a2a11717bf6..5448230c0e9 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -326,6 +326,7 @@ static void bfin_demux_error_irq(unsigned int int_err_irq, static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; +extern void bfin_gpio_irq_prepare(unsigned gpio); static void bfin_gpio_ack_irq(unsigned int irq) { @@ -364,35 +365,25 @@ static void bfin_gpio_unmask_irq(unsigned int irq) static unsigned int bfin_gpio_irq_startup(unsigned int irq) { - unsigned int ret; u16 gpionr = irq - IRQ_PF0; - char buf[8]; - if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { - snprintf(buf, sizeof buf, "IRQ %d", irq); - ret = gpio_request(gpionr, buf); - if (ret) - return ret; - } + if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) + bfin_gpio_irq_prepare(gpionr); gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); bfin_gpio_unmask_irq(irq); - return ret; + return 0; } static void bfin_gpio_irq_shutdown(unsigned int irq) { bfin_gpio_mask_irq(irq); - gpio_free(irq - IRQ_PF0); gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0); } static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) { - - unsigned int ret; - char buf[8]; u16 gpionr = irq - IRQ_PF0; if (type == IRQ_TYPE_PROBE) { @@ -404,12 +395,8 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { - if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { - snprintf(buf, sizeof buf, "IRQ %d", irq); - ret = gpio_request(gpionr, buf); - if (ret) - return ret; - } + if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) + bfin_gpio_irq_prepare(gpionr); gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); } else { @@ -595,6 +582,8 @@ static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = { (struct pin_int_t *)PINT3_MASK_SET, }; +extern void bfin_gpio_irq_prepare(unsigned gpio); + inline unsigned short get_irq_base(u8 bank, u8 bmap) { @@ -697,8 +686,6 @@ static void bfin_gpio_unmask_irq(unsigned int irq) static unsigned int bfin_gpio_irq_startup(unsigned int irq) { - unsigned int ret; - char buf[8]; u16 gpionr = irq_to_gpio(irq); u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; @@ -709,17 +696,13 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq) return -ENODEV; } - if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { - snprintf(buf, sizeof buf, "IRQ %d", irq); - ret = gpio_request(gpionr, buf); - if (ret) - return ret; - } + if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) + bfin_gpio_irq_prepare(gpionr); gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); bfin_gpio_unmask_irq(irq); - return ret; + return 0; } static void bfin_gpio_irq_shutdown(unsigned int irq) @@ -727,15 +710,12 @@ static void bfin_gpio_irq_shutdown(unsigned int irq) u16 gpionr = irq_to_gpio(irq); bfin_gpio_mask_irq(irq); - gpio_free(gpionr); gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); } static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) { - unsigned int ret; - char buf[8]; u16 gpionr = irq_to_gpio(irq); u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; u32 pintbit = PINT_BIT(pint_val); @@ -753,12 +733,8 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { - if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { - snprintf(buf, sizeof buf, "IRQ %d", irq); - ret = gpio_request(gpionr, buf); - if (ret) - return ret; - } + if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) + bfin_gpio_irq_prepare(gpionr); gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); } else { @@ -766,8 +742,6 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) return 0; } - gpio_direction_input(gpionr); - if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */ else -- cgit v1.2.3 From 5f004c2009ef95212349f7c7d87e8ff829d15c31 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 25 Apr 2008 02:11:24 +0800 Subject: [Blackfin] arch: reorganize some of the board-customization options so that similar things are together and only available as needed Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/Kconfig | 63 ++++++++++++++++++++++++--------------------------- 1 file changed, 30 insertions(+), 33 deletions(-) diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 75bceee9b9a..eba22c21982 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -272,6 +272,20 @@ config CMDLINE to the kernel, you may specify one here. As a minimum, you should specify the memory size and the root device (e.g., mem=8M, root=/dev/nfs). +config BOOT_LOAD + hex "Kernel load address for booting" + default "0x1000" + range 0x1000 0x20000000 + help + This option allows you to set the load address of the kernel. + This can be useful if you are on a board which has a small amount + of memory or you wish to reserve some memory at the beginning of + the address space. + + Note that you need to keep this value above 4k (0x1000) as this + memory region is used to capture NULL pointer references as well + as some core kernel functions. + comment "Clock/PLL Setup" config CLKIN_HZ @@ -303,6 +317,7 @@ config MEM_ADD_WIDTH int "Memory Address Width" depends on BFIN_KERNEL_CLOCK depends on (!BF54x) + range 8 11 default 9 if BFIN533_EZKIT default 9 if BFIN561_EZKIT default 9 if H8606_HVSISTEMAS @@ -365,14 +380,7 @@ config SCLK_DIV int "System Clock Divider" depends on BFIN_KERNEL_CLOCK range 1 15 - default 5 if BFIN533_EZKIT - default 5 if BFIN533_STAMP - default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM) - default 5 if BFIN533_BLUETECHNIX_CM - default 4 if BFIN537_BLUETECHNIX_CM - default 4 if BFIN561_BLUETECHNIX_CM - default 5 if BFIN561_EZKIT - default 3 if H8606_HVSISTEMAS + default 5 help This sets the frequency of the system clock (including SDRAM or DDR). This can be between 1 and 15 @@ -386,6 +394,19 @@ config MAX_MEM_SIZE This is the max memory size that the kernel will create CPLB tables for. Your system will not be able to handle any more. +choice + prompt "DDR SDRAM Chip Type" + depends on BFIN_KERNEL_CLOCK + depends on BF54x + default MEM_MT46V32M16_5B + +config MEM_MT46V32M16_6T + bool "MT46V32M16_6T" + +config MEM_MT46V32M16_5B + bool "MT46V32M16_5B" +endchoice + # # Max & Min Speeds for various Chips # @@ -454,17 +475,7 @@ source kernel/time/Kconfig comment "Memory Setup" -choice - prompt "DDR SDRAM Chip Type" - depends on (BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM) - default MEM_MT46V32M16_5B - -config MEM_MT46V32M16_6T - bool "MT46V32M16_6T" - -config MEM_MT46V32M16_5B - bool "MT46V32M16_5B" -endchoice +comment "Misc" config ENET_FLASH_PIN int "PF port/pin used for flash and ethernet sharing" @@ -476,20 +487,6 @@ config ENET_FLASH_PIN code. For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc. -config BOOT_LOAD - hex "Kernel load address for booting" - default "0x1000" - range 0x1000 0x20000000 - help - This option allows you to set the load address of the kernel. - This can be useful if you are on a board which has a small amount - of memory or you wish to reserve some memory at the beginning of - the address space. - - Note that you need to keep this value above 4k (0x1000) as this - memory region is used to capture NULL pointer references as well - as some core kernel functions. - choice prompt "Blackfin Exception Scratch Register" default BFIN_SCRATCH_REG_RETN -- cgit v1.2.3 From 8e9d5c7daff8b74bf3be62cfe0ba48b5af1fa12f Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 24 Apr 2008 08:46:19 +0800 Subject: [Blackfin] arch: Add platform support for MTD DATAFLASH Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf537/boards/stamp.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index e95478252c8..d4cbcb8774e 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -503,6 +503,15 @@ static struct bfin5xx_spi_chip spidev_chip_info = { }; #endif +#if defined(CONFIG_MTD_DATAFLASH) \ + || defined(CONFIG_MTD_DATAFLASH_MODULE) +/* DataFlash chip */ +static struct bfin5xx_spi_chip data_flash_chip_info = { + .enable_dma = 0, /* use dma transfer with this chip*/ + .bits_per_word = 8, +}; +#endif + static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ || defined(CONFIG_MTD_M25P80_MODULE) @@ -517,7 +526,17 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .mode = SPI_MODE_3, }, #endif - +#if defined(CONFIG_MTD_DATAFLASH) \ + || defined(CONFIG_MTD_DATAFLASH_MODULE) + { /* DataFlash chip */ + .modalias = "mtd_dataflash", + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, /* Framework bus number */ + .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ + .controller_data = &data_flash_chip_info, + .mode = SPI_MODE_3, + }, +#endif #if defined(CONFIG_SPI_ADC_BF533) \ || defined(CONFIG_SPI_ADC_BF533_MODULE) { -- cgit v1.2.3 From 2d191233882a031304f41cfc6abfb70536780645 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Apr 2008 08:58:44 +0800 Subject: [Blackfin] arch: define our own BUG() so we can dump the blackfin hardware trace buffer Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/bug.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/asm-blackfin/bug.h b/include/asm-blackfin/bug.h index 41e53b29f16..6d3e11b1fc5 100644 --- a/include/asm-blackfin/bug.h +++ b/include/asm-blackfin/bug.h @@ -1,4 +1,17 @@ #ifndef _BLACKFIN_BUG_H #define _BLACKFIN_BUG_H + +#ifdef CONFIG_BUG +#define HAVE_ARCH_BUG + +#define BUG() do { \ + dump_bfin_trace_buffer(); \ + printk(KERN_EMERG "BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \ + panic("BUG!"); \ +} while (0) + +#endif + #include + #endif -- cgit v1.2.3 From 18628e4375264edb53e6d9aaaf91f1a480019304 Mon Sep 17 00:00:00 2001 From: "Robert P. J. Day" Date: Thu, 24 Apr 2008 09:02:00 +0800 Subject: [Blackfin] arch: Clean up the definition and correct the commentary for current_thread_info(). Signed-off-by: Robert P. J. Day Acked-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/thread_info.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/include/asm-blackfin/thread_info.h b/include/asm-blackfin/thread_info.h index 15b99cf4f50..bc2fe5accf2 100644 --- a/include/asm-blackfin/thread_info.h +++ b/include/asm-blackfin/thread_info.h @@ -81,14 +81,11 @@ struct thread_info { #define init_thread_info (init_thread_union.thread_info) #define init_stack (init_thread_union.stack) -/* How to get the thread information struct from C */ - -static inline struct thread_info *current_thread_info(void) - __attribute__ ((__const__)); - -/* Given a task stack pointer, you can find it's task structure - * just by masking it to the 8K boundary. +/* Given a task stack pointer, you can find its corresponding + * thread_info structure just by masking it to the THREAD_SIZE + * boundary (currently 8K as you can see above). */ +__attribute_const__ static inline struct thread_info *current_thread_info(void) { struct thread_info *ti; -- cgit v1.2.3 From 4d555630704d3f6c0257dde3e622f9295f221c8b Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Fri, 25 Apr 2008 03:28:10 +0800 Subject: [Blackfin] arch: Update anomaly list. Signed-off-by: Sonic Zhang Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf527/anomaly.h | 80 +++++++++++++++++++++++++------ include/asm-blackfin/mach-bf533/anomaly.h | 10 +++- include/asm-blackfin/mach-bf537/anomaly.h | 17 ++++++- include/asm-blackfin/mach-bf548/anomaly.h | 1 + include/asm-blackfin/mach-bf561/anomaly.h | 6 ++- 5 files changed, 96 insertions(+), 18 deletions(-) diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h index a89120445be..735fa02fafb 100644 --- a/include/asm-blackfin/mach-bf527/anomaly.h +++ b/include/asm-blackfin/mach-bf527/anomaly.h @@ -2,12 +2,12 @@ * File: include/asm-blackfin/mach-bf527/anomaly.h * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Copyright (C) 2004-2007 Analog Devices Inc. + * Copyright (C) 2004-2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ /* This file shoule be up to date with: - * - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List + * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -15,35 +15,85 @@ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) -/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) -/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ -#define ANOMALY_05000301 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (1) /* Incorrect Access of OTP_STATUS During otp_write() Function */ #define ANOMALY_05000328 (1) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ #define ANOMALY_05000337 (1) -/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */ +/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ +#define ANOMALY_05000341 (1) +/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ #define ANOMALY_05000342 (1) -/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ +/* USB Calibration Value Is Not Initialized */ +#define ANOMALY_05000346 (1) +/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ #define ANOMALY_05000347 (1) +/* Security Features Are Not Functional */ +#define ANOMALY_05000348 (__SILICON_REVISION__ < 1) +/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ +#define ANOMALY_05000355 (1) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* Incorrect Revision Number in DSPID Register */ +#define ANOMALY_05000364 (__SILICON_REVISION__ > 0) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* New Feature: Higher Default CCLK Rate */ +#define ANOMALY_05000368 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (1) +/* Authentication Fails To Initiate */ +#define ANOMALY_05000376 (__SILICON_REVISION__ > 0) +/* Data Read From L3 Memory by USB DMA May be Corrupted */ +#define ANOMALY_05000380 (1) +/* USB Full-speed Mode not Fully Tested */ +#define ANOMALY_05000381 (1) +/* New Feature: Boot from OTP Memory */ +#define ANOMALY_05000385 (1) +/* New Feature: bfrom_SysControl() Routine */ +#define ANOMALY_05000386 (1) +/* New Feature: Programmable Preboot Settings */ +#define ANOMALY_05000387 (1) +/* Reset Vector Must Not Be in SDRAM Memory Space */ +#define ANOMALY_05000389 (1) +/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */ +#define ANOMALY_05000392 (1) +/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000393 (1) +/* New Feature: Log Buffer Functionality */ +#define ANOMALY_05000394 (1) +/* New Feature: Hook Routine Functionality */ +#define ANOMALY_05000395 (1) +/* New Feature: Header Indirect Bit */ +#define ANOMALY_05000396 (1) +/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */ +#define ANOMALY_05000397 (1) +/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */ +#define ANOMALY_05000398 (1) +/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */ +#define ANOMALY_05000399 (1) +/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ +#define ANOMALY_05000401 (1) /* Anomalies that don't exist on this proc */ -#define ANOMALY_05000323 (0) -#define ANOMALY_05000244 (0) -#define ANOMALY_05000198 (0) #define ANOMALY_05000125 (0) #define ANOMALY_05000158 (0) -#define ANOMALY_05000273 (0) +#define ANOMALY_05000183 (0) +#define ANOMALY_05000198 (0) +#define ANOMALY_05000230 (0) +#define ANOMALY_05000244 (0) +#define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) +#define ANOMALY_05000266 (0) +#define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) -#define ANOMALY_05000230 (0) +#define ANOMALY_05000312 (0) +#define ANOMALY_05000323 (0) +#define ANOMALY_05000363 (0) + #endif diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h index 98209d40abb..5a6dcc5fa36 100644 --- a/include/asm-blackfin/mach-bf533/anomaly.h +++ b/include/asm-blackfin/mach-bf533/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List + * - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -251,10 +251,18 @@ #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ #define ANOMALY_05000357 (1) +/* UART Break Signal Issues */ +#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ #define ANOMALY_05000366 (1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) +/* PPI Does Not Start Properly In Specific Mode */ +#define ANOMALY_05000400 (__SILICON_REVISION__ == 5) +/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ +#define ANOMALY_05000402 (__SILICON_REVISION__ == 5) +/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ +#define ANOMALY_05000403 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000266 (0) diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index 746a794b311..a6b08facb24 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List + * - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -132,10 +132,24 @@ #define ANOMALY_05000322 (1) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) +/* New Feature: UART Remains Enabled after UART Boot (Not Available on Older Silicon) */ +#define ANOMALY_05000350 (__SILICON_REVISION__ < 3) +/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ +#define ANOMALY_05000355 (1) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ #define ANOMALY_05000357 (1) /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ #define ANOMALY_05000359 (1) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (1) +/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ +#define ANOMALY_05000402 (__SILICON_REVISION__ >= 3) +/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ +#define ANOMALY_05000403 (1) + + /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) @@ -146,5 +160,6 @@ #define ANOMALY_05000266 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000323 (0) +#define ANOMALY_05000363 (0) #endif diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index 850dc12eb7f..49d3cebc529 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -93,5 +93,6 @@ #define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000323 (0) +#define ANOMALY_05000363 (0) #endif diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h index 0c1d4619393..82157caa96a 100644 --- a/include/asm-blackfin/mach-bf561/anomaly.h +++ b/include/asm-blackfin/mach-bf561/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List + * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -256,10 +256,14 @@ #define ANOMALY_05000357 (1) /* Conflicting Column Address Widths Causes SDRAM Errors */ #define ANOMALY_05000362 (1) +/* UART Break Signal Issues */ +#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ #define ANOMALY_05000366 (1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) +/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ +#define ANOMALY_05000403 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000158 (0) -- cgit v1.2.3 From 7f1c906808a36630990d83d872935c079b76595b Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Fri, 25 Apr 2008 03:36:31 +0800 Subject: [Blackfin] arch: try to remove condition that causes double fault, by checking current before it gets dereferenced Signed-off-by: Robin Getz Signed-off-by: Bryan Wu --- arch/blackfin/kernel/traps.c | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index de249d6fdd9..d0f67542207 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -137,17 +137,30 @@ static void decode_address(char *buf, unsigned long address) /* FLAT does not have its text aligned to the start of * the map while FDPIC ELF does ... */ - if (current->mm && - (address > current->mm->start_code) && - (address < current->mm->end_code)) - offset = address - current->mm->start_code; - else - offset = (address - vma->vm_start) + (vma->vm_pgoff << PAGE_SHIFT); - - sprintf(buf, "<0x%p> [ %s + 0x%lx ]", - (void *)address, name, offset); + + /* before we can check flat/fdpic, we need to + * make sure current is valid + */ + if ((unsigned long)current >= FIXED_CODE_START && + !((unsigned long)current & 0x3)) { + if (current->mm && + (address > current->mm->start_code) && + (address < current->mm->end_code)) + offset = address - current->mm->start_code; + else + offset = (address - vma->vm_start) + + (vma->vm_pgoff << PAGE_SHIFT); + + sprintf(buf, "<0x%p> [ %s + 0x%lx ]", + (void *)address, name, offset); + } else + sprintf(buf, "<0x%p> [ %s vma:0x%lx-0x%lx]", + (void *)address, name, + vma->vm_start, vma->vm_end); + if (!in_atomic) mmput(mm); + goto done; } @@ -658,7 +671,8 @@ void dump_bfin_process(struct pt_regs *fp) /* Because we are crashing, and pointers could be bad, we check things * pretty closely before we use them */ - if (!((unsigned long)current & 0x3) && current->pid) { + if ((unsigned long)current >= FIXED_CODE_START && + !((unsigned long)current & 0x3) && current->pid) { printk(KERN_NOTICE "CURRENT PROCESS:\n"); if (current->comm >= (char *)FIXED_CODE_START) printk(KERN_NOTICE "COMM=%s PID=%d\n", -- cgit v1.2.3 From 37b6972ad8fb08d438fd600888aff212b1b193b0 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 25 Apr 2008 02:19:17 +0800 Subject: [Blackfin] arch: BF54x memsizes are in mbits, not mbytes Pointed-out-by: Michael Hennerich Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index d6668328be7..b0ae5cd4420 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -681,10 +681,10 @@ static inline int __init get_mem_size(void) # endif # elif defined(EBIU_DDRCTL1) switch (bfin_read_EBIU_DDRCTL1() & 0xc0000) { - case DEVSZ_64: return 64; - case DEVSZ_128: return 128; - case DEVSZ_256: return 256; - case DEVSZ_512: return 512; + case DEVSZ_64: return 64 / 8; + case DEVSZ_128: return 128 / 8; + case DEVSZ_256: return 256 / 8; + case DEVSZ_512: return 512 / 8; default: return 0; } # endif -- cgit v1.2.3 From 5be36d22b28f01e5074f78b29aa6128da0a53641 Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Fri, 25 Apr 2008 03:09:15 +0800 Subject: [Blackfin] arch: add Blackfin on-chip SIR IrDA driver support - add platform device resources in board files - add new bfin_sir.h to each machines Signed-off-by: Graf Yang Signed-off-by: Bryan Wu --- arch/blackfin/kernel/bfin_dma_5xx.c | 4 +- arch/blackfin/mach-bf527/boards/ezkit.c | 30 +++++ arch/blackfin/mach-bf533/boards/H8606.c | 23 ++++ arch/blackfin/mach-bf533/boards/cm_bf533.c | 23 ++++ arch/blackfin/mach-bf533/boards/ezkit.c | 23 ++++ arch/blackfin/mach-bf533/boards/ip0x.c | 24 ++++ arch/blackfin/mach-bf533/boards/stamp.c | 23 ++++ arch/blackfin/mach-bf537/boards/cm_bf537.c | 30 +++++ arch/blackfin/mach-bf537/boards/generic_board.c | 30 +++++ arch/blackfin/mach-bf537/boards/minotaur.c | 30 +++++ arch/blackfin/mach-bf537/boards/pnav10.c | 29 +++++ arch/blackfin/mach-bf537/boards/stamp.c | 30 +++++ arch/blackfin/mach-bf548/boards/cm_bf548.c | 44 +++++++ arch/blackfin/mach-bf548/boards/ezkit.c | 44 +++++++ arch/blackfin/mach-bf561/boards/cm_bf561.c | 23 ++++ arch/blackfin/mach-bf561/boards/ezkit.c | 23 ++++ include/asm-blackfin/mach-bf527/bfin_serial_5xx.h | 48 ++++--- include/asm-blackfin/mach-bf527/bfin_sir.h | 133 +++++++++++++++++++ include/asm-blackfin/mach-bf527/blackfin.h | 15 +++ include/asm-blackfin/mach-bf533/bfin_serial_5xx.h | 50 +++++--- include/asm-blackfin/mach-bf533/bfin_sir.h | 120 +++++++++++++++++ include/asm-blackfin/mach-bf533/blackfin.h | 15 +++ include/asm-blackfin/mach-bf537/bfin_serial_5xx.h | 48 ++++--- include/asm-blackfin/mach-bf537/bfin_sir.h | 133 +++++++++++++++++++ include/asm-blackfin/mach-bf537/blackfin.h | 15 +++ include/asm-blackfin/mach-bf548/bfin_serial_5xx.h | 48 ++++--- include/asm-blackfin/mach-bf548/bfin_sir.h | 149 ++++++++++++++++++++++ include/asm-blackfin/mach-bf548/blackfin.h | 15 +++ include/asm-blackfin/mach-bf561/bfin_serial_5xx.h | 50 +++++--- include/asm-blackfin/mach-bf561/bfin_sir.h | 120 +++++++++++++++++ include/asm-blackfin/mach-bf561/blackfin.h | 14 ++ 31 files changed, 1322 insertions(+), 84 deletions(-) create mode 100644 include/asm-blackfin/mach-bf527/bfin_sir.h create mode 100644 include/asm-blackfin/mach-bf533/bfin_sir.h create mode 100644 include/asm-blackfin/mach-bf537/bfin_sir.h create mode 100644 include/asm-blackfin/mach-bf548/bfin_sir.h create mode 100644 include/asm-blackfin/mach-bf561/bfin_sir.h diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c index 18fc8a83594..df4d2a5b8e3 100644 --- a/arch/blackfin/kernel/bfin_dma_5xx.c +++ b/arch/blackfin/kernel/bfin_dma_5xx.c @@ -108,10 +108,10 @@ int request_dma(unsigned int channel, char *device_id) if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) { if (strncmp(device_id, "BFIN_UART", 9) == 0) dma_ch[channel].regs->peripheral_map |= - (channel - CH_UART2_RX + 0xC); + ((channel - CH_UART2_RX + 0xC)<<12); else dma_ch[channel].regs->peripheral_map |= - (channel - CH_UART2_RX + 0x6); + ((channel - CH_UART2_RX + 0x6)<<12); } #endif diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index be20f79a7fe..583d53811f0 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -707,6 +707,32 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +static struct resource bfin_sir_resources[] = { +#ifdef CONFIG_BFIN_SIR0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + .start = 0xFFC02000, + .end = 0xFFC020FF, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device bfin_sir_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir_resources), + .resource = bfin_sir_resources, +}; +#endif + #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) static struct resource bfin_twi0_resource[] = { [0] = { @@ -874,6 +900,10 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_uart_device, #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) + &bfin_sir_device, +#endif + #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) &i2c_bfin_twi_device, #endif diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c index 39c3dd3d595..7cc4864f6aa 100644 --- a/arch/blackfin/mach-bf533/boards/H8606.c +++ b/arch/blackfin/mach-bf533/boards/H8606.c @@ -304,6 +304,25 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +static struct resource bfin_sir_resources[] = { +#ifdef CONFIG_BFIN_SIR0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device bfin_sir_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir_resources), + .resource = bfin_sir_resources, +}; +#endif + #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) #include @@ -403,6 +422,10 @@ static struct platform_device *h8606_devices[] __initdata = { &serial8250_device, #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) + &bfin_sir_device, +#endif + #if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE) &opencores_kbd_device, #endif diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c index 7e7b7c9a5c8..a03149c7268 100644 --- a/arch/blackfin/mach-bf533/boards/cm_bf533.c +++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c @@ -234,6 +234,25 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +static struct resource bfin_sir_resources[] = { +#ifdef CONFIG_BFIN_SIR0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device bfin_sir_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir_resources), + .resource = bfin_sir_resources, +}; +#endif + #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) static struct platform_device bfin_sport0_uart_device = { .name = "bfin-sport-uart", @@ -327,6 +346,10 @@ static struct platform_device *cm_bf533_devices[] __initdata = { &bfin_uart_device, #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) + &bfin_sir_device, +#endif + #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) &bfin_sport0_uart_device, &bfin_sport1_uart_device, diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c index 35c1efdf8e1..08a7943949a 100644 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ b/arch/blackfin/mach-bf533/boards/ezkit.c @@ -237,6 +237,25 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +static struct resource bfin_sir_resources[] = { +#ifdef CONFIG_BFIN_SIR0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device bfin_sir_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir_resources), + .resource = bfin_sir_resources, +}; +#endif + #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) #define PATA_INT 55 @@ -352,6 +371,10 @@ static struct platform_device *ezkit_devices[] __initdata = { &bfin_uart_device, #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) + &bfin_sir_device, +#endif + #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) &bfin_pata_device, #endif diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c index 4af61474a99..5864892de31 100644 --- a/arch/blackfin/mach-bf533/boards/ip0x.c +++ b/arch/blackfin/mach-bf533/boards/ip0x.c @@ -196,6 +196,25 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +static struct resource bfin_sir_resources[] = { +#ifdef CONFIG_BFIN_SIR0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device bfin_sir_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir_resources), + .resource = bfin_sir_resources, +}; +#endif + #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) static struct resource isp1362_hcd_resources[] = { { @@ -251,6 +270,11 @@ static struct platform_device *ip0x_devices[] __initdata = { #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) &bfin_uart_device, #endif + +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) + &bfin_sir_device, +#endif + #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) &isp1362_hcd_device, #endif diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index 3a727d3676e..fddce32901a 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c @@ -370,6 +370,25 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +static struct resource bfin_sir_resources[] = { +#ifdef CONFIG_BFIN_SIR0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device bfin_sir_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir_resources), + .resource = bfin_sir_resources, +}; +#endif + #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) static struct platform_device bfin_sport0_uart_device = { .name = "bfin-sport-uart", @@ -525,6 +544,10 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_uart_device, #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) + &bfin_sir_device, +#endif + #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) &bfin_sport0_uart_device, &bfin_sport1_uart_device, diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c index 199fde69b96..d8a23cd9b9e 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c @@ -325,6 +325,32 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +static struct resource bfin_sir_resources[] = { +#ifdef CONFIG_BFIN_SIR0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + .start = 0xFFC02000, + .end = 0xFFC020FF, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device bfin_sir_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir_resources), + .resource = bfin_sir_resources, +}; +#endif + #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) static struct resource bfin_twi0_resource[] = { [0] = { @@ -415,6 +441,10 @@ static struct platform_device *cm_bf537_devices[] __initdata = { &bfin_uart_device, #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) + &bfin_sir_device, +#endif + #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) &i2c_bfin_twi_device, #endif diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c index b3d78ea755c..7d250828dad 100644 --- a/arch/blackfin/mach-bf537/boards/generic_board.c +++ b/arch/blackfin/mach-bf537/boards/generic_board.c @@ -554,6 +554,32 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +static struct resource bfin_sir_resources[] = { +#ifdef CONFIG_BFIN_SIR0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + .start = 0xFFC02000, + .end = 0xFFC020FF, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device bfin_sir_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir_resources), + .resource = bfin_sir_resources, +}; +#endif + #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) static struct resource bfin_twi0_resource[] = { [0] = { @@ -674,6 +700,10 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_uart_device, #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) + &bfin_sir_device, +#endif + #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) &i2c_bfin_twi_device, #endif diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c index 4ea7173915e..18ddf7a5200 100644 --- a/arch/blackfin/mach-bf537/boards/minotaur.c +++ b/arch/blackfin/mach-bf537/boards/minotaur.c @@ -225,6 +225,32 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +static struct resource bfin_sir_resources[] = { +#ifdef CONFIG_BFIN_SIR0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + .start = 0xFFC02000, + .end = 0xFFC020FF, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device bfin_sir_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir_resources), + .resource = bfin_sir_resources, +}; +#endif + #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) static struct resource bfin_twi0_resource[] = { [0] = { @@ -284,6 +310,10 @@ static struct platform_device *minotaur_devices[] __initdata = { &bfin_uart_device, #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) + &bfin_sir_device, +#endif + #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) &i2c_bfin_twi_device, #endif diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index 0b3e22b1b68..51c3bab14a6 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c @@ -452,6 +452,31 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +static struct resource bfin_sir_resources[] = { +#ifdef CONFIG_BFIN_SIR0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + .start = 0xFFC02000, + .end = 0xFFC020FF, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device bfin_sir_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir_resources), + .resource = bfin_sir_resources, +}; +#endif static struct platform_device *stamp_devices[] __initdata = { #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) @@ -493,6 +518,10 @@ static struct platform_device *stamp_devices[] __initdata = { #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) &bfin_uart_device, #endif + +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) + &bfin_sir_device, +#endif }; static int __init stamp_init(void) diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index d4cbcb8774e..0cec14b1ef5 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -698,6 +698,32 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +static struct resource bfin_sir_resources[] = { +#ifdef CONFIG_BFIN_SIR0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + .start = 0xFFC02000, + .end = 0xFFC020FF, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device bfin_sir_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir_resources), + .resource = bfin_sir_resources, +}; +#endif + #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) static struct resource bfin_twi0_resource[] = { [0] = { @@ -847,6 +873,10 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_uart_device, #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) + &bfin_sir_device, +#endif + #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) &i2c_bfin_twi_device, #endif diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c index 1aa3c1b86bc..e3e8479fffb 100644 --- a/arch/blackfin/mach-bf548/boards/cm_bf548.c +++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c @@ -184,6 +184,46 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +static struct resource bfin_sir_resources[] = { +#ifdef CONFIG_BFIN_SIR0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + .start = 0xFFC02000, + .end = 0xFFC020FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_BFIN_SIR2 + { + .start = 0xFFC02100, + .end = 0xFFC021FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_BFIN_SIR3 + { + .start = 0xFFC03100, + .end = 0xFFC031FF, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device bfin_sir_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir_resources), + .resource = bfin_sir_resources, +}; +#endif + #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) static struct resource smsc911x_resources[] = { { @@ -559,6 +599,10 @@ static struct platform_device *cm_bf548_devices[] __initdata = { &bfin_uart_device, #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) + &bfin_sir_device, +#endif + #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) &bf54x_lq043_device, #endif diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 548820d25eb..231dfbd3bc1 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -188,6 +188,46 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +static struct resource bfin_sir_resources[] = { +#ifdef CONFIG_BFIN_SIR0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + .start = 0xFFC02000, + .end = 0xFFC020FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_BFIN_SIR2 + { + .start = 0xFFC02100, + .end = 0xFFC021FF, + .flags = IORESOURCE_MEM, + }, +#endif +#ifdef CONFIG_BFIN_SIR3 + { + .start = 0xFFC03100, + .end = 0xFFC031FF, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device bfin_sir_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir_resources), + .resource = bfin_sir_resources, +}; +#endif + #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) static struct resource smsc911x_resources[] = { { @@ -660,6 +700,10 @@ static struct platform_device *ezkit_devices[] __initdata = { &bfin_uart_device, #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) + &bfin_sir_device, +#endif + #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) &bf54x_lq043_device, #endif diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c index 4a3e0853f2a..9fd580952fd 100644 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c @@ -283,6 +283,25 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +static struct resource bfin_sir_resources[] = { +#ifdef CONFIG_BFIN_SIR0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device bfin_sir_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir_resources), + .resource = bfin_sir_resources, +}; +#endif + #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) #define PATA_INT 119 @@ -330,6 +349,10 @@ static struct platform_device *cm_bf561_devices[] __initdata = { &bfin_uart_device, #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) + &bfin_sir_device, +#endif + #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) &isp1362_hcd_device, #endif diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 8eb79e526ad..0d74b7d9920 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -220,6 +220,25 @@ static struct platform_device bfin_uart_device = { }; #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +static struct resource bfin_sir_resources[] = { +#ifdef CONFIG_BFIN_SIR0 + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +#endif +}; + +static struct platform_device bfin_sir_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir_resources), + .resource = bfin_sir_resources, +}; +#endif + #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) static struct mtd_partition ezkit_partitions[] = { { @@ -445,6 +464,10 @@ static struct platform_device *ezkit_devices[] __initdata = { &bfin_uart_device, #endif +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) + &bfin_sir_device, +#endif + #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) &bfin_pata_device, #endif diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h index c0694ecd2ec..f0ab2736a68 100644 --- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h @@ -1,22 +1,38 @@ +/* + * file: include/asm-blackfin/mach-bf527/bfin_serial_5xx.h + * based on: + * author: + * + * created: + * description: + * blackfin serial driver head file + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + #include #include #include -#define NR_PORTS 2 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ - #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) @@ -92,7 +108,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) bfin_write16(uart->port.membase + OFFSET_LSR, -1); } -struct bfin_serial_port bfin_serial_ports[NR_PORTS]; +struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; diff --git a/include/asm-blackfin/mach-bf527/bfin_sir.h b/include/asm-blackfin/mach-bf527/bfin_sir.h new file mode 100644 index 00000000000..0612d0c9501 --- /dev/null +++ b/include/asm-blackfin/mach-bf527/bfin_sir.h @@ -0,0 +1,133 @@ +/* + * Blackfin Infra-red Driver + * + * Copyright 2006-2008 Analog Devices Inc. + * + * Enter bugs at http://blackfin.uclinux.org/ + * + * Licensed under the GPL-2 or later. + * + */ + +#include +#include +#include + +#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) +#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) +#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER) +#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) +#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR) +#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) +#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) + +#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) +#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) +#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v) +#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) +#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) +#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) + +#ifdef CONFIG_SIR_BFIN_DMA +struct dma_rx_buf { + char *buf; + int head; + int tail; + }; +#endif /* CONFIG_SIR_BFIN_DMA */ + +struct bfin_sir_port { + unsigned char __iomem *membase; + unsigned int irq; + unsigned int lsr; + unsigned long clk; + struct net_device *dev; +#ifdef CONFIG_SIR_BFIN_DMA + int tx_done; + struct dma_rx_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; +#endif /* CONFIG_SIR_BFIN_DMA */ + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; +}; + +struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; + +struct bfin_sir_port_res { + unsigned long base_addr; + int irq; + unsigned int rx_dma_channel; + unsigned int tx_dma_channel; +}; + +struct bfin_sir_port_res bfin_sir_port_resource[] = { +#ifdef CONFIG_BFIN_SIR0 + { + 0xFFC00400, + IRQ_UART0_RX, + CH_UART0_RX, + CH_UART0_TX, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + 0xFFC02000, + IRQ_UART1_RX, + CH_UART1_RX, + CH_UART1_TX, + }, +#endif +}; + +int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); + +struct bfin_sir_self { + struct bfin_sir_port *sir_port; + spinlock_t lock; + unsigned int open; + int speed; + int newspeed; + + struct sk_buff *txskb; + struct sk_buff *rxskb; + struct net_device_stats stats; + struct device *dev; + struct irlap_cb *irlap; + struct qos_info qos; + + iobuff_t tx_buff; + iobuff_t rx_buff; + + struct work_struct work; + int mtt; +}; + +static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port) +{ + unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR); + port->lsr |= (lsr & (BI|FE|PE|OE)); + return lsr | port->lsr; +} + +static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port) +{ + port->lsr = 0; + bfin_read16(port->membase + OFFSET_LSR); +} + +#define DRIVER_NAME "bfin_sir" + +static void bfin_sir_hw_init(void) +{ +#ifdef CONFIG_BFIN_SIR0 + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); +#endif + +#ifdef CONFIG_BFIN_SIR1 + peripheral_request(P_UART1_TX, DRIVER_NAME); + peripheral_request(P_UART1_RX, DRIVER_NAME); +#endif + SSYNC(); +} diff --git a/include/asm-blackfin/mach-bf527/blackfin.h b/include/asm-blackfin/mach-bf527/blackfin.h index 1bd07e30781..2891727b617 100644 --- a/include/asm-blackfin/mach-bf527/blackfin.h +++ b/include/asm-blackfin/mach-bf527/blackfin.h @@ -64,6 +64,21 @@ #define STATUS_P1 0x02 #define STATUS_P0 0x01 +#define BFIN_UART_NR_PORTS 2 + +#define OFFSET_THR 0x00 /* Transmit Holding register */ +#define OFFSET_RBR 0x00 /* Receive Buffer register */ +#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +#define OFFSET_IER 0x04 /* Interrupt Enable Register */ +#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ +#define OFFSET_LCR 0x0C /* Line Control Register */ +#define OFFSET_MCR 0x10 /* Modem Control Register */ +#define OFFSET_LSR 0x14 /* Line Status Register */ +#define OFFSET_MSR 0x18 /* Modem Status Register */ +#define OFFSET_SCR 0x1C /* SCR Scratch Register */ +#define OFFSET_GCTL 0x24 /* Global Control Register */ + /* DPMC*/ #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h index b6f513bee56..fbe88dee3e2 100644 --- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h @@ -1,22 +1,38 @@ +/* + * file: include/asm-blackfin/mach-bf533/bfin_serial_5xx.h + * based on: + * author: + * + * created: + * description: + * blackfin serial driver head file + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + #include #include #include -#define NR_PORTS 1 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ - #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) @@ -84,7 +100,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) bfin_write16(uart->port.membase + OFFSET_LSR, -1); } -struct bfin_serial_port bfin_serial_ports[NR_PORTS]; +struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; @@ -115,7 +131,7 @@ struct bfin_serial_res bfin_serial_resource[] = { #define DRIVER_NAME "bfin-uart" -int nr_ports = NR_PORTS; +int nr_ports = BFIN_UART_NR_PORTS; static void bfin_serial_hw_init(struct bfin_serial_port *uart) { diff --git a/include/asm-blackfin/mach-bf533/bfin_sir.h b/include/asm-blackfin/mach-bf533/bfin_sir.h new file mode 100644 index 00000000000..cefcf8bb505 --- /dev/null +++ b/include/asm-blackfin/mach-bf533/bfin_sir.h @@ -0,0 +1,120 @@ +/* + * Blackfin Infra-red Driver + * + * Copyright 2006-2008 Analog Devices Inc. + * + * Enter bugs at http://blackfin.uclinux.org/ + * + * Licensed under the GPL-2 or later. + * + */ + +#include +#include +#include + +#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) +#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) +#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER) +#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) +#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR) +#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) +#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) + +#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) +#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) +#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v) +#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) +#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) +#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) + +#ifdef CONFIG_SIR_BFIN_DMA +struct dma_rx_buf { + char *buf; + int head; + int tail; + }; +#endif /* CONFIG_SIR_BFIN_DMA */ + +struct bfin_sir_port { + unsigned char __iomem *membase; + unsigned int irq; + unsigned int lsr; + unsigned long clk; + struct net_device *dev; +#ifdef CONFIG_SIR_BFIN_DMA + int tx_done; + struct dma_rx_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; +#endif /* CONFIG_SIR_BFIN_DMA */ + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; +}; + +struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; + +struct bfin_sir_port_res { + unsigned long base_addr; + int irq; + unsigned int rx_dma_channel; + unsigned int tx_dma_channel; +}; + +struct bfin_sir_port_res bfin_sir_port_resource[] = { +#ifdef CONFIG_BFIN_SIR0 + { + 0xFFC00400, + IRQ_UART_RX, + CH_UART_RX, + CH_UART_TX, + }, +#endif +}; + +int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); + +struct bfin_sir_self { + struct bfin_sir_port *sir_port; + spinlock_t lock; + unsigned int open; + int speed; + int newspeed; + + struct sk_buff *txskb; + struct sk_buff *rxskb; + struct net_device_stats stats; + struct device *dev; + struct irlap_cb *irlap; + struct qos_info qos; + + iobuff_t tx_buff; + iobuff_t rx_buff; + + struct work_struct work; + int mtt; +}; + +static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port) +{ + unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR); + port->lsr |= (lsr & (BI|FE|PE|OE)); + return lsr | port->lsr; +} + +static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port) +{ + port->lsr = 0; + bfin_read16(port->membase + OFFSET_LSR); +} + +#define DRIVER_NAME "bfin_sir" + +static void bfin_sir_hw_init(void) +{ +#ifdef CONFIG_BFIN_SIR0 + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); +#endif + SSYNC(); +} diff --git a/include/asm-blackfin/mach-bf533/blackfin.h b/include/asm-blackfin/mach-bf533/blackfin.h index f3b240abf17..d80971b4e3a 100644 --- a/include/asm-blackfin/mach-bf533/blackfin.h +++ b/include/asm-blackfin/mach-bf533/blackfin.h @@ -42,4 +42,19 @@ #include "cdefBF532.h" #endif +#define BFIN_UART_NR_PORTS 1 + +#define OFFSET_THR 0x00 /* Transmit Holding register */ +#define OFFSET_RBR 0x00 /* Receive Buffer register */ +#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +#define OFFSET_IER 0x04 /* Interrupt Enable Register */ +#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ +#define OFFSET_LCR 0x0C /* Line Control Register */ +#define OFFSET_MCR 0x10 /* Modem Control Register */ +#define OFFSET_LSR 0x14 /* Line Status Register */ +#define OFFSET_MSR 0x18 /* Modem Status Register */ +#define OFFSET_SCR 0x1C /* SCR Scratch Register */ +#define OFFSET_GCTL 0x24 /* Global Control Register */ + #endif /* _MACH_BLACKFIN_H_ */ diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h index 8fc672d3105..fd100a415b9 100644 --- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h @@ -1,22 +1,38 @@ +/* + * file: include/asm-blackfin/mach-bf537/bfin_serial_5xx.h + * based on: + * author: + * + * created: + * description: + * blackfin serial driver header files + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + #include #include #include -#define NR_PORTS 2 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ - #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) @@ -92,7 +108,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) bfin_write16(uart->port.membase + OFFSET_LSR, -1); } -struct bfin_serial_port bfin_serial_ports[NR_PORTS]; +struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; diff --git a/include/asm-blackfin/mach-bf537/bfin_sir.h b/include/asm-blackfin/mach-bf537/bfin_sir.h new file mode 100644 index 00000000000..0612d0c9501 --- /dev/null +++ b/include/asm-blackfin/mach-bf537/bfin_sir.h @@ -0,0 +1,133 @@ +/* + * Blackfin Infra-red Driver + * + * Copyright 2006-2008 Analog Devices Inc. + * + * Enter bugs at http://blackfin.uclinux.org/ + * + * Licensed under the GPL-2 or later. + * + */ + +#include +#include +#include + +#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) +#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) +#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER) +#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) +#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR) +#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) +#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) + +#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) +#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) +#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v) +#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) +#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) +#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) + +#ifdef CONFIG_SIR_BFIN_DMA +struct dma_rx_buf { + char *buf; + int head; + int tail; + }; +#endif /* CONFIG_SIR_BFIN_DMA */ + +struct bfin_sir_port { + unsigned char __iomem *membase; + unsigned int irq; + unsigned int lsr; + unsigned long clk; + struct net_device *dev; +#ifdef CONFIG_SIR_BFIN_DMA + int tx_done; + struct dma_rx_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; +#endif /* CONFIG_SIR_BFIN_DMA */ + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; +}; + +struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; + +struct bfin_sir_port_res { + unsigned long base_addr; + int irq; + unsigned int rx_dma_channel; + unsigned int tx_dma_channel; +}; + +struct bfin_sir_port_res bfin_sir_port_resource[] = { +#ifdef CONFIG_BFIN_SIR0 + { + 0xFFC00400, + IRQ_UART0_RX, + CH_UART0_RX, + CH_UART0_TX, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + 0xFFC02000, + IRQ_UART1_RX, + CH_UART1_RX, + CH_UART1_TX, + }, +#endif +}; + +int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); + +struct bfin_sir_self { + struct bfin_sir_port *sir_port; + spinlock_t lock; + unsigned int open; + int speed; + int newspeed; + + struct sk_buff *txskb; + struct sk_buff *rxskb; + struct net_device_stats stats; + struct device *dev; + struct irlap_cb *irlap; + struct qos_info qos; + + iobuff_t tx_buff; + iobuff_t rx_buff; + + struct work_struct work; + int mtt; +}; + +static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port) +{ + unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR); + port->lsr |= (lsr & (BI|FE|PE|OE)); + return lsr | port->lsr; +} + +static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port) +{ + port->lsr = 0; + bfin_read16(port->membase + OFFSET_LSR); +} + +#define DRIVER_NAME "bfin_sir" + +static void bfin_sir_hw_init(void) +{ +#ifdef CONFIG_BFIN_SIR0 + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); +#endif + +#ifdef CONFIG_BFIN_SIR1 + peripheral_request(P_UART1_TX, DRIVER_NAME); + peripheral_request(P_UART1_RX, DRIVER_NAME); +#endif + SSYNC(); +} diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h index 4f10ee0ae10..cffc786b2a2 100644 --- a/include/asm-blackfin/mach-bf537/blackfin.h +++ b/include/asm-blackfin/mach-bf537/blackfin.h @@ -136,6 +136,21 @@ #define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) #define BFIN_UART_GCTL UART0_GCTL +#define BFIN_UART_NR_PORTS 2 + +#define OFFSET_THR 0x00 /* Transmit Holding register */ +#define OFFSET_RBR 0x00 /* Receive Buffer register */ +#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +#define OFFSET_IER 0x04 /* Interrupt Enable Register */ +#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ +#define OFFSET_LCR 0x0C /* Line Control Register */ +#define OFFSET_MCR 0x10 /* Modem Control Register */ +#define OFFSET_LSR 0x14 /* Line Status Register */ +#define OFFSET_MSR 0x18 /* Modem Status Register */ +#define OFFSET_SCR 0x1C /* SCR Scratch Register */ +#define OFFSET_GCTL 0x24 /* Global Control Register */ + /* DPMC*/ #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h index 7e6339f62a5..6547027cd3e 100644 --- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h @@ -1,22 +1,38 @@ +/* + * file: include/asm-blackfin/mach-bf548/bfin_serial_5xx.h + * based on: + * author: + * + * created: + * description: + * blackfin serial driver head file + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + #include #include #include -#define NR_PORTS 4 - -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_GCTL 0x08 /* Global Control Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */ -#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */ -#define OFFSET_THR 0x28 /* Transmit Holding register */ -#define OFFSET_RBR 0x2C /* Receive Buffer register */ - #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) @@ -80,7 +96,7 @@ struct bfin_serial_port { #endif }; -struct bfin_serial_port bfin_serial_ports[NR_PORTS]; +struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; diff --git a/include/asm-blackfin/mach-bf548/bfin_sir.h b/include/asm-blackfin/mach-bf548/bfin_sir.h new file mode 100644 index 00000000000..5e94271c7e3 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/bfin_sir.h @@ -0,0 +1,149 @@ +/* + * Blackfin Infra-red Driver + * + * Copyright 2006-2008 Analog Devices Inc. + * + * Enter bugs at http://blackfin.uclinux.org/ + * + * Licensed under the GPL-2 or later. + * + */ + +#include +#include +#include + +#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) +#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) +#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET) +#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) +#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) +#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR) +#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) + +#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) +#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) +#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v) +#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v) +#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) +#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v) +#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) +#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1) +#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) + +#ifdef CONFIG_SIR_BFIN_DMA +struct dma_rx_buf { + char *buf; + int head; + int tail; + }; +#endif /* CONFIG_SIR_BFIN_DMA */ + +struct bfin_sir_port { + unsigned char __iomem *membase; + unsigned int irq; + unsigned int lsr; + unsigned long clk; + struct net_device *dev; +#ifdef CONFIG_SIR_BFIN_DMA + int tx_done; + struct dma_rx_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; +#endif /* CONFIG_SIR_BFIN_DMA */ + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; +}; + +struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; + +struct bfin_sir_port_res { + unsigned long base_addr; + int irq; + unsigned int rx_dma_channel; + unsigned int tx_dma_channel; +}; + +struct bfin_sir_port_res bfin_sir_port_resource[] = { +#ifdef CONFIG_BFIN_SIR0 + { + 0xFFC00400, + IRQ_UART0_RX, + CH_UART0_RX, + CH_UART0_TX, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + 0xFFC02000, + IRQ_UART1_RX, + CH_UART1_RX, + CH_UART1_TX, + }, +#endif +#ifdef CONFIG_BFIN_SIR2 + { + 0xFFC02100, + IRQ_UART2_RX, + CH_UART2_RX, + CH_UART2_TX, + }, +#endif +#ifdef CONFIG_BFIN_SIR3 + { + 0xFFC03100, + IRQ_UART3_RX, + CH_UART3_RX, + CH_UART3_TX, + }, +#endif +}; + +int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); + +struct bfin_sir_self { + struct bfin_sir_port *sir_port; + spinlock_t lock; + unsigned int open; + int speed; + int newspeed; + + struct sk_buff *txskb; + struct sk_buff *rxskb; + struct net_device_stats stats; + struct device *dev; + struct irlap_cb *irlap; + struct qos_info qos; + + iobuff_t tx_buff; + iobuff_t rx_buff; + + struct work_struct work; + int mtt; +}; + +#define DRIVER_NAME "bfin_sir" + +static void bfin_sir_hw_init(void) +{ +#ifdef CONFIG_BFIN_SIR0 + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); +#endif + +#ifdef CONFIG_BFIN_SIR1 + peripheral_request(P_UART1_TX, DRIVER_NAME); + peripheral_request(P_UART1_RX, DRIVER_NAME); +#endif + +#ifdef CONFIG_BFIN_SIR2 + peripheral_request(P_UART2_TX, DRIVER_NAME); + peripheral_request(P_UART2_RX, DRIVER_NAME); +#endif + +#ifdef CONFIG_BFIN_SIR3 + peripheral_request(P_UART3_TX, DRIVER_NAME); + peripheral_request(P_UART3_RX, DRIVER_NAME); +#endif + SSYNC(); +} diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h index b8509c16ecd..d6ee74ac046 100644 --- a/include/asm-blackfin/mach-bf548/blackfin.h +++ b/include/asm-blackfin/mach-bf548/blackfin.h @@ -166,6 +166,21 @@ #define BFIN_UART_SCR UART1_SCR #define BFIN_UART_GCTL UART1_GCTL +#define BFIN_UART_NR_PORTS 4 + +#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +#define OFFSET_GCTL 0x08 /* Global Control Register */ +#define OFFSET_LCR 0x0C /* Line Control Register */ +#define OFFSET_MCR 0x10 /* Modem Control Register */ +#define OFFSET_LSR 0x14 /* Line Status Register */ +#define OFFSET_MSR 0x18 /* Modem Status Register */ +#define OFFSET_SCR 0x1C /* SCR Scratch Register */ +#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */ +#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */ +#define OFFSET_THR 0x28 /* Transmit Holding register */ +#define OFFSET_RBR 0x2C /* Receive Buffer register */ + /* PLL_DIV Masks */ #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h index b6f513bee56..8a4e66d1db3 100644 --- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h @@ -1,22 +1,38 @@ +/* + * file: include/asm-blackfin/mach-bf561/bfin_serial_5xx.h + * based on: + * author: + * + * created: + * description: + * blackfin serial driver head file + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + #include #include #include -#define NR_PORTS 1 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ - #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) @@ -84,7 +100,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) bfin_write16(uart->port.membase + OFFSET_LSR, -1); } -struct bfin_serial_port bfin_serial_ports[NR_PORTS]; +struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; @@ -115,7 +131,7 @@ struct bfin_serial_res bfin_serial_resource[] = { #define DRIVER_NAME "bfin-uart" -int nr_ports = NR_PORTS; +int nr_ports = BFIN_UART_NR_PORTS; static void bfin_serial_hw_init(struct bfin_serial_port *uart) { diff --git a/include/asm-blackfin/mach-bf561/bfin_sir.h b/include/asm-blackfin/mach-bf561/bfin_sir.h new file mode 100644 index 00000000000..cefcf8bb505 --- /dev/null +++ b/include/asm-blackfin/mach-bf561/bfin_sir.h @@ -0,0 +1,120 @@ +/* + * Blackfin Infra-red Driver + * + * Copyright 2006-2008 Analog Devices Inc. + * + * Enter bugs at http://blackfin.uclinux.org/ + * + * Licensed under the GPL-2 or later. + * + */ + +#include +#include +#include + +#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) +#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) +#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER) +#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) +#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR) +#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) +#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) + +#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) +#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) +#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v) +#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) +#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) +#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) + +#ifdef CONFIG_SIR_BFIN_DMA +struct dma_rx_buf { + char *buf; + int head; + int tail; + }; +#endif /* CONFIG_SIR_BFIN_DMA */ + +struct bfin_sir_port { + unsigned char __iomem *membase; + unsigned int irq; + unsigned int lsr; + unsigned long clk; + struct net_device *dev; +#ifdef CONFIG_SIR_BFIN_DMA + int tx_done; + struct dma_rx_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; +#endif /* CONFIG_SIR_BFIN_DMA */ + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; +}; + +struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; + +struct bfin_sir_port_res { + unsigned long base_addr; + int irq; + unsigned int rx_dma_channel; + unsigned int tx_dma_channel; +}; + +struct bfin_sir_port_res bfin_sir_port_resource[] = { +#ifdef CONFIG_BFIN_SIR0 + { + 0xFFC00400, + IRQ_UART_RX, + CH_UART_RX, + CH_UART_TX, + }, +#endif +}; + +int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); + +struct bfin_sir_self { + struct bfin_sir_port *sir_port; + spinlock_t lock; + unsigned int open; + int speed; + int newspeed; + + struct sk_buff *txskb; + struct sk_buff *rxskb; + struct net_device_stats stats; + struct device *dev; + struct irlap_cb *irlap; + struct qos_info qos; + + iobuff_t tx_buff; + iobuff_t rx_buff; + + struct work_struct work; + int mtt; +}; + +static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port) +{ + unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR); + port->lsr |= (lsr & (BI|FE|PE|OE)); + return lsr | port->lsr; +} + +static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port) +{ + port->lsr = 0; + bfin_read16(port->membase + OFFSET_LSR); +} + +#define DRIVER_NAME "bfin_sir" + +static void bfin_sir_hw_init(void) +{ +#ifdef CONFIG_BFIN_SIR0 + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); +#endif + SSYNC(); +} diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h index 3a16df2c86d..0ea8666e676 100644 --- a/include/asm-blackfin/mach-bf561/blackfin.h +++ b/include/asm-blackfin/mach-bf561/blackfin.h @@ -69,5 +69,19 @@ #define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) #define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) +#define BFIN_UART_NR_PORTS 1 + +#define OFFSET_THR 0x00 /* Transmit Holding register */ +#define OFFSET_RBR 0x00 /* Receive Buffer register */ +#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +#define OFFSET_IER 0x04 /* Interrupt Enable Register */ +#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ +#define OFFSET_LCR 0x0C /* Line Control Register */ +#define OFFSET_MCR 0x10 /* Modem Control Register */ +#define OFFSET_LSR 0x14 /* Line Status Register */ +#define OFFSET_MSR 0x18 /* Modem Status Register */ +#define OFFSET_SCR 0x1C /* SCR Scratch Register */ +#define OFFSET_GCTL 0x24 /* Global Control Register */ #endif /* _MACH_BLACKFIN_H_ */ -- cgit v1.2.3 From 565c0d3ff438d18aa8c3201979fb1f5d1872ab11 Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Fri, 25 Apr 2008 03:10:04 +0800 Subject: [Blackfin] arch: fix bug - before assign new channel to the map register, need clear the bits first. http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=2445 Signed-off-by: Graf Yang Signed-off-by: Bryan Wu --- arch/blackfin/kernel/bfin_dma_5xx.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c index df4d2a5b8e3..fd5448d6107 100644 --- a/arch/blackfin/kernel/bfin_dma_5xx.c +++ b/arch/blackfin/kernel/bfin_dma_5xx.c @@ -106,12 +106,15 @@ int request_dma(unsigned int channel, char *device_id) #ifdef CONFIG_BF54x if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) { - if (strncmp(device_id, "BFIN_UART", 9) == 0) + if (strncmp(device_id, "BFIN_UART", 9) == 0) { + dma_ch[channel].regs->peripheral_map &= 0x0FFF; dma_ch[channel].regs->peripheral_map |= ((channel - CH_UART2_RX + 0xC)<<12); - else + } else { + dma_ch[channel].regs->peripheral_map &= 0x0FFF; dma_ch[channel].regs->peripheral_map |= ((channel - CH_UART2_RX + 0x6)<<12); + } } #endif -- cgit v1.2.3 From 00d205a1ce1a24a1a9d9ebfbddbae56021cba826 Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Fri, 25 Apr 2008 03:26:48 +0800 Subject: [Blackfin] arch: lose unnecessary dependency on CONFIG_BFIN_ICACHE for MPU Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu --- arch/blackfin/kernel/cplb-mpu/cplbmgr.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index 44bbfe26ce4..99f2831e296 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c @@ -24,8 +24,6 @@ #include #include -#ifdef CONFIG_BFIN_ICACHE - #define FAULT_RW (1 << 16) #define FAULT_USERSUPV (1 << 17) @@ -370,5 +368,3 @@ void set_mask_dcplbs(unsigned long *masks) } enable_dcplb(); } - -#endif -- cgit v1.2.3 From 5d750b9e4f6ca7d366b4954517ff8be9ee07e1bf Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Fri, 25 Apr 2008 05:02:33 +0800 Subject: [Blackfin] arch: Remove the circular buffering mechanism for exceptions Remove the circular buffering mechanism for exceptions. Instead, point RETX at a safe location from which to fetch three NOPs. This safe location is now in the fixed code area, and also used for certain anomaly workarounds, to ensure that user space can find a valid ICPLB when things are built with CONFIG_MPU. Also, save I/DCPLB_FAULT_ADDRESS when lowering to level 5, since the hardware reg is valid only at exception level. Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu --- arch/blackfin/kernel/traps.c | 15 ++-- arch/blackfin/mach-common/entry.S | 121 ++++++++---------------------- arch/blackfin/mach-common/ints-priority.c | 2 - 3 files changed, 40 insertions(+), 98 deletions(-) diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index d0f67542207..5b847070dae 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -67,6 +67,8 @@ void __init trap_init(void) CSYNC(); } +void *saved_icplb_fault_addr, *saved_dcplb_fault_addr; + int kstack_depth_to_print = 48; static void decode_address(char *buf, unsigned long address) @@ -703,10 +705,7 @@ void dump_bfin_mem(struct pt_regs *fp) unsigned short *addr, *erraddr, val = 0, err = 0; char sti = 0, buf[6]; - if (unlikely((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)) - erraddr = (void *)fp->pc; - else - erraddr = (void *)fp->retx; + erraddr = (void *)fp->pc; printk(KERN_NOTICE "return address: [0x%p]; contents of:", erraddr); @@ -830,9 +829,9 @@ unlock: if (((long)fp->seqstat & SEQSTAT_EXCAUSE) && (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) { - decode_address(buf, bfin_read_DCPLB_FAULT_ADDR()); + decode_address(buf, saved_dcplb_fault_addr); printk(KERN_NOTICE "DCPLB_FAULT_ADDR: %s\n", buf); - decode_address(buf, bfin_read_ICPLB_FAULT_ADDR()); + decode_address(buf, saved_icplb_fault_addr); printk(KERN_NOTICE "ICPLB_FAULT_ADDR: %s\n", buf); } @@ -940,8 +939,8 @@ void panic_cplb_error(int cplb_panic, struct pt_regs *fp) oops_in_progress = 1; - printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", (void *)bfin_read_DCPLB_FAULT_ADDR()); - printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", (void *)bfin_read_ICPLB_FAULT_ADDR()); + printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", saved_dcplb_fault_addr); + printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", saved_icplb_fault_addr); dump_bfin_process(fp); dump_bfin_mem(fp); show_regs(fp); diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index a504c65d999..f2fb87e9a46 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -38,6 +38,7 @@ #include #include #include +#include #include /* TIF_NEED_RESCHED */ #include #include @@ -52,15 +53,6 @@ # define EX_SCRATCH_REG CYCLES #endif -#if ANOMALY_05000281 -ENTRY(_safe_speculative_execution) - NOP; - NOP; - NOP; - jump _safe_speculative_execution; -ENDPROC(_safe_speculative_execution) -#endif - #ifdef CONFIG_EXCPT_IRQ_SYSC_L1 .section .l1.text #else @@ -230,6 +222,26 @@ ENTRY(_ex_trap_c) [p4] = p5; csync; + p4.l = lo(DCPLB_FAULT_ADDR); + p4.h = hi(DCPLB_FAULT_ADDR); + r7 = [p4]; + p5.h = _saved_dcplb_fault_addr; + p5.l = _saved_dcplb_fault_addr; + [p5] = r7; + + r7 = [p4 + (ICPLB_FAULT_ADDR - DCPLB_FAULT_ADDR)]; + p5.h = _saved_icplb_fault_addr; + p5.l = _saved_icplb_fault_addr; + [p5] = r7; + + p4.l = __retx; + p4.h = __retx; + r6 = retx; + [p4] = r6; + p4.l = lo(SAFE_USER_INSTRUCTION); + p4.h = hi(SAFE_USER_INSTRUCTION); + retx = p4; + /* Disable all interrupts, but make sure level 5 is enabled so * we can switch to that level. Save the old mask. */ cli r6; @@ -239,23 +251,6 @@ ENTRY(_ex_trap_c) r6 = 0x3f; sti r6; - /* Save the excause into a circular buffer, in case the instruction - * which caused this excecptions causes others. - */ - P5.l = _in_ptr_excause; - P5.h = _in_ptr_excause; - R7 = [P5]; - R7 += 4; - R6 = 0xF; - R7 = R7 & R6; - [P5] = R7; - R6.l = _excause_circ_buf; - R6.h = _excause_circ_buf; - R7 = R7 + R6; - p5 = R7; - R6 = SEQSTAT; - [P5] = R6; - (R7:6,P5:4) = [sp++]; ASTAT = [sp++]; SP = EX_SCRATCH_REG; @@ -312,6 +307,11 @@ ENDPROC(_double_fault) ENTRY(_exception_to_level5) SAVE_ALL_SYS + p4.l = __retx; + p4.h = __retx; + r6 = [p4]; + [sp + PT_PC] = r6; + /* Restore interrupt mask. We haven't pushed RETI, so this * doesn't enable interrupts until we return from this handler. */ p4.l = _excpt_saved_imask; @@ -333,42 +333,11 @@ ENTRY(_exception_to_level5) r0 = [p2]; /* Read current IPEND */ [sp + PT_IPEND] = r0; /* Store IPEND */ - /* Pop the excause from the circular buffer and push it on the stack - * (in the right place - if you change the location of SEQSTAT, you - * must change this offset. - */ -.L_excep_to_5_again: - P5.l = _out_ptr_excause; - P5.h = _out_ptr_excause; - R7 = [P5]; - R7 += 4; - R6 = 0xF; - R7 = R7 & R6; - [P5] = R7; - R6.l = _excause_circ_buf; - R6.h = _excause_circ_buf; - R7 = R7 + R6; - P5 = R7; - R1 = [P5]; - [SP + PT_SEQSTAT] = r1; - r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ SP += -12; call _trap_c; SP += 12; - /* See if anything else is in the exception buffer - * if there is, process it - */ - P5.l = _out_ptr_excause; - P5.h = _out_ptr_excause; - P4.l = _in_ptr_excause; - P4.h = _in_ptr_excause; - R6 = [P5]; - R7 = [P4]; - CC = R6 == R7; - if ! CC JUMP .L_excep_to_5_again - call _ret_from_exception; RESTORE_ALL_SYS rti; @@ -732,8 +701,8 @@ ENTRY(_return_from_int) [p0] = p1; csync; #if ANOMALY_05000281 - r0.l = _safe_speculative_execution; - r0.h = _safe_speculative_execution; + r0.l = lo(SAFE_USER_INSTRUCTION); + r0.h = hi(SAFE_USER_INSTRUCTION); reti = r0; #endif r0 = 0x801f (z); @@ -746,8 +715,8 @@ ENDPROC(_return_from_int) ENTRY(_lower_to_irq14) #if ANOMALY_05000281 - r0.l = _safe_speculative_execution; - r0.h = _safe_speculative_execution; + r0.l = lo(SAFE_USER_INSTRUCTION); + r0.h = hi(SAFE_USER_INSTRUCTION); reti = r0; #endif r0 = 0x401f; @@ -814,20 +783,6 @@ _schedule_and_signal: rti; ENDPROC(_lower_to_irq14) -/* Make sure when we start, that the circular buffer is initialized properly - * R0 and P0 are call clobbered, so we can use them here. - */ -ENTRY(_init_exception_buff) - r0 = 0; - p0.h = _in_ptr_excause; - p0.l = _in_ptr_excause; - [p0] = r0; - p0.h = _out_ptr_excause; - p0.l = _out_ptr_excause; - [p0] = r0; - rts; -ENDPROC(_init_exception_buff) - /* We handle this 100% in exception space - to reduce overhead * Only potiential problem is if the software buffer gets swapped out of the * CPLB table - then double fault. - so we don't let this happen in other places @@ -1403,17 +1358,7 @@ _exception_stack_top: _last_cplb_fault_retx: .long 0; #endif -/* - * Single instructions can have multiple faults, which need to be - * handled by traps.c, in irq5. We store the exception cause to ensure - * we don't miss a double fault condition - */ -ENTRY(_in_ptr_excause) - .long 0; -ENTRY(_out_ptr_excause) + /* Used to save the real RETX when temporarily storing a safe + * return address. */ +__retx: .long 0; -ALIGN -ENTRY(_excause_circ_buf) - .rept 4 - .long 0 - .endr diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 5448230c0e9..f5fd768022e 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -939,8 +939,6 @@ int __init init_arch_irq(void) local_irq_disable(); - init_exception_buff(); - #ifdef CONFIG_BF54x # ifdef CONFIG_PINTx_REASSIGN pint[0]->assign = CONFIG_PINT0_ASSIGN; -- cgit v1.2.3 From 1e78042c77dcc255abd456398981549269c63238 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Fri, 25 Apr 2008 04:31:23 +0800 Subject: [Blackfin] arch: take DDR DEVWD into consideration as well for BF548 Pointed-out-by: Michael Hennerich Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index b0ae5cd4420..8efea004aec 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -680,13 +680,20 @@ static inline int __init get_mem_size(void) return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL()); # endif # elif defined(EBIU_DDRCTL1) - switch (bfin_read_EBIU_DDRCTL1() & 0xc0000) { - case DEVSZ_64: return 64 / 8; - case DEVSZ_128: return 128 / 8; - case DEVSZ_256: return 256 / 8; - case DEVSZ_512: return 512 / 8; - default: return 0; + u32 ddrctl = bfin_read_EBIU_DDRCTL1(); + int ret = 0; + switch (ddrctl & 0xc0000) { + case DEVSZ_64: ret = 64 / 8; + case DEVSZ_128: ret = 128 / 8; + case DEVSZ_256: ret = 256 / 8; + case DEVSZ_512: ret = 512 / 8; + } + switch (ddrctl & 0x30000) { + case DEVWD_4: ret *= 2; + case DEVWD_8: ret *= 2; + case DEVWD_16: break; } + return ret; # endif #endif BUG(); -- cgit v1.2.3 From 2fb6cb41ecb315b1d84849663bb2793cdc41a96d Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Fri, 25 Apr 2008 04:39:28 +0800 Subject: [Blackfin] arch: Add a warning about the value of CLKIN. Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu --- arch/blackfin/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index eba22c21982..795d0ac67c2 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -289,7 +289,7 @@ config BOOT_LOAD comment "Clock/PLL Setup" config CLKIN_HZ - int "Crystal Frequency in Hz" + int "Frequency of the crystal on the board in Hz" default "11059200" if BFIN533_STAMP default "27000000" if BFIN533_EZKIT default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS) @@ -298,6 +298,8 @@ config CLKIN_HZ default "10000000" if BFIN532_IP0X help The frequency of CLKIN crystal oscillator on the board in Hz. + Warning: This value should match the crystal on the board. Otherwise, + peripherals won't work properly. config BFIN_KERNEL_CLOCK bool "Re-program Clocks while Kernel boots?" -- cgit v1.2.3 From 8e39df215c4b1d3e6f9e62f92d35ab1aa11104eb Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Fri, 25 Apr 2008 04:41:49 +0800 Subject: [Blackfin] arch: Equalize include files: Add PLL_DIV Masks Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf561/defBF561.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h index bee30230187..366c9b9a0cb 100644 --- a/include/asm-blackfin/mach-bf561/defBF561.h +++ b/include/asm-blackfin/mach-bf561/defBF561.h @@ -871,6 +871,8 @@ /* PLL_DIV Masks */ #define SCLK_DIV(x) (x) /* SCLK = VCO / x */ +#define CSEL 0x30 /* Core Select */ +#define SSEL 0xf /* System Select */ #define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ #define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ #define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ -- cgit v1.2.3 From fe44193c55e26b9b835722b5ee2519972f59c540 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Fri, 25 Apr 2008 04:52:11 +0800 Subject: [Blackfin] arch: Functional power management support: Remove broken cpu frequency scaling drivers Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf527/Makefile | 2 - arch/blackfin/mach-bf527/cpu.c | 161 -------------------------------------- arch/blackfin/mach-bf533/Makefile | 2 - arch/blackfin/mach-bf533/cpu.c | 158 ------------------------------------- arch/blackfin/mach-bf537/Makefile | 2 - arch/blackfin/mach-bf537/cpu.c | 159 ------------------------------------- arch/blackfin/mach-bf548/Makefile | 2 - arch/blackfin/mach-bf548/cpu.c | 159 ------------------------------------- 8 files changed, 645 deletions(-) delete mode 100644 arch/blackfin/mach-bf527/cpu.c delete mode 100644 arch/blackfin/mach-bf533/cpu.c delete mode 100644 arch/blackfin/mach-bf537/cpu.c delete mode 100644 arch/blackfin/mach-bf548/cpu.c diff --git a/arch/blackfin/mach-bf527/Makefile b/arch/blackfin/mach-bf527/Makefile index 9f99f5d0bcd..4eddb580319 100644 --- a/arch/blackfin/mach-bf527/Makefile +++ b/arch/blackfin/mach-bf527/Makefile @@ -5,5 +5,3 @@ extra-y := head.o obj-y := ints-priority.o dma.o - -obj-$(CONFIG_CPU_FREQ) += cpu.o diff --git a/arch/blackfin/mach-bf527/cpu.c b/arch/blackfin/mach-bf527/cpu.c deleted file mode 100644 index 1975402b1db..00000000000 --- a/arch/blackfin/mach-bf527/cpu.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * File: arch/blackfin/mach-bf527/cpu.c - * Based on: arch/blackfin/mach-bf537/cpu.c - * Author: michael.kang@analog.com - * - * Created: - * Description: clock scaling for the bf527 - * - * Modified: - * Copyright 2004-2007 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -/* CONFIG_CLKIN_HZ=11059200 */ -#define VCO5 (CONFIG_CLKIN_HZ*45) /*497664000 */ -#define VCO4 (CONFIG_CLKIN_HZ*36) /*398131200 */ -#define VCO3 (CONFIG_CLKIN_HZ*27) /*298598400 */ -#define VCO2 (CONFIG_CLKIN_HZ*18) /*199065600 */ -#define VCO1 (CONFIG_CLKIN_HZ*9) /*99532800 */ -#define VCO(x) VCO##x - -#define MFREQ(x) {VCO(x), VCO(x)/4}, {VCO(x), VCO(x)/2}, {VCO(x), VCO(x)} -/* frequency */ -static struct cpufreq_frequency_table bf527_freq_table[] = { - MFREQ(1), - MFREQ(3), - {VCO4, VCO4 / 2}, {VCO4, VCO4}, - MFREQ(5), - {0, CPUFREQ_TABLE_END}, -}; - -/* - * dpmc_fops->ioctl() - * static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) - */ -static int bf527_getfreq(unsigned int cpu) -{ - unsigned long cclk_mhz; - - /* The driver only support single cpu */ - if (cpu == 0) - dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz); - else - cclk_mhz = -1; - - return cclk_mhz; -} - -static int bf527_target(struct cpufreq_policy *policy, - unsigned int target_freq, unsigned int relation) -{ - unsigned long cclk_mhz; - unsigned long vco_mhz; - unsigned long flags; - unsigned int index; - struct cpufreq_freqs freqs; - - if (cpufreq_frequency_table_target - (policy, bf527_freq_table, target_freq, relation, &index)) - return -EINVAL; - - cclk_mhz = bf527_freq_table[index].frequency; - vco_mhz = bf527_freq_table[index].index; - - dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz); - freqs.old = bf527_getfreq(0); - freqs.new = cclk_mhz; - freqs.cpu = 0; - - pr_debug - ("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n", - cclk_mhz, vco_mhz, index, target_freq, freqs.old); - - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); - local_irq_save(flags); - dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz); - local_irq_restore(flags); - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - - vco_mhz = get_vco(); - cclk_mhz = get_cclk(); - return 0; -} - -/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on - * this platform, anyway. - */ -static int bf527_verify_speed(struct cpufreq_policy *policy) -{ - return cpufreq_frequency_table_verify(policy, &bf527_freq_table); -} - -static int __init __bf527_cpu_init(struct cpufreq_policy *policy) -{ - if (policy->cpu != 0) - return -EINVAL; - - policy->governor = CPUFREQ_DEFAULT_GOVERNOR; - - policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; - /*Now ,only support one cpu */ - policy->cur = bf527_getfreq(0); - cpufreq_frequency_table_get_attr(bf527_freq_table, policy->cpu); - return cpufreq_frequency_table_cpuinfo(policy, bf527_freq_table); -} - -static struct freq_attr *bf527_freq_attr[] = { - &cpufreq_freq_attr_scaling_available_freqs, - NULL, -}; - -static struct cpufreq_driver bf527_driver = { - .verify = bf527_verify_speed, - .target = bf527_target, - .get = bf527_getfreq, - .init = __bf527_cpu_init, - .name = "bf527", - .owner = THIS_MODULE, - .attr = bf527_freq_attr, -}; - -static int __init bf527_cpu_init(void) -{ - return cpufreq_register_driver(&bf527_driver); -} - -static void __exit bf527_cpu_exit(void) -{ - cpufreq_unregister_driver(&bf527_driver); -} - -MODULE_AUTHOR("Mickael Kang"); -MODULE_DESCRIPTION("cpufreq driver for bf527 CPU"); -MODULE_LICENSE("GPL"); - -module_init(bf527_cpu_init); -module_exit(bf527_cpu_exit); diff --git a/arch/blackfin/mach-bf533/Makefile b/arch/blackfin/mach-bf533/Makefile index 8cce1736360..aa9f2647ee0 100644 --- a/arch/blackfin/mach-bf533/Makefile +++ b/arch/blackfin/mach-bf533/Makefile @@ -5,5 +5,3 @@ extra-y := head.o obj-y := ints-priority.o dma.o - -obj-$(CONFIG_CPU_FREQ) += cpu.o diff --git a/arch/blackfin/mach-bf533/cpu.c b/arch/blackfin/mach-bf533/cpu.c deleted file mode 100644 index b7a0e0fbd9a..00000000000 --- a/arch/blackfin/mach-bf533/cpu.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * File: arch/blackfin/mach-bf533/cpu.c - * Based on: - * Author: michael.kang@analog.com - * - * Created: - * Description: clock scaling for the bf533 - * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -/* CONFIG_CLKIN_HZ=11059200 */ -#define VCO5 (CONFIG_CLKIN_HZ*45) /*497664000 */ -#define VCO4 (CONFIG_CLKIN_HZ*36) /*398131200 */ -#define VCO3 (CONFIG_CLKIN_HZ*27) /*298598400 */ -#define VCO2 (CONFIG_CLKIN_HZ*18) /*199065600 */ -#define VCO1 (CONFIG_CLKIN_HZ*9) /*99532800 */ -#define VCO(x) VCO##x - -#define FREQ(x) {VCO(x),VCO(x)/4},{VCO(x),VCO(x)/2},{VCO(x),VCO(x)} -/* frequency */ -static struct cpufreq_frequency_table bf533_freq_table[] = { - FREQ(1), - FREQ(3), - {VCO4, VCO4 / 2}, {VCO4, VCO4}, - FREQ(5), - {0, CPUFREQ_TABLE_END}, -}; - -/* - * dpmc_fops->ioctl() - * static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) - */ -static int bf533_getfreq(unsigned int cpu) -{ - unsigned long cclk_mhz, vco_mhz; - - /* The driver only support single cpu */ - if (cpu == 0) - dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz); - else - cclk_mhz = -1; - return cclk_mhz; -} - -static int bf533_target(struct cpufreq_policy *policy, - unsigned int target_freq, unsigned int relation) -{ - unsigned long cclk_mhz; - unsigned long vco_mhz; - unsigned long flags; - unsigned int index, vco_index; - int i; - - struct cpufreq_freqs freqs; - if (cpufreq_frequency_table_target(policy, bf533_freq_table, target_freq, relation, &index)) - return -EINVAL; - cclk_mhz = bf533_freq_table[index].frequency; - vco_mhz = bf533_freq_table[index].index; - - dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz); - freqs.old = bf533_getfreq(0); - freqs.new = cclk_mhz; - freqs.cpu = 0; - - pr_debug("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n", - cclk_mhz, vco_mhz, index, target_freq, freqs.old); - - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); - local_irq_save(flags); - dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz); - local_irq_restore(flags); - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - - vco_mhz = get_vco(); - cclk_mhz = get_cclk(); - return 0; -} - -/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on - * this platform, anyway. - */ -static int bf533_verify_speed(struct cpufreq_policy *policy) -{ - return cpufreq_frequency_table_verify(policy, &bf533_freq_table); -} - -static int __init __bf533_cpu_init(struct cpufreq_policy *policy) -{ - int result; - - if (policy->cpu != 0) - return -EINVAL; - - policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; - /*Now ,only support one cpu */ - policy->cur = bf533_getfreq(0); - cpufreq_frequency_table_get_attr(bf533_freq_table, policy->cpu); - return cpufreq_frequency_table_cpuinfo(policy, bf533_freq_table); -} - -static struct freq_attr *bf533_freq_attr[] = { - &cpufreq_freq_attr_scaling_available_freqs, - NULL, -}; - -static struct cpufreq_driver bf533_driver = { - .verify = bf533_verify_speed, - .target = bf533_target, - .get = bf533_getfreq, - .init = __bf533_cpu_init, - .name = "bf533", - .owner = THIS_MODULE, - .attr = bf533_freq_attr, -}; - -static int __init bf533_cpu_init(void) -{ - return cpufreq_register_driver(&bf533_driver); -} - -static void __exit bf533_cpu_exit(void) -{ - cpufreq_unregister_driver(&bf533_driver); -} - -MODULE_AUTHOR("Mickael Kang"); -MODULE_DESCRIPTION("cpufreq driver for BF533 CPU"); -MODULE_LICENSE("GPL"); - -module_init(bf533_cpu_init); -module_exit(bf533_cpu_exit); diff --git a/arch/blackfin/mach-bf537/Makefile b/arch/blackfin/mach-bf537/Makefile index 7e7c9c8ac5b..68e5478e95a 100644 --- a/arch/blackfin/mach-bf537/Makefile +++ b/arch/blackfin/mach-bf537/Makefile @@ -5,5 +5,3 @@ extra-y := head.o obj-y := ints-priority.o dma.o - -obj-$(CONFIG_CPU_FREQ) += cpu.o diff --git a/arch/blackfin/mach-bf537/cpu.c b/arch/blackfin/mach-bf537/cpu.c deleted file mode 100644 index 0442c4c7f72..00000000000 --- a/arch/blackfin/mach-bf537/cpu.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * File: arch/blackfin/mach-bf537/cpu.c - * Based on: - * Author: michael.kang@analog.com - * - * Created: - * Description: clock scaling for the bf537 - * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -/* CONFIG_CLKIN_HZ=11059200 */ -#define VCO5 (CONFIG_CLKIN_HZ*45) /*497664000 */ -#define VCO4 (CONFIG_CLKIN_HZ*36) /*398131200 */ -#define VCO3 (CONFIG_CLKIN_HZ*27) /*298598400 */ -#define VCO2 (CONFIG_CLKIN_HZ*18) /*199065600 */ -#define VCO1 (CONFIG_CLKIN_HZ*9) /*99532800 */ -#define VCO(x) VCO##x - -#define MFREQ(x) {VCO(x),VCO(x)/4},{VCO(x),VCO(x)/2},{VCO(x),VCO(x)} -/* frequency */ -static struct cpufreq_frequency_table bf537_freq_table[] = { - MFREQ(1), - MFREQ(3), - {VCO4, VCO4 / 2}, {VCO4, VCO4}, - MFREQ(5), - {0, CPUFREQ_TABLE_END}, -}; - -/* - * dpmc_fops->ioctl() - * static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) - */ -static int bf537_getfreq(unsigned int cpu) -{ - unsigned long cclk_mhz; - - /* The driver only support single cpu */ - if (cpu == 0) - dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz); - else - cclk_mhz = -1; - - return cclk_mhz; -} - -static int bf537_target(struct cpufreq_policy *policy, - unsigned int target_freq, unsigned int relation) -{ - unsigned long cclk_mhz; - unsigned long vco_mhz; - unsigned long flags; - unsigned int index; - struct cpufreq_freqs freqs; - - if (cpufreq_frequency_table_target(policy, bf537_freq_table, target_freq, relation, &index)) - return -EINVAL; - - cclk_mhz = bf537_freq_table[index].frequency; - vco_mhz = bf537_freq_table[index].index; - - dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz); - freqs.old = bf537_getfreq(0); - freqs.new = cclk_mhz; - freqs.cpu = 0; - - pr_debug("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n", - cclk_mhz, vco_mhz, index, target_freq, freqs.old); - - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); - local_irq_save(flags); - dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz); - local_irq_restore(flags); - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - - vco_mhz = get_vco(); - cclk_mhz = get_cclk(); - return 0; -} - -/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on - * this platform, anyway. - */ -static int bf537_verify_speed(struct cpufreq_policy *policy) -{ - return cpufreq_frequency_table_verify(policy, &bf537_freq_table); -} - -static int __init __bf537_cpu_init(struct cpufreq_policy *policy) -{ - if (policy->cpu != 0) - return -EINVAL; - - policy->governor = CPUFREQ_DEFAULT_GOVERNOR; - - policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; - /*Now ,only support one cpu */ - policy->cur = bf537_getfreq(0); - cpufreq_frequency_table_get_attr(bf537_freq_table, policy->cpu); - return cpufreq_frequency_table_cpuinfo(policy, bf537_freq_table); -} - -static struct freq_attr *bf537_freq_attr[] = { - &cpufreq_freq_attr_scaling_available_freqs, - NULL, -}; - -static struct cpufreq_driver bf537_driver = { - .verify = bf537_verify_speed, - .target = bf537_target, - .get = bf537_getfreq, - .init = __bf537_cpu_init, - .name = "bf537", - .owner = THIS_MODULE, - .attr = bf537_freq_attr, -}; - -static int __init bf537_cpu_init(void) -{ - return cpufreq_register_driver(&bf537_driver); -} - -static void __exit bf537_cpu_exit(void) -{ - cpufreq_unregister_driver(&bf537_driver); -} - -MODULE_AUTHOR("Mickael Kang"); -MODULE_DESCRIPTION("cpufreq driver for BF537 CPU"); -MODULE_LICENSE("GPL"); - -module_init(bf537_cpu_init); -module_exit(bf537_cpu_exit); diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile index 7e7c9c8ac5b..68e5478e95a 100644 --- a/arch/blackfin/mach-bf548/Makefile +++ b/arch/blackfin/mach-bf548/Makefile @@ -5,5 +5,3 @@ extra-y := head.o obj-y := ints-priority.o dma.o - -obj-$(CONFIG_CPU_FREQ) += cpu.o diff --git a/arch/blackfin/mach-bf548/cpu.c b/arch/blackfin/mach-bf548/cpu.c deleted file mode 100644 index 4298a3ccfbf..00000000000 --- a/arch/blackfin/mach-bf548/cpu.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * File: arch/blackfin/mach-bf548/cpu.c - * Based on: - * Author: - * - * Created: - * Description: clock scaling for the bf54x - * - * Modified: - * Copyright 2004-2007 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -/* CONFIG_CLKIN_HZ=25000000 */ -#define VCO5 (CONFIG_CLKIN_HZ*45) -#define VCO4 (CONFIG_CLKIN_HZ*36) -#define VCO3 (CONFIG_CLKIN_HZ*27) -#define VCO2 (CONFIG_CLKIN_HZ*18) -#define VCO1 (CONFIG_CLKIN_HZ*9) -#define VCO(x) VCO##x - -#define MFREQ(x) {VCO(x),VCO(x)/4},{VCO(x),VCO(x)/2},{VCO(x),VCO(x)} -/* frequency */ -static struct cpufreq_frequency_table bf548_freq_table[] = { - MFREQ(1), - MFREQ(3), - {VCO4, VCO4 / 2}, {VCO4, VCO4}, - MFREQ(5), - {0, CPUFREQ_TABLE_END}, -}; - -/* - * dpmc_fops->ioctl() - * static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) - */ -static int bf548_getfreq(unsigned int cpu) -{ - unsigned long cclk_mhz; - - /* The driver only support single cpu */ - if (cpu == 0) - dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz); - else - cclk_mhz = -1; - - return cclk_mhz; -} - -static int bf548_target(struct cpufreq_policy *policy, - unsigned int target_freq, unsigned int relation) -{ - unsigned long cclk_mhz; - unsigned long vco_mhz; - unsigned long flags; - unsigned int index; - struct cpufreq_freqs freqs; - - if (cpufreq_frequency_table_target(policy, bf548_freq_table, target_freq, relation, &index)) - return -EINVAL; - - cclk_mhz = bf548_freq_table[index].frequency; - vco_mhz = bf548_freq_table[index].index; - - dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz); - freqs.old = bf548_getfreq(0); - freqs.new = cclk_mhz; - freqs.cpu = 0; - - pr_debug("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n", - cclk_mhz, vco_mhz, index, target_freq, freqs.old); - - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); - local_irq_save(flags); - dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz); - local_irq_restore(flags); - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - - vco_mhz = get_vco(); - cclk_mhz = get_cclk(); - return 0; -} - -/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on - * this platform, anyway. - */ -static int bf548_verify_speed(struct cpufreq_policy *policy) -{ - return cpufreq_frequency_table_verify(policy, &bf548_freq_table); -} - -static int __init __bf548_cpu_init(struct cpufreq_policy *policy) -{ - if (policy->cpu != 0) - return -EINVAL; - - policy->governor = CPUFREQ_DEFAULT_GOVERNOR; - - policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; - /*Now ,only support one cpu */ - policy->cur = bf548_getfreq(0); - cpufreq_frequency_table_get_attr(bf548_freq_table, policy->cpu); - return cpufreq_frequency_table_cpuinfo(policy, bf548_freq_table); -} - -static struct freq_attr *bf548_freq_attr[] = { - &cpufreq_freq_attr_scaling_available_freqs, - NULL, -}; - -static struct cpufreq_driver bf548_driver = { - .verify = bf548_verify_speed, - .target = bf548_target, - .get = bf548_getfreq, - .init = __bf548_cpu_init, - .name = "bf548", - .owner = THIS_MODULE, - .attr = bf548_freq_attr, -}; - -static int __init bf548_cpu_init(void) -{ - return cpufreq_register_driver(&bf548_driver); -} - -static void __exit bf548_cpu_exit(void) -{ - cpufreq_unregister_driver(&bf548_driver); -} - -MODULE_AUTHOR("Mickael Kang"); -MODULE_DESCRIPTION("cpufreq driver for BF548 CPU"); -MODULE_LICENSE("GPL"); - -module_init(bf548_cpu_init); -module_exit(bf548_cpu_exit); -- cgit v1.2.3 From e6c91b64dd6e4c3adf39483c85a936eef9465e19 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Fri, 25 Apr 2008 04:58:29 +0800 Subject: [Blackfin] arch: Functional power management support: Add support for cpu frequency scaling Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- arch/blackfin/kernel/time-ts.c | 30 +++++- arch/blackfin/kernel/time.c | 19 +--- arch/blackfin/mach-common/Makefile | 3 +- arch/blackfin/mach-common/cpufreq.c | 194 ++++++++++++++++++++++++++++++++++++ include/asm-blackfin/time.h | 36 +++++++ 5 files changed, 263 insertions(+), 19 deletions(-) create mode 100644 arch/blackfin/mach-common/cpufreq.c create mode 100644 include/asm-blackfin/time.h diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c index 1ce8cb1e498..4482c47c09e 100644 --- a/arch/blackfin/kernel/time-ts.c +++ b/arch/blackfin/kernel/time-ts.c @@ -16,11 +16,35 @@ #include #include #include +#include #include +#include #ifdef CONFIG_CYCLES_CLOCKSOURCE +/* Accelerators for sched_clock() + * convert from cycles(64bits) => nanoseconds (64bits) + * basic equation: + * ns = cycles / (freq / ns_per_sec) + * ns = cycles * (ns_per_sec / freq) + * ns = cycles * (10^9 / (cpu_khz * 10^3)) + * ns = cycles * (10^6 / cpu_khz) + * + * Then we use scaling math (suggested by george@mvista.com) to get: + * ns = cycles * (10^6 * SC / cpu_khz) / SC + * ns = cycles * cyc2ns_scale / SC + * + * And since SC is a constant power of two, we can convert the div + * into a shift. + * + * We can use khz divisor instead of mhz to keep a better precision, since + * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits. + * (mathieu.desnoyers@polymtl.ca) + * + * -johnstul@us.ibm.com "math is hard, lets go shopping!" + */ + static unsigned long cyc2ns_scale; #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ @@ -82,8 +106,9 @@ static void bfin_timer_set_mode(enum clock_event_mode mode, { switch (mode) { case CLOCK_EVT_MODE_PERIODIC: { - unsigned long tcount = ((get_cclk() / (HZ * 1)) - 1); + unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1); bfin_write_TCNTL(TMPWR); + bfin_write_TSCALE(TIME_SCALE - 1); CSYNC(); bfin_write_TPERIOD(tcount); bfin_write_TCOUNT(tcount); @@ -92,6 +117,7 @@ static void bfin_timer_set_mode(enum clock_event_mode mode, break; } case CLOCK_EVT_MODE_ONESHOT: + bfin_write_TSCALE(0); bfin_write_TCOUNT(0); bfin_write_TCNTL(TMPWR | TMREN); CSYNC(); @@ -115,7 +141,7 @@ static void __init bfin_timer_init(void) /* * the TSCALE prescaler counter. */ - bfin_write_TSCALE(0); + bfin_write_TSCALE(TIME_SCALE - 1); bfin_write_TPERIOD(0); bfin_write_TCOUNT(0); diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c index 715b3945e4c..eb235232045 100644 --- a/arch/blackfin/kernel/time.c +++ b/arch/blackfin/kernel/time.c @@ -6,9 +6,10 @@ * Created: * Description: This file contains the bfin-specific time handling details. * Most of the stuff is located in the machine specific files. + * FIXME: (This file is subject for removal) * * Modified: - * Copyright 2004-2006 Analog Devices Inc. + * Copyright 2004-2008 Analog Devices Inc. * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * @@ -35,6 +36,7 @@ #include #include +#include /* This is an NTP setting */ #define TICK_SIZE (tick_nsec / 1000) @@ -47,21 +49,6 @@ static struct irqaction bfin_timer_irq = { .flags = IRQF_DISABLED }; -/* - * The way that the Blackfin core timer works is: - * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE) - * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT) - * - * If you take the fastest clock (1ns, or 1GHz to make the math work easier) - * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter - * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need - * to use TSCALE, and program it to zero (which is pass CCLK through). - * If you feel like using it, try to keep HZ * TIMESCALE to some - * value that divides easy (like power of 2). - */ - -#define TIME_SCALE 1 - static void time_sched_init(irq_handler_t timer_routine) { diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile index 15e33ca1ce8..393081e9b68 100644 --- a/arch/blackfin/mach-common/Makefile +++ b/arch/blackfin/mach-common/Makefile @@ -6,4 +6,5 @@ obj-y := \ cache.o cacheinit.o entry.o \ interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o -obj-$(CONFIG_PM) += pm.o dpmc.o +obj-$(CONFIG_PM) += pm.o dpmc.o +obj-$(CONFIG_CPU_FREQ) += cpufreq.o diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c new file mode 100644 index 00000000000..ed81e00d20e --- /dev/null +++ b/arch/blackfin/mach-common/cpufreq.c @@ -0,0 +1,194 @@ +/* + * File: arch/blackfin/mach-common/cpufreq.c + * Based on: + * Author: + * + * Created: + * Description: Blackfin core clock scaling + * + * Modified: + * Copyright 2004-2008 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include + + +/* this is the table of CCLK frequencies, in Hz */ +/* .index is the entry in the auxillary dpm_state_table[] */ +static struct cpufreq_frequency_table bfin_freq_table[] = { + { + .frequency = CPUFREQ_TABLE_END, + .index = 0, + }, + { + .frequency = CPUFREQ_TABLE_END, + .index = 1, + }, + { + .frequency = CPUFREQ_TABLE_END, + .index = 2, + }, + { + .frequency = CPUFREQ_TABLE_END, + .index = 0, + }, +}; + +static struct bfin_dpm_state { + unsigned int csel; /* system clock divider */ + unsigned int tscale; /* change the divider on the core timer interrupt */ +} dpm_state_table[3]; + +/**************************************************************************/ + +static unsigned int bfin_getfreq(unsigned int cpu) +{ + /* The driver only support single cpu */ + if (cpu != 0) + return -1; + + return get_cclk(); +} + + +static int bfin_target(struct cpufreq_policy *policy, + unsigned int target_freq, unsigned int relation) +{ + unsigned int index, plldiv, tscale; + unsigned long flags, cclk_hz; + struct cpufreq_freqs freqs; + + if (cpufreq_frequency_table_target(policy, bfin_freq_table, + target_freq, relation, &index)) + return -EINVAL; + + cclk_hz = bfin_freq_table[index].frequency; + + freqs.old = bfin_getfreq(0); + freqs.new = cclk_hz; + freqs.cpu = 0; + + pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n", + cclk_hz, target_freq, freqs.old); + + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + local_irq_save(flags); + plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel; + tscale = dpm_state_table[index].tscale; + bfin_write_PLL_DIV(plldiv); + /* we have to adjust the core timer, because it is using cclk */ + bfin_write_TSCALE(tscale); + SSYNC(); + local_irq_restore(flags); + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return 0; +} + +static int bfin_verify_speed(struct cpufreq_policy *policy) +{ + return cpufreq_frequency_table_verify(policy, bfin_freq_table); +} + +static int __init __bfin_cpu_init(struct cpufreq_policy *policy) +{ + + unsigned long cclk, sclk, csel, min_cclk; + int index; + +#ifdef CONFIG_CYCLES_CLOCKSOURCE +/* + * Clocksource CYCLES is still CONTINUOUS but not longer MONOTONIC in case we enable + * CPU frequency scaling, since CYCLES runs off Core Clock. + */ + printk(KERN_WARNING "CPU frequency scaling not supported: Clocksource not suitable\n" + return -ENODEV; +#endif + + if (policy->cpu != 0) + return -EINVAL; + + cclk = get_cclk(); + sclk = get_sclk(); + +#if ANOMALY_05000273 + min_cclk = sclk * 2; +#else + min_cclk = sclk; +#endif + csel = ((bfin_read_PLL_DIV() & CSEL) >> 4); + + for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) { + bfin_freq_table[index].frequency = cclk >> index; + dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */ + dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1; + + pr_debug("cpufreq: freq:%d csel:%d tscale:%d\n", + bfin_freq_table[index].frequency, + dpm_state_table[index].csel, + dpm_state_table[index].tscale); + } + + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + + policy->cpuinfo.transition_latency = (bfin_read_PLL_LOCKCNT() / (sclk / 1000000)) * 1000; + /*Now ,only support one cpu */ + policy->cur = cclk; + cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu); + return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table); +} + +static struct freq_attr *bfin_freq_attr[] = { + &cpufreq_freq_attr_scaling_available_freqs, + NULL, +}; + +static struct cpufreq_driver bfin_driver = { + .verify = bfin_verify_speed, + .target = bfin_target, + .get = bfin_getfreq, + .init = __bfin_cpu_init, + .name = "bfin cpufreq", + .owner = THIS_MODULE, + .attr = bfin_freq_attr, +}; + +static int __init bfin_cpu_init(void) +{ + return cpufreq_register_driver(&bfin_driver); +} + +static void __exit bfin_cpu_exit(void) +{ + cpufreq_unregister_driver(&bfin_driver); +} + +MODULE_AUTHOR("Michael Hennerich "); +MODULE_DESCRIPTION("cpufreq driver for Blackfin"); +MODULE_LICENSE("GPL"); + +module_init(bfin_cpu_init); +module_exit(bfin_cpu_exit); diff --git a/include/asm-blackfin/time.h b/include/asm-blackfin/time.h new file mode 100644 index 00000000000..6e5859b6ea3 --- /dev/null +++ b/include/asm-blackfin/time.h @@ -0,0 +1,36 @@ +/* + * asm-blackfin/time.h: + * + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _ASM_BLACKFIN_TIME_H +#define _ASM_BLACKFIN_TIME_H + +/* + * The way that the Blackfin core timer works is: + * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE) + * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT) + * + * If you take the fastest clock (1ns, or 1GHz to make the math work easier) + * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter + * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need + * to use TSCALE, and program it to zero (which is pass CCLK through). + * If you feel like using it, try to keep HZ * TIMESCALE to some + * value that divides easy (like power of 2). + */ + +#ifndef CONFIG_CPU_FREQ +#define TIME_SCALE 1 +#else +/* + * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 . + * Whenever we change the Core Clock frequency changes we immediately + * adjust the Core Timer Presale Register. This way we don't lose time. + */ +#define TIME_SCALE 4 +#endif + +#endif -- cgit v1.2.3 From 0c11700dbfaf0aa5336bd667373ee09db245f3ea Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 25 Apr 2008 08:29:11 +0800 Subject: [Blackfin] arch: add include/boot .gitignore files Signed-off-by: Mike Frysinger Signed-off-by: Andrew Morton Signed-off-by: Bryan Wu --- arch/blackfin/boot/.gitignore | 1 + include/asm-blackfin/.gitignore | 1 + 2 files changed, 2 insertions(+) create mode 100644 arch/blackfin/boot/.gitignore create mode 100644 include/asm-blackfin/.gitignore diff --git a/arch/blackfin/boot/.gitignore b/arch/blackfin/boot/.gitignore new file mode 100644 index 00000000000..3ae03994b88 --- /dev/null +++ b/arch/blackfin/boot/.gitignore @@ -0,0 +1 @@ ++vmImage diff --git a/include/asm-blackfin/.gitignore b/include/asm-blackfin/.gitignore new file mode 100644 index 00000000000..7858564a446 --- /dev/null +++ b/include/asm-blackfin/.gitignore @@ -0,0 +1 @@ ++mach -- cgit v1.2.3 From 7d01b475ab17018756c8df27c2ee3c220fab05f8 Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Fri, 29 Feb 2008 11:31:08 +0800 Subject: Blackfin Serial Driver: Enable IR function when user application (irattach /dev/ttyBFx -s) call TIOCSETD ioctl with line discipline N_IRDA Signed-off-by: Graf Yang Signed-off-by: Bryan Wu --- drivers/serial/bfin_5xx.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c index 46bb47f37b9..4e0b8cd4d4e 100644 --- a/drivers/serial/bfin_5xx.c +++ b/drivers/serial/bfin_5xx.c @@ -900,6 +900,31 @@ bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser) return 0; } +/* + * Enable the IrDA function if tty->ldisc.num is N_IRDA. + * In other cases, disable IrDA function. + */ +static void bfin_set_ldisc(struct tty_struct *tty) +{ + int line = tty->index; + unsigned short val; + + if (line >= tty->driver->num) + return; + + switch (tty->ldisc.num) { + case N_IRDA: + val = UART_GET_GCTL(&bfin_serial_ports[line]); + val |= (IREN | RPOLC); + UART_PUT_GCTL(&bfin_serial_ports[line], val); + break; + default: + val = UART_GET_GCTL(&bfin_serial_ports[line]); + val &= ~(IREN | RPOLC); + UART_PUT_GCTL(&bfin_serial_ports[line], val); + } +} + static struct uart_ops bfin_serial_pops = { .tx_empty = bfin_serial_tx_empty, .set_mctrl = bfin_serial_set_mctrl, @@ -1261,6 +1286,7 @@ static int __init bfin_serial_init(void) ret = uart_register_driver(&bfin_serial_reg); if (ret == 0) { + bfin_serial_reg.tty_driver->set_ldisc = bfin_set_ldisc; ret = platform_driver_register(&bfin_serial_driver); if (ret) { pr_debug("uart register failed\n"); -- cgit v1.2.3 From 0c44a86d9e19021b38a7d7835f25210ef74b2612 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Apr 2008 04:56:02 +0800 Subject: Blackfin Serial Driver: punt unused lsr variable Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- drivers/serial/bfin_5xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c index 4e0b8cd4d4e..b773764ddab 100644 --- a/drivers/serial/bfin_5xx.c +++ b/drivers/serial/bfin_5xx.c @@ -749,7 +749,7 @@ bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, struct bfin_serial_port *uart = (struct bfin_serial_port *)port; unsigned long flags; unsigned int baud, quot; - unsigned short val, ier, lsr, lcr = 0; + unsigned short val, ier, lcr = 0; switch (termios->c_cflag & CSIZE) { case CS8: -- cgit v1.2.3 From 1a3a4c7130d6f39b56efc259d653f6dec4990ea3 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Wed, 23 Apr 2008 09:43:20 +0800 Subject: Blackfin Serial Driver: Fix bug - kernel hangs when accessing uart 0 on bf537 when booting u-boot and linux on uart 1 Wait only when this UART is enabled. http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3995 Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu --- drivers/serial/bfin_5xx.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c index b773764ddab..1dc9b583fa6 100644 --- a/drivers/serial/bfin_5xx.c +++ b/drivers/serial/bfin_5xx.c @@ -806,10 +806,6 @@ bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15); - do { - lsr = UART_GET_LSR(uart); - } while (!(lsr & TEMT)); - /* Disable UART */ ier = UART_GET_IER(uart); #ifdef CONFIG_BF54x -- cgit v1.2.3 From 2ade972996feb8f81d7cf2deaf8321e33770c91a Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Fri, 25 Apr 2008 02:55:49 +0800 Subject: Blackfin Serial Driver: use BFIN_UART_NR_PORTS to help SIR driver in uart port. Signed-off-by: Graf Yang Signed-off-by: Bryan Wu --- drivers/serial/bfin_5xx.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c index 1dc9b583fa6..8dab6644297 100644 --- a/drivers/serial/bfin_5xx.c +++ b/drivers/serial/bfin_5xx.c @@ -151,7 +151,8 @@ void kgdb_put_debug_char(int chr) { struct bfin_serial_port *uart; - if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS) + if (CONFIG_KGDB_UART_PORT < 0 + || CONFIG_KGDB_UART_PORT >= BFIN_UART_NR_PORTS) uart = &bfin_serial_ports[0]; else uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT]; @@ -173,7 +174,8 @@ int kgdb_get_debug_char(void) struct bfin_serial_port *uart; unsigned char chr; - if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS) + if (CONFIG_KGDB_UART_PORT < 0 + || CONFIG_KGDB_UART_PORT >= BFIN_UART_NR_PORTS) uart = &bfin_serial_ports[0]; else uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT]; @@ -1193,7 +1195,7 @@ static struct uart_driver bfin_serial_reg = { .dev_name = BFIN_SERIAL_NAME, .major = BFIN_SERIAL_MAJOR, .minor = BFIN_SERIAL_MINOR, - .nr = NR_PORTS, + .nr = BFIN_UART_NR_PORTS, .cons = BFIN_SERIAL_CONSOLE, }; -- cgit v1.2.3 From 50e2e15afaac59c955f43d78d0a1e53cf8a76370 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 25 Apr 2008 03:03:03 +0800 Subject: Blackfin Serial Driver: the uart break anomaly has been given its own number, so switch to it Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- drivers/serial/bfin_5xx.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c index 8dab6644297..47ca7b0267d 100644 --- a/drivers/serial/bfin_5xx.c +++ b/drivers/serial/bfin_5xx.c @@ -194,7 +194,7 @@ int kgdb_get_debug_char(void) } #endif -#if ANOMALY_05000230 && defined(CONFIG_SERIAL_BFIN_PIO) +#if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO) # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold) # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v)) #else @@ -239,7 +239,7 @@ static void bfin_serial_rx_chars(struct bfin_serial_port *uart) } #endif - if (ANOMALY_05000230) { + if (ANOMALY_05000363) { /* The BF533 (and BF561) family of processors have a nice anomaly * where they continuously generate characters for a "single" break. * We have to basically ignore this flood until the "next" valid @@ -251,9 +251,6 @@ static void bfin_serial_rx_chars(struct bfin_serial_port *uart) * timeout was picked as it must absolutely be larger than 1 * character time +/- some percent. So 1.5 sounds good. All other * Blackfin families operate properly. Woo. - * Note: While Anomaly 05000230 does not directly address this, - * the changes that went in for it also fixed this issue. - * That anomaly was fixed in 0.5+ silicon. I like bunnies. */ if (anomaly_start.tv_sec) { struct timeval curr; @@ -287,7 +284,7 @@ static void bfin_serial_rx_chars(struct bfin_serial_port *uart) } if (status & BI) { - if (ANOMALY_05000230) + if (ANOMALY_05000363) if (bfin_revid() < 5) do_gettimeofday(&anomaly_start); uart->port.icount.brk++; -- cgit v1.2.3 From 0a2784233785226fe5882c8af15118476f89e98e Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Fri, 25 Apr 2008 04:36:47 +0800 Subject: Blackfin Serial Driver: fix bug - use mod_timer to replace only add_timer. http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=4045 If adding timer in both timer handler and rx interrupt, a timer may be added when it is till in the pending list. Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu --- drivers/serial/bfin_5xx.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c index 47ca7b0267d..5f55534a290 100644 --- a/drivers/serial/bfin_5xx.c +++ b/drivers/serial/bfin_5xx.c @@ -506,8 +506,7 @@ void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) uart->rx_dma_buf.tail = uart->rx_dma_buf.head; } - uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; - add_timer(&(uart->rx_dma_timer)); + mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES); } static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id) @@ -550,9 +549,7 @@ static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id) clear_dma_irqstat(uart->rx_dma_channel); spin_unlock(&uart->port.lock); - del_timer(&(uart->rx_dma_timer)); - uart->rx_dma_timer.expires = jiffies; - add_timer(&(uart->rx_dma_timer)); + mod_timer(&(uart->rx_dma_timer), jiffies); return IRQ_HANDLED; } -- cgit v1.2.3 From 2dc63a84b2db23b9680646aff93917211613bf1a Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 25 Apr 2008 08:04:56 +0800 Subject: Blackfin char driver for Blackfin on-chip OTP memory (v3) initial char driver for otp memory (only read supported atm ... needs real examples/docs for write support) v2-v3: - fixup __initdata with __initconst, as we are heading for 2.6.26 Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu Acked-by: Jiri Slaby --- drivers/char/Kconfig | 28 +++++++ drivers/char/Makefile | 1 + drivers/char/bfin-otp.c | 189 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 218 insertions(+) create mode 100644 drivers/char/bfin-otp.c diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index a87b89db08e..2906ee7bd29 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -481,6 +481,34 @@ config BRIQ_PANEL It's safe to say N here. +config BFIN_OTP + tristate "Blackfin On-Chip OTP Memory Support" + depends on BLACKFIN && (BF52x || BF54x) + default y + help + If you say Y here, you will get support for a character device + interface into the One Time Programmable memory pages that are + stored on the Blackfin processor. This will not get you access + to the secure memory pages however. You will need to write your + own secure code and reader for that. + + To compile this driver as a module, choose M here: the module + will be called bfin-otp. + + If unsure, it is safe to say Y. + +config BFIN_OTP_WRITE_ENABLE + bool "Enable writing support of OTP pages" + depends on BFIN_OTP + default n + help + If you say Y here, you will enable support for writing of the + OTP pages. This is dangerous by nature as you can only program + the pages once, so only enable this option when you actually + need it so as to not inadvertently clobber data. + + If unsure, say N. + config PRINTER tristate "Parallel printer support" depends on PARPORT diff --git a/drivers/char/Makefile b/drivers/char/Makefile index 5407b761561..4c1c584e9eb 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_VIOTAPE) += viotape.o obj-$(CONFIG_HVCS) += hvcs.o obj-$(CONFIG_SGI_MBCS) += mbcs.o obj-$(CONFIG_BRIQ_PANEL) += briq_panel.o +obj-$(CONFIG_BFIN_OTP) += bfin-otp.o obj-$(CONFIG_PRINTER) += lp.o obj-$(CONFIG_TIPAR) += tipar.o diff --git a/drivers/char/bfin-otp.c b/drivers/char/bfin-otp.c new file mode 100644 index 00000000000..0a01329451e --- /dev/null +++ b/drivers/char/bfin-otp.c @@ -0,0 +1,189 @@ +/* + * Blackfin On-Chip OTP Memory Interface + * Supports BF52x/BF54x + * + * Copyright 2007-2008 Analog Devices Inc. + * + * Enter bugs at http://blackfin.uclinux.org/ + * + * Licensed under the GPL-2 or later. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define stamp(fmt, args...) pr_debug("%s:%i: " fmt "\n", __func__, __LINE__, ## args) +#define stampit() stamp("here i am") +#define pr_init(fmt, args...) ({ static const __initconst char __fmt[] = fmt; printk(__fmt, ## args); }) + +#define DRIVER_NAME "bfin-otp" +#define PFX DRIVER_NAME ": " + +static DEFINE_MUTEX(bfin_otp_lock); + +/* OTP Boot ROM functions */ +#define _BOOTROM_OTP_COMMAND 0xEF000018 +#define _BOOTROM_OTP_READ 0xEF00001A +#define _BOOTROM_OTP_WRITE 0xEF00001C + +static u32 (* const otp_command)(u32 command, u32 value) = (void *)_BOOTROM_OTP_COMMAND; +static u32 (* const otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)_BOOTROM_OTP_READ; +static u32 (* const otp_write)(u32 page, u32 flags, u64 *page_content) = (void *)_BOOTROM_OTP_WRITE; + +/* otp_command(): defines for "command" */ +#define OTP_INIT 0x00000001 +#define OTP_CLOSE 0x00000002 + +/* otp_{read,write}(): defines for "flags" */ +#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */ +#define OTP_UPPER_HALF 0x00000001 +#define OTP_NO_ECC 0x00000010 /* do not use ECC */ +#define OTP_LOCK 0x00000020 /* sets page protection bit for page */ +#define OTP_ACCESS_READ 0x00001000 +#define OTP_ACCESS_READWRITE 0x00002000 + +/* Return values for all functions */ +#define OTP_SUCCESS 0x00000000 +#define OTP_MASTER_ERROR 0x001 +#define OTP_WRITE_ERROR 0x003 +#define OTP_READ_ERROR 0x005 +#define OTP_ACC_VIO_ERROR 0x009 +#define OTP_DATA_MULT_ERROR 0x011 +#define OTP_ECC_MULT_ERROR 0x021 +#define OTP_PREV_WR_ERROR 0x041 +#define OTP_DATA_SB_WARN 0x100 +#define OTP_ECC_SB_WARN 0x200 + +/** + * bfin_otp_read - Read OTP pages + * + * All reads must be in half page chunks (half page == 64 bits). + */ +static ssize_t bfin_otp_read(struct file *file, char __user *buff, size_t count, loff_t *pos) +{ + ssize_t bytes_done; + u32 page, flags, ret; + u64 content; + + stampit(); + + if (count % sizeof(u64)) + return -EMSGSIZE; + + if (mutex_lock_interruptible(&bfin_otp_lock)) + return -ERESTARTSYS; + + bytes_done = 0; + page = *pos / (sizeof(u64) * 2); + while (bytes_done < count) { + flags = (*pos % (sizeof(u64) * 2) ? OTP_UPPER_HALF : OTP_LOWER_HALF); + stamp("processing page %i (%s)", page, (flags == OTP_UPPER_HALF ? "upper" : "lower")); + ret = otp_read(page, flags, &content); + if (ret & OTP_MASTER_ERROR) { + bytes_done = -EIO; + break; + } + if (copy_to_user(buff + bytes_done, &content, sizeof(content))) { + bytes_done = -EFAULT; + break; + } + if (flags == OTP_UPPER_HALF) + ++page; + bytes_done += sizeof(content); + *pos += sizeof(content); + } + + mutex_unlock(&bfin_otp_lock); + + return bytes_done; +} + +#ifdef CONFIG_BFIN_OTP_WRITE_ENABLE +/** + * bfin_otp_write - Write OTP pages + * + * All writes must be in half page chunks (half page == 64 bits). + */ +static ssize_t bfin_otp_write(struct file *filp, const char __user *buff, size_t count, loff_t *pos) +{ + stampit(); + + if (count % sizeof(u64)) + return -EMSGSIZE; + + if (mutex_lock_interruptible(&bfin_otp_lock)) + return -ERESTARTSYS; + + /* need otp_init() documentation before this can be implemented */ + + mutex_unlock(&bfin_otp_lock); + + return -EINVAL; +} +#else +# define bfin_otp_write NULL +#endif + +static struct file_operations bfin_otp_fops = { + .owner = THIS_MODULE, + .read = bfin_otp_read, + .write = bfin_otp_write, +}; + +static struct miscdevice bfin_otp_misc_device = { + .minor = MISC_DYNAMIC_MINOR, + .name = DRIVER_NAME, + .fops = &bfin_otp_fops, +}; + +/** + * bfin_otp_init - Initialize module + * + * Registers the device and notifier handler. Actual device + * initialization is handled by bfin_otp_open(). + */ +static int __init bfin_otp_init(void) +{ + int ret; + + stampit(); + + ret = misc_register(&bfin_otp_misc_device); + if (ret) { + pr_init(KERN_ERR PFX "unable to register a misc device\n"); + return ret; + } + + pr_init(KERN_INFO PFX "initialized\n"); + + return 0; +} + +/** + * bfin_otp_exit - Deinitialize module + * + * Unregisters the device and notifier handler. Actual device + * deinitialization is handled by bfin_otp_close(). + */ +static void __exit bfin_otp_exit(void) +{ + stampit(); + + misc_deregister(&bfin_otp_misc_device); +} + +module_init(bfin_otp_init); +module_exit(bfin_otp_exit); + +MODULE_AUTHOR("Mike Frysinger "); +MODULE_DESCRIPTION("Blackfin OTP Memory Interface"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3