From 99e6a4d22f7c7bda0cd8978333c2e85fba02f181 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 8 Oct 2008 17:30:58 +0530 Subject: OMAP3: PM: CPUidle: base driver and support for C1-C2 Basic CPUidle driver for OMAP3 with deepest sleep state supported being MPU CSWR. Signed-off-by: Rajendra Nayak Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/cpuidle34xx.c | 255 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/pm.h | 1 + arch/arm/mach-omap2/pm34xx.c | 4 +- 4 files changed, 260 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-omap2/cpuidle34xx.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 8cb16777661..1d54ad349bf 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -31,7 +31,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o -obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o +obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o endif diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c new file mode 100644 index 00000000000..858b216b63b --- /dev/null +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -0,0 +1,255 @@ +/* + * linux/arch/arm/mach-omap2/cpuidle34xx.c + * + * OMAP3 CPU IDLE Routines + * + * Copyright (C) 2008 Texas Instruments, Inc. + * Rajendra Nayak + * + * Copyright (C) 2007 Texas Instruments, Inc. + * Karthik Dasu + * + * Copyright (C) 2006 Nokia Corporation + * Tony Lindgren + * + * Copyright (C) 2005 Texas Instruments, Inc. + * Richard Woodruff + * + * Based on pm.c for omap2 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include + +#ifdef CONFIG_CPU_IDLE + +#define OMAP3_MAX_STATES 7 +#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */ +#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */ +#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */ +#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */ +#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */ +#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */ + +struct omap3_processor_cx { + u8 valid; + u8 type; + u32 sleep_latency; + u32 wakeup_latency; + u32 mpu_state; + u32 core_state; + u32 threshold; + u32 flags; +}; + +struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; +struct omap3_processor_cx current_cx_state; +struct powerdomain *mpu_pd; + +static int omap3_idle_bm_check(void) +{ + return 0; +} + +/** + * omap3_enter_idle - Programs OMAP3 to enter the specified state + * @dev: cpuidle device + * @state: The target state to be programmed + * + * Called from the CPUidle framework to program the device to the + * specified target state selected by the governor. + */ +static int omap3_enter_idle(struct cpuidle_device *dev, + struct cpuidle_state *state) +{ + struct omap3_processor_cx *cx = cpuidle_get_statedata(state); + struct timespec ts_preidle, ts_postidle, ts_idle; + + current_cx_state = *cx; + + /* Used to keep track of the total time in idle */ + getnstimeofday(&ts_preidle); + + local_irq_disable(); + local_fiq_disable(); + + /* Program MPU to target state */ + if (cx->mpu_state < PWRDM_POWER_ON) + pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state); + + /* Execute ARM wfi */ + omap_sram_idle(); + + /* Program MPU to ON */ + if (cx->mpu_state < PWRDM_POWER_ON) + pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON); + + getnstimeofday(&ts_postidle); + ts_idle = timespec_sub(ts_postidle, ts_preidle); + + local_irq_enable(); + local_fiq_enable(); + + return timespec_to_ns(&ts_idle); +} + +/** + * omap3_enter_idle_bm - Checks for any bus activity + * @dev: cpuidle device + * @state: The target state to be programmed + * + * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This + * function checks for any pending activity and then programs the + * device to the specified or a safer state. + */ +static int omap3_enter_idle_bm(struct cpuidle_device *dev, + struct cpuidle_state *state) +{ + if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { + if (dev->safe_state) + return dev->safe_state->enter(dev, dev->safe_state); + } + return omap3_enter_idle(dev, state); +} + +DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); + +/* omap3_init_power_states - Initialises the OMAP3 specific C states. + * + * Below is the desciption of each C state. + * C1 . MPU WFI + Core active + * C2 . MPU CSWR + Core active + * C3 . MPU OFF + Core active + * C4 . MPU CSWR + Core CSWR + * C5 . MPU OFF + Core CSWR + * C6 . MPU OFF + Core OFF + */ +void omap_init_power_states(void) +{ + /* C1 . MPU WFI + Core active */ + omap3_power_states[OMAP3_STATE_C1].valid = 1; + omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1; + omap3_power_states[OMAP3_STATE_C1].sleep_latency = 10; + omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 10; + omap3_power_states[OMAP3_STATE_C1].threshold = 30; + omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON; + omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON; + omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID; + + /* C2 . MPU CSWR + Core active */ + omap3_power_states[OMAP3_STATE_C2].valid = 1; + omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2; + omap3_power_states[OMAP3_STATE_C2].sleep_latency = 50; + omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 50; + omap3_power_states[OMAP3_STATE_C2].threshold = 300; + omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_RET; + omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; + omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; + + /* C3 . MPU OFF + Core active */ + omap3_power_states[OMAP3_STATE_C3].valid = 0; + omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3; + omap3_power_states[OMAP3_STATE_C3].sleep_latency = 1500; + omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 1800; + omap3_power_states[OMAP3_STATE_C3].threshold = 4000; + omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_OFF; + omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; + omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID; + + /* C4 . MPU CSWR + Core CSWR*/ + omap3_power_states[OMAP3_STATE_C4].valid = 0; + omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4; + omap3_power_states[OMAP3_STATE_C4].sleep_latency = 2500; + omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 7500; + omap3_power_states[OMAP3_STATE_C4].threshold = 12000; + omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_RET; + omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_RET; + omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID | + CPUIDLE_FLAG_CHECK_BM; + + /* C5 . MPU OFF + Core CSWR */ + omap3_power_states[OMAP3_STATE_C5].valid = 0; + omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5; + omap3_power_states[OMAP3_STATE_C5].sleep_latency = 3000; + omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 8500; + omap3_power_states[OMAP3_STATE_C5].threshold = 15000; + omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_OFF; + omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET; + omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID | + CPUIDLE_FLAG_CHECK_BM; + + /* C6 . MPU OFF + Core OFF */ + omap3_power_states[OMAP3_STATE_C6].valid = 0; + omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6; + omap3_power_states[OMAP3_STATE_C6].sleep_latency = 10000; + omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 30000; + omap3_power_states[OMAP3_STATE_C6].threshold = 300000; + omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF; + omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_OFF; + omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID | + CPUIDLE_FLAG_CHECK_BM; +} + +struct cpuidle_driver omap3_idle_driver = { + .name = "omap3_idle", + .owner = THIS_MODULE, +}; + +/** + * omap3_idle_init - Init routine for OMAP3 idle + * + * Registers the OMAP3 specific cpuidle driver with the cpuidle + * framework with the valid set of states. + */ +int omap3_idle_init(void) +{ + int i, count = 0; + struct omap3_processor_cx *cx; + struct cpuidle_state *state; + struct cpuidle_device *dev; + + mpu_pd = pwrdm_lookup("mpu_pwrdm"); + + omap_init_power_states(); + cpuidle_register_driver(&omap3_idle_driver); + + dev = &per_cpu(omap3_idle_dev, smp_processor_id()); + + for (i = 1; i < OMAP3_MAX_STATES; i++) { + cx = &omap3_power_states[i]; + state = &dev->states[count]; + + if (!cx->valid) + continue; + cpuidle_set_statedata(state, cx); + state->exit_latency = cx->sleep_latency + cx->wakeup_latency; + state->target_residency = cx->threshold; + state->flags = cx->flags; + state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ? + omap3_enter_idle_bm : omap3_enter_idle; + if (cx->type == OMAP3_STATE_C1) + dev->safe_state = state; + sprintf(state->name, "C%d", count+1); + count++; + } + + if (!count) + return -EINVAL; + dev->state_count = count; + + if (cpuidle_register_device(dev)) { + printk(KERN_ERR "%s: CPUidle register device failed\n", + __func__); + return -EIO; + } + + return 0; +} +device_initcall(omap3_idle_init); +#endif /* CONFIG_CPU_IDLE */ diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 7eb769f4ef3..2edf1ba12dc 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -18,6 +18,7 @@ extern u32 sleep_while_idle; extern void *omap3_secure_ram_storage; extern void omap3_pm_off_mode_enable(int); +extern void omap_sram_idle(void); extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 01b95eaae75..0c49db8afa9 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -318,7 +318,7 @@ static void restore_table_entry(void) restore_control_register(control_reg_value); } -static void omap_sram_idle(void) +void omap_sram_idle(void) { /* Variable to tell what needs to be saved and restored * in omap_sram_idle*/ @@ -1101,7 +1101,9 @@ static int __init omap3_pm_init(void) suspend_set_ops(&omap_pm_ops); #endif /* CONFIG_SUSPEND */ +#ifndef CONFIG_CPU_IDLE pm_idle = omap3_pm_idle; +#endif pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm); /* -- cgit v1.2.3 From 20b01669885483ba2102d5a71c662bb6ae1bed0b Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 8 Oct 2008 17:31:22 +0530 Subject: OMAP3: PM: CPUidle: support retention and off-mode C-states This patch adds support and enables state C4(MPU RET + CORE RET) and MPU OFF states (C3 and C5.) Signed-off-by: Rajendra Nayak Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/cpuidle34xx.c | 28 ++++++++++++++++------------ arch/arm/mach-omap2/pm.h | 2 ++ arch/arm/mach-omap2/pm34xx.c | 6 ++---- 3 files changed, 20 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 858b216b63b..0bf1bc359ea 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -26,6 +26,8 @@ #include #include +#include +#include #ifdef CONFIG_CPU_IDLE @@ -50,10 +52,12 @@ struct omap3_processor_cx { struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; struct omap3_processor_cx current_cx_state; -struct powerdomain *mpu_pd; +struct powerdomain *mpu_pd, *core_pd; static int omap3_idle_bm_check(void) { + if (!omap3_can_sleep()) + return 1; return 0; } @@ -79,24 +83,23 @@ static int omap3_enter_idle(struct cpuidle_device *dev, local_irq_disable(); local_fiq_disable(); - /* Program MPU to target state */ - if (cx->mpu_state < PWRDM_POWER_ON) - pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state); + set_pwrdm_state(mpu_pd, cx->mpu_state); + set_pwrdm_state(core_pd, cx->core_state); + + if (omap_irq_pending()) + goto return_sleep_time; /* Execute ARM wfi */ omap_sram_idle(); - /* Program MPU to ON */ - if (cx->mpu_state < PWRDM_POWER_ON) - pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON); - +return_sleep_time: getnstimeofday(&ts_postidle); ts_idle = timespec_sub(ts_postidle, ts_preidle); local_irq_enable(); local_fiq_enable(); - return timespec_to_ns(&ts_idle); + return (u32)timespec_to_ns(&ts_idle)/1000; } /** @@ -153,7 +156,7 @@ void omap_init_power_states(void) omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; /* C3 . MPU OFF + Core active */ - omap3_power_states[OMAP3_STATE_C3].valid = 0; + omap3_power_states[OMAP3_STATE_C3].valid = 1; omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3; omap3_power_states[OMAP3_STATE_C3].sleep_latency = 1500; omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 1800; @@ -163,7 +166,7 @@ void omap_init_power_states(void) omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID; /* C4 . MPU CSWR + Core CSWR*/ - omap3_power_states[OMAP3_STATE_C4].valid = 0; + omap3_power_states[OMAP3_STATE_C4].valid = 1; omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4; omap3_power_states[OMAP3_STATE_C4].sleep_latency = 2500; omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 7500; @@ -174,7 +177,7 @@ void omap_init_power_states(void) CPUIDLE_FLAG_CHECK_BM; /* C5 . MPU OFF + Core CSWR */ - omap3_power_states[OMAP3_STATE_C5].valid = 0; + omap3_power_states[OMAP3_STATE_C5].valid = 1; omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5; omap3_power_states[OMAP3_STATE_C5].sleep_latency = 3000; omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 8500; @@ -215,6 +218,7 @@ int omap3_idle_init(void) struct cpuidle_device *dev; mpu_pd = pwrdm_lookup("mpu_pwrdm"); + core_pd = pwrdm_lookup("core_pwrdm"); omap_init_power_states(); cpuidle_register_driver(&omap3_idle_driver); diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 2edf1ba12dc..379e35034cc 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -19,6 +19,8 @@ extern u32 sleep_while_idle; extern void *omap3_secure_ram_storage; extern void omap3_pm_off_mode_enable(int); extern void omap_sram_idle(void); +extern int omap3_can_sleep(void); +extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state); extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 0c49db8afa9..69c47edcc0f 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -76,8 +76,6 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm; static struct powerdomain *core_pwrdm, *per_pwrdm; static struct powerdomain *cam_pwrdm; -static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state); - static inline void omap3_per_save_context(void) { omap_gpio_save_context(); @@ -503,7 +501,7 @@ static int omap3_fclks_active(void) return 0; } -static int omap3_can_sleep(void) +int omap3_can_sleep(void) { if (!sleep_while_idle) return 0; @@ -517,7 +515,7 @@ static int omap3_can_sleep(void) /* This sets pwrdm state (other than mpu & core. Currently only ON & * RET are supported. Function is assuming that clkdm doesn't have * hw_sup mode enabled. */ -static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) +int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) { u32 cur_state; int sleep_switch = 0; -- cgit v1.2.3 From c98e223006ffd4c5e4cd0f75c5a10bd2b45508d5 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 28 Oct 2008 17:30:07 -0700 Subject: OMAP3: PM: CPUidle: obey enable_off_mode flag If 'enable_off_mode' is not set, force powerdomain states to RET instead of OFF. Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/cpuidle34xx.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 0bf1bc359ea..1120494064d 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -29,6 +29,8 @@ #include #include +#include "pm.h" + #ifdef CONFIG_CPU_IDLE #define OMAP3_MAX_STATES 7 @@ -74,6 +76,7 @@ static int omap3_enter_idle(struct cpuidle_device *dev, { struct omap3_processor_cx *cx = cpuidle_get_statedata(state); struct timespec ts_preidle, ts_postidle, ts_idle; + u32 mpu_state = cx->mpu_state, core_state = cx->core_state; current_cx_state = *cx; @@ -83,8 +86,15 @@ static int omap3_enter_idle(struct cpuidle_device *dev, local_irq_disable(); local_fiq_disable(); - set_pwrdm_state(mpu_pd, cx->mpu_state); - set_pwrdm_state(core_pd, cx->core_state); + if (!enable_off_mode) { + if (mpu_state < PWRDM_POWER_RET) + mpu_state = PWRDM_POWER_RET; + if (core_state < PWRDM_POWER_RET) + core_state = PWRDM_POWER_RET; + } + + set_pwrdm_state(mpu_pd, mpu_state); + set_pwrdm_state(core_pd, core_state); if (omap_irq_pending()) goto return_sleep_time; -- cgit v1.2.3 From 0f724ed92b0ad152a03b7a194815787eeeec17a4 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 28 Oct 2008 17:32:11 -0700 Subject: OMAP3: PM: CPUidle: check activity for C2, C3, correct accounting Use the activity check for states C2 and C3 as well. This is primarily to prevent deeper states during UART activity. Also, if a different state is chosen than the target state, update the 'last_state' accordingly so that CPUidle state accounting is coorect. Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/cpuidle34xx.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 1120494064d..b0bee34c510 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "pm.h" @@ -124,11 +125,15 @@ return_sleep_time: static int omap3_enter_idle_bm(struct cpuidle_device *dev, struct cpuidle_state *state) { + struct cpuidle_state *new_state = state; + if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { - if (dev->safe_state) - return dev->safe_state->enter(dev, dev->safe_state); + BUG_ON(!dev->safe_state); + new_state = dev->safe_state; } - return omap3_enter_idle(dev, state); + + dev->last_state = new_state; + return omap3_enter_idle(dev, new_state); } DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); @@ -163,7 +168,8 @@ void omap_init_power_states(void) omap3_power_states[OMAP3_STATE_C2].threshold = 300; omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_RET; omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; - omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; + omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID | + CPUIDLE_FLAG_CHECK_BM; /* C3 . MPU OFF + Core active */ omap3_power_states[OMAP3_STATE_C3].valid = 1; @@ -173,7 +179,8 @@ void omap_init_power_states(void) omap3_power_states[OMAP3_STATE_C3].threshold = 4000; omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_OFF; omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; - omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID; + omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID | + CPUIDLE_FLAG_CHECK_BM; /* C4 . MPU CSWR + Core CSWR*/ omap3_power_states[OMAP3_STATE_C4].valid = 1; @@ -198,7 +205,7 @@ void omap_init_power_states(void) CPUIDLE_FLAG_CHECK_BM; /* C6 . MPU OFF + Core OFF */ - omap3_power_states[OMAP3_STATE_C6].valid = 0; + omap3_power_states[OMAP3_STATE_C6].valid = 1; omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6; omap3_power_states[OMAP3_STATE_C6].sleep_latency = 10000; omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 30000; -- cgit v1.2.3 From 0343371e22dcfec9291193ad3e771dbce3a93670 Mon Sep 17 00:00:00 2001 From: Kalle Jokiniemi Date: Fri, 26 Sep 2008 11:04:20 +0300 Subject: OMAP3: PM: CPUidle: fix init sequencing Previously omap3_idle_init() was called in device_init, while omap_pm_init() is called at late_initcall. This causes the cpu idle driver to call omap_sram_idle before it is properly initialized. This patch fixes the issue by moving omap3_idle_init into omap3_pm_init. Signed-off-by: Kalle Jokiniemi Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/cpuidle34xx.c | 8 ++++++-- arch/arm/mach-omap2/pm.h | 1 + arch/arm/mach-omap2/pm34xx.c | 3 +-- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index b0bee34c510..ad3af11f8f6 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -227,7 +227,7 @@ struct cpuidle_driver omap3_idle_driver = { * Registers the OMAP3 specific cpuidle driver with the cpuidle * framework with the valid set of states. */ -int omap3_idle_init(void) +int __init omap3_idle_init(void) { int i, count = 0; struct omap3_processor_cx *cx; @@ -272,5 +272,9 @@ int omap3_idle_init(void) return 0; } -device_initcall(omap3_idle_init); +#else +int __init omap3_idle_init(void) +{ + return 0; +} #endif /* CONFIG_CPU_IDLE */ diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 379e35034cc..0bf345db714 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -21,6 +21,7 @@ extern void omap3_pm_off_mode_enable(int); extern void omap_sram_idle(void); extern int omap3_can_sleep(void); extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state); +extern int omap3_idle_init(void); extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 69c47edcc0f..501b00100d5 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -1099,9 +1099,8 @@ static int __init omap3_pm_init(void) suspend_set_ops(&omap_pm_ops); #endif /* CONFIG_SUSPEND */ -#ifndef CONFIG_CPU_IDLE pm_idle = omap3_pm_idle; -#endif + omap3_idle_init(); pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm); /* -- cgit v1.2.3 From 06d8f065b3bac1673825be744d22742ad72f9c2a Mon Sep 17 00:00:00 2001 From: Peter 'p2' De Schrijver Date: Fri, 13 Mar 2009 18:19:16 +0200 Subject: OMAP3: PM: CPUidle: Add new lower-latency C1 state This patch introduces a new C state which allows MPU to go to WFI but keeps the core domain active. This offers a much better wakeup latency (3us vs 10s of us for the current C1) at the cost of a higher power consumption. Signed-off-by: Peter 'p2' De Schrijver Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/cpuidle34xx.c | 125 ++++++++++++++++++++++++-------------- 1 file changed, 81 insertions(+), 44 deletions(-) diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index ad3af11f8f6..c11377ddc18 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -25,8 +25,9 @@ #include #include -#include #include +#include +#include #include #include @@ -34,13 +35,14 @@ #ifdef CONFIG_CPU_IDLE -#define OMAP3_MAX_STATES 7 +#define OMAP3_MAX_STATES 8 #define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */ -#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */ -#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */ -#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */ -#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */ -#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */ +#define OMAP3_STATE_C2 2 /* C2 - MPU WFI + Core inactive */ +#define OMAP3_STATE_C3 3 /* C3 - MPU CSWR + Core inactive */ +#define OMAP3_STATE_C4 4 /* C4 - MPU OFF + Core iactive */ +#define OMAP3_STATE_C5 5 /* C5 - MPU RET + Core RET */ +#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core RET */ +#define OMAP3_STATE_C7 7 /* C7 - MPU OFF + Core OFF */ struct omap3_processor_cx { u8 valid; @@ -64,6 +66,20 @@ static int omap3_idle_bm_check(void) return 0; } +static int _cpuidle_allow_idle(struct powerdomain *pwrdm, + struct clockdomain *clkdm) +{ + omap2_clkdm_allow_idle(clkdm); + return 0; +} + +static int _cpuidle_deny_idle(struct powerdomain *pwrdm, + struct clockdomain *clkdm) +{ + omap2_clkdm_deny_idle(clkdm); + return 0; +} + /** * omap3_enter_idle - Programs OMAP3 to enter the specified state * @dev: cpuidle device @@ -100,9 +116,19 @@ static int omap3_enter_idle(struct cpuidle_device *dev, if (omap_irq_pending()) goto return_sleep_time; + if (cx->type == OMAP3_STATE_C1) { + pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle); + pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle); + } + /* Execute ARM wfi */ omap_sram_idle(); + if (cx->type == OMAP3_STATE_C1) { + pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle); + pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle); + } + return_sleep_time: getnstimeofday(&ts_postidle); ts_idle = timespec_sub(ts_postidle, ts_preidle); @@ -141,79 +167,90 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); /* omap3_init_power_states - Initialises the OMAP3 specific C states. * * Below is the desciption of each C state. - * C1 . MPU WFI + Core active - * C2 . MPU CSWR + Core active - * C3 . MPU OFF + Core active - * C4 . MPU CSWR + Core CSWR - * C5 . MPU OFF + Core CSWR - * C6 . MPU OFF + Core OFF + * C1 . MPU WFI + Core active + * C2 . MPU WFI + Core inactive + * C3 . MPU CSWR + Core inactive + * C4 . MPU OFF + Core inactive + * C5 . MPU CSWR + Core CSWR + * C6 . MPU OFF + Core CSWR + * C7 . MPU OFF + Core OFF */ void omap_init_power_states(void) { /* C1 . MPU WFI + Core active */ omap3_power_states[OMAP3_STATE_C1].valid = 1; omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1; - omap3_power_states[OMAP3_STATE_C1].sleep_latency = 10; - omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 10; - omap3_power_states[OMAP3_STATE_C1].threshold = 30; + omap3_power_states[OMAP3_STATE_C1].sleep_latency = 2; + omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 2; + omap3_power_states[OMAP3_STATE_C1].threshold = 5; omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON; omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON; omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID; - /* C2 . MPU CSWR + Core active */ + /* C2 . MPU WFI + Core inactive */ omap3_power_states[OMAP3_STATE_C2].valid = 1; omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2; - omap3_power_states[OMAP3_STATE_C2].sleep_latency = 50; - omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 50; - omap3_power_states[OMAP3_STATE_C2].threshold = 300; - omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_RET; + omap3_power_states[OMAP3_STATE_C2].sleep_latency = 10; + omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 10; + omap3_power_states[OMAP3_STATE_C2].threshold = 30; + omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON; omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; - omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID | - CPUIDLE_FLAG_CHECK_BM; + omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; - /* C3 . MPU OFF + Core active */ + /* C3 . MPU CSWR + Core inactive */ omap3_power_states[OMAP3_STATE_C3].valid = 1; omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3; - omap3_power_states[OMAP3_STATE_C3].sleep_latency = 1500; - omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 1800; - omap3_power_states[OMAP3_STATE_C3].threshold = 4000; - omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_OFF; + omap3_power_states[OMAP3_STATE_C3].sleep_latency = 50; + omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 50; + omap3_power_states[OMAP3_STATE_C3].threshold = 300; + omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET; omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_CHECK_BM; - /* C4 . MPU CSWR + Core CSWR*/ + /* C4 . MPU OFF + Core inactive */ omap3_power_states[OMAP3_STATE_C4].valid = 1; omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4; - omap3_power_states[OMAP3_STATE_C4].sleep_latency = 2500; - omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 7500; - omap3_power_states[OMAP3_STATE_C4].threshold = 12000; - omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_RET; - omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_RET; + omap3_power_states[OMAP3_STATE_C4].sleep_latency = 1500; + omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 1800; + omap3_power_states[OMAP3_STATE_C4].threshold = 4000; + omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF; + omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON; omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_CHECK_BM; - /* C5 . MPU OFF + Core CSWR */ + /* C5 . MPU CSWR + Core CSWR*/ omap3_power_states[OMAP3_STATE_C5].valid = 1; omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5; - omap3_power_states[OMAP3_STATE_C5].sleep_latency = 3000; - omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 8500; - omap3_power_states[OMAP3_STATE_C5].threshold = 15000; - omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_OFF; + omap3_power_states[OMAP3_STATE_C5].sleep_latency = 2500; + omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 7500; + omap3_power_states[OMAP3_STATE_C5].threshold = 12000; + omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET; omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET; omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_CHECK_BM; - /* C6 . MPU OFF + Core OFF */ + /* C6 . MPU OFF + Core CSWR */ omap3_power_states[OMAP3_STATE_C6].valid = 1; omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6; - omap3_power_states[OMAP3_STATE_C6].sleep_latency = 10000; - omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 30000; - omap3_power_states[OMAP3_STATE_C6].threshold = 300000; + omap3_power_states[OMAP3_STATE_C6].sleep_latency = 3000; + omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 8500; + omap3_power_states[OMAP3_STATE_C6].threshold = 15000; omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF; - omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_OFF; + omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET; omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_CHECK_BM; + + /* C7 . MPU OFF + Core OFF */ + omap3_power_states[OMAP3_STATE_C7].valid = 1; + omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7; + omap3_power_states[OMAP3_STATE_C7].sleep_latency = 10000; + omap3_power_states[OMAP3_STATE_C7].wakeup_latency = 30000; + omap3_power_states[OMAP3_STATE_C7].threshold = 300000; + omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF; + omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF; + omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID | + CPUIDLE_FLAG_CHECK_BM; } struct cpuidle_driver omap3_idle_driver = { -- cgit v1.2.3 From 8e431edb60ef175e6aa986e8260b23cc267a13fb Mon Sep 17 00:00:00 2001 From: Sanjeev Premi Date: Fri, 13 Mar 2009 21:34:25 +0530 Subject: OMAP3: PM: CPUidle: Start C-state definitions from base 0 The current definition of C-states starts from base 1. Whereas, the cpuidle driver uses base 0. This patch eliminates need for explicit mapping (add/ sbutract) due to different base values. Signed-off-by: Sanjeev Premi Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/cpuidle34xx.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index c11377ddc18..5128b8c26b0 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -35,14 +35,14 @@ #ifdef CONFIG_CPU_IDLE -#define OMAP3_MAX_STATES 8 -#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */ -#define OMAP3_STATE_C2 2 /* C2 - MPU WFI + Core inactive */ -#define OMAP3_STATE_C3 3 /* C3 - MPU CSWR + Core inactive */ -#define OMAP3_STATE_C4 4 /* C4 - MPU OFF + Core iactive */ -#define OMAP3_STATE_C5 5 /* C5 - MPU RET + Core RET */ -#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core RET */ -#define OMAP3_STATE_C7 7 /* C7 - MPU OFF + Core OFF */ +#define OMAP3_MAX_STATES 7 +#define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */ +#define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */ +#define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */ +#define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */ +#define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */ +#define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */ +#define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */ struct omap3_processor_cx { u8 valid; @@ -279,7 +279,7 @@ int __init omap3_idle_init(void) dev = &per_cpu(omap3_idle_dev, smp_processor_id()); - for (i = 1; i < OMAP3_MAX_STATES; i++) { + for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) { cx = &omap3_power_states[i]; state = &dev->states[count]; -- cgit v1.2.3 From 7139178e9baf44dab454b757ed91a9ee149ad0f2 Mon Sep 17 00:00:00 2001 From: Jouni Hogander Date: Tue, 28 Oct 2008 10:59:05 +0200 Subject: OMAP3: PM: Use pwrdm_set_next_pwrst instead of set_pwrdm_state in idle loop It is more efficient to use pwrdm_set_next_pwrst for mpu, core and neon instead of set_pwrdm_state in idle loop. It is anyway known that those are active in idle loop. So no need to use set_pwrdm_state. Signed-off-by: Jouni Hogander Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/cpuidle34xx.c | 4 ++-- arch/arm/mach-omap2/pm34xx.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 5128b8c26b0..1d10c4aa935 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -110,8 +110,8 @@ static int omap3_enter_idle(struct cpuidle_device *dev, core_state = PWRDM_POWER_RET; } - set_pwrdm_state(mpu_pd, mpu_state); - set_pwrdm_state(core_pd, core_state); + pwrdm_set_next_pwrst(mpu_pd, mpu_state); + pwrdm_set_next_pwrst(core_pd, core_state); if (omap_irq_pending()) goto return_sleep_time; diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 501b00100d5..c77f6db8a63 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -359,7 +359,7 @@ void omap_sram_idle(void) /* NEON control */ if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) - set_pwrdm_state(neon_pwrdm, mpu_next_state); + pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); /* PER */ per_next_state = pwrdm_read_next_pwrst(per_pwrdm); -- cgit v1.2.3 From da869621c3cd93d5a8361f243b50e5d48d12bd14 Mon Sep 17 00:00:00 2001 From: Peter 'p2' De Schrijver Date: Tue, 10 Mar 2009 18:05:19 +0200 Subject: OMAP3: PM: idle: Remove fclk check for idle loop This patch removes the check to see if some functional clocks are still enabled before entering sleep. This is no longer needed when using safe state (C1) that keeps CORE active. Signed-off-by: Peter 'p2' De Schrijver Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/pm34xx.c | 42 ------------------------------------------ 1 file changed, 42 deletions(-) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index c77f6db8a63..4e87b61ca04 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -461,54 +461,12 @@ void omap_sram_idle(void) omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); } -/* - * Check if functional clocks are enabled before entering - * sleep. This function could be behind CONFIG_PM_DEBUG - * when all drivers are configuring their sysconfig registers - * properly and using their clocks properly. - */ -static int omap3_fclks_active(void) -{ - u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0, - fck_cam = 0, fck_per = 0, fck_usbhost = 0; - - fck_core1 = cm_read_mod_reg(CORE_MOD, - CM_FCLKEN1); - if (omap_rev() > OMAP3430_REV_ES1_0) { - fck_core3 = cm_read_mod_reg(CORE_MOD, - OMAP3430ES2_CM_FCLKEN3); - fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, - CM_FCLKEN); - fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, - CM_FCLKEN); - } else - fck_sgx = cm_read_mod_reg(GFX_MOD, - OMAP3430ES2_CM_FCLKEN3); - fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD, - CM_FCLKEN); - fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD, - CM_FCLKEN); - fck_per = cm_read_mod_reg(OMAP3430_PER_MOD, - CM_FCLKEN); - - /* Ignore UART clocks. These are handled by UART core (serial.c) */ - fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2); - fck_per &= ~OMAP3430_EN_UART3; - - if (fck_core1 | fck_core3 | fck_sgx | fck_dss | - fck_cam | fck_per | fck_usbhost) - return 1; - return 0; -} - int omap3_can_sleep(void) { if (!sleep_while_idle) return 0; if (!omap_uart_can_sleep()) return 0; - if (omap3_fclks_active()) - return 0; return 1; } -- cgit v1.2.3 From cf22854cee10e16e28b1dde136c37e82b7d503ee Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 20 Mar 2009 15:21:02 +0200 Subject: OMAP3: PM: Added resched check into idle calls Fixes a bug where scheduling is delayed until next wakeup due to race condition (e.g. interrupt requests scheduling just before omap_sram_idle is entered.) Signed-off-by: Tero Kristo Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/cpuidle34xx.c | 3 ++- arch/arm/mach-omap2/pm34xx.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 1d10c4aa935..a26d6a08ae3 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -22,6 +22,7 @@ * published by the Free Software Foundation. */ +#include #include #include @@ -113,7 +114,7 @@ static int omap3_enter_idle(struct cpuidle_device *dev, pwrdm_set_next_pwrst(mpu_pd, mpu_state); pwrdm_set_next_pwrst(core_pd, core_state); - if (omap_irq_pending()) + if (omap_irq_pending() || need_resched()) goto return_sleep_time; if (cx->type == OMAP3_STATE_C1) { diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 4e87b61ca04..81ed252a0f8 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -523,7 +523,7 @@ static void omap3_pm_idle(void) if (!omap3_can_sleep()) goto out; - if (omap_irq_pending()) + if (omap_irq_pending() || need_resched()) goto out; omap_sram_idle(); -- cgit v1.2.3