From a3342421363642d03b2ae3ecd27e3041de043e99 Mon Sep 17 00:00:00 2001 From: Lucas Correia Villa Real Date: Mon, 25 Apr 2005 18:36:50 +0100 Subject: [PATCH] ARM: 2640/1: Adds DRAM/BANKSIZE_MASK definitions for S3C2400 Patch from Lucas Correia Villa Real Adds DRAM refresh definitions and sets the BANKSIZE_MASK for the S3C2400 on include/asm-arm/arch-s3c2400/regs-mem.h Signed-off-by: Lucas Correia Villa Real Signed-off-by: Ben Dooks Signed-off-by: Russell King --- include/asm-arm/arch-s3c2410/regs-mem.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h index 1a1328ac0d7..a2d7d0cec04 100644 --- a/include/asm-arm/arch-s3c2410/regs-mem.h +++ b/include/asm-arm/arch-s3c2410/regs-mem.h @@ -12,6 +12,7 @@ * Changelog: * 29-Sep-2004 BJD Initial include for Linux * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA + * 04-Apr-2005 LCVR Added S3C2400 DRAM/BANKSIZE_MASK definitions * */ @@ -183,6 +184,12 @@ #define S3C2410_REFRESH_TRP_3clk (1<<20) #define S3C2410_REFRESH_TRP_4clk (2<<20) +#define S3C2400_REFRESH_DRAM_TRP_MASK (3<<20) +#define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20) +#define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20) +#define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20) +#define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20) + #define S3C2410_REFRESH_TSRC_MASK (3<<18) #define S3C2410_REFRESH_TSRC_4clk (0<<18) #define S3C2410_REFRESH_TSRC_5clk (1<<18) @@ -205,6 +212,7 @@ #define S3C2410_BANKSIZE_4M (0x5 << 0) #define S3C2410_BANKSIZE_2M (0x4 << 0) #define S3C2410_BANKSIZE_MASK (0x7 << 0) +#define S3C2400_BANKSIZE_MASK (0x4 << 0) #define S3C2410_BANKSIZE_SCLK_EN (1<<4) #define S3C2410_BANKSIZE_SCKE_EN (1<<5) #define S3C2410_BANKSIZE_BURST (1<<7) -- cgit v1.2.3 From b7ebcc108a1754a1d044b49c0acf977a7e86ae71 Mon Sep 17 00:00:00 2001 From: Lucas Correia Villa Real Date: Mon, 25 Apr 2005 18:40:31 +0100 Subject: [PATCH] ARM: 2641/1: Adds S3C2400_SPPIN_nCS to arch-s3c2410/regs-spi.h Patch from Lucas Correia Villa Real Adds a define to the SPI Card Select bit on the S3C2400 into include/asm-arm/arch-s3c2410/regs-spi.h Signed-off-by: Lucas Correia Villa Real Signed-off-by: Russell King --- include/asm-arm/arch-s3c2410/regs-spi.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/asm-arm/arch-s3c2410/regs-spi.h b/include/asm-arm/arch-s3c2410/regs-spi.h index cb502a88158..338217858c7 100644 --- a/include/asm-arm/arch-s3c2410/regs-spi.h +++ b/include/asm-arm/arch-s3c2410/regs-spi.h @@ -12,6 +12,7 @@ * 20-04-2004 KF Created file * 04-10-2004 BJD Removed VA address (no longer mapped) * tidied file for submission + * 03-04-2005 LCVR Added S3C2400_SPPIN_nCS definition */ #ifndef __ASM_ARCH_REGS_SPI_H @@ -46,6 +47,7 @@ #define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */ #define S3C2410_SPPIN_RESERVED (1<<1) +#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */ #define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */ -- cgit v1.2.3 From bd7b170201149fd82bc3212cb570a7a7386463a4 Mon Sep 17 00:00:00 2001 From: Lucas Correia Villa Real Date: Mon, 25 Apr 2005 23:12:50 +0100 Subject: [PATCH] ARM: 2644/1: Adds S3C2400 support to uncompress.h Patch from Lucas Correia Villa Real The S3C2400 doesn't have a cpuid information stored anywhere. This patch adds support to the S3C2400 at include/asm-arm/arch-s3c2400/uncompress.h by initializing the cpuid variable to the S3C2410, as they share the same routine. The GSTATUS1 pin is then used only if not compiling for the S3C2400. Signed-off-by: Lucas Correia Villa Real Signed-off-by: Ben Dooks Signed-off-by: Russell King --- include/asm-arm/arch-s3c2410/uncompress.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h index ad4252e2779..d7a4a8354fa 100644 --- a/include/asm-arm/arch-s3c2410/uncompress.h +++ b/include/asm-arm/arch-s3c2410/uncompress.h @@ -16,6 +16,7 @@ * 12-Oct-2004 BJD Take account of debug uart configuration * 15-Nov-2004 BJD Fixed uart configuration * 22-Feb-2005 BJD Added watchdog to uncompress + * 04-Apr-2005 LCVR Added support to S3C2400 (no cpuid at GSTATUS1) */ #ifndef __ASM_ARCH_UNCOMPRESS_H @@ -69,9 +70,12 @@ uart_rd(unsigned int reg) static void putc(char ch) { - int cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1); + int cpuid = S3C2410_GSTATUS1_2410; +#ifndef CONFIG_CPU_S3C2400 + cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1); cpuid &= S3C2410_GSTATUS1_IDMASK; +#endif if (ch == '\n') putc('\r'); /* expand newline to \r\n */ -- cgit v1.2.3 From eec99e345e0568767009341ac35fb5a499301499 Mon Sep 17 00:00:00 2001 From: Lucas Correia Villa Real Date: Mon, 25 Apr 2005 23:13:15 +0100 Subject: [PATCH] ARM: 2645/1: Adds IIS definitions for the S3C2400 Patch from Lucas Correia Villa Real Adds IISFCON definitions for the S3C2400 at include/asm-arm/arch-s3c2400/regs-iis.h. Signed-off-by: Lucas Correia Villa Real Signed-off-by: Ben Dooks Signed-off-by: Russell King --- include/asm-arm/arch-s3c2410/regs-iis.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h index 7ae8e1f45bc..385b07d510d 100644 --- a/include/asm-arm/arch-s3c2410/regs-iis.h +++ b/include/asm-arm/arch-s3c2410/regs-iis.h @@ -14,6 +14,7 @@ * 26-06-2003 BJD Finished off definitions for register addresses * 12-03-2004 BJD Updated include protection * 07-03-2005 BJD Added FIFO size flags and S3C2440 MPLL + * 05-04-2005 LCVR Added IISFCON definitions for the S3C2400 */ #ifndef __ASM_ARCH_REGS_IIS_H @@ -68,5 +69,14 @@ #define S3C2410_IISFCON_RXMASK (0x3f) #define S3C2410_IISFCON_RXSHIFT (0) +#define S3C2400_IISFCON_TXDMA (1<<11) +#define S3C2400_IISFCON_RXDMA (1<<10) +#define S3C2400_IISFCON_TXENABLE (1<<9) +#define S3C2400_IISFCON_RXENABLE (1<<8) +#define S3C2400_IISFCON_TXMASK (0x07 << 4) +#define S3C2400_IISFCON_TXSHIFT (4) +#define S3C2400_IISFCON_RXMASK (0x07) +#define S3C2400_IISFCON_RXSHIFT (0) + #define S3C2410_IISFIFO (0x10) #endif /* __ASM_ARCH_REGS_IIS_H */ -- cgit v1.2.3 From 41130d37a449dbff3593c8585a102d5e9173eea7 Mon Sep 17 00:00:00 2001 From: Jeff Lackey Date: Mon, 25 Apr 2005 23:38:55 +0100 Subject: [PATCH] ARM: 2650/1: PXA27x sleep - workaround Errata 39 & 50 (Patch 2667) Patch from Jeff Lackey This patch updates arch/arm/mach-pxa/sleep.S to support the PXA270 CPU. It works around Errata 39 & 50 from the Intel(R) PXA27x Processor Family Specification Update. Signed-off-by: Jeff Lackey Signed-off-by: Russell King --- arch/arm/mach-pxa/sleep.S | 56 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 50 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index 16cad2c2497..5786ccad938 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S @@ -18,6 +18,11 @@ #include +#ifdef CONFIG_PXA27x // workaround for Errata 50 +#define MDREFR_KDIV 0x200a4000 // all banks +#define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0 +#endif + .text /* @@ -28,7 +33,9 @@ ENTRY(pxa_cpu_suspend) +#ifndef CONFIG_IWMMXT mra r2, r3, acc0 +#endif stmfd sp!, {r2 - r12, lr} @ save registers on stack @ get coprocessor registers @@ -61,14 +68,23 @@ ENTRY(pxa_cpu_suspend) @ prepare value for sleep mode mov r1, #3 @ sleep mode - @ prepare to put SDRAM into self-refresh manually + @ prepare pointer to physical address 0 (virtual mapping in generic.c) + mov r2, #UNCACHED_PHYS_0 + + @ prepare SDRAM refresh settings ldr r4, =MDREFR ldr r5, [r4] + + @ enable SDRAM self-refresh mode orr r5, r5, #MDREFR_SLFRSH - @ prepare pointer to physical address 0 (virtual mapping in generic.c) - mov r2, #UNCACHED_PHYS_0 +#ifdef CONFIG_PXA27x + @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50) + ldr r6, =MDREFR_KDIV + orr r5, r5, r6 +#endif +#ifdef CONFIG_PXA25x @ Intel PXA255 Specification Update notes problems @ about suspending with PXBus operating above 133MHz @ (see Errata 31, GPIO output signals, ... unpredictable in sleep @@ -100,6 +116,18 @@ ENTRY(pxa_cpu_suspend) mov r0, #0 mcr p14, 0, r0, c6, c0, 0 orr r0, r0, #2 @ initiate change bit +#endif +#ifdef CONFIG_PXA27x + @ Intel PXA270 Specification Update notes problems sleeping + @ with core operating above 91 MHz + @ (see Errata 50, ...processor does not exit from sleep...) + + ldr r6, =CCCR + ldr r8, [r6] @ keep original value for resume + + ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value + mov r0, #0x2 @ prepare value for CLKCFG +#endif @ align execution to a cache line b 1f @@ -111,6 +139,7 @@ ENTRY(pxa_cpu_suspend) @ All needed values are now in registers. @ These last instructions should be in cache +#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) @ initiate the frequency change... str r7, [r6] mcr p14, 0, r0, c6, c0, 0 @@ -118,14 +147,27 @@ ENTRY(pxa_cpu_suspend) @ restore the original cpu speed value for resume str r8, [r6] - @ put SDRAM into self-refresh - str r5, [r4] + @ need 6 13-MHz cycles before changing PWRMODE + @ just set frequency to 91-MHz... 6*91/13 = 42 + + mov r0, #42 +10: subs r0, r0, #1 + bne 10b +#endif + + @ Do not reorder... + @ Intel PXA270 Specification Update notes problems performing + @ external accesses after SDRAM is put in self-refresh mode + @ (see Errata 39 ...hangs when entering self-refresh mode) @ force address lines low by reading at physical address 0 ldr r3, [r2] + @ put SDRAM into self-refresh + str r5, [r4] + @ enter sleep mode - mcr p14, 0, r1, c7, c0, 0 + mcr p14, 0, r1, c7, c0, 0 @ PWRMODE 20: b 20b @ loop waiting for sleep @@ -188,7 +230,9 @@ resume_after_mmu: bl cpu_xscale_proc_init #endif ldmfd sp!, {r2, r3} +#ifndef CONFIG_IWMMXT mar acc0, r2, r3 +#endif ldmfd sp!, {r4 - r12, pc} @ return to caller -- cgit v1.2.3 From 2fac6f3fec2303649e9cd572255776cb93d3f888 Mon Sep 17 00:00:00 2001 From: Deepak Saxena Date: Mon, 25 Apr 2005 23:40:05 +0100 Subject: [PATCH] ARM: 2653/1: Fix memset and memzero macro double-reference of parameters Patch from Deepak Saxena The current memset() and memzero() macros on ARM reference the incoming parameters more than once and this can cause uninted side-effects. The issue was found while debugging SCTP protocol and with the specific usage of memzero(skb_put(skb,size),size). This call would call skb_put(skb,size) twice leading to badness. The fixed version copies the incoming parameters into local variables and uses those instead. Signed-off-by: Deepak Saxena Signed-off-by: Russell King --- include/asm-arm/string.h | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/include/asm-arm/string.h b/include/asm-arm/string.h index 2a8ab162412..e50c4a39b69 100644 --- a/include/asm-arm/string.h +++ b/include/asm-arm/string.h @@ -29,15 +29,22 @@ extern void __memzero(void *ptr, __kernel_size_t n); #define memset(p,v,n) \ ({ \ - if ((n) != 0) { \ + void *__p = (p); size_t __n = n; \ + if ((__n) != 0) { \ if (__builtin_constant_p((v)) && (v) == 0) \ - __memzero((p),(n)); \ + __memzero((__p),(__n)); \ else \ - memset((p),(v),(n)); \ + memset((__p),(v),(__n)); \ } \ - (p); \ + (__p); \ }) -#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); }) +#define memzero(p,n) \ + ({ \ + void *__p = (p); size_t __n = n; \ + if ((__n) != 0) \ + __memzero((__p),(__n)); \ + (__p); \ + }) #endif -- cgit v1.2.3