From ac1ff0477cbe640a6a3652a0cd1aa78026f19246 Mon Sep 17 00:00:00 2001 From: Arthur Othieno Date: Sat, 3 Sep 2005 15:55:51 -0700 Subject: [PATCH] ppc32: Re-order cputable for 750CXe DD2.4 entry "745/755" (pvr_value:0x00083000) is a catch-all entry. Since arch/ppc/kernel/misc.S:identify_cpu() returns on first match, move this lower in the table so 750CXe DD2.4 (pvr_value:0x00083214) may be correctly enumerated. Signed-off-by: Arthur Othieno Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/cputable.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index 61382341bb0..9ab2fad5e56 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -198,20 +198,6 @@ struct cpu_spec cpu_specs[] = { .num_pmcs = 4, .cpu_setup = __setup_cpu_750 }, - { /* 745/755 */ - .pvr_mask = 0xfffff000, - .pvr_value = 0x00083000, - .cpu_name = "745/755", - .cpu_features = CPU_FTR_COMMON | - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, - .cpu_user_features = COMMON_PPC, - .icache_bsize = 32, - .dcache_bsize = 32, - .num_pmcs = 4, - .cpu_setup = __setup_cpu_750 - }, { /* 750CX (80100 and 8010x?) */ .pvr_mask = 0xfffffff0, .pvr_value = 0x00080100, @@ -254,6 +240,20 @@ struct cpu_spec cpu_specs[] = { .num_pmcs = 4, .cpu_setup = __setup_cpu_750cx }, + { /* 745/755 */ + .pvr_mask = 0xfffff000, + .pvr_value = 0x00083000, + .cpu_name = "745/755", + .cpu_features = CPU_FTR_COMMON | + CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | + CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | + CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, + .cpu_user_features = COMMON_PPC, + .icache_bsize = 32, + .dcache_bsize = 32, + .num_pmcs = 4, + .cpu_setup = __setup_cpu_750 + }, { /* 750FX rev 1.x */ .pvr_mask = 0xffffff00, .pvr_value = 0x70000100, -- cgit v1.2.3