From 548d849574847b788fe846fe21a41386063be161 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 4 Nov 2008 14:02:46 +0000 Subject: [ARM] omap: introduce clock operations structure Collect up all the common enable/disable clock operation functions into a separate operations structure. Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 8 ++++---- arch/arm/mach-omap2/clock24xx.c | 16 +++++++++++++++- arch/arm/mach-omap2/clock24xx.h | 13 +++---------- arch/arm/mach-omap2/clock34xx.c | 10 +++++++++- arch/arm/mach-omap2/clock34xx.h | 11 +++-------- 5 files changed, 34 insertions(+), 24 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index ad721e0cbf7..d3213f565d5 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -274,8 +274,8 @@ int _omap2_clk_enable(struct clk *clk) if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) return 0; - if (clk->enable) - return clk->enable(clk); + if (clk->ops && clk->ops->enable) + return clk->ops->enable(clk); if (unlikely(clk->enable_reg == NULL)) { printk(KERN_ERR "clock.c: Enable for %s without enable code\n", @@ -304,8 +304,8 @@ void _omap2_clk_disable(struct clk *clk) if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) return; - if (clk->disable) { - clk->disable(clk); + if (clk->ops && clk->ops->disable) { + clk->ops->disable(clk); return; } diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index d382eb0184a..866a618c4d8 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -34,12 +34,16 @@ #include "memory.h" #include "clock.h" -#include "clock24xx.h" #include "prm.h" #include "prm-regbits-24xx.h" #include "cm.h" #include "cm-regbits-24xx.h" +static const struct clkops clkops_oscck; +static const struct clkops clkops_fixed; + +#include "clock24xx.h" + /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ #define EN_APLL_STOPPED 0 #define EN_APLL_LOCKED 3 @@ -96,6 +100,11 @@ static void omap2_disable_osc_ck(struct clk *clk) OMAP24XX_PRCM_CLKSRC_CTRL); } +static const struct clkops clkops_oscck = { + .enable = &omap2_enable_osc_ck, + .disable = &omap2_disable_osc_ck, +}; + #ifdef OLD_CK /* Recalculate SYST_CLK */ static void omap2_sys_clk_recalc(struct clk * clk) @@ -149,6 +158,11 @@ static void omap2_clk_fixed_disable(struct clk *clk) cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); } +static const struct clkops clkops_fixed = { + .enable = &omap2_clk_fixed_enable, + .disable = &omap2_clk_fixed_disable, +}; + /* * Uses the current prcm set to tell if a rate is valid. * You can go slower, but not faster within a given rate set. diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 8c57a2e180f..2aa0b5e6560 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -31,10 +31,6 @@ static void omap2_sys_clk_recalc(struct clk *clk); static void omap2_osc_clk_recalc(struct clk *clk); static void omap2_sys_clk_recalc(struct clk *clk); static void omap2_dpllcore_recalc(struct clk *clk); -static int omap2_clk_fixed_enable(struct clk *clk); -static void omap2_clk_fixed_disable(struct clk *clk); -static int omap2_enable_osc_ck(struct clk *clk); -static void omap2_disable_osc_ck(struct clk *clk); static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. @@ -633,11 +629,10 @@ static struct clk func_32k_ck = { /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ .name = "osc_ck", + .ops = &clkops_oscck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", - .enable = &omap2_enable_osc_ck, - .disable = &omap2_disable_osc_ck, .recalc = &omap2_osc_clk_recalc, }; @@ -695,6 +690,7 @@ static struct clk dpll_ck = { static struct clk apll96_ck = { .name = "apll96_ck", + .ops = &clkops_fixed, .parent = &sys_ck, .rate = 96000000, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | @@ -702,13 +698,12 @@ static struct clk apll96_ck = { .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, - .enable = &omap2_clk_fixed_enable, - .disable = &omap2_clk_fixed_disable, .recalc = &propagate_rate, }; static struct clk apll54_ck = { .name = "apll54_ck", + .ops = &clkops_fixed, .parent = &sys_ck, .rate = 54000000, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | @@ -716,8 +711,6 @@ static struct clk apll54_ck = { .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, - .enable = &omap2_clk_fixed_enable, - .disable = &omap2_clk_fixed_disable, .recalc = &propagate_rate, }; diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 31bb7010bd4..2f2d43db2dd 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -33,12 +33,15 @@ #include "memory.h" #include "clock.h" -#include "clock34xx.h" #include "prm.h" #include "prm-regbits-34xx.h" #include "cm.h" #include "cm-regbits-34xx.h" +static const struct clkops clkops_noncore_dpll_ops; + +#include "clock34xx.h" + /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ #define DPLL_AUTOIDLE_DISABLE 0x0 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 @@ -270,6 +273,11 @@ static void omap3_noncore_dpll_disable(struct clk *clk) _omap3_noncore_dpll_stop(clk); } +static const struct clkops clkops_noncore_dpll_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, +}; + /** * omap3_dpll_autoidle_read - read a DPLL's autoidle bits * @clk: struct clk * of the DPLL to read diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index a826094d89b..8b188fb9bea 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -32,8 +32,6 @@ static void omap3_clkoutx2_recalc(struct clk *clk); static void omap3_dpll_allow_idle(struct clk *clk); static void omap3_dpll_deny_idle(struct clk *clk); static u32 omap3_dpll_autoidle_read(struct clk *clk); -static int omap3_noncore_dpll_enable(struct clk *clk); -static void omap3_noncore_dpll_disable(struct clk *clk); /* Maximum DPLL multiplier, divider values for OMAP3 */ #define OMAP3_MAX_DPLL_MULT 2048 @@ -347,11 +345,10 @@ static struct dpll_data dpll2_dd = { static struct clk dpll2_ck = { .name = "dpll2_ck", + .ops = &clkops_noncore_dpll_ops, .parent = &sys_ck, .dpll_data = &dpll2_dd, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, - .enable = &omap3_noncore_dpll_enable, - .disable = &omap3_noncore_dpll_disable, .round_rate = &omap2_dpll_round_rate, .recalc = &omap3_dpll_recalc, }; @@ -582,11 +579,10 @@ static struct dpll_data dpll4_dd = { static struct clk dpll4_ck = { .name = "dpll4_ck", + .ops = &clkops_noncore_dpll_ops, .parent = &sys_ck, .dpll_data = &dpll4_dd, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, - .enable = &omap3_noncore_dpll_enable, - .disable = &omap3_noncore_dpll_disable, .round_rate = &omap2_dpll_round_rate, .recalc = &omap3_dpll_recalc, }; @@ -884,11 +880,10 @@ static struct dpll_data dpll5_dd = { static struct clk dpll5_ck = { .name = "dpll5_ck", + .ops = &clkops_noncore_dpll_ops, .parent = &sys_ck, .dpll_data = &dpll5_dd, .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, - .enable = &omap3_noncore_dpll_enable, - .disable = &omap3_noncore_dpll_disable, .round_rate = &omap2_dpll_round_rate, .recalc = &omap3_dpll_recalc, }; -- cgit v1.2.3