From 32c1ad9ab2ae4171d8f3dd0c70a611f799ad6775 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 18 Jun 2009 12:40:48 +0200 Subject: pcm037: add MT9T031 camera support Add support for the MT9T031 CMOS camera sensor from Aptina to the PCM037 board. Also add two I2C iomux pin definitions, needed for pcm037. Also remove now unneeded #ifdef CONFIG_I2C_IMX. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx3.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index 27f8d1b2bc6..2eb182f7387 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -602,6 +602,8 @@ enum iomux_pins { #define MX31_PIN_I2C_DAT__SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) #define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2) #define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_CSPI2_SS2__I2C3_SDA IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI2_SCLK__I2C3_SCL IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_ALT1) #define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC) -- cgit v1.2.3 From 8db5d1a64d36d0750b88c6c13feeaf0e00be2eb4 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 25 May 2009 12:21:38 +0200 Subject: MXC: pass base/irq to mxc_timer_init Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/common.h | 2 +- arch/arm/plat-mxc/time.c | 21 ++------------------- 2 files changed, 3 insertions(+), 20 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 02c3cd004db..1c48aefe4b6 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -20,7 +20,7 @@ extern void mx27_map_io(void); extern void mx31_map_io(void); extern void mx35_map_io(void); extern void mxc_init_irq(void); -extern void mxc_timer_init(struct clk *timer_clk); +extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); extern int mx21_clocks_init(unsigned long lref, unsigned long fref); extern int mx27_clocks_init(unsigned long fref); diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index 88fb3a57e02..7e71bb6270e 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c @@ -281,30 +281,13 @@ static int __init mxc_clockevent_init(struct clk *timer_clk) return 0; } -void __init mxc_timer_init(struct clk *timer_clk) +void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq) { uint32_t tctl_val; - int irq; clk_enable(timer_clk); - if (cpu_is_mx1()) { -#ifdef CONFIG_ARCH_MX1 - timer_base = IO_ADDRESS(TIM1_BASE_ADDR); - irq = TIM1_INT; -#endif - } else if (cpu_is_mx2()) { -#ifdef CONFIG_ARCH_MX2 - timer_base = IO_ADDRESS(GPT1_BASE_ADDR); - irq = MXC_INT_GPT1; -#endif - } else if (cpu_is_mx3()) { -#ifdef CONFIG_ARCH_MX3 - timer_base = IO_ADDRESS(GPT1_BASE_ADDR); - irq = MXC_INT_GPT; -#endif - } else - BUG(); + timer_base = base; /* * Initialise to a known state (all timers off, and timing reset) -- cgit v1.2.3 From be124c94279edf4306798100f120c386947d8724 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 4 Jun 2009 12:19:02 +0200 Subject: system.c: runtime base address Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/common.h | 1 + arch/arm/plat-mxc/system.c | 22 +++++++++++++--------- 2 files changed, 14 insertions(+), 9 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 1c48aefe4b6..1dc31d6dd43 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -29,5 +29,6 @@ extern int mx35_clocks_init(void); extern int mxc_register_gpios(void); extern int mxc_register_device(struct platform_device *pdev, void *data); extern void mxc_set_cpu_type(unsigned int type); +extern void mxc_arch_reset_init(void __iomem *); #endif diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 79c37577c91..15e30532f4a 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -30,29 +30,28 @@ #include #include -#ifdef CONFIG_ARCH_MX1 -#define WDOG_WCR_REG IO_ADDRESS(WDT_BASE_ADDR) -#define WDOG_WCR_ENABLE (1 << 0) -#else -#define WDOG_WCR_REG IO_ADDRESS(WDOG_BASE_ADDR) -#define WDOG_WCR_ENABLE (1 << 2) -#endif +static void __iomem *wdog_base; /* * Reset the system. It is called by machine_restart(). */ void arch_reset(char mode, const char *cmd) { - if (!cpu_is_mx1()) { + unsigned int wcr_enable; + + if (cpu_is_mx1()) { + wcr_enable = (1 << 0); + } else { struct clk *clk; clk = clk_get_sys("imx-wdt.0", NULL); if (!IS_ERR(clk)) clk_enable(clk); + wcr_enable = (1 << 2); } /* Assert SRS signal */ - __raw_writew(WDOG_WCR_ENABLE, WDOG_WCR_REG); + __raw_writew(wcr_enable, wdog_base); /* wait for reset to assert... */ mdelay(500); @@ -65,3 +64,8 @@ void arch_reset(char mode, const char *cmd) /* we'll take a jump through zero as a poor second */ cpu_reset(0); } + +void mxc_arch_reset_init(void __iomem *base) +{ + wdog_base = base; +} -- cgit v1.2.3 From abae61305684fffb0f1d779a1a678855ec5e8cfc Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 25 May 2009 17:22:18 +0200 Subject: mxc: remove ARCH_NR_GPIOS Use the default value of 256 which is enough for all i.MX SoCs. Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/mx27.h | 3 --- arch/arm/plat-mxc/include/mach/mx3x.h | 3 --- 2 files changed, 6 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 6e93f2c0b7b..063ac352465 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -120,7 +120,4 @@ extern int mx27_revision(void); /* Mandatory defines used globally */ -/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */ -#define ARCH_NR_GPIOS (192 + 16) - #endif /* __ASM_ARCH_MXC_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index b559a4bb576..44ca1b700f0 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -279,9 +279,6 @@ /* Mandatory defines used globally */ -/* this CPU supports up to 96 GPIOs */ -#define ARCH_NR_GPIOS 96 - #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) extern unsigned int system_rev; -- cgit v1.2.3 From d30c74a02f7652e784c32a10736a3c88db98820c Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 4 Jun 2009 13:29:57 +0200 Subject: MXC uncompress macros: determine uart base by machine type Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/uncompress.h | 60 ++++++++++++++++++++--------- 1 file changed, 42 insertions(+), 18 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index de6fe036598..98c8a60214d 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -26,8 +26,11 @@ #define __MXC_BOOT_UNCOMPRESS #include +#include -#define UART(x) (*(volatile unsigned long *)(serial_port + (x))) +static unsigned long uart_base; + +#define UART(x) (*(volatile unsigned long *)(uart_base + (x))) #define USR2 0x98 #define USR2_TXFE (1<<14) @@ -46,19 +49,10 @@ static void putc(int ch) { - static unsigned long serial_port = 0; - - if (unlikely(serial_port == 0)) { - do { - serial_port = UART1_BASE_ADDR; - if (UART(UCR1) & UCR1_UARTEN) - break; - serial_port = UART2_BASE_ADDR; - if (UART(UCR1) & UCR1_UARTEN) - break; - return; - } while (0); - } + if (!uart_base) + return; + if (!(UART(UCR1) & UCR1_UARTEN)) + return; while (!(UART(USR2) & USR2_TXFE)) barrier(); @@ -68,11 +62,41 @@ static void putc(int ch) #define flush() do { } while (0) -/* - * nothing to do - */ -#define arch_decomp_setup() +#define MX1_UART1_BASE_ADDR 0x00206000 +#define MX2X_UART1_BASE_ADDR 0x1000a000 +#define MX3X_UART1_BASE_ADDR 0x43F90000 + +static __inline__ void __arch_decomp_setup(unsigned long arch_id) +{ + switch (arch_id) { + case MACH_TYPE_MX1ADS: + case MACH_TYPE_SCB9328: + uart_base = MX1_UART1_BASE_ADDR; + break; + case MACH_TYPE_IMX27LITE: + case MACH_TYPE_MX27_3DS: + case MACH_TYPE_MX27ADS: + case MACH_TYPE_PCM038: + case MACH_TYPE_MX21ADS: + uart_base = MX2X_UART1_BASE_ADDR; + break; + case MACH_TYPE_MX31LITE: + case MACH_TYPE_ARMADILLO5X0: + case MACH_TYPE_MX31MOBOARD: + case MACH_TYPE_QONG: + case MACH_TYPE_MX31_3DS: + case MACH_TYPE_PCM037: + case MACH_TYPE_MX31ADS: + case MACH_TYPE_MX35_3DS: + case MACH_TYPE_PCM043: + uart_base = MX3X_UART1_BASE_ADDR; + break; + default: + break; + } +} +#define arch_decomp_setup() __arch_decomp_setup(arch_id) #define arch_decomp_wdog() #endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */ -- cgit v1.2.3 From ccc1a6f8eebf0eb8a5bee16293d1dc9b5eab1be3 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 4 Jun 2009 13:45:37 +0200 Subject: MXC: remove board specific setup of MXC_LL_UART_[PV]ADDR Signed-off-by: Sascha Hauer --- .../arm/plat-mxc/include/mach/board-armadillo5x0.h | 7 --- arch/arm/plat-mxc/include/mach/board-mx21ads.h | 6 --- arch/arm/plat-mxc/include/mach/board-mx27ads.h | 6 --- arch/arm/plat-mxc/include/mach/board-mx27lite.h | 5 -- arch/arm/plat-mxc/include/mach/board-mx27pdk.h | 5 -- arch/arm/plat-mxc/include/mach/board-mx31ads.h | 5 -- arch/arm/plat-mxc/include/mach/board-mx31lilly.h | 5 -- arch/arm/plat-mxc/include/mach/board-mx31lite.h | 3 -- arch/arm/plat-mxc/include/mach/board-mx31moboard.h | 5 -- arch/arm/plat-mxc/include/mach/board-mx31pdk.h | 5 -- arch/arm/plat-mxc/include/mach/board-mx35pdk.h | 5 -- arch/arm/plat-mxc/include/mach/board-pcm037.h | 5 -- arch/arm/plat-mxc/include/mach/board-pcm038.h | 5 -- arch/arm/plat-mxc/include/mach/board-pcm043.h | 5 -- arch/arm/plat-mxc/include/mach/board-qong.h | 5 -- arch/arm/plat-mxc/include/mach/debug-macro.S | 59 ++++++++-------------- arch/arm/plat-mxc/include/mach/mx1.h | 4 -- 17 files changed, 21 insertions(+), 119 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h index 8769e910e55..0376c133c9f 100644 --- a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h +++ b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h @@ -12,11 +12,4 @@ #ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__ #define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__ -#include - -/* mandatory for CONFIG_DEBUG_LL */ - -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) - #endif diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h index 06701df74c4..0cf4fa29510 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx21ads.h +++ b/arch/arm/plat-mxc/include/mach/board-mx21ads.h @@ -14,12 +14,6 @@ #ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__ #define __ASM_ARCH_MXC_BOARD_MX21ADS_H__ -/* - * MXC UART EVB board level configurations - */ -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) - /* * Memory-mapped I/O on MX21ADS base board */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h index d42f4e6116f..7776d230327 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h +++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h @@ -25,12 +25,6 @@ #define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \ MXC_MAX_VIRTUAL_INTS) -/* - * MXC UART EVB board level configurations - */ -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) - /* * @name Memory Size parameters */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h index a870f8ea244..ea87551d273 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx27lite.h +++ b/arch/arm/plat-mxc/include/mach/board-mx27lite.h @@ -11,9 +11,4 @@ #ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__ #define __ASM_ARCH_MXC_BOARD_MX27LITE_H__ -/* mandatory for CONFIG_DEBUG_LL */ - -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) - #endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h index 552b55d714d..fec1bcfa916 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h +++ b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h @@ -11,9 +11,4 @@ #ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__ #define __ASM_ARCH_MXC_BOARD_MX27PDK_H__ -/* mandatory for CONFIG_DEBUG_LL */ - -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) - #endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h index 06e6895f7f6..2cbfa35e82f 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h @@ -114,9 +114,4 @@ #define MXC_MAX_EXP_IO_LINES 16 -/* mandatory for CONFIG_DEBUG_LL */ - -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) - #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h index 78cf31e22e4..eb5a5024622 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h @@ -22,11 +22,6 @@ #ifndef __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ #define __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ -/* mandatory for CONFIG_LL_DEBUG */ - -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000) - #ifndef __ASSEMBLY__ enum mx31lilly_boards { diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h index 52fbdf2d6f2..8e64325d690 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h @@ -11,8 +11,5 @@ #ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__ #define __ASM_ARCH_MXC_BOARD_MX31LITE_H__ -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) - #endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h index 303fd2434a2..d5be6b5a6ac 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h @@ -19,11 +19,6 @@ #ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ #define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ -/* mandatory for CONFIG_DEBUG_LL */ - -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000) - #ifndef __ASSEMBLY__ enum mx31moboard_boards { diff --git a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h index 519bab3eb28..2bbd6ed17f5 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h @@ -11,11 +11,6 @@ #ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__ #define __ASM_ARCH_MXC_BOARD_MX31PDK_H__ -/* mandatory for CONFIG_DEBUG_LL */ - -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) - /* Definitions for components on the Debug board */ /* Base address of CPLD controller on the Debug board */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h index 1111037d6d9..383f1c04df0 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h +++ b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h @@ -19,9 +19,4 @@ #ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__ #define __ASM_ARCH_MXC_BOARD_MX35PDK_H__ -/* mandatory for CONFIG_DEBUG_LL */ - -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) - #endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/plat-mxc/include/mach/board-pcm037.h index f0a1fa1938a..13411709b13 100644 --- a/arch/arm/plat-mxc/include/mach/board-pcm037.h +++ b/arch/arm/plat-mxc/include/mach/board-pcm037.h @@ -19,9 +19,4 @@ #ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__ #define __ASM_ARCH_MXC_BOARD_PCM037_H__ -/* mandatory for CONFIG_DEBUG_LL */ - -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) - #endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h index 4fcd7499e09..410f9786ed2 100644 --- a/arch/arm/plat-mxc/include/mach/board-pcm038.h +++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h @@ -19,11 +19,6 @@ #ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__ #define __ASM_ARCH_MXC_BOARD_PCM038_H__ -/* mandatory for CONFIG_DEBUG_LL */ - -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000) - #ifndef __ASSEMBLY__ /* * This CPU module needs a baseboard to work. After basic initializing diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/plat-mxc/include/mach/board-pcm043.h index 15fbdf16abc..1ac4e1682e5 100644 --- a/arch/arm/plat-mxc/include/mach/board-pcm043.h +++ b/arch/arm/plat-mxc/include/mach/board-pcm043.h @@ -19,9 +19,4 @@ #ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__ #define __ASM_ARCH_MXC_BOARD_PCM043_H__ -/* mandatory for CONFIG_LL_DEBUG */ - -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) - #endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h index 04033ec637d..6d88c7af4b2 100644 --- a/arch/arm/plat-mxc/include/mach/board-qong.h +++ b/arch/arm/plat-mxc/include/mach/board-qong.h @@ -11,11 +11,6 @@ #ifndef __ASM_ARCH_MXC_BOARD_QONG_H__ #define __ASM_ARCH_MXC_BOARD_QONG_H__ -/* mandatory for CONFIG_DEBUG_LL */ - -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) - /* NOR FLASH */ #define QONG_NOR_SIZE (128*1024*1024) diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index bbc5f6753cf..4f85acd74af 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -11,52 +11,35 @@ * */ -#include - -#ifdef CONFIG_MACH_MX31ADS -#include -#endif -#ifdef CONFIG_MACH_PCM037 -#include -#endif -#ifdef CONFIG_MACH_MX31LITE -#include -#endif -#ifdef CONFIG_MACH_MX27ADS -#include -#endif -#ifdef CONFIG_MACH_MX21ADS -#include -#endif -#ifdef CONFIG_MACH_PCM038 -#include +#ifdef CONFIG_ARCH_MX1 +#include +#define UART_PADDR UART1_BASE_ADDR +#define UART_VADDR IO_ADDRESS(UART1_BASE_ADDR) #endif -#ifdef CONFIG_MACH_MX31_3DS -#include -#endif -#ifdef CONFIG_MACH_QONG -#include -#endif -#ifdef CONFIG_MACH_PCM043 -#include -#endif -#ifdef CONFIG_MACH_MX27_3DS -#include + +#ifdef CONFIG_ARCH_MX2 +#ifdef UART_PADDR +#error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#ifdef CONFIG_MACH_ARMADILLO5X0 -#include +#include +#define UART_PADDR UART1_BASE_ADDR +#define UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) #endif -#ifdef CONFIG_MACH_MX35_3DS -#include + +#ifdef CONFIG_ARCH_MX3 +#ifdef UART_PADDR +#error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#ifdef CONFIG_MACH_MX27LITE -#include +#include +#define UART_PADDR UART1_BASE_ADDR +#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) #endif + .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - ldreq \rx, =MXC_LL_UART_PADDR @ physical - ldrne \rx, =MXC_LL_UART_VADDR @ virtual + ldreq \rx, =UART_PADDR @ physical + ldrne \rx, =UART_VADDR @ virtual .endm .macro senduart,rd,rx diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 1000bf330bc..786836965cf 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -179,8 +179,4 @@ #define DMA_REQ_UART1_T 30 #define DMA_REQ_UART1_R 31 -/* mandatory for CONFIG_DEBUG_LL */ -#define MXC_LL_UART_PADDR UART1_BASE_ADDR -#define MXC_LL_UART_VADDR IO_ADDRESS(UART1_BASE_ADDR) - #endif /* __ASM_ARCH_MXC_MX1_H__ */ -- cgit v1.2.3 From 12308dfe3776ff5741fc675f2a352165e1628098 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 27 May 2009 18:33:58 +0200 Subject: mxc: remove do not include directly Everyone should be free to include the files he actually needs. Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/mx1.h | 4 ---- arch/arm/plat-mxc/include/mach/mx21.h | 5 ----- arch/arm/plat-mxc/include/mach/mx27.h | 4 ---- arch/arm/plat-mxc/include/mach/mx2x.h | 4 ---- arch/arm/plat-mxc/include/mach/mx3x.h | 4 ---- 5 files changed, 21 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 786836965cf..ee60d64728c 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -12,10 +12,6 @@ #ifndef __ASM_ARCH_MXC_MX1_H__ #define __ASM_ARCH_MXC_MX1_H__ -#ifndef __ASM_ARCH_MXC_HARDWARE_H__ -#error "Do not include directly." -#endif - #include /* diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 8b070a041a9..21112c695ec 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -25,11 +25,6 @@ #ifndef __ASM_ARCH_MXC_MX21_H__ #define __ASM_ARCH_MXC_MX21_H__ -#ifndef __ASM_ARCH_MXC_HARDWARE_H__ -#error "Do not include directly." -#endif - - /* Memory regions and CS */ #define SDRAM_BASE_ADDR 0xC0000000 #define CSD1_BASE_ADDR 0xC4000000 diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 063ac352465..dc3ad9aa952 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -24,10 +24,6 @@ #ifndef __ASM_ARCH_MXC_MX27_H__ #define __ASM_ARCH_MXC_MX27_H__ -#ifndef __ASM_ARCH_MXC_HARDWARE_H__ -#error "Do not include directly." -#endif - /* IRAM */ #define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index fc40d3ab8c5..5982ae5a00d 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -23,10 +23,6 @@ #ifndef __ASM_ARCH_MXC_MX2x_H__ #define __ASM_ARCH_MXC_MX2x_H__ -#ifndef __ASM_ARCH_MXC_HARDWARE_H__ -#error "Do not include directly." -#endif - /* The following addresses are common between i.MX21 and i.MX27 */ /* Register offests */ diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 44ca1b700f0..16f68e8f4cf 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -11,10 +11,6 @@ #ifndef __ASM_ARCH_MXC_MX31_H__ #define __ASM_ARCH_MXC_MX31_H__ -#ifndef __ASM_ARCH_MXC_HARDWARE_H__ -#error "Do not include directly." -#endif - /* * MX31 memory map: * -- cgit v1.2.3 From c5aa0ad0c557c63dcaf8c8d75a3dd4c5e90724b3 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 25 May 2009 17:36:19 +0200 Subject: mxc: turn to soc specific init_irq functions Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/common.h | 7 ++++++- arch/arm/plat-mxc/irq.c | 4 ++-- 2 files changed, 8 insertions(+), 3 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 1dc31d6dd43..cd8f215c1ad 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -19,7 +19,12 @@ extern void mx21_map_io(void); extern void mx27_map_io(void); extern void mx31_map_io(void); extern void mx35_map_io(void); -extern void mxc_init_irq(void); +extern void mxc_init_irq(void __iomem *); +extern void mx1_init_irq(void); +extern void mx21_init_irq(void); +extern void mx27_init_irq(void); +extern void mx31_init_irq(void); +extern void mx35_init_irq(void); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); extern int mx21_clocks_init(unsigned long lref, unsigned long fref); diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c index 8aee76304f8..618a8b24ed1 100644 --- a/arch/arm/plat-mxc/irq.c +++ b/arch/arm/plat-mxc/irq.c @@ -113,11 +113,11 @@ static struct irq_chip mxc_avic_chip = { * interrupts. It registers the interrupt enable and disable functions * to the kernel for each interrupt source. */ -void __init mxc_init_irq(void) +void __init mxc_init_irq(void __iomem *irqbase) { int i; - avic_base = IO_ADDRESS(AVIC_BASE_ADDR); + avic_base = irqbase; /* put the AVIC into the reset value with * all interrupts disabled -- cgit v1.2.3 From 997d74b18ae1d0d8f4c4469a5d1ce8d73ca8402c Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 4 Jun 2009 10:32:08 +0200 Subject: MXC iomux-v3: Fix defines for PAD_CTL registers The old defines leaked in from an old version of the patch. Change the defines to match the register layout of the iomuxer. Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-v3.h | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index 7cd84547658..cd06df9370c 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -68,28 +68,24 @@ struct pad_desc { /* * Use to set PAD control */ -#define PAD_CTL_DRIVE_VOLTAGE_3_3_V 0 -#define PAD_CTL_DRIVE_VOLTAGE_1_8_V 1 -#define PAD_CTL_NO_HYSTERESIS 0 -#define PAD_CTL_HYSTERESIS 1 +#define PAD_CTL_DVS (1 << 13) +#define PAD_CTL_HYS (1 << 8) -#define PAD_CTL_PULL_DISABLED 0x0 -#define PAD_CTL_PULL_KEEPER 0xa -#define PAD_CTL_PULL_DOWN_100K 0xc -#define PAD_CTL_PULL_UP_47K 0xd -#define PAD_CTL_PULL_UP_100K 0xe -#define PAD_CTL_PULL_UP_22K 0xf +#define PAD_CTL_PKE (1 << 7) +#define PAD_CTL_PUE (1 << 6) +#define PAD_CTL_PUS_100K_DOWN (0 << 4) +#define PAD_CTL_PUS_47K_UP (1 << 4) +#define PAD_CTL_PUS_100K_UP (2 << 4) +#define PAD_CTL_PUS_22K_UP (3 << 4) -#define PAD_CTL_OUTPUT_CMOS 0 -#define PAD_CTL_OUTPUT_OPEN_DRAIN 1 +#define PAD_CTL_ODE (1 << 3) -#define PAD_CTL_DRIVE_STRENGTH_NORM 0 -#define PAD_CTL_DRIVE_STRENGTH_HIGH 1 -#define PAD_CTL_DRIVE_STRENGTH_MAX 2 +#define PAD_CTL_DSE_STANDARD (0 << 1) +#define PAD_CTL_DSE_HIGH (1 << 1) +#define PAD_CTL_DSE_MAX (2 << 1) -#define PAD_CTL_SLEW_RATE_SLOW 0 -#define PAD_CTL_SLEW_RATE_FAST 1 +#define PAD_CTL_SRE_FAST (1 << 0) /* * setups a single pad: -- cgit v1.2.3 From f497d0153a6b53b4cfd004de5f10b14bf630d852 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Mar 2009 11:29:31 +0100 Subject: imxfb: calculate bpix value from bits_per_pixel Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/imxfb.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h index 9f0101157ec..66259f6158e 100644 --- a/arch/arm/plat-mxc/include/mach/imxfb.h +++ b/arch/arm/plat-mxc/include/mach/imxfb.h @@ -13,7 +13,8 @@ #define PCR_BPIX_4 (2 << 25) #define PCR_BPIX_8 (3 << 25) #define PCR_BPIX_12 (4 << 25) -#define PCR_BPIX_16 (4 << 25) +#define PCR_BPIX_16 (5 << 25) +#define PCR_BPIX_18 (6 << 25) #define PCR_PIXPOL (1 << 24) #define PCR_FLMPOL (1 << 23) #define PCR_LPPOL (1 << 22) -- cgit v1.2.3 From 343684ffb793a3c371579b7bbc16724713ee5ac7 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 19 Mar 2009 08:25:41 +0100 Subject: imxfb: Add support for multiple displays Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/imxfb.h | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h index 66259f6158e..5263506b7dd 100644 --- a/arch/arm/plat-mxc/include/mach/imxfb.h +++ b/arch/arm/plat-mxc/include/mach/imxfb.h @@ -2,6 +2,8 @@ * This structure describes the machine which we are running on. */ +#include + #define PCR_TFT (1 << 31) #define PCR_COLOR (1 << 30) #define PCR_PBSIZ_1 (0 << 28) @@ -47,29 +49,21 @@ #define DMACR_HM(x) (((x) & 0xf) << 16) #define DMACR_TM(x) ((x) & 0xf) -struct imx_fb_platform_data { - u_long pixclock; - - u_short xres; - u_short yres; - - u_int nonstd; - u_char bpp; - u_char hsync_len; - u_char left_margin; - u_char right_margin; +struct imx_fb_videomode { + struct fb_videomode mode; + u32 pcr; + unsigned char bpp; +}; - u_char vsync_len; - u_char upper_margin; - u_char lower_margin; - u_char sync; +struct imx_fb_platform_data { + struct imx_fb_videomode *mode; + int num_modes; u_int cmap_greyscale:1, cmap_inverse:1, cmap_static:1, unused:29; - u_int pcr; u_int pwmr; u_int lscr1; u_int dmacr; -- cgit v1.2.3 From 8afaada2dc9247ffcd2982be824cd290ace18f55 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 15 Jun 2009 12:36:25 +0200 Subject: mxc gpio: CONFIG_ARCH_* -> cpu_is_*() Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/gpio.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 7506d963be4..b7071572035 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -162,7 +162,6 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) } } -#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1) /* MX1 and MX3 has one interrupt *per* gpio port */ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) { @@ -174,9 +173,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) mxc_gpio_irq_handler(port, irq_stat); } -#endif -#ifdef CONFIG_ARCH_MX2 /* MX2 has one interrupt *for all* gpio ports */ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) { @@ -195,7 +192,6 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) mxc_gpio_irq_handler(&port[i], irq_stat); } } -#endif static struct irq_chip gpio_irq_chip = { .ack = gpio_ack_irq, @@ -284,17 +280,18 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) /* its a serious configuration bug when it fails */ BUG_ON( gpiochip_add(&port[i].chip) < 0 ); -#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1) - /* setup one handler for each entry */ - set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); - set_irq_data(port[i].irq, &port[i]); -#endif + if (cpu_is_mx1() || cpu_is_mx3()) { + /* setup one handler for each entry */ + set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); + set_irq_data(port[i].irq, &port[i]); + } + } + + if (cpu_is_mx2()) { + /* setup one handler for all GPIO interrupts */ + set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler); + set_irq_data(port[0].irq, port); } -#ifdef CONFIG_ARCH_MX2 - /* setup one handler for all GPIO interrupts */ - set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler); - set_irq_data(port[0].irq, port); -#endif return 0; } -- cgit v1.2.3 From 494f22dddc6308b9c35984118ff4cb1681ad8e48 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 27 May 2009 18:26:51 +0200 Subject: MXC gpio interrupt support: move register definitions to .c file Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/gpio.c | 17 +++++++++++++++++ arch/arm/plat-mxc/include/mach/mx1.h | 14 -------------- arch/arm/plat-mxc/include/mach/mx2x.h | 14 -------------- arch/arm/plat-mxc/include/mach/mx3x.h | 14 -------------- 4 files changed, 17 insertions(+), 42 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index b7071572035..f0315edb3eb 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -29,6 +29,23 @@ static struct mxc_gpio_port *mxc_gpio_ports; static int gpio_table_size; +#define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2()) + +#define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00) +#define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04) +#define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08) +#define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C) +#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10) +#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14) +#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18) +#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18) + +#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0) +#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1) +#define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2) +#define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3) +#define GPIO_INT_NONE 0x4 + /* Note: This driver assumes 32 GPIOs are handled in one register */ static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index) diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index ee60d64728c..1b2890a5c45 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -134,20 +134,6 @@ #define GPIO_INT_PORTD 62 #define WDT_INT 63 -/* gpio and gpio based interrupt handling */ -#define GPIO_DR 0x1C -#define GPIO_GDIR 0x00 -#define GPIO_PSR 0x24 -#define GPIO_ICR1 0x28 -#define GPIO_ICR2 0x2C -#define GPIO_IMR 0x30 -#define GPIO_ISR 0x34 -#define GPIO_INT_LOW_LEV 0x3 -#define GPIO_INT_HIGH_LEV 0x2 -#define GPIO_INT_RISE_EDGE 0x0 -#define GPIO_INT_FALL_EDGE 0x1 -#define GPIO_INT_NONE 0x4 - /* DMA */ #define DMA_REQ_UART3_T 2 #define DMA_REQ_UART3_R 3 diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index 5982ae5a00d..db5d921e0fe 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -150,20 +150,6 @@ #define MXC_INT_GPIO 8 #define MXC_INT_CSPI3 6 -/* gpio and gpio based interrupt handling */ -#define GPIO_DR 0x1C -#define GPIO_GDIR 0x00 -#define GPIO_PSR 0x24 -#define GPIO_ICR1 0x28 -#define GPIO_ICR2 0x2C -#define GPIO_IMR 0x30 -#define GPIO_ISR 0x34 -#define GPIO_INT_LOW_LEV 0x3 -#define GPIO_INT_HIGH_LEV 0x2 -#define GPIO_INT_RISE_EDGE 0x0 -#define GPIO_INT_FALL_EDGE 0x1 -#define GPIO_INT_NONE 0x4 - /* fixed DMA request numbers */ #define DMA_REQ_CSI_RX 31 #define DMA_REQ_CSI_STAT 30 diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 16f68e8f4cf..009f4440276 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -259,20 +259,6 @@ #define SYSTEM_REV_MIN CHIP_REV_1_0 #define SYSTEM_REV_NUM 3 -/* gpio and gpio based interrupt handling */ -#define GPIO_DR 0x00 -#define GPIO_GDIR 0x04 -#define GPIO_PSR 0x08 -#define GPIO_ICR1 0x0C -#define GPIO_ICR2 0x10 -#define GPIO_IMR 0x14 -#define GPIO_ISR 0x18 -#define GPIO_INT_LOW_LEV 0x0 -#define GPIO_INT_HIGH_LEV 0x1 -#define GPIO_INT_RISE_EDGE 0x2 -#define GPIO_INT_FALL_EDGE 0x3 -#define GPIO_INT_NONE 0x4 - /* Mandatory defines used globally */ #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) -- cgit v1.2.3 From 5ef881bbecc72862fa379cb286a50f2781db4cec Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 19 Jun 2009 11:35:08 +0200 Subject: MXC: pwm driver fixes - fix off-by-one error in divider calculation - disable pwm in pwm_disable Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/pwm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c index ae34198a79d..42dd17b89ff 100644 --- a/arch/arm/plat-mxc/pwm.c +++ b/arch/arm/plat-mxc/pwm.c @@ -72,7 +72,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR); writel(period_cycles, pwm->mmio_base + MX3_PWMPR); - writel(MX3_PWMCR_PRESCALER(prescale - 1) | + writel(MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_CLKSRC_IPG_HIGH | MX3_PWMCR_EN, pwm->mmio_base + MX3_PWMCR); } else if (cpu_is_mx1() || cpu_is_mx21()) { @@ -118,6 +118,8 @@ EXPORT_SYMBOL(pwm_enable); void pwm_disable(struct pwm_device *pwm) { + writel(0, pwm->mmio_base + MX3_PWMCR); + if (pwm->clk_enabled) { clk_disable(pwm->clk); pwm->clk_enabled = 0; -- cgit v1.2.3 From 6d73665f052a8dadf6f33dfd2546e15199ad7c5f Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 3 Jun 2009 11:22:32 +0200 Subject: MXC PLL decoding: calculate mfn value with less magic Also, use cpu_is_* macros rather than CONFIG_ARCH_* Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/clock.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c index 92e13566cd4..f653213b741 100644 --- a/arch/arm/plat-mxc/clock.c +++ b/arch/arm/plat-mxc/clock.c @@ -39,6 +39,7 @@ #include #include +#include static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); @@ -363,12 +364,11 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq) mfn_abs = mfn; -#if !defined CONFIG_ARCH_MX1 && !defined CONFIG_ARCH_MX21 - if (mfn >= 0x200) { - mfn |= 0xFFFFFE00; - mfn_abs = -mfn; - } -#endif + /* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit + * 2's complements number + */ + if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) + mfn_abs = 0x400 - mfn; freq *= 2; freq /= pd + 1; @@ -376,8 +376,10 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq) ll = (unsigned long long)freq * mfn_abs; do_div(ll, mfd + 1); - if (mfn < 0) + + if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) ll = -ll; + ll = (freq * mfi) + ll; return ll; -- cgit v1.2.3 From 7dae1134cd4117c1a579f8ae58ce13c1c1ff7164 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Sat, 7 Feb 2009 13:34:01 +0100 Subject: [ARM] MXC: Switch MX1 to clkdev support Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 8986b741223..0617c19f85c 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -9,6 +9,7 @@ choice config ARCH_MX1 bool "MX1-based" select CPU_ARM920T + select COMMON_CLKDEV help This enables support for systems based on the Freescale i.MX1 family -- cgit v1.2.3 From 5e63ff9a973a19b78bb0eef22df8946b36e09f0f Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Sat, 7 Feb 2009 13:37:29 +0100 Subject: [ARM] MXC: remove the now unused #ifndef CONFIG_COMMON_CLKDEV Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/clock.c | 154 ---------------------------------------------- 1 file changed, 154 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c index f653213b741..9e8fbd57495 100644 --- a/arch/arm/plat-mxc/clock.c +++ b/arch/arm/plat-mxc/clock.c @@ -48,76 +48,6 @@ static DEFINE_MUTEX(clocks_mutex); * Standard clock functions defined in include/linux/clk.h *-------------------------------------------------------------------------*/ -/* - * All the code inside #ifndef CONFIG_COMMON_CLKDEV can be removed once all - * MXC architectures have switched to using clkdev. - */ -#ifndef CONFIG_COMMON_CLKDEV -/* - * Retrieve a clock by name. - * - * Note that we first try to use device id on the bus - * and clock name. If this fails, we try to use ".". If this fails, - * we try to use clock name only. - * The reference count to the clock's module owner ref count is incremented. - */ -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *p, *clk = ERR_PTR(-ENOENT); - int idno; - const char *str; - - if (id == NULL) - return clk; - - if (dev == NULL || dev->bus != &platform_bus_type) - idno = -1; - else - idno = to_platform_device(dev)->id; - - mutex_lock(&clocks_mutex); - - list_for_each_entry(p, &clocks, node) { - if (p->id == idno && - strcmp(id, p->name) == 0 && try_module_get(p->owner)) { - clk = p; - goto found; - } - } - - str = strrchr(id, '.'); - if (str) { - int cnt = str - id; - str++; - idno = simple_strtol(str, NULL, 10); - list_for_each_entry(p, &clocks, node) { - if (p->id == idno && - strlen(p->name) == cnt && - strncmp(id, p->name, cnt) == 0 && - try_module_get(p->owner)) { - clk = p; - goto found; - } - } - } - - list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { - clk = p; - goto found; - } - } - - printk(KERN_WARNING "clk: Unable to get requested clock: %s\n", id); - -found: - mutex_unlock(&clocks_mutex); - - return clk; -} -EXPORT_SYMBOL(clk_get); -#endif - static void __clk_disable(struct clk *clk) { if (clk == NULL || IS_ERR(clk)) @@ -194,16 +124,6 @@ unsigned long clk_get_rate(struct clk *clk) } EXPORT_SYMBOL(clk_get_rate); -#ifndef CONFIG_COMMON_CLKDEV -/* Decrement the clock's module reference count */ -void clk_put(struct clk *clk) -{ - if (clk && !IS_ERR(clk)) - module_put(clk->owner); -} -EXPORT_SYMBOL(clk_put); -#endif - /* Round the requested clock rate to the nearest supported * rate that is less than or equal to the requested rate. * This is dependent on the clock's current parent. @@ -266,80 +186,6 @@ struct clk *clk_get_parent(struct clk *clk) } EXPORT_SYMBOL(clk_get_parent); -#ifndef CONFIG_COMMON_CLKDEV -/* - * Add a new clock to the clock tree. - */ -int clk_register(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - mutex_lock(&clocks_mutex); - list_add(&clk->node, &clocks); - mutex_unlock(&clocks_mutex); - - return 0; -} -EXPORT_SYMBOL(clk_register); - -/* Remove a clock from the clock tree */ -void clk_unregister(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return; - - mutex_lock(&clocks_mutex); - list_del(&clk->node); - mutex_unlock(&clocks_mutex); -} -EXPORT_SYMBOL(clk_unregister); - -#ifdef CONFIG_PROC_FS -static int mxc_clock_read_proc(char *page, char **start, off_t off, - int count, int *eof, void *data) -{ - struct clk *clkp; - char *p = page; - int len; - - list_for_each_entry(clkp, &clocks, node) { - p += sprintf(p, "%s-%d:\t\t%lu, %d", clkp->name, clkp->id, - clk_get_rate(clkp), clkp->usecount); - if (clkp->parent) - p += sprintf(p, ", %s-%d\n", clkp->parent->name, - clkp->parent->id); - else - p += sprintf(p, "\n"); - } - - len = (p - page) - off; - if (len < 0) - len = 0; - - *eof = (len <= count) ? 1 : 0; - *start = page + off; - - return len; -} - -static int __init mxc_setup_proc_entry(void) -{ - struct proc_dir_entry *res; - - res = create_proc_read_entry("cpu/clocks", 0, NULL, - mxc_clock_read_proc, NULL); - if (!res) { - printk(KERN_ERR "Failed to create proc/cpu/clocks\n"); - return -ENOMEM; - } - return 0; -} - -late_initcall(mxc_setup_proc_entry); -#endif /* CONFIG_PROC_FS */ -#endif - /* * Get the resulting clock rate from a PLL register value and the input * frequency. PLLs with this register layout can at least be found on -- cgit v1.2.3 From 88e29a8d21fb9687ad6972a44571b295acaf0d74 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 25 Jun 2009 14:11:52 +0200 Subject: MX3: add additional USB pins to iomux Signed-off-by: Daniel Mack Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx3.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index 2eb182f7387..a3b206ce78b 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -635,6 +635,19 @@ enum iomux_pins { #define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) +#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) #define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) #define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) #define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) -- cgit v1.2.3 From af5b1df7136570dae9ac4c1cd193053c61b0ed8f Mon Sep 17 00:00:00 2001 From: Eric Benard Date: Thu, 16 Jul 2009 16:26:33 +0200 Subject: Add support for Eukrea's CPUIMX27 CPUIMX27 is built around Freescale's i.MX27 and has up to 64MB of NOR Flash, up to 512MB of NAND Flash and up to 256MB of mDDR, it includes an ethernet PHY in MII mode, an I2C RTC and a ST16554 QuadUART on nCS3. Signed-off-by: Eric Benard Signed-off-by: Sascha Hauer --- .../plat-mxc/include/mach/board-eukrea_cpuimx27.h | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h new file mode 100644 index 00000000000..91bcce65469 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2009 Eric Benard - eric@eukrea.com + * + * Based on board-pcm038.h which is : + * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ +#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ + +#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ */ -- cgit v1.2.3 From a961bf380b93741c2191f8efc8f5f1c65224b216 Mon Sep 17 00:00:00 2001 From: Eric Benard Date: Thu, 16 Jul 2009 16:26:34 +0200 Subject: Add support for Eukrea's MBIMX27 MBIMX27 is the evaluation board for CPUIMX27 and integrates : a QVGA TFT, a SPI touchscreen controler, a SDCard connector wired to SDHC1. Signed-off-by: Eric Benard Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h index 91bcce65469..a1fd5830af4 100644 --- a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h +++ b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h @@ -22,4 +22,19 @@ #ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ #define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ +#ifndef __ASSEMBLY__ +/* + * This CPU module needs a baseboard to work. After basic initializing + * its own devices, it calls baseboard's init function. + * TODO: Add your own baseboard init function and call it from + * inside eukrea_cpuimx27_init(). + * + * This example here is for the development board. Refer + * eukrea_mbimx27-baseboard.c + */ + +extern void eukrea_mbimx27_baseboard_init(void); + +#endif + #endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ */ -- cgit v1.2.3 From 12b8eb865285c95d6e2c02555f066e3f949e090d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 25 May 2009 10:50:52 +0200 Subject: MXC: use variable for irq controller base in entry-macro.S This allows us to determine the irq controller base address on runtime. Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/entry-macro.S | 3 ++- arch/arm/plat-mxc/irq.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S index 5f01d60da84..7cf290efe76 100644 --- a/arch/arm/plat-mxc/include/mach/entry-macro.S +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S @@ -18,7 +18,8 @@ .endm .macro get_irqnr_preamble, base, tmp - ldr \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR) + ldr \base, =avic_base + ldr \base, [\base] #ifdef CONFIG_MXC_IRQ_PRIOR ldr r4, [\base, #AVIC_NIMASK] #endif diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c index 618a8b24ed1..778ddfe57d8 100644 --- a/arch/arm/plat-mxc/irq.c +++ b/arch/arm/plat-mxc/irq.c @@ -44,7 +44,7 @@ #define AVIC_FIPNDH 0x60 /* fast int pending high */ #define AVIC_FIPNDL 0x64 /* fast int pending low */ -static void __iomem *avic_base; +void __iomem *avic_base; int imx_irq_set_priority(unsigned char irq, unsigned char prio) { -- cgit v1.2.3 From fc2a9f0bc7f6dd4966dc57fb98b8697c83b6d035 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 27 May 2009 18:09:54 +0200 Subject: MXC: i.MX25 timer support Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/time.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index 7e71bb6270e..59e33a3bf7f 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c @@ -47,7 +47,7 @@ #define MX2_TSTAT_CAPT (1 << 1) #define MX2_TSTAT_COMP (1 << 0) -/* MX31, MX35 */ +/* MX31, MX35, MX25 */ #define MX3_TCTL_WAITEN (1 << 3) #define MX3_TCTL_CLK_IPG (1 << 6) #define MX3_TCTL_FRR (1 << 9) @@ -66,7 +66,7 @@ static inline void gpt_irq_disable(void) { unsigned int tmp; - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_mx25()) __raw_writel(0, timer_base + MX3_IR); else { tmp = __raw_readl(timer_base + MXC_TCTL); @@ -76,7 +76,7 @@ static inline void gpt_irq_disable(void) static inline void gpt_irq_enable(void) { - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_mx25()) __raw_writel(1<<0, timer_base + MX3_IR); else { __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, @@ -90,7 +90,7 @@ static void gpt_irq_acknowledge(void) __raw_writel(0, timer_base + MX1_2_TSTAT); if (cpu_is_mx2()) __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_mx25()) __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); } @@ -117,7 +117,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_mx25()) clocksource_mxc.read = mx3_get_cycles; clocksource_mxc.mult = clocksource_hz2mult(c, @@ -180,7 +180,7 @@ static void mxc_set_mode(enum clock_event_mode mode, if (mode != clockevent_mode) { /* Set event time into far-far future */ - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_mx25()) __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, timer_base + MX3_TCMP); else @@ -233,7 +233,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) struct clock_event_device *evt = &clockevent_mxc; uint32_t tstat; - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_mx25()) tstat = __raw_readl(timer_base + MX3_TSTAT); else tstat = __raw_readl(timer_base + MX1_2_TSTAT); @@ -264,7 +264,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_mx25()) clockevent_mxc.set_next_event = mx3_set_next_event; clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, @@ -296,7 +296,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq) __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ - if (cpu_is_mx3()) + if (cpu_is_mx3() || cpu_is_mx25()) tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; else tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; -- cgit v1.2.3 From 6134b2cbb0e24f897fd1063745638397809fca29 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 4 Jun 2009 11:16:22 +0200 Subject: iomux-v3: Allow for a runtime base address also, check for a valid pad_ctrl_ofs before changing the pad control register. Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-v3.h | 5 +++++ arch/arm/plat-mxc/iomux-v3.c | 15 ++++++++++----- 2 files changed, 15 insertions(+), 5 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index cd06df9370c..a0fa4026546 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -113,5 +113,10 @@ void mxc_iomux_v3_release_pad(struct pad_desc *pad); */ void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count); +/* + * Initialise the iomux controller + */ +void mxc_iomux_v3_init(void __iomem *iomux_v3_base); + #endif /* __MACH_IOMUX_V3_H__*/ diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c index 77a078f9513..851ca99bf1b 100644 --- a/arch/arm/plat-mxc/iomux-v3.c +++ b/arch/arm/plat-mxc/iomux-v3.c @@ -29,7 +29,7 @@ #include #include -#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR) +static void __iomem *base; static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG]; @@ -45,14 +45,14 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad) if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map)) return -EBUSY; if (pad->mux_ctrl_ofs) - __raw_writel(pad->mux_mode, IOMUX_BASE + pad->mux_ctrl_ofs); + __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs); if (pad->select_input_ofs) __raw_writel(pad->select_input, - IOMUX_BASE + pad->select_input_ofs); + base + pad->select_input_ofs); - if (!(pad->pad_ctrl & NO_PAD_CTRL)) - __raw_writel(pad->pad_ctrl, IOMUX_BASE + pad->pad_ctrl_ofs); + if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs) + __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs); return 0; } EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); @@ -96,3 +96,8 @@ void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count) } } EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads); + +void mxc_iomux_v3_init(void __iomem *iomux_v3_base) +{ + base = iomux_v3_base; +} -- cgit v1.2.3 From a058cbc17901108de9179dccdb29dff0e00c79fe Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 19 Jun 2009 11:08:07 +0200 Subject: mxc pwm: add mx25 support Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/pwm.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c index 42dd17b89ff..5cdbd605ac0 100644 --- a/arch/arm/plat-mxc/pwm.c +++ b/arch/arm/plat-mxc/pwm.c @@ -32,6 +32,7 @@ #define MX3_PWMPR 0x10 /* PWM Period Register */ #define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16) +#define MX3_PWMCR_CLKSRC_IPG (1 << 16) #define MX3_PWMCR_EN (1 << 0) @@ -55,9 +56,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) return -EINVAL; - if (cpu_is_mx27() || cpu_is_mx3()) { + if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25()) { unsigned long long c; unsigned long period_cycles, duty_cycles, prescale; + u32 cr; + c = clk_get_rate(pwm->clk); c = c * period_ns; do_div(c, 1000000000); @@ -72,9 +75,15 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR); writel(period_cycles, pwm->mmio_base + MX3_PWMPR); - writel(MX3_PWMCR_PRESCALER(prescale) | - MX3_PWMCR_CLKSRC_IPG_HIGH | MX3_PWMCR_EN, - pwm->mmio_base + MX3_PWMCR); + + cr = MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_EN; + + if (cpu_is_mx25()) + cr |= MX3_PWMCR_CLKSRC_IPG; + else + cr |= MX3_PWMCR_CLKSRC_IPG_HIGH; + + writel(cr, pwm->mmio_base + MX3_PWMCR); } else if (cpu_is_mx1() || cpu_is_mx21()) { /* The PWM subsystem allows for exact frequencies. However, * I cannot connect a scope on my device to the PWM line and -- cgit v1.2.3 From 8c25c36f33157a2e2a1fcd60b6dc00feace80631 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 4 Jun 2009 11:32:12 +0200 Subject: Add i.MX25 support Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/Kconfig | 8 +++++ arch/arm/plat-mxc/gpio.c | 2 +- arch/arm/plat-mxc/include/mach/common.h | 3 ++ arch/arm/plat-mxc/include/mach/debug-macro.S | 9 ++++++ arch/arm/plat-mxc/include/mach/hardware.h | 4 +++ arch/arm/plat-mxc/include/mach/irqs.h | 2 ++ arch/arm/plat-mxc/include/mach/memory.h | 2 ++ arch/arm/plat-mxc/include/mach/mx25.h | 44 ++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/mxc.h | 13 ++++++++ arch/arm/plat-mxc/include/mach/timex.h | 2 ++ arch/arm/plat-mxc/include/mach/uncompress.h | 1 + 11 files changed, 89 insertions(+), 1 deletion(-) create mode 100644 arch/arm/plat-mxc/include/mach/mx25.h (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 0617c19f85c..e342a2e6160 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -20,6 +20,13 @@ config ARCH_MX2 help This enables support for systems based on the Freescale i.MX2 family +config ARCH_MX25 + bool "MX25-based" + select CPU_ARM926T + select COMMON_CLKDEV + help + This enables support for systems based on the Freescale i.MX25 family + config ARCH_MX3 bool "MX3-based" select CPU_V6 @@ -32,6 +39,7 @@ endchoice source "arch/arm/mach-mx1/Kconfig" source "arch/arm/mach-mx2/Kconfig" source "arch/arm/mach-mx3/Kconfig" +source "arch/arm/mach-mx25/Kconfig" endmenu diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index f0315edb3eb..cfc4a8b43e6 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -297,7 +297,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) /* its a serious configuration bug when it fails */ BUG_ON( gpiochip_add(&port[i].chip) < 0 ); - if (cpu_is_mx1() || cpu_is_mx3()) { + if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) { /* setup one handler for each entry */ set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); set_irq_data(port[i].irq, &port[i]); diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index cd8f215c1ad..4e7af741239 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -16,18 +16,21 @@ struct clk; extern void mx1_map_io(void); extern void mx21_map_io(void); +extern void mx25_map_io(void); extern void mx27_map_io(void); extern void mx31_map_io(void); extern void mx35_map_io(void); extern void mxc_init_irq(void __iomem *); extern void mx1_init_irq(void); extern void mx21_init_irq(void); +extern void mx25_init_irq(void); extern void mx27_init_irq(void); extern void mx31_init_irq(void); extern void mx35_init_irq(void); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); extern int mx21_clocks_init(unsigned long lref, unsigned long fref); +extern int mx25_clocks_init(unsigned long fref); extern int mx27_clocks_init(unsigned long fref); extern int mx31_clocks_init(unsigned long fref); extern int mx35_clocks_init(void); diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 4f85acd74af..bf683de56b7 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -17,6 +17,15 @@ #define UART_VADDR IO_ADDRESS(UART1_BASE_ADDR) #endif +#ifdef CONFIG_ARCH_MX25 +#ifdef UART_PADDR +#error "CONFIG_DEBUG_LL is incompatible with multiple archs" +#endif +#include +#define UART_PADDR UART1_BASE_ADDR +#define UART_VADDR MX25_AIPS1_IO_ADDRESS(UART1_BASE_ADDR) +#endif + #ifdef CONFIG_ARCH_MX2 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index 42e4ee37ca1..569af3239c3 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -42,6 +42,10 @@ # include #endif +#ifdef CONFIG_ARCH_MX25 +# include +#endif + #include #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 518a36504b8..f39e016c1cc 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -24,6 +24,8 @@ #define MXC_GPIO_IRQS (32 * 6) #elif defined CONFIG_ARCH_MX3 #define MXC_GPIO_IRQS (32 * 3) +#elif defined CONFIG_ARCH_MX25 +#define MXC_GPIO_IRQS (32 * 4) #endif /* diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 6065e00176e..42db7394111 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -22,6 +22,8 @@ #endif #elif defined CONFIG_ARCH_MX3 #define PHYS_OFFSET UL(0x80000000) +#elif defined CONFIG_ARCH_MX25 +#define PHYS_OFFSET UL(0x80000000) #endif #if defined(CONFIG_MX1_VIDEO) diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h new file mode 100644 index 00000000000..ec64bd9a8ab --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -0,0 +1,44 @@ +#ifndef __MACH_MX25_H__ +#define __MACH_MX25_H__ + +#define MX25_AIPS1_BASE_ADDR 0x43F00000 +#define MX25_AIPS1_BASE_ADDR_VIRT 0xFC000000 +#define MX25_AIPS1_SIZE SZ_1M +#define MX25_AIPS2_BASE_ADDR 0x53F00000 +#define MX25_AIPS2_BASE_ADDR_VIRT 0xFC200000 +#define MX25_AIPS2_SIZE SZ_1M +#define MX25_AVIC_BASE_ADDR 0x68000000 +#define MX25_AVIC_BASE_ADDR_VIRT 0xFC400000 +#define MX25_AVIC_SIZE SZ_1M + +#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) + +#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) +#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) +#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) + +#define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000) +#define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000) +#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) +#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) + +#define MX25_AIPS1_IO_ADDRESS(x) \ + (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) +#define MX25_AIPS2_IO_ADDRESS(x) \ + (((x) - MX25_AIPS2_BASE_ADDR) + MX25_AIPS2_BASE_ADDR_VIRT) +#define MX25_AVIC_IO_ADDRESS(x) \ + (((x) - MX25_AVIC_BASE_ADDR) + MX25_AVIC_BASE_ADDR_VIRT) + +#define __in_range(addr, name) ((addr) >= name##_BASE_ADDR && (addr) < name##_BASE_ADDR + name##_SIZE) + +#define MX25_IO_ADDRESS(x) \ + (void __force __iomem *) \ + (__in_range(x, MX25_AIPS1) ? MX25_AIPS1_IO_ADDRESS(x) : \ + __in_range(x, MX25_AIPS2) ? MX25_AIPS2_IO_ADDRESS(x) : \ + __in_range(x, MX25_AVIC) ? MX25_AVIC_IO_ADDRESS(x) : \ + 0xDEADBEEF) + +#define UART1_BASE_ADDR 0x43f90000 +#define UART2_BASE_ADDR 0x43f94000 + +#endif /* __MACH_MX25_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 5fa2a07f4ea..882b816729b 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -26,6 +26,7 @@ #define MXC_CPU_MX1 1 #define MXC_CPU_MX21 21 +#define MXC_CPU_MX25 25 #define MXC_CPU_MX27 27 #define MXC_CPU_MX31 31 #define MXC_CPU_MX35 35 @@ -58,6 +59,18 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx21() (0) #endif +#ifdef CONFIG_ARCH_MX25 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX25 +# endif +# define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25) +#else +# define cpu_is_mx25() (0) +#endif + #ifdef CONFIG_MACH_MX27 # ifdef mxc_cpu_type # undef mxc_cpu_type diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index 07b4a73c9d2..0707b7d5b5c 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -26,6 +26,8 @@ #define CLOCK_TICK_RATE 13300000 #elif defined CONFIG_ARCH_MX3 #define CLOCK_TICK_RATE 16625000 +#elif defined CONFIG_ARCH_MX25 +#define CLOCK_TICK_RATE 16000000 #endif #endif /* __ASM_ARCH_MXC_TIMEX_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 98c8a60214d..b6650e705e3 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -63,6 +63,7 @@ static void putc(int ch) #define flush() do { } while (0) #define MX1_UART1_BASE_ADDR 0x00206000 +#define MX25_UART1_BASE_ADDR 0x43f90000 #define MX2X_UART1_BASE_ADDR 0x1000a000 #define MX3X_UART1_BASE_ADDR 0x43F90000 -- cgit v1.2.3 From 635baf6b40ebaef683abf87d677467cba71a0d50 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 4 Jun 2009 11:32:46 +0200 Subject: Freescale i.MX25 PDK (3ds) board support Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/uncompress.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index b6650e705e3..1e24499f20b 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -74,6 +74,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) case MACH_TYPE_SCB9328: uart_base = MX1_UART1_BASE_ADDR; break; + case MACH_TYPE_MX25_3DS: + uart_base = MX25_UART1_BASE_ADDR; + break; case MACH_TYPE_IMX27LITE: case MACH_TYPE_MX27_3DS: case MACH_TYPE_MX27ADS: -- cgit v1.2.3 From 8e5be212cba6675dc363a224ce4a98bb07039b4b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lothar=20Wa=C3=9Fmann?= Date: Wed, 15 Jul 2009 15:19:34 +0200 Subject: i.MX25 iomux definitions (corrected version) Signed-off-by: Lothar Wassmann Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx25.h | 517 ++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/iomux.h | 6 + 2 files changed, 523 insertions(+) create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx25.h (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h new file mode 100644 index 00000000000..810c47f56e7 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h @@ -0,0 +1,517 @@ +/* + * arch/arm/plat-mxc/include/mach/iomux-mx25.h + * + * Copyright (C) 2009 by Lothar Wassmann + * + * based on arch/arm/mach-mx25/mx25_pins.h + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * and + * arch/arm/plat-mxc/include/mach/iomux-mx35.h + * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __IOMUX_MX25_H__ +#define __IOMUX_MX25_H__ + +#include + +#ifndef GPIO_PORTA +#error Please include mach/iomux.h +#endif + +/* + * + * @brief MX25 I/O Pin List + * + * @ingroup GPIO_MX25 + */ + +#ifndef __ASSEMBLY__ + +/* + * IOMUX/PAD Bit field definitions + */ + +#define MX25_PAD_A10__A10 IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A10__GPIO_4_0 IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A13__A13 IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A13__GPIO_4_1 IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A14__A14 IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A14__GPIO_2_0 IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A15__A15 IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A15__GPIO_2_1 IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A16__A16 IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A16__GPIO_2_2 IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A17__A17 IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A17__GPIO_2_3 IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A18__A18 IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A18__GPIO_2_4 IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A18__FEC_COL IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTL) + +#define MX25_PAD_A19__A19 IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A19__FEC_RX_ER IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTL) +#define MX25_PAD_A19__GPIO_2_5 IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A20__A20 IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A20__GPIO_2_6 IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A20__FEC_RDATA2 IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTL) + +#define MX25_PAD_A21__A21 IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A21__GPIO_2_7 IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A21__FEC_RDATA3 IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTL) + +#define MX25_PAD_A22__A22 IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A22__GPIO_2_8 IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A23__A23 IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A23__GPIO_2_9 IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A24__A24 IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A24__GPIO_2_10 IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A24__FEC_RX_CLK IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTL) + +#define MX25_PAD_A25__A25 IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A25__GPIO_2_11 IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A25__FEC_CRS IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTL) + +#define MX25_PAD_EB0__EB0 IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_EB0__AUD4_TXD IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL) +#define MX25_PAD_EB0__GPIO_2_12 IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_EB1__EB1 IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_EB1__AUD4_RXD IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL) +#define MX25_PAD_EB1__GPIO_2_13 IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_OE__OE IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_OE__AUD4_TXC IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_OE__GPIO_2_14 IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CS0__CS0 IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL) +#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_NF_CE0__NF_CE0 IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTL) +#define MX25_PAD_NF_CE0__GPIO_3_22 IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_ECB__ECB IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_ECB__UART5_TXD_MUX IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_ECB__GPIO_3_23 IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LBA__LBA IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LBA__UART5_RXD_MUX IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL) +#define MX25_PAD_LBA__GPIO_3_24 IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_BCLK__BCLK IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_BCLK__GPIO_4_4 IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_RW__RW IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_RW__AUD4_TXFS IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL) +#define MX25_PAD_RW__GPIO_3_25 IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_NFWE_B__NFWE_B IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFWE_B__GPIO_3_26 IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_NFRE_B__NFRE_B IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFRE_B__GPIO_3_27 IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_NFALE__NFALE IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFALE__GPIO_3_28 IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_NFCLE__NFCLE IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFCLE__GPIO_3_29 IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_NFWP_B__NFWP_B IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFWP_B__GPIO_3_30 IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_NFRB__NFRB IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE) +#define MX25_PAD_NFRB__GPIO_3_31 IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D15__D15 IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D15__LD16 IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D15__GPIO_4_5 IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D14__D14 IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D14__LD17 IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D14__GPIO_4_6 IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D13__D13 IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D13__LD18 IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D13__GPIO_4_7 IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D12__D12 IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D12__GPIO_4_8 IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D11__D11 IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D11__GPIO_4_9 IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D10__D10 IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D10__GPIO_4_10 IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D10__USBOTG_OC IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP) + +#define MX25_PAD_D9__D9 IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D9__GPIO_4_11 IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D9__USBH2_PWR IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE) + +#define MX25_PAD_D8__D8 IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D8__GPIO_4_12 IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D8__USBH2_OC IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP) + +#define MX25_PAD_D7__D7 IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D7__GPIO_4_13 IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D6__D6 IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D6__GPIO_4_14 IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D5__D5 IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D5__GPIO_4_15 IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D4__D4 IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D4__GPIO_4_16 IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D3__D3 IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D3__GPIO_4_17 IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D2__D2 IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D2__GPIO_4_18 IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D1__D1 IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D1__GPIO_4_19 IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D0__D0 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D0__GPIO_4_20 IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD0__LD0 IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD0__CSI_D0 IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL) +#define MX25_PAD_LD0__GPIO_2_15 IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD1__LD1 IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD1__CSI_D1 IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL) +#define MX25_PAD_LD1__GPIO_2_16 IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD2__LD2 IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD2__GPIO_2_17 IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD3__LD3 IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD3__GPIO_2_18 IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD4__LD4 IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD4__GPIO_2_19 IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD5__LD5 IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD5__GPIO_1_19 IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD6__LD6 IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD6__GPIO_1_20 IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD7__LD7 IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTL) + +#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTL) + +#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTL) + +#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTL) + +#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTL) + +#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTL) + +#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTL) + +#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTL) + +#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_HSYNC__GPIO_1_22 IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_VSYNC__VSYNC IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSYNC__GPIO_1_23 IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LSCLK__LSCLK IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LSCLK__GPIO_1_24 IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_OE_ACD__OE_ACD IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTL) + +#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_PWM__GPIO_1_26 IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_PWM__USBH2_OC IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP) + +#define MX25_PAD_CSI_D2__CSI_D2 IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D2__UART5_RXD_MUX IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D2__GPIO_1_27 IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_D3__CSI_D3 IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D3__GPIO_1_28 IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_D4__CSI_D4 IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D4__UART5_RTS IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D4__GPIO_1_29 IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_D5__CSI_D5 IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D5__GPIO_1_30 IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_D6__CSI_D6 IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D6__GPIO_1_31 IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_D7__CSI_D7 IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D7__GPIO_1_6 IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_D8__CSI_D8 IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D8__GPIO_1_7 IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_D9__CSI_D9 IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D9__GPIO_4_21 IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_MCLK__CSI_MCLK IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_MCLK__GPIO_1_8 IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_VSYNC__CSI_VSYNC IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_VSYNC__GPIO_1_9 IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_HSYNC__CSI_HSYNC IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_HSYNC__GPIO_1_10 IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_I2C1_CLK__GPIO_1_12 IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_I2C1_DAT__GPIO_1_13 IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MISO__GPIO_1_15 IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS0__GPIO_1_16 IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS1__GPIO_1_17 IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSPI1_RDY__CSPI1_RDY IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE) +#define MX25_PAD_CSPI1_RDY__GPIO_2_22 IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN) +#define MX25_PAD_UART1_RXD__GPIO_4_22 IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_TXD__GPIO_4_23 IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP) +#define MX25_PAD_UART1_RTS__CSI_D0 IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL) +#define MX25_PAD_UART1_RTS__GPIO_4_24 IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP) +#define MX25_PAD_UART1_CTS__CSI_D1 IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL) +#define MX25_PAD_UART1_CTS__GPIO_4_25 IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_RXD__GPIO_4_26 IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_TXD__GPIO_4_27 IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_RTS__FEC_COL IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTL) +#define MX25_PAD_UART2_RTS__GPIO_4_28 IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART2_CTS__FEC_RX_ER IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTL) +#define MX25_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_CTS__GPIO_4_29 IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) +#define MX25_PAD_SD1_CMD__FEC_RDATA2 IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTL) +#define MX25_PAD_SD1_CMD__GPIO_2_23 IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) +#define MX25_PAD_SD1_CLK__FEC_RDATA3 IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTL) +#define MX25_PAD_SD1_CLK__GPIO_2_24 IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) +#define MX25_PAD_SD1_DATA0__GPIO_2_25 IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) +#define MX25_PAD_SD1_DATA1__AUD7_RXD IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA1__GPIO_2_26 IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) +#define MX25_PAD_SD1_DATA2__FEC_RX_CLK IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTL) +#define MX25_PAD_SD1_DATA2__GPIO_2_27 IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) +#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTL) +#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE) +#define MX25_PAD_KPP_ROW0__GPIO_2_29 IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, PAD_CTL_PKE) +#define MX25_PAD_KPP_ROW1__GPIO_2_30 IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, PAD_CTL_PKE) +#define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW2__GPIO_2_31 IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, PAD_CTL_PKE) +#define MX25_PAD_KPP_ROW3__CSI_LD1 IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW3__GPIO_3_0 IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) +#define MX25_PAD_KPP_COL0__GPIO_3_1 IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) +#define MX25_PAD_KPP_COL1__GPIO_3_2 IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) +#define MX25_PAD_KPP_COL2__GPIO_3_3 IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) +#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTL) +#define MX25_PAD_FEC_MDC__AUD4_TXD IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDC__GPIO_3_5 IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP) +#define MX25_PAD_FEC_MDIO__AUD4_RXD IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDIO__GPIO_3_6 IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTL) +#define MX25_PAD_FEC_TDATA0__GPIO_3_7 IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTL) +#define MX25_PAD_FEC_TDATA1__AUD4_TXFS IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA1__GPIO_3_8 IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTL) +#define MX25_PAD_FEC_TX_EN__GPIO_3_9 IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL) +#define MX25_PAD_FEC_RDATA0__GPIO_3_10 IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL) +#define MX25_PAD_FEC_RDATA1__GPIO_3_11 IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL) +#define MX25_PAD_FEC_RX_DV__CAN2_RX IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP) +#define MX25_PAD_FEC_RX_DV__GPIO_3_12 IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN) +#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_RTCK__RTCK IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_RTCK__OWIRE IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_RTCK__GPIO_3_14 IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_DE_B__DE_B IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_DE_B__GPIO_2_20 IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_TDO__TDO IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_GPIO_A__GPIO_A IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_A__CAN1_TX IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP) +#define MX25_PAD_GPIO_A__USBOTG_PWR IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE) + +#define MX25_PAD_GPIO_B__GPIO_B IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_B__CAN1_RX IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K) +#define MX25_PAD_GPIO_B__USBOTG_OC IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP) + +#define MX25_PAD_GPIO_C__GPIO_C IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP) + +#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP) + +#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_F__AUD7_TXC IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_VSTBY_REQ__VSTBY_REQ IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_REQ__AUD7_TXFS IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_REQ__GPIO_3_17 IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_ACK__VSTBY_ACK IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_ACK__GPIO_3_18 IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_POWER_FAIL__POWER_FAIL IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_POWER_FAIL__AUD7_RXD IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL) +#define MX25_PAD_POWER_FAIL__GPIO_3_19 IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CLKO__CLKO IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CLKO__GPIO_2_21 IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_BOOT_MODE0__GPIO_4_30 IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_BOOT_MODE1__GPIO_4_31 IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CTL_GRP_DVS_MISC IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_FEC IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DVS_JTAG IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_NFC IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_CSI IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_WEIM IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_DDR IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DVS_CRM IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_KPP IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_SDHC1 IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_LCD IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_UART IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DVS_NFC IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DVS_CSI IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_CSPI1 IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DDRTYPE IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL) + +#endif // __ASSEMBLY__ +#endif // __IOMUX_MX25_H__ diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h index 171f8adc110..6d49f8ae325 100644 --- a/arch/arm/plat-mxc/include/mach/iomux.h +++ b/arch/arm/plat-mxc/include/mach/iomux.h @@ -49,6 +49,9 @@ #ifdef CONFIG_ARCH_MX2 # define GPIO_PORT_MAX 5 #endif +#ifdef CONFIG_ARCH_MX25 +# define GPIO_PORT_MAX 3 +#endif #ifndef GPIO_PORT_MAX # error "GPIO config port count unknown!" @@ -107,6 +110,9 @@ #include #endif #endif +#ifdef CONFIG_ARCH_MX25 +#include +#endif /* decode irq number to use with IMR(x), ISR(x) and friends */ -- cgit v1.2.3 From fd6ac7bb9d671d36fd7536c68fde977d197756ab Mon Sep 17 00:00:00 2001 From: Dmitriy Taychenachev Date: Fri, 31 Jul 2009 20:29:22 +0900 Subject: MXC: add basic MXC91231 support Signed-off-by: Dmitriy Taychenachev Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/Kconfig | 8 + arch/arm/plat-mxc/include/mach/common.h | 6 + arch/arm/plat-mxc/include/mach/debug-macro.S | 8 + arch/arm/plat-mxc/include/mach/hardware.h | 4 + arch/arm/plat-mxc/include/mach/irqs.h | 2 + arch/arm/plat-mxc/include/mach/memory.h | 2 + arch/arm/plat-mxc/include/mach/mxc.h | 15 +- arch/arm/plat-mxc/include/mach/mxc91231.h | 315 +++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/system.h | 10 + arch/arm/plat-mxc/include/mach/timex.h | 2 + arch/arm/plat-mxc/include/mach/uncompress.h | 4 + arch/arm/plat-mxc/system.c | 7 + arch/arm/plat-mxc/time.c | 2 +- 13 files changed, 383 insertions(+), 2 deletions(-) create mode 100644 arch/arm/plat-mxc/include/mach/mxc91231.h (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index e342a2e6160..ca5c7c22634 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -34,12 +34,20 @@ config ARCH_MX3 help This enables support for systems based on the Freescale i.MX3 family +config ARCH_MXC91231 + bool "MXC91231-based" + select CPU_V6 + select COMMON_CLKDEV + help + This enables support for systems based on the Freescale MXC91231 family + endchoice source "arch/arm/mach-mx1/Kconfig" source "arch/arm/mach-mx2/Kconfig" source "arch/arm/mach-mx3/Kconfig" source "arch/arm/mach-mx25/Kconfig" +source "arch/arm/mach-mxc91231/Kconfig" endmenu diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 4e7af741239..286cb9b0a25 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -20,6 +20,7 @@ extern void mx25_map_io(void); extern void mx27_map_io(void); extern void mx31_map_io(void); extern void mx35_map_io(void); +extern void mxc91231_map_io(void); extern void mxc_init_irq(void __iomem *); extern void mx1_init_irq(void); extern void mx21_init_irq(void); @@ -27,6 +28,7 @@ extern void mx25_init_irq(void); extern void mx27_init_irq(void); extern void mx31_init_irq(void); extern void mx35_init_irq(void); +extern void mxc91231_init_irq(void); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); extern int mx21_clocks_init(unsigned long lref, unsigned long fref); @@ -34,9 +36,13 @@ extern int mx25_clocks_init(unsigned long fref); extern int mx27_clocks_init(unsigned long fref); extern int mx31_clocks_init(unsigned long fref); extern int mx35_clocks_init(void); +extern int mxc91231_clocks_init(unsigned long fref); extern int mxc_register_gpios(void); extern int mxc_register_device(struct platform_device *pdev, void *data); extern void mxc_set_cpu_type(unsigned int type); extern void mxc_arch_reset_init(void __iomem *); +extern void mxc91231_power_off(void); +extern void mxc91231_arch_reset(int, const char *); +extern void mxc91231_prepare_idle(void); #endif diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index bf683de56b7..15b2b148a10 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -44,6 +44,14 @@ #define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) #endif +#ifdef CONFIG_ARCH_MXC91231 +#ifdef UART_PADDR +#error "CONFIG_DEBUG_LL is incompatible with multiple archs" +#endif +#include +#define UART_PADDR MXC91231_UART2_BASE_ADDR +#define UART_VADDR MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) +#endif .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index 569af3239c3..78db75475f6 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -46,6 +46,10 @@ # include #endif +#ifdef CONFIG_ARCH_MXC91231 +# include +#endif + #include #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index f39e016c1cc..ead9d592168 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -26,6 +26,8 @@ #define MXC_GPIO_IRQS (32 * 3) #elif defined CONFIG_ARCH_MX25 #define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_ARCH_MXC91231 +#define MXC_GPIO_IRQS (32 * 4) #endif /* diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 42db7394111..d3afafdcc0e 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -24,6 +24,8 @@ #define PHYS_OFFSET UL(0x80000000) #elif defined CONFIG_ARCH_MX25 #define PHYS_OFFSET UL(0x80000000) +#elif defined CONFIG_ARCH_MXC91231 +#define PHYS_OFFSET UL(0x90000000) #endif #if defined(CONFIG_MX1_VIDEO) diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 882b816729b..51990536b84 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -30,6 +30,7 @@ #define MXC_CPU_MX27 27 #define MXC_CPU_MX31 31 #define MXC_CPU_MX35 35 +#define MXC_CPU_MXC91231 91231 #ifndef __ASSEMBLY__ extern unsigned int __mxc_cpu_type; @@ -107,13 +108,25 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx35() (0) #endif +#ifdef CONFIG_ARCH_MXC91231 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MXC91231 +# endif +# define cpu_is_mxc91231() (mxc_cpu_type == MXC_CPU_MXC91231) +#else +# define cpu_is_mxc91231() (0) +#endif + #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10) #define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4) #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) #endif -#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) +#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231()) #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) #endif /* __ASM_ARCH_MXC_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h new file mode 100644 index 00000000000..81484d1ef23 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h @@ -0,0 +1,315 @@ +/* + * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. + * - Platform specific register memory map + * + * Copyright 2005-2007 Motorola, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __MACH_MXC91231_H__ +#define __MACH_MXC91231_H__ + +/* + * L2CC + */ +#define MXC91231_L2CC_BASE_ADDR 0x30000000 +#define MXC91231_L2CC_BASE_ADDR_VIRT 0xF9000000 +#define MXC91231_L2CC_SIZE SZ_64K + +/* + * AIPS 1 + */ +#define MXC91231_AIPS1_BASE_ADDR 0x43F00000 +#define MXC91231_AIPS1_BASE_ADDR_VIRT 0xFC000000 +#define MXC91231_AIPS1_SIZE SZ_1M + +#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR +#define MXC91231_MAX_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x04000) +#define MXC91231_EVTMON_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x08000) +#define MXC91231_CLKCTL_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x0C000) +#define MXC91231_ETB_SLOT4_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x10000) +#define MXC91231_ETB_SLOT5_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x14000) +#define MXC91231_ECT_CTIO_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x18000) +#define MXC91231_I2C_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x80000) +#define MXC91231_MU_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x88000) +#define MXC91231_UART1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x90000) +#define MXC91231_UART2_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x94000) +#define MXC91231_DSM_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x98000) +#define MXC91231_OWIRE_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x9C000) +#define MXC91231_SSI1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA0000) +#define MXC91231_KPP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA8000) +#define MXC91231_IOMUX_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xAC000) +#define MXC91231_CTI_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xB8000) + +/* + * AIPS 2 + */ +#define MXC91231_AIPS2_BASE_ADDR 0x53F00000 +#define MXC91231_AIPS2_BASE_ADDR_VIRT 0xFC100000 +#define MXC91231_AIPS2_SIZE SZ_1M + +#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) +#define MXC91231_GPT1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x90000) +#define MXC91231_EPIT1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x94000) +#define MXC91231_SCC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xAC000) +#define MXC91231_RNGA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xB0000) +#define MXC91231_IPU_CTRL_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC0000) +#define MXC91231_AUDMUX_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC4000) +#define MXC91231_EDIO_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC8000) +#define MXC91231_GPIO1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xCC000) +#define MXC91231_GPIO2_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD0000) +#define MXC91231_SDMA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD4000) +#define MXC91231_RTC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD8000) +#define MXC91231_WDOG1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xDC000) +#define MXC91231_PWM_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE0000) +#define MXC91231_GPIO3_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE4000) +#define MXC91231_WDOG2_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE8000) +#define MXC91231_RTIC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xEC000) +#define MXC91231_LPMC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xF0000) + +/* + * SPBA global module 0 + */ +#define MXC91231_SPBA0_BASE_ADDR 0x50000000 +#define MXC91231_SPBA0_BASE_ADDR_VIRT 0xFC200000 +#define MXC91231_SPBA0_SIZE SZ_1M + +#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) +#define MXC91231_MMC_SDHC2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x08000) +#define MXC91231_UART3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x0C000) +#define MXC91231_CSPI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x10000) +#define MXC91231_SSI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x14000) +#define MXC91231_SIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x18000) +#define MXC91231_IIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x1C000) +#define MXC91231_CTI_SDMA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x20000) +#define MXC91231_USBOTG_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x24000) +#define MXC91231_USBOTG_DATA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x28000) +#define MXC91231_CSPI1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x30000) +#define MXC91231_SPBA_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x3C000) +#define MXC91231_IOMUX_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x40000) +#define MXC91231_CRM_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x44000) +#define MXC91231_CRM_AP_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x48000) +#define MXC91231_PLL0_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x4C000) +#define MXC91231_PLL1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x50000) +#define MXC91231_PLL2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x54000) +#define MXC91231_GPIO4_SH_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x58000) +#define MXC91231_HAC_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000) +#define MXC91231_SAHARA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000) +#define MXC91231_PLL3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x60000) + +/* + * SPBA global module 1 + */ +#define MXC91231_SPBA1_BASE_ADDR 0x52000000 +#define MXC91231_SPBA1_BASE_ADDR_VIRT 0xFC300000 +#define MXC91231_SPBA1_SIZE SZ_1M + +#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) +#define MXC91231_EL1T_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x38000) + +/*! + * Defines for SPBA modules + */ +#define MXC91231_SPBA_SDHC1 0x04 +#define MXC91231_SPBA_SDHC2 0x08 +#define MXC91231_SPBA_UART3 0x0C +#define MXC91231_SPBA_CSPI2 0x10 +#define MXC91231_SPBA_SSI2 0x14 +#define MXC91231_SPBA_SIM 0x18 +#define MXC91231_SPBA_IIM 0x1C +#define MXC91231_SPBA_CTI_SDMA 0x20 +#define MXC91231_SPBA_USBOTG_CTRL_REGS 0x24 +#define MXC91231_SPBA_USBOTG_DATA_REGS 0x28 +#define MXC91231_SPBA_CSPI1 0x30 +#define MXC91231_SPBA_MQSPI 0x34 +#define MXC91231_SPBA_EL1T 0x38 +#define MXC91231_SPBA_IOMUX 0x40 +#define MXC91231_SPBA_CRM_COM 0x44 +#define MXC91231_SPBA_CRM_AP 0x48 +#define MXC91231_SPBA_PLL0 0x4C +#define MXC91231_SPBA_PLL1 0x50 +#define MXC91231_SPBA_PLL2 0x54 +#define MXC91231_SPBA_GPIO4 0x58 +#define MXC91231_SPBA_SAHARA 0x5C + +/* + * ROMP and AVIC + */ +#define MXC91231_ROMP_BASE_ADDR 0x60000000 +#define MXC91231_ROMP_BASE_ADDR_VIRT 0xFC400000 +#define MXC91231_ROMP_SIZE SZ_64K + +#define MXC91231_AVIC_BASE_ADDR 0x68000000 +#define MXC91231_AVIC_BASE_ADDR_VIRT 0xFC410000 +#define MXC91231_AVIC_SIZE SZ_64K + +/* + * NAND, SDRAM, WEIM, M3IF, EMI controllers + */ +#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 +#define MXC91231_X_MEMC_BASE_ADDR_VIRT 0xFC420000 +#define MXC91231_X_MEMC_SIZE SZ_64K + +#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) +#define MXC91231_ESDCTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x1000) +#define MXC91231_WEIM_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x2000) +#define MXC91231_M3IF_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x3000) +#define MXC91231_EMI_CTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x4000) + +/* + * Memory regions and CS + * CPLD is connected on CS4 + * CS5 is TP1021 or it is not connected + * */ +#define MXC91231_FB_RAM_BASE_ADDR 0x78000000 +#define MXC91231_FB_RAM_SIZE SZ_256K +#define MXC91231_CSD0_BASE_ADDR 0x80000000 +#define MXC91231_CSD1_BASE_ADDR 0x90000000 +#define MXC91231_CS0_BASE_ADDR 0xA0000000 +#define MXC91231_CS1_BASE_ADDR 0xA8000000 +#define MXC91231_CS2_BASE_ADDR 0xB0000000 +#define MXC91231_CS3_BASE_ADDR 0xB2000000 +#define MXC91231_CS4_BASE_ADDR 0xB4000000 +#define MXC91231_CS5_BASE_ADDR 0xB6000000 + +/* Is given address belongs to the specified memory region? */ +#define ADDRESS_IN_REGION(addr, start, size) \ + (((addr) >= (start)) && ((addr) < (start)+(size))) + +/* Is given address belongs to the specified named `module'? */ +#define MXC91231_IS_MODULE(addr, module) \ + ADDRESS_IN_REGION(addr, MXC91231_ ## module ## _BASE_ADDR, \ + MXC91231_ ## module ## _SIZE) +/* + * This macro defines the physical to virtual address mapping for all the + * peripheral modules. It is used by passing in the physical address as x + * and returning the virtual address. If the physical address is not mapped, + * it returns 0xDEADBEEF + */ + +#define MXC91231_IO_ADDRESS(x) \ + (void __iomem *) \ + (MXC91231_IS_MODULE(x, L2CC) ? MXC91231_L2CC_IO_ADDRESS(x) : \ + MXC91231_IS_MODULE(x, AIPS1) ? MXC91231_AIPS1_IO_ADDRESS(x) : \ + MXC91231_IS_MODULE(x, AIPS2) ? MXC91231_AIPS2_IO_ADDRESS(x) : \ + MXC91231_IS_MODULE(x, SPBA0) ? MXC91231_SPBA0_IO_ADDRESS(x) : \ + MXC91231_IS_MODULE(x, SPBA1) ? MXC91231_SPBA1_IO_ADDRESS(x) : \ + MXC91231_IS_MODULE(x, ROMP) ? MXC91231_ROMP_IO_ADDRESS(x) : \ + MXC91231_IS_MODULE(x, AVIC) ? MXC91231_AVIC_IO_ADDRESS(x) : \ + MXC91231_IS_MODULE(x, X_MEMC) ? MXC91231_X_MEMC_IO_ADDRESS(x) : \ + 0xDEADBEEF) + + +/* + * define the address mapping macros: in physical address order + */ +#define MXC91231_L2CC_IO_ADDRESS(x) \ + (((x) - MXC91231_L2CC_BASE_ADDR) + MXC91231_L2CC_BASE_ADDR_VIRT) + +#define MXC91231_AIPS1_IO_ADDRESS(x) \ + (((x) - MXC91231_AIPS1_BASE_ADDR) + MXC91231_AIPS1_BASE_ADDR_VIRT) + +#define MXC91231_SPBA0_IO_ADDRESS(x) \ + (((x) - MXC91231_SPBA0_BASE_ADDR) + MXC91231_SPBA0_BASE_ADDR_VIRT) + +#define MXC91231_SPBA1_IO_ADDRESS(x) \ + (((x) - MXC91231_SPBA1_BASE_ADDR) + MXC91231_SPBA1_BASE_ADDR_VIRT) + +#define MXC91231_AIPS2_IO_ADDRESS(x) \ + (((x) - MXC91231_AIPS2_BASE_ADDR) + MXC91231_AIPS2_BASE_ADDR_VIRT) + +#define MXC91231_ROMP_IO_ADDRESS(x) \ + (((x) - MXC91231_ROMP_BASE_ADDR) + MXC91231_ROMP_BASE_ADDR_VIRT) + +#define MXC91231_AVIC_IO_ADDRESS(x) \ + (((x) - MXC91231_AVIC_BASE_ADDR) + MXC91231_AVIC_BASE_ADDR_VIRT) + +#define MXC91231_X_MEMC_IO_ADDRESS(x) \ + (((x) - MXC91231_X_MEMC_BASE_ADDR) + MXC91231_X_MEMC_BASE_ADDR_VIRT) + +/* + * Interrupt numbers + */ +#define MXC91231_INT_GPIO3 0 +#define MXC91231_INT_EL1T_CI 1 +#define MXC91231_INT_EL1T_RFCI 2 +#define MXC91231_INT_EL1T_RFI 3 +#define MXC91231_INT_EL1T_MCU 4 +#define MXC91231_INT_EL1T_IPI 5 +#define MXC91231_INT_MU_GEN 6 +#define MXC91231_INT_GPIO4 7 +#define MXC91231_INT_MMC_SDHC2 8 +#define MXC91231_INT_MMC_SDHC1 9 +#define MXC91231_INT_I2C 10 +#define MXC91231_INT_SSI2 11 +#define MXC91231_INT_SSI1 12 +#define MXC91231_INT_CSPI2 13 +#define MXC91231_INT_CSPI1 14 +#define MXC91231_INT_RTIC 15 +#define MXC91231_INT_SAHARA 15 +#define MXC91231_INT_HAC 15 +#define MXC91231_INT_UART3_RX 16 +#define MXC91231_INT_UART3_TX 17 +#define MXC91231_INT_UART3_MINT 18 +#define MXC91231_INT_ECT 19 +#define MXC91231_INT_SIM_IPB 20 +#define MXC91231_INT_SIM_DATA 21 +#define MXC91231_INT_RNGA 22 +#define MXC91231_INT_DSM_AP 23 +#define MXC91231_INT_KPP 24 +#define MXC91231_INT_RTC 25 +#define MXC91231_INT_PWM 26 +#define MXC91231_INT_GEMK_AP 27 +#define MXC91231_INT_EPIT 28 +#define MXC91231_INT_GPT 29 +#define MXC91231_INT_UART2_RX 30 +#define MXC91231_INT_UART2_TX 31 +#define MXC91231_INT_UART2_MINT 32 +#define MXC91231_INT_NANDFC 33 +#define MXC91231_INT_SDMA 34 +#define MXC91231_INT_USB_WAKEUP 35 +#define MXC91231_INT_USB_SOF 36 +#define MXC91231_INT_PMU_EVTMON 37 +#define MXC91231_INT_USB_FUNC 38 +#define MXC91231_INT_USB_DMA 39 +#define MXC91231_INT_USB_CTRL 40 +#define MXC91231_INT_IPU_ERR 41 +#define MXC91231_INT_IPU_SYN 42 +#define MXC91231_INT_UART1_RX 43 +#define MXC91231_INT_UART1_TX 44 +#define MXC91231_INT_UART1_MINT 45 +#define MXC91231_INT_IIM 46 +#define MXC91231_INT_MU_RX_OR 47 +#define MXC91231_INT_MU_TX_OR 48 +#define MXC91231_INT_SCC_SCM 49 +#define MXC91231_INT_SCC_SMN 50 +#define MXC91231_INT_GPIO2 51 +#define MXC91231_INT_GPIO1 52 +#define MXC91231_INT_MQSPI1 53 +#define MXC91231_INT_MQSPI2 54 +#define MXC91231_INT_WDOG2 55 +#define MXC91231_INT_EXT_INT7 56 +#define MXC91231_INT_EXT_INT6 57 +#define MXC91231_INT_EXT_INT5 58 +#define MXC91231_INT_EXT_INT4 59 +#define MXC91231_INT_EXT_INT3 60 +#define MXC91231_INT_EXT_INT2 61 +#define MXC91231_INT_EXT_INT1 62 +#define MXC91231_INT_EXT_INT0 63 + +#define MXC91231_MAX_INT_LINES 63 +#define MXC91231_MAX_EXT_LINES 8 + +#endif /* __MACH_MXC91231_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index e56241af870..ef00199568d 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -21,8 +21,18 @@ #ifndef __ASM_ARCH_MXC_SYSTEM_H__ #define __ASM_ARCH_MXC_SYSTEM_H__ +#include +#include + static inline void arch_idle(void) { +#ifdef CONFIG_ARCH_MXC91231 + if (cpu_is_mxc91231()) { + /* Need this to set DSM low-power mode */ + mxc91231_prepare_idle(); + } +#endif + cpu_do_idle(); } diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index 0707b7d5b5c..527a6c24788 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -28,6 +28,8 @@ #define CLOCK_TICK_RATE 16625000 #elif defined CONFIG_ARCH_MX25 #define CLOCK_TICK_RATE 16000000 +#elif defined CONFIG_ARCH_MXC91231 +#define CLOCK_TICK_RATE 13000000 #endif #endif /* __ASM_ARCH_MXC_TIMEX_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 1e24499f20b..082a3908256 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -66,6 +66,7 @@ static void putc(int ch) #define MX25_UART1_BASE_ADDR 0x43f90000 #define MX2X_UART1_BASE_ADDR 0x1000a000 #define MX3X_UART1_BASE_ADDR 0x43F90000 +#define MX3X_UART2_BASE_ADDR 0x43F94000 static __inline__ void __arch_decomp_setup(unsigned long arch_id) { @@ -95,6 +96,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) case MACH_TYPE_PCM043: uart_base = MX3X_UART1_BASE_ADDR; break; + case MACH_TYPE_MAGX_ZN5: + uart_base = MX3X_UART2_BASE_ADDR; + break; default: break; } diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 15e30532f4a..97f42799fa5 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -27,6 +27,7 @@ #include #include +#include #include #include @@ -39,6 +40,12 @@ void arch_reset(char mode, const char *cmd) { unsigned int wcr_enable; +#ifdef CONFIG_ARCH_MXC91231 + if (cpu_is_mxc91231()) { + mxc91231_arch_reset(mode, cmd); + return; + } +#endif if (cpu_is_mx1()) { wcr_enable = (1 << 0); } else { diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index 59e33a3bf7f..844567ee35f 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c @@ -47,7 +47,7 @@ #define MX2_TSTAT_CAPT (1 << 1) #define MX2_TSTAT_COMP (1 << 0) -/* MX31, MX35, MX25 */ +/* MX31, MX35, MX25, MXC91231 */ #define MX3_TCTL_WAITEN (1 << 3) #define MX3_TCTL_CLK_IPG (1 << 6) #define MX3_TCTL_FRR (1 << 9) -- cgit v1.2.3 From 94da274b4982f5b36b55bde0c76d3ef8233bceda Mon Sep 17 00:00:00 2001 From: Dmitriy Taychenachev Date: Fri, 31 Jul 2009 20:29:23 +0900 Subject: MXC: add iomux pins configuration support for MXC91231 Signed-off-by: Dmitriy Taychenachev Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mxc91231.h | 287 ++++++++++++++++++++++++ 1 file changed, 287 insertions(+) create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mxc91231.h (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h new file mode 100644 index 00000000000..9f13061192c --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h @@ -0,0 +1,287 @@ +/* + * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008 by Sascha Hauer + * Copyright (C) 2009 by Dmitriy Taychenachev + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __MACH_IOMUX_MXC91231_H__ +#define __MACH_IOMUX_MXC91231_H__ + +/* + * various IOMUX output functions + */ + +#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */ +#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */ +#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */ +#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */ +#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */ +#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ +#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ +#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ +#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ +#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ +#define IOMUX_ICONFIG_FUNC 2 /* used as function */ +#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ +#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */ + +#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO) +#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC) +#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1) +#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2) + +/* + * setups a single pin: + * - reserves the pin so that it is not claimed by another driver + * - setups the iomux according to the configuration + * - if the pin is configured as a GPIO, we claim it throug kernel gpiolib + */ +int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label); +/* + * setups mutliple pins + * convenient way to call the above function with tables + */ +int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, + const char *label); + +/* + * releases a single pin: + * - make it available for a future use by another driver + * - frees the GPIO if the pin was configured as GPIO + * - DOES NOT reconfigure the IOMUX in its reset state + */ +void mxc_iomux_release_pin(const unsigned int pin_mode); +/* + * releases multiple pins + * convenvient way to call the above function with tables + */ +void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count); + +#define MUX_SIDE_AP (0) +#define MUX_SIDE_SP (1) + +#define MUX_SIDE_SHIFT (26) +#define MUX_SIDE_MASK (0x1 << MUX_SIDE_SHIFT) + +#define MUX_GPIO_PORT_SHIFT (23) +#define MUX_GPIO_PORT_MASK (0x7 << MUX_GPIO_PORT_SHIFT) + +#define MUX_GPIO_PIN_SHIFT (20) +#define MUX_GPIO_PIN_MASK (0x1f << MUX_GPIO_PIN_SHIFT) + +#define MUX_REG_SHIFT (15) +#define MUX_REG_MASK (0x1f << MUX_REG_SHIFT) + +#define MUX_FIELD_SHIFT (13) +#define MUX_FIELD_MASK (0x3 << MUX_FIELD_SHIFT) + +#define MUX_PADGRP_SHIFT (8) +#define MUX_PADGRP_MASK (0x1f << MUX_PADGRP_SHIFT) + +#define MUX_PIN_MASK (0xffffff << 8) + +#define GPIO_PORT_MAX (3) + +#define IOMUX_PIN(side, gport, gpin, ctlreg, ctlfield, padgrp) \ + (((side) << MUX_SIDE_SHIFT) | \ + (gport << MUX_GPIO_PORT_SHIFT) | \ + ((gpin) << MUX_GPIO_PIN_SHIFT) | \ + ((ctlreg) << MUX_REG_SHIFT) | \ + ((ctlfield) << MUX_FIELD_SHIFT) | \ + ((padgrp) << MUX_PADGRP_SHIFT)) + +#define MUX_MODE_OUT_SHIFT (4) +#define MUX_MODE_IN_SHIFT (0) +#define MUX_MODE_SHIFT (0) +#define MUX_MODE_MASK (0xff << MUX_MODE_SHIFT) + +#define IOMUX_MODE(pin, mode) \ + (pin | (mode << MUX_MODE_SHIFT)) + +enum iomux_pins { + /* AP Side pins */ + MXC91231_PIN_AP_CLE = IOMUX_PIN(0, 0, 0, 0, 0, 24), + MXC91231_PIN_AP_ALE = IOMUX_PIN(0, 0, 1, 0, 1, 24), + MXC91231_PIN_AP_CE_B = IOMUX_PIN(0, 0, 2, 0, 2, 24), + MXC91231_PIN_AP_RE_B = IOMUX_PIN(0, 0, 3, 0, 3, 24), + MXC91231_PIN_AP_WE_B = IOMUX_PIN(0, 0, 4, 1, 0, 24), + MXC91231_PIN_AP_WP_B = IOMUX_PIN(0, 0, 5, 1, 1, 24), + MXC91231_PIN_AP_BSY_B = IOMUX_PIN(0, 0, 6, 1, 2, 24), + MXC91231_PIN_AP_U1_TXD = IOMUX_PIN(0, 0, 7, 1, 3, 28), + MXC91231_PIN_AP_U1_RXD = IOMUX_PIN(0, 0, 8, 2, 0, 28), + MXC91231_PIN_AP_U1_RTS_B = IOMUX_PIN(0, 0, 9, 2, 1, 28), + MXC91231_PIN_AP_U1_CTS_B = IOMUX_PIN(0, 0, 10, 2, 2, 28), + MXC91231_PIN_AP_AD1_TXD = IOMUX_PIN(0, 0, 11, 2, 3, 9), + MXC91231_PIN_AP_AD1_RXD = IOMUX_PIN(0, 0, 12, 3, 0, 9), + MXC91231_PIN_AP_AD1_TXC = IOMUX_PIN(0, 0, 13, 3, 1, 9), + MXC91231_PIN_AP_AD1_TXFS = IOMUX_PIN(0, 0, 14, 3, 2, 9), + MXC91231_PIN_AP_AD2_TXD = IOMUX_PIN(0, 0, 15, 3, 3, 9), + MXC91231_PIN_AP_AD2_RXD = IOMUX_PIN(0, 0, 16, 4, 0, 9), + MXC91231_PIN_AP_AD2_TXC = IOMUX_PIN(0, 0, 17, 4, 1, 9), + MXC91231_PIN_AP_AD2_TXFS = IOMUX_PIN(0, 0, 18, 4, 2, 9), + MXC91231_PIN_AP_OWDAT = IOMUX_PIN(0, 0, 19, 4, 3, 28), + MXC91231_PIN_AP_IPU_LD17 = IOMUX_PIN(0, 0, 20, 5, 0, 28), + MXC91231_PIN_AP_IPU_D3_VSYNC = IOMUX_PIN(0, 0, 21, 5, 1, 28), + MXC91231_PIN_AP_IPU_D3_HSYNC = IOMUX_PIN(0, 0, 22, 5, 2, 28), + MXC91231_PIN_AP_IPU_D3_CLK = IOMUX_PIN(0, 0, 23, 5, 3, 28), + MXC91231_PIN_AP_IPU_D3_DRDY = IOMUX_PIN(0, 0, 24, 6, 0, 28), + MXC91231_PIN_AP_IPU_D3_CONTR = IOMUX_PIN(0, 0, 25, 6, 1, 28), + MXC91231_PIN_AP_IPU_D0_CS = IOMUX_PIN(0, 0, 26, 6, 2, 28), + MXC91231_PIN_AP_IPU_LD16 = IOMUX_PIN(0, 0, 27, 6, 3, 28), + MXC91231_PIN_AP_IPU_D2_CS = IOMUX_PIN(0, 0, 28, 7, 0, 28), + MXC91231_PIN_AP_IPU_PAR_RS = IOMUX_PIN(0, 0, 29, 7, 1, 28), + MXC91231_PIN_AP_IPU_D3_PS = IOMUX_PIN(0, 0, 30, 7, 2, 28), + MXC91231_PIN_AP_IPU_D3_CLS = IOMUX_PIN(0, 0, 31, 7, 3, 28), + MXC91231_PIN_AP_IPU_RD = IOMUX_PIN(0, 1, 0, 8, 0, 28), + MXC91231_PIN_AP_IPU_WR = IOMUX_PIN(0, 1, 1, 8, 1, 28), + MXC91231_PIN_AP_IPU_LD0 = IOMUX_PIN(0, 7, 0, 8, 2, 28), + MXC91231_PIN_AP_IPU_LD1 = IOMUX_PIN(0, 7, 0, 8, 3, 28), + MXC91231_PIN_AP_IPU_LD2 = IOMUX_PIN(0, 7, 0, 9, 0, 28), + MXC91231_PIN_AP_IPU_LD3 = IOMUX_PIN(0, 1, 2, 9, 1, 28), + MXC91231_PIN_AP_IPU_LD4 = IOMUX_PIN(0, 1, 3, 9, 2, 28), + MXC91231_PIN_AP_IPU_LD5 = IOMUX_PIN(0, 1, 4, 9, 3, 28), + MXC91231_PIN_AP_IPU_LD6 = IOMUX_PIN(0, 1, 5, 10, 0, 28), + MXC91231_PIN_AP_IPU_LD7 = IOMUX_PIN(0, 1, 6, 10, 1, 28), + MXC91231_PIN_AP_IPU_LD8 = IOMUX_PIN(0, 1, 7, 10, 2, 28), + MXC91231_PIN_AP_IPU_LD9 = IOMUX_PIN(0, 1, 8, 10, 3, 28), + MXC91231_PIN_AP_IPU_LD10 = IOMUX_PIN(0, 1, 9, 11, 0, 28), + MXC91231_PIN_AP_IPU_LD11 = IOMUX_PIN(0, 1, 10, 11, 1, 28), + MXC91231_PIN_AP_IPU_LD12 = IOMUX_PIN(0, 1, 11, 11, 2, 28), + MXC91231_PIN_AP_IPU_LD13 = IOMUX_PIN(0, 1, 12, 11, 3, 28), + MXC91231_PIN_AP_IPU_LD14 = IOMUX_PIN(0, 1, 13, 12, 0, 28), + MXC91231_PIN_AP_IPU_LD15 = IOMUX_PIN(0, 1, 14, 12, 1, 28), + MXC91231_PIN_AP_KPROW4 = IOMUX_PIN(0, 7, 0, 12, 2, 10), + MXC91231_PIN_AP_KPROW5 = IOMUX_PIN(0, 1, 16, 12, 3, 10), + MXC91231_PIN_AP_GPIO_AP_B17 = IOMUX_PIN(0, 1, 17, 13, 0, 10), + MXC91231_PIN_AP_GPIO_AP_B18 = IOMUX_PIN(0, 1, 18, 13, 1, 10), + MXC91231_PIN_AP_KPCOL3 = IOMUX_PIN(0, 1, 19, 13, 2, 11), + MXC91231_PIN_AP_KPCOL4 = IOMUX_PIN(0, 1, 20, 13, 3, 11), + MXC91231_PIN_AP_KPCOL5 = IOMUX_PIN(0, 1, 21, 14, 0, 11), + MXC91231_PIN_AP_GPIO_AP_B22 = IOMUX_PIN(0, 1, 22, 14, 1, 11), + MXC91231_PIN_AP_GPIO_AP_B23 = IOMUX_PIN(0, 1, 23, 14, 2, 11), + MXC91231_PIN_AP_CSI_D0 = IOMUX_PIN(0, 1, 24, 14, 3, 21), + MXC91231_PIN_AP_CSI_D1 = IOMUX_PIN(0, 1, 25, 15, 0, 21), + MXC91231_PIN_AP_CSI_D2 = IOMUX_PIN(0, 1, 26, 15, 1, 21), + MXC91231_PIN_AP_CSI_D3 = IOMUX_PIN(0, 1, 27, 15, 2, 21), + MXC91231_PIN_AP_CSI_D4 = IOMUX_PIN(0, 1, 28, 15, 3, 21), + MXC91231_PIN_AP_CSI_D5 = IOMUX_PIN(0, 1, 29, 16, 0, 21), + MXC91231_PIN_AP_CSI_D6 = IOMUX_PIN(0, 1, 30, 16, 1, 21), + MXC91231_PIN_AP_CSI_D7 = IOMUX_PIN(0, 1, 31, 16, 2, 21), + MXC91231_PIN_AP_CSI_D8 = IOMUX_PIN(0, 2, 0, 16, 3, 21), + MXC91231_PIN_AP_CSI_D9 = IOMUX_PIN(0, 2, 1, 17, 0, 21), + MXC91231_PIN_AP_CSI_MCLK = IOMUX_PIN(0, 2, 2, 17, 1, 21), + MXC91231_PIN_AP_CSI_VSYNC = IOMUX_PIN(0, 2, 3, 17, 2, 21), + MXC91231_PIN_AP_CSI_HSYNC = IOMUX_PIN(0, 2, 4, 17, 3, 21), + MXC91231_PIN_AP_CSI_PIXCLK = IOMUX_PIN(0, 2, 5, 18, 0, 21), + MXC91231_PIN_AP_I2CLK = IOMUX_PIN(0, 2, 6, 18, 1, 12), + MXC91231_PIN_AP_I2DAT = IOMUX_PIN(0, 2, 7, 18, 2, 12), + MXC91231_PIN_AP_GPIO_AP_C8 = IOMUX_PIN(0, 2, 8, 18, 3, 9), + MXC91231_PIN_AP_GPIO_AP_C9 = IOMUX_PIN(0, 2, 9, 19, 0, 9), + MXC91231_PIN_AP_GPIO_AP_C10 = IOMUX_PIN(0, 2, 10, 19, 1, 9), + MXC91231_PIN_AP_GPIO_AP_C11 = IOMUX_PIN(0, 2, 11, 19, 2, 9), + MXC91231_PIN_AP_GPIO_AP_C12 = IOMUX_PIN(0, 2, 12, 19, 3, 9), + MXC91231_PIN_AP_GPIO_AP_C13 = IOMUX_PIN(0, 2, 13, 20, 0, 28), + MXC91231_PIN_AP_GPIO_AP_C14 = IOMUX_PIN(0, 2, 14, 20, 1, 28), + MXC91231_PIN_AP_GPIO_AP_C15 = IOMUX_PIN(0, 2, 15, 20, 2, 9), + MXC91231_PIN_AP_GPIO_AP_C16 = IOMUX_PIN(0, 2, 16, 20, 3, 9), + MXC91231_PIN_AP_GPIO_AP_C17 = IOMUX_PIN(0, 2, 17, 21, 0, 9), + MXC91231_PIN_AP_ED_INT0 = IOMUX_PIN(0, 2, 18, 21, 1, 22), + MXC91231_PIN_AP_ED_INT1 = IOMUX_PIN(0, 2, 19, 21, 2, 22), + MXC91231_PIN_AP_ED_INT2 = IOMUX_PIN(0, 2, 20, 21, 3, 22), + MXC91231_PIN_AP_ED_INT3 = IOMUX_PIN(0, 2, 21, 22, 0, 22), + MXC91231_PIN_AP_ED_INT4 = IOMUX_PIN(0, 2, 22, 22, 1, 23), + MXC91231_PIN_AP_ED_INT5 = IOMUX_PIN(0, 2, 23, 22, 2, 23), + MXC91231_PIN_AP_ED_INT6 = IOMUX_PIN(0, 2, 24, 22, 3, 23), + MXC91231_PIN_AP_ED_INT7 = IOMUX_PIN(0, 2, 25, 23, 0, 23), + MXC91231_PIN_AP_U2_DSR_B = IOMUX_PIN(0, 2, 26, 23, 1, 28), + MXC91231_PIN_AP_U2_RI_B = IOMUX_PIN(0, 2, 27, 23, 2, 28), + MXC91231_PIN_AP_U2_CTS_B = IOMUX_PIN(0, 2, 28, 23, 3, 28), + MXC91231_PIN_AP_U2_DTR_B = IOMUX_PIN(0, 2, 29, 24, 0, 28), + MXC91231_PIN_AP_KPROW0 = IOMUX_PIN(0, 7, 0, 24, 1, 10), + MXC91231_PIN_AP_KPROW1 = IOMUX_PIN(0, 1, 15, 24, 2, 10), + MXC91231_PIN_AP_KPROW2 = IOMUX_PIN(0, 7, 0, 24, 3, 10), + MXC91231_PIN_AP_KPROW3 = IOMUX_PIN(0, 7, 0, 25, 0, 10), + MXC91231_PIN_AP_KPCOL0 = IOMUX_PIN(0, 7, 0, 25, 1, 11), + MXC91231_PIN_AP_KPCOL1 = IOMUX_PIN(0, 7, 0, 25, 2, 11), + MXC91231_PIN_AP_KPCOL2 = IOMUX_PIN(0, 7, 0, 25, 3, 11), + + /* Shared pins */ + MXC91231_PIN_SP_U3_TXD = IOMUX_PIN(1, 3, 0, 0, 0, 28), + MXC91231_PIN_SP_U3_RXD = IOMUX_PIN(1, 3, 1, 0, 1, 28), + MXC91231_PIN_SP_U3_RTS_B = IOMUX_PIN(1, 3, 2, 0, 2, 28), + MXC91231_PIN_SP_U3_CTS_B = IOMUX_PIN(1, 3, 3, 0, 3, 28), + MXC91231_PIN_SP_USB_TXOE_B = IOMUX_PIN(1, 3, 4, 1, 0, 28), + MXC91231_PIN_SP_USB_DAT_VP = IOMUX_PIN(1, 3, 5, 1, 1, 28), + MXC91231_PIN_SP_USB_SE0_VM = IOMUX_PIN(1, 3, 6, 1, 2, 28), + MXC91231_PIN_SP_USB_RXD = IOMUX_PIN(1, 3, 7, 1, 3, 28), + MXC91231_PIN_SP_UH2_TXOE_B = IOMUX_PIN(1, 3, 8, 2, 0, 28), + MXC91231_PIN_SP_UH2_SPEED = IOMUX_PIN(1, 3, 9, 2, 1, 28), + MXC91231_PIN_SP_UH2_SUSPEN = IOMUX_PIN(1, 3, 10, 2, 2, 28), + MXC91231_PIN_SP_UH2_TXDP = IOMUX_PIN(1, 3, 11, 2, 3, 28), + MXC91231_PIN_SP_UH2_RXDP = IOMUX_PIN(1, 3, 12, 3, 0, 28), + MXC91231_PIN_SP_UH2_RXDM = IOMUX_PIN(1, 3, 13, 3, 1, 28), + MXC91231_PIN_SP_UH2_OVR = IOMUX_PIN(1, 3, 14, 3, 2, 28), + MXC91231_PIN_SP_UH2_PWR = IOMUX_PIN(1, 3, 15, 3, 3, 28), + MXC91231_PIN_SP_SD1_DAT0 = IOMUX_PIN(1, 3, 16, 4, 0, 25), + MXC91231_PIN_SP_SD1_DAT1 = IOMUX_PIN(1, 3, 17, 4, 1, 25), + MXC91231_PIN_SP_SD1_DAT2 = IOMUX_PIN(1, 3, 18, 4, 2, 25), + MXC91231_PIN_SP_SD1_DAT3 = IOMUX_PIN(1, 3, 19, 4, 3, 25), + MXC91231_PIN_SP_SD1_CMD = IOMUX_PIN(1, 3, 20, 5, 0, 25), + MXC91231_PIN_SP_SD1_CLK = IOMUX_PIN(1, 3, 21, 5, 1, 25), + MXC91231_PIN_SP_SD2_DAT0 = IOMUX_PIN(1, 3, 22, 5, 2, 26), + MXC91231_PIN_SP_SD2_DAT1 = IOMUX_PIN(1, 3, 23, 5, 3, 26), + MXC91231_PIN_SP_SD2_DAT2 = IOMUX_PIN(1, 3, 24, 6, 0, 26), + MXC91231_PIN_SP_SD2_DAT3 = IOMUX_PIN(1, 3, 25, 6, 1, 26), + MXC91231_PIN_SP_GPIO_SP_A26 = IOMUX_PIN(1, 3, 26, 6, 2, 28), + MXC91231_PIN_SP_SPI1_CLK = IOMUX_PIN(1, 3, 27, 6, 3, 13), + MXC91231_PIN_SP_SPI1_MOSI = IOMUX_PIN(1, 3, 28, 7, 0, 13), + MXC91231_PIN_SP_SPI1_MISO = IOMUX_PIN(1, 3, 29, 7, 1, 13), + MXC91231_PIN_SP_SPI1_SS0 = IOMUX_PIN(1, 3, 30, 7, 2, 13), + MXC91231_PIN_SP_SPI1_SS1 = IOMUX_PIN(1, 3, 31, 7, 3, 13), + MXC91231_PIN_SP_SD2_CMD = IOMUX_PIN(1, 7, 0, 8, 0, 26), + MXC91231_PIN_SP_SD2_CLK = IOMUX_PIN(1, 7, 0, 8, 1, 26), + MXC91231_PIN_SP_SIM1_RST_B = IOMUX_PIN(1, 2, 30, 8, 2, 28), + MXC91231_PIN_SP_SIM1_SVEN = IOMUX_PIN(1, 7, 0, 8, 3, 28), + MXC91231_PIN_SP_SIM1_CLK = IOMUX_PIN(1, 7, 0, 9, 0, 28), + MXC91231_PIN_SP_SIM1_TRXD = IOMUX_PIN(1, 7, 0, 9, 1, 28), + MXC91231_PIN_SP_SIM1_PD = IOMUX_PIN(1, 2, 31, 9, 2, 28), + MXC91231_PIN_SP_UH2_TXDM = IOMUX_PIN(1, 7, 0, 9, 3, 28), + MXC91231_PIN_SP_UH2_RXD = IOMUX_PIN(1, 7, 0, 10, 0, 28), +}; + +#define PIN_AP_MAX (104) +#define PIN_SP_MAX (41) + +#define PIN_MAX (PIN_AP_MAX + PIN_SP_MAX) + +/* + * Convenience values for use with mxc_iomux_mode() + * + * Format here is MXC91231_PIN_(pin name)__(function) + */ + +#define MXC91231_PIN_SP_USB_DAT_VP__USB_DAT_VP \ + IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_FUNC) +#define MXC91231_PIN_SP_USB_SE0_VM__USB_SE0_VM \ + IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_FUNC) +#define MXC91231_PIN_SP_USB_DAT_VP__RXD2 \ + IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_ALT1) +#define MXC91231_PIN_SP_USB_SE0_VM__TXD2 \ + IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_ALT1) + + +#endif /* __MACH_IOMUX_MXC91231_H__ */ -- cgit v1.2.3 From 89829d5fe31dc42825f2560c3c2c641709ed594e Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Mon, 10 Aug 2009 18:33:10 +0200 Subject: mx31: added one more pin definition Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx3.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index a3b206ce78b..67452732794 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -682,6 +682,7 @@ enum iomux_pins { #define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) #define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) #define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO) /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 * cspi1_ss1*/ -- cgit v1.2.3 From 7bc07ebc7d2e9ad57baf205840ce31e9243ed5e8 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 17 Apr 2009 16:52:25 +0200 Subject: mx3x: Fixup USB base addresses The i.MX31 and the i.MX35 have different USB base addresses. Adjust the resources accordingly. Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/mx31.h | 2 +- arch/arm/plat-mxc/include/mach/mx35.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 0b06941b613..14ac0dcc82f 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -4,7 +4,7 @@ #define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ #define MX31_IRAM_SIZE SZ_16K -#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) +#define MX31_OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) #define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) #define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 6465fefb42e..ab4cfec6c8a 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -5,6 +5,7 @@ #define MX35_IRAM_SIZE SZ_128K #define MXC_FEC_BASE_ADDR 0x50038000 +#define MX35_OTG_BASE_ADDR 0x53ff4000 #define MX35_NFC_BASE_ADDR 0xBB000000 /* -- cgit v1.2.3 From 4bd1527a64f847a8aaec4f6055d9498db2646626 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Wed, 12 Aug 2009 11:29:18 +0200 Subject: mx31: define various GPIOs used on mx31moboard Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx3.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index 67452732794..446f8676381 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -683,6 +683,17 @@ enum iomux_pins { #define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) #define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) #define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SRX0__GPIO2_2 IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SIMPD0__GPIO2_3 IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_DTR_DCE1__GPIO2_8 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) + /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 * cspi1_ss1*/ -- cgit v1.2.3