From 699a714501f028b1db2bf741111a0df856128899 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 30 Jul 2007 02:38:47 +0100 Subject: [ARM] 4533/1: AT91x40 timer support Support for the timers in the Atmel AT91x40 family of CPUs. Signed-off-by: Greg Ungerer Acked-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/mach-at91/at91x40_time.c | 80 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 arch/arm/mach-at91/at91x40_time.c (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c new file mode 100644 index 00000000000..eddc882f1b4 --- /dev/null +++ b/arch/arm/mach-at91/at91x40_time.c @@ -0,0 +1,80 @@ +/* + * arch/arm/mach-at91/at91x40_time.c + * + * (C) Copyright 2007, Greg Ungerer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * 3 counter/timer units present. + */ +#define AT91_TC_CLK0BASE 0 +#define AT91_TC_CLK1BASE 0x40 +#define AT91_TC_CLK2BASE 0x80 + +static unsigned long at91x40_gettimeoffset(void) +{ + return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128)); +} + +static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id) +{ + at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR); + timer_tick(); + return IRQ_HANDLED; +} + +static struct irqaction at91x40_timer_irq = { + .name = "at91_tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = at91x40_timer_interrupt +}; + +void __init at91x40_timer_init(void) +{ + unsigned int v; + + at91_sys_write(AT91_TC + AT91_TC_BCR, 0); + v = at91_sys_read(AT91_TC + AT91_TC_BMR); + v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE; + at91_sys_write(AT91_TC + AT91_TC_BMR, v); + + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS); + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG)); + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff); + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1); + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4)); + + setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq); + + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN)); +} + +struct sys_timer at91x40_timer = { + .init = at91x40_timer_init, + .offset = at91x40_gettimeoffset, +}; + -- cgit v1.2.3