From f099f39acf7575eff3dee3c562cec4e592876c33 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 9 Oct 2008 14:11:57 +0800 Subject: Blackfin arch: Make L2 SRAM cacheable Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu --- arch/blackfin/include/asm/cplb.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch/blackfin/include') diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index 05d6f05fb74..9e8b4035fce 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h @@ -55,7 +55,13 @@ #endif #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) -#define L2_MEMORY (CPLB_COMMON) +#ifdef CONFIG_BFIN_L2_CACHEABLE +#define L2_IMEMORY (SDRAM_IGENERIC) +#define L2_DMEMORY (SDRAM_DGENERIC) +#else +#define L2_IMEMORY (CPLB_COMMON) +#define L2_DMEMORY (CPLB_COMMON) +#endif #define SDRAM_DNON_CHBL (CPLB_COMMON) #define SDRAM_EBIU (CPLB_COMMON) #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) -- cgit v1.2.3