From b8a989893cbdeb6c97a7b5af5f38fb0e480235f9 Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Tue, 18 Nov 2008 17:48:22 +0800 Subject: Blackfin arch: SMP supporting patchset: Blackfin CPLB related code Blackfin dual core BF561 processor can support SMP like features. https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like In this patch, we provide SMP extend to Blackfin CPLB related code Signed-off-by: Graf Yang Signed-off-by: Bryan Wu --- arch/blackfin/kernel/cplb-nompu/cacheinit.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch/blackfin/kernel/cplb-nompu/cacheinit.c') diff --git a/arch/blackfin/kernel/cplb-nompu/cacheinit.c b/arch/blackfin/kernel/cplb-nompu/cacheinit.c index bd0831592c2..3a385aec67d 100644 --- a/arch/blackfin/kernel/cplb-nompu/cacheinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cacheinit.c @@ -25,9 +25,9 @@ #include #if defined(CONFIG_BFIN_ICACHE) -void __init bfin_icache_init(void) +void __cpuinit bfin_icache_init(u_long icplb[]) { - unsigned long *table = icplb_table; + unsigned long *table = icplb; unsigned long ctrl; int i; @@ -47,9 +47,9 @@ void __init bfin_icache_init(void) #endif #if defined(CONFIG_BFIN_DCACHE) -void __init bfin_dcache_init(void) +void __cpuinit bfin_dcache_init(u_long dcplb[]) { - unsigned long *table = dcplb_table; + unsigned long *table = dcplb; unsigned long ctrl; int i; @@ -64,6 +64,7 @@ void __init bfin_dcache_init(void) ctrl = bfin_read_DMEM_CONTROL(); ctrl |= DMEM_CNTR; bfin_write_DMEM_CONTROL(ctrl); + SSYNC(); } #endif -- cgit v1.2.3