From aa6f5ffbdba45aa8e19e5048648fc6c7b25376d3 Mon Sep 17 00:00:00 2001 From: merge Date: Thu, 22 Jan 2009 13:55:32 +0000 Subject: MERGE-via-pending-tracking-hist-MERGE-via-stable-tracking-MERGE-via-mokopatches-tracking-fix-stray-endmenu-patch-1232632040-1232632141 pending-tracking-hist top was MERGE-via-stable-tracking-MERGE-via-mokopatches-tracking-fix-stray-endmenu-patch-1232632040-1232632141 / fdf777a63bcb59e0dfd78bfe2c6242e01f6d4eb9 ... parent commitmessage: From: merge MERGE-via-stable-tracking-hist-MERGE-via-mokopatches-tracking-fix-stray-endmenu-patch-1232632040 stable-tracking-hist top was MERGE-via-mokopatches-tracking-fix-stray-endmenu-patch-1232632040 / 90463bfd2d5a3c8b52f6e6d71024a00e052b0ced ... parent commitmessage: From: merge MERGE-via-mokopatches-tracking-hist-fix-stray-endmenu-patch mokopatches-tracking-hist top was fix-stray-endmenu-patch / 3630e0be570de8057e7f8d2fe501ed353cdf34e6 ... parent commitmessage: From: Andy Green fix-stray-endmenu.patch Signed-off-by: Andy Green --- arch/blackfin/mach-bf548/Kconfig | 2 +- arch/blackfin/mach-bf548/Makefile | 2 - arch/blackfin/mach-bf548/boards/cm_bf548.c | 166 +++++++++++++- arch/blackfin/mach-bf548/boards/ezkit.c | 156 ++++++++++--- arch/blackfin/mach-bf548/dma.c | 2 +- arch/blackfin/mach-bf548/head.S | 158 ------------- arch/blackfin/mach-bf548/include/mach/anomaly.h | 5 + arch/blackfin/mach-bf548/include/mach/bf548.h | 2 +- arch/blackfin/mach-bf548/include/mach/bfin_sir.h | 166 -------------- arch/blackfin/mach-bf548/include/mach/blackfin.h | 2 +- .../mach-bf548/include/mach/cdefBF54x_base.h | 114 ++++----- arch/blackfin/mach-bf548/include/mach/dma.h | 32 +-- arch/blackfin/mach-bf548/include/mach/irq.h | 2 +- arch/blackfin/mach-bf548/include/mach/mem_init.h | 255 --------------------- arch/blackfin/mach-bf548/include/mach/mem_map.h | 6 + 15 files changed, 353 insertions(+), 717 deletions(-) delete mode 100644 arch/blackfin/mach-bf548/head.S delete mode 100644 arch/blackfin/mach-bf548/include/mach/bfin_sir.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/mem_init.h (limited to 'arch/blackfin/mach-bf548') diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig index 1bfcd8f646a..dcf65715905 100644 --- a/arch/blackfin/mach-bf548/Kconfig +++ b/arch/blackfin/mach-bf548/Kconfig @@ -250,7 +250,7 @@ config IRQ_OTPSEC default 11 config IRQ_TIMER0 int "IRQ_TIMER0" - default 11 + default 8 config IRQ_TIMER1 int "IRQ_TIMER1" default 11 diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile index 68e5478e95a..56994b675f9 100644 --- a/arch/blackfin/mach-bf548/Makefile +++ b/arch/blackfin/mach-bf548/Makefile @@ -2,6 +2,4 @@ # arch/blackfin/mach-bf537/Makefile # -extra-y := head.o - obj-y := ints-priority.o dma.o diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c index 24192aaa927..f53ad682530 100644 --- a/arch/blackfin/mach-bf548/boards/cm_bf548.c +++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -42,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -186,44 +188,107 @@ static struct platform_device bfin_uart_device = { #endif #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) -static struct resource bfin_sir_resources[] = { #ifdef CONFIG_BFIN_SIR0 +static struct resource bfin_sir0_resources[] = { { .start = 0xFFC00400, .end = 0xFFC004FF, .flags = IORESOURCE_MEM, }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX+1, + .flags = IORESOURCE_DMA, + }, +}; +static struct platform_device bfin_sir0_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir0_resources), + .resource = bfin_sir0_resources, +}; #endif #ifdef CONFIG_BFIN_SIR1 +static struct resource bfin_sir1_resources[] = { { .start = 0xFFC02000, .end = 0xFFC020FF, .flags = IORESOURCE_MEM, }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX+1, + .flags = IORESOURCE_DMA, + }, +}; +static struct platform_device bfin_sir1_device = { + .name = "bfin_sir", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_sir1_resources), + .resource = bfin_sir1_resources, +}; #endif #ifdef CONFIG_BFIN_SIR2 +static struct resource bfin_sir2_resources[] = { { .start = 0xFFC02100, .end = 0xFFC021FF, .flags = IORESOURCE_MEM, }, + { + .start = IRQ_UART2_RX, + .end = IRQ_UART2_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART2_RX, + .end = CH_UART2_RX+1, + .flags = IORESOURCE_DMA, + }, +}; +static struct platform_device bfin_sir2_device = { + .name = "bfin_sir", + .id = 2, + .num_resources = ARRAY_SIZE(bfin_sir2_resources), + .resource = bfin_sir2_resources, +}; #endif #ifdef CONFIG_BFIN_SIR3 +static struct resource bfin_sir3_resources[] = { { .start = 0xFFC03100, .end = 0xFFC031FF, .flags = IORESOURCE_MEM, }, -#endif + { + .start = IRQ_UART3_RX, + .end = IRQ_UART3_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART3_RX, + .end = CH_UART3_RX+1, + .flags = IORESOURCE_DMA, + }, }; - -static struct platform_device bfin_sir_device = { +static struct platform_device bfin_sir3_device = { .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir_resources), - .resource = bfin_sir_resources, + .id = 3, + .num_resources = ARRAY_SIZE(bfin_sir3_resources), + .resource = bfin_sir3_resources, }; #endif +#endif #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) static struct resource smsc911x_resources[] = { @@ -271,8 +336,8 @@ static struct musb_hdrc_config musb_config = { .dyn_fifo = 0, .soft_con = 1, .dma = 1, - .num_eps = 7, - .dma_channels = 7, + .num_eps = 8, + .dma_channels = 8, .gpio_vrsel = GPIO_PH6, }; @@ -302,6 +367,19 @@ static struct platform_device musb_device = { }; #endif +static struct resource bfin_gpios_resources = { + .start = 0, + .end = MAX_BLACKFIN_GPIOS - 1, + .flags = IORESOURCE_IRQ, +}; + +static struct platform_device bfin_gpios_device = { + .name = "simple-gpio", + .id = -1, + .num_resources = 1, + .resource = &bfin_gpios_resources, +}; + #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) static struct resource bfin_atapi_resources[] = { { @@ -372,9 +450,58 @@ static struct platform_device bf5xx_nand_device = { #endif #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) +static struct bfin_sd_host bfin_sdh_data = { + .dma_chan = CH_SDH, + .irq_int0 = IRQ_SDH_MASK0, + .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0}, +}; + static struct platform_device bf54x_sdh_device = { .name = "bfin-sdh", .id = 0, + .dev = { + .platform_data = &bfin_sdh_data, + }, +}; +#endif + +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) +static struct mtd_partition para_partitions[] = { + { + .name = "bootloader(nor)", + .size = 0x40000, + .offset = 0, + }, { + .name = "linux kernel(nor)", + .size = 0x400000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "file system(nor)", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct physmap_flash_data para_flash_data = { + .width = 2, + .parts = para_partitions, + .nr_parts = ARRAY_SIZE(para_partitions), +}; + +static struct resource para_flash_resource = { + .start = 0x20000000, + .end = 0x207fffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device para_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = ¶_flash_data, + }, + .num_resources = 1, + .resource = ¶_flash_resource, }; #endif @@ -642,7 +769,18 @@ static struct platform_device *cm_bf548_devices[] __initdata = { #endif #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) - &bfin_sir_device, +#ifdef CONFIG_BFIN_SIR0 + &bfin_sir0_device, +#endif +#ifdef CONFIG_BFIN_SIR1 + &bfin_sir1_device, +#endif +#ifdef CONFIG_BFIN_SIR2 + &bfin_sir2_device, +#endif +#ifdef CONFIG_BFIN_SIR3 + &bfin_sir3_device, +#endif #endif #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) @@ -679,7 +817,7 @@ static struct platform_device *cm_bf548_devices[] __initdata = { #endif #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) -/* &i2c_bfin_twi0_device, */ + &i2c_bfin_twi0_device, #if !defined(CONFIG_BF542) &i2c_bfin_twi1_device, #endif @@ -688,6 +826,12 @@ static struct platform_device *cm_bf548_devices[] __initdata = { #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) &bfin_device_gpiokeys, #endif + +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) + ¶_flash_device, +#endif + + &bfin_gpios_device, }; static int __init cm_bf548_init(void) diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 5288187a3ac..309c16014ca 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #include #include @@ -52,16 +53,16 @@ /* * Name the Board for the /proc/cpuinfo */ -const char bfin_board_name[] = "ADSP-BF548-EZKIT"; +const char bfin_board_name[] = "ADI BF548-EZKIT"; /* * Driver needs to know address, irq and flag pin. */ #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) -static struct resource bfin_isp1761_resources[] = { +#include +static struct resource bfin_isp1760_resources[] = { [0] = { - .name = "isp1761-regs", .start = 0x2C0C0000, .end = 0x2C0C0000 + 0xfffff, .flags = IORESOURCE_MEM, @@ -73,32 +74,25 @@ static struct resource bfin_isp1761_resources[] = { }, }; -static struct platform_device bfin_isp1761_device = { - .name = "isp1761", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_isp1761_resources), - .resource = bfin_isp1761_resources, +static struct isp1760_platform_data isp1760_priv = { + .is_isp1761 = 0, + .port1_disable = 0, + .bus_width_16 = 1, + .port1_otg = 0, + .analog_oc = 0, + .dack_polarity_high = 0, + .dreq_polarity_high = 0, }; -static struct platform_device *bfin_isp1761_devices[] = { - &bfin_isp1761_device, +static struct platform_device bfin_isp1760_device = { + .name = "isp1760-hcd", + .id = 0, + .dev = { + .platform_data = &isp1760_priv, + }, + .num_resources = ARRAY_SIZE(bfin_isp1760_resources), + .resource = bfin_isp1760_resources, }; - -int __init bfin_isp1761_init(void) -{ - unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices); - - printk(KERN_INFO "%s(): registering device resources\n", __func__); - set_irq_type(bfin_isp1761_resources[1].start, IRQF_TRIGGER_FALLING); - - return platform_add_devices(bfin_isp1761_devices, num_devices); -} - -void __exit bfin_isp1761_exit(void) -{ - platform_device_unregister(&bfin_isp1761_device); -} -arch_initcall(bfin_isp1761_init); #endif #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) @@ -262,44 +256,107 @@ static struct platform_device bfin_uart_device = { #endif #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) -static struct resource bfin_sir_resources[] = { #ifdef CONFIG_BFIN_SIR0 +static struct resource bfin_sir0_resources[] = { { .start = 0xFFC00400, .end = 0xFFC004FF, .flags = IORESOURCE_MEM, }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX+1, + .flags = IORESOURCE_DMA, + }, +}; +static struct platform_device bfin_sir0_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir0_resources), + .resource = bfin_sir0_resources, +}; #endif #ifdef CONFIG_BFIN_SIR1 +static struct resource bfin_sir1_resources[] = { { .start = 0xFFC02000, .end = 0xFFC020FF, .flags = IORESOURCE_MEM, }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX+1, + .flags = IORESOURCE_DMA, + }, +}; +static struct platform_device bfin_sir1_device = { + .name = "bfin_sir", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_sir1_resources), + .resource = bfin_sir1_resources, +}; #endif #ifdef CONFIG_BFIN_SIR2 +static struct resource bfin_sir2_resources[] = { { .start = 0xFFC02100, .end = 0xFFC021FF, .flags = IORESOURCE_MEM, }, + { + .start = IRQ_UART2_RX, + .end = IRQ_UART2_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART2_RX, + .end = CH_UART2_RX+1, + .flags = IORESOURCE_DMA, + }, +}; +static struct platform_device bfin_sir2_device = { + .name = "bfin_sir", + .id = 2, + .num_resources = ARRAY_SIZE(bfin_sir2_resources), + .resource = bfin_sir2_resources, +}; #endif #ifdef CONFIG_BFIN_SIR3 +static struct resource bfin_sir3_resources[] = { { .start = 0xFFC03100, .end = 0xFFC031FF, .flags = IORESOURCE_MEM, }, -#endif + { + .start = IRQ_UART3_RX, + .end = IRQ_UART3_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART3_RX, + .end = CH_UART3_RX+1, + .flags = IORESOURCE_DMA, + }, }; - -static struct platform_device bfin_sir_device = { +static struct platform_device bfin_sir3_device = { .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir_resources), - .resource = bfin_sir_resources, + .id = 3, + .num_resources = ARRAY_SIZE(bfin_sir3_resources), + .resource = bfin_sir3_resources, }; #endif +#endif #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) static struct resource smsc911x_resources[] = { @@ -347,8 +404,8 @@ static struct musb_hdrc_config musb_config = { .dyn_fifo = 0, .soft_con = 1, .dma = 1, - .num_eps = 7, - .dma_channels = 7, + .num_eps = 8, + .dma_channels = 8, .gpio_vrsel = GPIO_PE7, }; @@ -448,9 +505,19 @@ static struct platform_device bf5xx_nand_device = { #endif #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) + +static struct bfin_sd_host bfin_sdh_data = { + .dma_chan = CH_SDH, + .irq_int0 = IRQ_SDH_MASK0, + .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0}, +}; + static struct platform_device bf54x_sdh_device = { .name = "bfin-sdh", .id = 0, + .dev = { + .platform_data = &bfin_sdh_data, + }, }; #endif @@ -589,7 +656,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { { .modalias = "ad7877", .platform_data = &bfin_ad7877_ts_info, - .irq = IRQ_PJ11, /* newer boards (Rev 1.4+) use IRQ_PB4 */ + .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */ .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 2, @@ -812,7 +879,18 @@ static struct platform_device *ezkit_devices[] __initdata = { #endif #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) - &bfin_sir_device, +#ifdef CONFIG_BFIN_SIR0 + &bfin_sir0_device, +#endif +#ifdef CONFIG_BFIN_SIR1 + &bfin_sir1_device, +#endif +#ifdef CONFIG_BFIN_SIR2 + &bfin_sir2_device, +#endif +#ifdef CONFIG_BFIN_SIR3 + &bfin_sir3_device, +#endif #endif #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) @@ -827,6 +905,10 @@ static struct platform_device *ezkit_devices[] __initdata = { &musb_device, #endif +#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) + &bfin_isp1760_device, +#endif + #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) &bfin_atapi_device, #endif diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c index 74730eb8ae1..535980652bf 100644 --- a/arch/blackfin/mach-bf548/dma.c +++ b/arch/blackfin/mach-bf548/dma.c @@ -32,7 +32,7 @@ #include #include -struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { +struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { (struct dma_register *) DMA0_NEXT_DESC_PTR, (struct dma_register *) DMA1_NEXT_DESC_PTR, (struct dma_register *) DMA2_NEXT_DESC_PTR, diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S deleted file mode 100644 index 93b361dff27..00000000000 --- a/arch/blackfin/mach-bf548/head.S +++ /dev/null @@ -1,158 +0,0 @@ -/* - * File: arch/blackfin/mach-bf548/head.S - * Based on: arch/blackfin/mach-bf537/head.S - * Author: Jeff Dionne COPYRIGHT 1998 D. Jeff Dionne - * - * Created: 1998 - * Description: Startup code for Blackfin BF548 - * - * Modified: - * Copyright 2004-2007 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#ifdef CONFIG_BFIN_KERNEL_CLOCK -#include -#include -#endif - -.section .l1.text -#ifdef CONFIG_BFIN_KERNEL_CLOCK -ENTRY(_start_dma_code) - - /* Enable PHY CLK buffer output */ - p0.h = hi(VR_CTL); - p0.l = lo(VR_CTL); - r0.l = w[p0]; - bitset(r0, 14); - w[p0] = r0.l; - ssync; - - p0.h = hi(SIC_IWR0); - p0.l = lo(SIC_IWR0); - r0.l = 0x1; - r0.h = 0x0; - [p0] = r0; - SSYNC; - - /* - * Set PLL_CTL - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK - * - [7] = output delay (add 200ps of delay to mem signals) - * - [6] = input delay (add 200ps of input delay to mem signals) - * - [5] = PDWN : 1=All Clocks off - * - [3] = STOPCK : 1=Core Clock off - * - [1] = PLL_OFF : 1=Disable Power to PLL - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL - * all other bits set to zero - */ - - p0.h = hi(PLL_LOCKCNT); - p0.l = lo(PLL_LOCKCNT); - r0 = 0x300(Z); - w[p0] = r0.l; - ssync; - - /* enable self refresh via SRREQ */ - P2.H = hi(EBIU_RSTCTL); - P2.L = lo(EBIU_RSTCTL); - R0 = [P2]; - BITSET (R0, 3); - [P2] = R0; - SSYNC; - - /* wait for SRACK bit to be set */ -.LSRR_MODE: - R0 = [P2]; - CC = BITTST(R0, 4); - if !CC JUMP .LSRR_MODE; - - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ - r0 = r0 << 9; /* Shift it over, */ - r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ - r0 = r1 | r0; - r1 = PLL_BYPASS; /* Bypass the PLL? */ - r1 = r1 << 8; /* Shift it over */ - r0 = r1 | r0; /* add them all together */ -#ifdef ANOMALY_05000265 - BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */ -#endif - - p0.h = hi(PLL_CTL); - p0.l = lo(PLL_CTL); /* Load the address */ - cli r2; /* Disable interrupts */ - ssync; - w[p0] = r0.l; /* Set the value */ - idle; /* Wait for the PLL to stablize */ - sti r2; /* Enable interrupts */ - -.Lcheck_again: - p0.h = hi(PLL_STAT); - p0.l = lo(PLL_STAT); - R0 = W[P0](Z); - CC = BITTST(R0,5); - if ! CC jump .Lcheck_again; - - /* Configure SCLK & CCLK Dividers */ - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); - p0.h = hi(PLL_DIV); - p0.l = lo(PLL_DIV); - w[p0] = r0.l; - ssync; - - /* disable self refresh by clearing SRREQ */ - P2.H = hi(EBIU_RSTCTL); - P2.L = lo(EBIU_RSTCTL); - R0 = [P2]; - CC = BITTST(R0, 0); - if CC jump .Lskipddrrst; - BITSET (R0, 0); -.Lskipddrrst: - BITCLR (R0, 3); - [P2] = R0; - SSYNC; - - p0.l = lo(EBIU_DDRCTL0); - p0.h = hi(EBIU_DDRCTL0); - r0.l = lo(mem_DDRCTL0); - r0.h = hi(mem_DDRCTL0); - [p0] = r0; - ssync; - - p0.l = lo(EBIU_DDRCTL1); - p0.h = hi(EBIU_DDRCTL1); - r0.l = lo(mem_DDRCTL1); - r0.h = hi(mem_DDRCTL1); - [p0] = r0; - ssync; - - p0.l = lo(EBIU_DDRCTL2); - p0.h = hi(EBIU_DDRCTL2); - r0.l = lo(mem_DDRCTL2); - r0.h = hi(mem_DDRCTL2); - [p0] = r0; - ssync; - - RTS; -ENDPROC(_start_dma_code) -#endif /* CONFIG_BFIN_KERNEL_CLOCK */ diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h index 816b09278f6..3b5430999f4 100644 --- a/arch/blackfin/mach-bf548/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h @@ -157,6 +157,8 @@ #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) /* Software System Reset Corrupts PLL_LOCKCNT Register */ #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) @@ -173,5 +175,8 @@ #define ANOMALY_05000311 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000363 (0) +#define ANOMALY_05000412 (0) +#define ANOMALY_05000432 (0) +#define ANOMALY_05000435 (0) #endif diff --git a/arch/blackfin/mach-bf548/include/mach/bf548.h b/arch/blackfin/mach-bf548/include/mach/bf548.h index 49f9b403d45..f0e56998481 100644 --- a/arch/blackfin/mach-bf548/include/mach/bf548.h +++ b/arch/blackfin/mach-bf548/include/mach/bf548.h @@ -122,7 +122,7 @@ #endif #ifndef CPU -#error Unknown CPU type - This kernel doesn't seem to be configured properly +#error "Unknown CPU type - This kernel doesn't seem to be configured properly" #endif #endif /* __MACH_BF48_H__ */ diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_sir.h b/arch/blackfin/mach-bf548/include/mach/bfin_sir.h deleted file mode 100644 index c41f9cf0026..00000000000 --- a/arch/blackfin/mach-bf548/include/mach/bfin_sir.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Blackfin Infra-red Driver - * - * Copyright 2006-2008 Analog Devices Inc. - * - * Enter bugs at http://blackfin.uclinux.org/ - * - * Licensed under the GPL-2 or later. - * - */ - -#include -#include -#include - -#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) -#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) -#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET) -#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) -#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) -#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR) -#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) - -#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) -#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) -#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v) -#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v) -#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) -#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v) -#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) -#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1) -#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) - -#ifdef CONFIG_SIR_BFIN_DMA -struct dma_rx_buf { - char *buf; - int head; - int tail; - }; -#endif /* CONFIG_SIR_BFIN_DMA */ - -struct bfin_sir_port { - unsigned char __iomem *membase; - unsigned int irq; - unsigned int lsr; - unsigned long clk; - struct net_device *dev; -#ifdef CONFIG_SIR_BFIN_DMA - int tx_done; - struct dma_rx_buf rx_dma_buf; - struct timer_list rx_dma_timer; - int rx_dma_nrows; -#endif /* CONFIG_SIR_BFIN_DMA */ - unsigned int tx_dma_channel; - unsigned int rx_dma_channel; -}; - -struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; - -struct bfin_sir_port_res { - unsigned long base_addr; - int irq; - unsigned int rx_dma_channel; - unsigned int tx_dma_channel; -}; - -struct bfin_sir_port_res bfin_sir_port_resource[] = { -#ifdef CONFIG_BFIN_SIR0 - { - 0xFFC00400, - IRQ_UART0_RX, - CH_UART0_RX, - CH_UART0_TX, - }, -#endif -#ifdef CONFIG_BFIN_SIR1 - { - 0xFFC02000, - IRQ_UART1_RX, - CH_UART1_RX, - CH_UART1_TX, - }, -#endif -#ifdef CONFIG_BFIN_SIR2 - { - 0xFFC02100, - IRQ_UART2_RX, - CH_UART2_RX, - CH_UART2_TX, - }, -#endif -#ifdef CONFIG_BFIN_SIR3 - { - 0xFFC03100, - IRQ_UART3_RX, - CH_UART3_RX, - CH_UART3_TX, - }, -#endif -}; - -int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); - -struct bfin_sir_self { - struct bfin_sir_port *sir_port; - spinlock_t lock; - unsigned int open; - int speed; - int newspeed; - - struct sk_buff *txskb; - struct sk_buff *rxskb; - struct net_device_stats stats; - struct device *dev; - struct irlap_cb *irlap; - struct qos_info qos; - - iobuff_t tx_buff; - iobuff_t rx_buff; - - struct work_struct work; - int mtt; -}; - -#define DRIVER_NAME "bfin_sir" - -static int bfin_sir_hw_init(void) -{ - int ret = -ENODEV; -#ifdef CONFIG_BFIN_SIR0 - ret = peripheral_request(P_UART0_TX, DRIVER_NAME); - if (ret) - return ret; - ret = peripheral_request(P_UART0_RX, DRIVER_NAME); - if (ret) - return ret; -#endif - -#ifdef CONFIG_BFIN_SIR1 - ret = peripheral_request(P_UART1_TX, DRIVER_NAME); - if (ret) - return ret; - ret = peripheral_request(P_UART1_RX, DRIVER_NAME); - if (ret) - return ret; -#endif - -#ifdef CONFIG_BFIN_SIR2 - ret = peripheral_request(P_UART2_TX, DRIVER_NAME); - if (ret) - return ret; - ret = peripheral_request(P_UART2_RX, DRIVER_NAME); - if (ret) - return ret; -#endif - -#ifdef CONFIG_BFIN_SIR3 - ret = peripheral_request(P_UART3_TX, DRIVER_NAME); - if (ret) - return ret; - ret = peripheral_request(P_UART3_RX, DRIVER_NAME); - if (ret) - return ret; -#endif - return ret; -} diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h index d6ee74ac046..0c0e3e2c3c2 100644 --- a/arch/blackfin/mach-bf548/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h @@ -111,7 +111,7 @@ /* UART 0*/ -/* DMA Channnel */ +/* DMA Channel */ #define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX() #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val) #define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX() diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h index 57ac8cb9b1f..6e636c418cb 100644 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h @@ -34,7 +34,6 @@ #include #include "defBF54x_base.h" -#include /* ************************************************************** */ /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ @@ -43,63 +42,9 @@ /* PLL Registers */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -/* Writing to PLL_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_PLL_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1, iwr2; - - if (val == bfin_read_PLL_CTL()) - return; - - local_irq_save(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SIC_IWR0); - iwr1 = bfin_read32(SIC_IWR1); - iwr2 = bfin_read32(SIC_IWR2); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR0, IWR_ENABLE(0)); - bfin_write32(SIC_IWR1, 0); - bfin_write32(SIC_IWR2, 0); - - bfin_write16(PLL_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR0, iwr0); - bfin_write32(SIC_IWR1, iwr1); - bfin_write32(SIC_IWR2, iwr2); - local_irq_restore(flags); -} #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) -/* Writing to VR_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_VR_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1, iwr2; - - if (val == bfin_read_VR_CTL()) - return; - - local_irq_save(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SIC_IWR0); - iwr1 = bfin_read32(SIC_IWR1); - iwr2 = bfin_read32(SIC_IWR2); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR0, IWR_ENABLE(0)); - bfin_write32(SIC_IWR1, 0); - bfin_write32(SIC_IWR2, 0); - - bfin_write16(VR_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR0, iwr0); - bfin_write32(SIC_IWR1, iwr1); - bfin_write32(SIC_IWR2, iwr2); - local_irq_restore(flags); -} #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) @@ -2746,5 +2691,64 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST #define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST +/* These need to be last due to the cdef/linux inter-dependencies */ +#include + +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1, iwr2; + + if (val == bfin_read_PLL_CTL()) + return; + + local_irq_save_hw(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + iwr2 = bfin_read32(SIC_IWR2); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + bfin_write32(SIC_IWR2, 0); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + bfin_write32(SIC_IWR2, iwr2); + local_irq_restore_hw(flags); +} + +/* Writing to VR_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_VR_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1, iwr2; + + if (val == bfin_read_VR_CTL()) + return; + + local_irq_save_hw(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + iwr2 = bfin_read32(SIC_IWR2); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + bfin_write32(SIC_IWR2, 0); + + bfin_write16(VR_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + bfin_write32(SIC_IWR2, iwr2); + local_irq_restore_hw(flags); +} + #endif /* _CDEF_BF54X_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/dma.h b/arch/blackfin/mach-bf548/include/mach/dma.h index 36a2ef7e784..a30d242c739 100644 --- a/arch/blackfin/mach-bf548/include/mach/dma.h +++ b/arch/blackfin/mach-bf548/include/mach/dma.h @@ -1,32 +1,8 @@ -/* - * file: include/asm-blackfin/mach-bf548/dma.h - * based on: - * author: +/* mach/dma.h - arch-specific DMA defines * - * created: - * description: - * system mmr register map - * rev: + * Copyright 2004-2008 Analog Devices Inc. * - * modified: - * - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. + * Licensed under the GPL-2 or later. */ #ifndef _MACH_DMA_H_ @@ -71,6 +47,6 @@ #define CH_MEM_STREAM3_DEST 30 #define CH_MEM_STREAM3_SRC 31 -#define MAX_BLACKFIN_DMA_CHANNEL 32 +#define MAX_DMA_CHANNELS 32 #endif diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h index ad380d1f587..60299a71e09 100644 --- a/arch/blackfin/mach-bf548/include/mach/irq.h +++ b/arch/blackfin/mach-bf548/include/mach/irq.h @@ -158,7 +158,7 @@ Events (highest priority) EMU 0 #define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ #define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ -#define SYS_IRQS IRQ_PINT3 +#define SYS_IRQS IRQ_PINT3 #define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) #define IRQ_PA0 BFIN_PA_IRQ(0) diff --git a/arch/blackfin/mach-bf548/include/mach/mem_init.h b/arch/blackfin/mach-bf548/include/mach/mem_init.h deleted file mode 100644 index ab0b863eee6..00000000000 --- a/arch/blackfin/mach-bf548/include/mach/mem_init.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * File: include/asm-blackfin/mach-bf548/mem_init.h - * Based on: - * Author: - * - * Created: - * Description: - * - * Rev: - * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1) -#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000) -#define DDR_CLK_HZ(x) (1000*1000*1000/x) - -#if (CONFIG_MEM_MT46V32M16_6T) -#define DDR_SIZE DEVSZ_512 -#define DDR_WIDTH DEVWD_16 -#define DDR_MAX_tCK 13 - -#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60)) -#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42)) -#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) -#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72)) -#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) - -#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) -#define DDR_tWTR DDR_TWTR(1) -#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12)) -#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) -#endif - -#if (CONFIG_MEM_MT46V32M16_5B) -#define DDR_SIZE DEVSZ_512 -#define DDR_WIDTH DEVWD_16 -#define DDR_MAX_tCK 13 - -#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55)) -#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40)) -#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) -#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70)) -#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) - -#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) -#define DDR_tWTR DDR_TWTR(2) -#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10)) -#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) -#endif - -#if (CONFIG_MEM_GENERIC_BOARD) -#define DDR_SIZE DEVSZ_512 -#define DDR_WIDTH DEVWD_16 -#define DDR_MAX_tCK 13 - -#define DDR_tRCD DDR_TRCD(3) -#define DDR_tWTR DDR_TWTR(2) -#define DDR_tWR DDR_TWR(2) -#define DDR_tMRD DDR_TMRD(2) -#define DDR_tRP DDR_TRP(3) -#define DDR_tRAS DDR_TRAS(7) -#define DDR_tRC DDR_TRC(10) -#define DDR_tRFC DDR_TRFC(12) -#define DDR_tREFI DDR_TREFI(1288) -#endif - -#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK)) -# error "CONFIG_SCLK_HZ is too small (133333333 Hz)." -#endif - - -#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI) -#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \ - | DDR_tMRD | DDR_tWR | DDR_tRCD) -#define mem_DDRCTL2 DDR_CL - - -#if defined CONFIG_CLKIN_HALF -#define CLKIN_HALF 1 -#else -#define CLKIN_HALF 0 -#endif - -#if defined CONFIG_PLL_BYPASS -#define PLL_BYPASS 1 -#else -#define PLL_BYPASS 0 -#endif - -/***************************************Currently Not Being Used *********************************/ -#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 -#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 -#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) -#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 -#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 - -#if (flash_EBIU_AMBCTL_TT > 3) -#define flash_EBIU_AMBCTL0_TT B0TT_4 -#endif -#if (flash_EBIU_AMBCTL_TT == 3) -#define flash_EBIU_AMBCTL0_TT B0TT_3 -#endif -#if (flash_EBIU_AMBCTL_TT == 2) -#define flash_EBIU_AMBCTL0_TT B0TT_2 -#endif -#if (flash_EBIU_AMBCTL_TT < 2) -#define flash_EBIU_AMBCTL0_TT B0TT_1 -#endif - -#if (flash_EBIU_AMBCTL_ST > 3) -#define flash_EBIU_AMBCTL0_ST B0ST_4 -#endif -#if (flash_EBIU_AMBCTL_ST == 3) -#define flash_EBIU_AMBCTL0_ST B0ST_3 -#endif -#if (flash_EBIU_AMBCTL_ST == 2) -#define flash_EBIU_AMBCTL0_ST B0ST_2 -#endif -#if (flash_EBIU_AMBCTL_ST < 2) -#define flash_EBIU_AMBCTL0_ST B0ST_1 -#endif - -#if (flash_EBIU_AMBCTL_HT > 2) -#define flash_EBIU_AMBCTL0_HT B0HT_3 -#endif -#if (flash_EBIU_AMBCTL_HT == 2) -#define flash_EBIU_AMBCTL0_HT B0HT_2 -#endif -#if (flash_EBIU_AMBCTL_HT == 1) -#define flash_EBIU_AMBCTL0_HT B0HT_1 -#endif -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) -#define flash_EBIU_AMBCTL0_HT B0HT_0 -#endif -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) -#define flash_EBIU_AMBCTL0_HT B0HT_1 -#endif - -#if (flash_EBIU_AMBCTL_WAT > 14) -#define flash_EBIU_AMBCTL0_WAT B0WAT_15 -#endif -#if (flash_EBIU_AMBCTL_WAT == 14) -#define flash_EBIU_AMBCTL0_WAT B0WAT_14 -#endif -#if (flash_EBIU_AMBCTL_WAT == 13) -#define flash_EBIU_AMBCTL0_WAT B0WAT_13 -#endif -#if (flash_EBIU_AMBCTL_WAT == 12) -#define flash_EBIU_AMBCTL0_WAT B0WAT_12 -#endif -#if (flash_EBIU_AMBCTL_WAT == 11) -#define flash_EBIU_AMBCTL0_WAT B0WAT_11 -#endif -#if (flash_EBIU_AMBCTL_WAT == 10) -#define flash_EBIU_AMBCTL0_WAT B0WAT_10 -#endif -#if (flash_EBIU_AMBCTL_WAT == 9) -#define flash_EBIU_AMBCTL0_WAT B0WAT_9 -#endif -#if (flash_EBIU_AMBCTL_WAT == 8) -#define flash_EBIU_AMBCTL0_WAT B0WAT_8 -#endif -#if (flash_EBIU_AMBCTL_WAT == 7) -#define flash_EBIU_AMBCTL0_WAT B0WAT_7 -#endif -#if (flash_EBIU_AMBCTL_WAT == 6) -#define flash_EBIU_AMBCTL0_WAT B0WAT_6 -#endif -#if (flash_EBIU_AMBCTL_WAT == 5) -#define flash_EBIU_AMBCTL0_WAT B0WAT_5 -#endif -#if (flash_EBIU_AMBCTL_WAT == 4) -#define flash_EBIU_AMBCTL0_WAT B0WAT_4 -#endif -#if (flash_EBIU_AMBCTL_WAT == 3) -#define flash_EBIU_AMBCTL0_WAT B0WAT_3 -#endif -#if (flash_EBIU_AMBCTL_WAT == 2) -#define flash_EBIU_AMBCTL0_WAT B0WAT_2 -#endif -#if (flash_EBIU_AMBCTL_WAT == 1) -#define flash_EBIU_AMBCTL0_WAT B0WAT_1 -#endif - -#if (flash_EBIU_AMBCTL_RAT > 14) -#define flash_EBIU_AMBCTL0_RAT B0RAT_15 -#endif -#if (flash_EBIU_AMBCTL_RAT == 14) -#define flash_EBIU_AMBCTL0_RAT B0RAT_14 -#endif -#if (flash_EBIU_AMBCTL_RAT == 13) -#define flash_EBIU_AMBCTL0_RAT B0RAT_13 -#endif -#if (flash_EBIU_AMBCTL_RAT == 12) -#define flash_EBIU_AMBCTL0_RAT B0RAT_12 -#endif -#if (flash_EBIU_AMBCTL_RAT == 11) -#define flash_EBIU_AMBCTL0_RAT B0RAT_11 -#endif -#if (flash_EBIU_AMBCTL_RAT == 10) -#define flash_EBIU_AMBCTL0_RAT B0RAT_10 -#endif -#if (flash_EBIU_AMBCTL_RAT == 9) -#define flash_EBIU_AMBCTL0_RAT B0RAT_9 -#endif -#if (flash_EBIU_AMBCTL_RAT == 8) -#define flash_EBIU_AMBCTL0_RAT B0RAT_8 -#endif -#if (flash_EBIU_AMBCTL_RAT == 7) -#define flash_EBIU_AMBCTL0_RAT B0RAT_7 -#endif -#if (flash_EBIU_AMBCTL_RAT == 6) -#define flash_EBIU_AMBCTL0_RAT B0RAT_6 -#endif -#if (flash_EBIU_AMBCTL_RAT == 5) -#define flash_EBIU_AMBCTL0_RAT B0RAT_5 -#endif -#if (flash_EBIU_AMBCTL_RAT == 4) -#define flash_EBIU_AMBCTL0_RAT B0RAT_4 -#endif -#if (flash_EBIU_AMBCTL_RAT == 3) -#define flash_EBIU_AMBCTL0_RAT B0RAT_3 -#endif -#if (flash_EBIU_AMBCTL_RAT == 2) -#define flash_EBIU_AMBCTL0_RAT B0RAT_2 -#endif -#if (flash_EBIU_AMBCTL_RAT == 1) -#define flash_EBIU_AMBCTL0_RAT B0RAT_1 -#endif - -#define flash_EBIU_AMBCTL0 \ - (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ - flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h index a2228428dc0..70b9c119402 100644 --- a/arch/blackfin/mach-bf548/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf548/include/mach/mem_map.h @@ -108,4 +108,10 @@ #define L1_SCRATCH_START 0xFFB00000 #define L1_SCRATCH_LENGTH 0x1000 +#define GET_PDA_SAFE(preg) \ + preg.l = _cpu_pda; \ + preg.h = _cpu_pda; + +#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) + #endif/* _MEM_MAP_548_H_ */ -- cgit v1.2.3