From 39e96c8835c36b6867b4e18698b06746972cdfcc Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 18 Nov 2008 17:48:22 +0800 Subject: Blackfin arch: fix bug - dmacopy test case fail on all platform The cache code I added flushes 1 line too little if the start address is not aligned to the cache size. Cache align the start address so that when we straddle cache aligns, we get the right count. Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/mach-common/cache.S | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/blackfin/mach-common/cache.S') diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index db532181fbd..d6780b49524 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S @@ -25,9 +25,13 @@ */ .macro do_flush flushins:req optflushins optnopins label + R2 = -L1_CACHE_BYTES; + + /* start = (start & -L1_CACHE_BYTES) */ + R0 = R0 & R2; + /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */ R1 += -1; - R2 = -L1_CACHE_BYTES; R1 = R1 & R2; R1 += L1_CACHE_BYTES; -- cgit v1.2.3 From 7f6b2e7b1ff70bc60cedc9a00b01c1fad5c21371 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 28 Oct 2008 12:29:26 +0800 Subject: Blackfin arch: fix bug - kernel build with write back policy fails to be booted up Make sure IFLUSH is not the last instruction in the hardware loop to avoid infinite core stall. The dcache/icache function that only gets used in writeback mode was putting IFLUSH as the last instruction in the hardware loop ... we know from design that this may often lead to inifite core stalling, so switch the FLUSH/IFLUSH order. Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/mach-common/cache.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/blackfin/mach-common/cache.S') diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index d6780b49524..a028e945041 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S @@ -67,7 +67,7 @@ ENDPROC(_blackfin_icache_flush_range) /* Flush all cache lines assocoiated with this area of memory. */ ENTRY(_blackfin_icache_dcache_flush_range) - do_flush IFLUSH, FLUSH + do_flush FLUSH, IFLUSH ENDPROC(_blackfin_icache_dcache_flush_range) /* Throw away all D-cached data in specified region without any obligation to -- cgit v1.2.3