From 9693a85378b590cc7a4aa2db2174422585c7c8c4 Mon Sep 17 00:00:00 2001 From: Franck Bui-Huu Date: Fri, 2 Feb 2007 17:41:47 +0100 Subject: [MIPS] Add basic SMARTMIPS ASE support This patch adds trivial support for SMARTMIPS extension. This extension is currently implemented by 4KS[CD] CPUs. Basically it saves/restores ACX register, which is part of the SMARTMIPS ASE, when needed. This patch does *not* add any support for Smartmips MMU features. Futhermore this patch does not add explicit support for 4KS[CD] CPUs since they are respectively mips32 and mips32r2 compliant. So with the current processor configuration, a platform that has such CPUs needs to select both configs: CPU_HAS_SMARTMIPS SYS_HAS_CPU_MIPS32_R[12] This is due to the processor configuration which is mixing up all the architecture variants and the processor types. The drawback of this, is that we currently pass '-march=mips32' option to gcc when building a kernel instead of '-march=4ksc' for 4KSC case. This can lead to a kernel image a little bit bigger than required. Signed-off-by: Franck Bui-Huu Signed-off-by: Ralf Baechle --- arch/mips/configs/malta_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/mips/configs/malta_defconfig') diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 8d21bb96349..a5f379d626d 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -145,6 +145,7 @@ CONFIG_SYS_SUPPORTS_MULTITHREADING=y CONFIG_MIPS_MT_FPAFF=y # CONFIG_64BIT_PHYS_ADDR is not set CONFIG_CPU_HAS_LLSC=y +# CONFIG_CPU_HAS_SMARTMIPS is not set CONFIG_CPU_MIPSR2_IRQ_VI=y CONFIG_CPU_MIPSR2_SRS=y CONFIG_CPU_HAS_SYNC=y @@ -152,6 +153,7 @@ CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_IRQ_PER_CPU=y CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_SMARTMIPS=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y -- cgit v1.2.3