From 0db34215c7e0ef618e7b29fbf271194ca5434f8e Mon Sep 17 00:00:00 2001 From: "Kevin D. Kissell" Date: Thu, 12 Jul 2007 16:21:08 +0100 Subject: [MIPS] SMTC: Interrupt mask backstop hack To support multiple TC microthreads acting as "CPUs" within a VPE, VPE-wide interrupt mask bits must be specially manipulated during interrupt handling. To support legacy drivers and interrupt controller management code, SMTC has a "backstop" to track and if necessary restore the interrupt mask. This has some performance impact on interrupt service overhead. Disable it only if you know what you are doing. Signed-off-by: Ralf Baechle --- arch/mips/kernel/entry.S | 2 ++ arch/mips/kernel/genex.S | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S index 686249c5c32..e29598ae939 100644 --- a/arch/mips/kernel/entry.S +++ b/arch/mips/kernel/entry.S @@ -84,6 +84,7 @@ FEXPORT(restore_all) # restore full frame LONG_S sp, TI_REGS($28) jal deferred_smtc_ipi LONG_S s0, TI_REGS($28) +#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP /* Re-arm any temporarily masked interrupts not explicitly "acked" */ mfc0 v0, CP0_TCSTATUS ori v1, v0, TCSTATUS_IXMT @@ -110,6 +111,7 @@ FEXPORT(restore_all) # restore full frame _ehb xor t0, t0, t3 mtc0 t0, CP0_TCCONTEXT +#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */ #endif /* CONFIG_MIPS_MT_SMTC */ .set noat RESTORE_TEMP diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 297bd56c234..c0f19d638b9 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -243,9 +243,11 @@ NESTED(except_vec_vi_handler, 0, sp) */ mfc0 t1, CP0_STATUS and t0, a0, t1 +#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP mfc0 t2, CP0_TCCONTEXT or t0, t0, t2 mtc0 t0, CP0_TCCONTEXT +#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */ xor t1, t1, t0 mtc0 t1, CP0_STATUS _ehb -- cgit v1.2.3