From fa36b04386422951a7c73f9210403d1a2eaffe92 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 24 Oct 2008 19:53:55 +0200 Subject: MIPS: RB532: Set gpio interrupt status and level for CompactFlash This patch sets the correct interrupt status and level in order to get the CompactFlash adapter working. Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle --- arch/mips/rb532/gpio.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/mips/rb532') diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c index 76a7fd96d56..70c4a672637 100644 --- a/arch/mips/rb532/gpio.c +++ b/arch/mips/rb532/gpio.c @@ -310,6 +310,10 @@ int __init rb532_gpio_init(void) return -ENXIO; } + /* Set the interrupt status and level for the CF pin */ + rb532_gpio_set_int_level(&rb532_gpio_chip->chip, CF_GPIO_NUM, 1); + rb532_gpio_set_int_status(&rb532_gpio_chip->chip, CF_GPIO_NUM, 0); + return 0; } arch_initcall(rb532_gpio_init); -- cgit v1.2.3 From bc4c4e832a203f66959e5eb2ecc56b0b9525173e Mon Sep 17 00:00:00 2001 From: Phil Sutter Date: Mon, 27 Oct 2008 02:29:57 +0100 Subject: MIPS: RB532: Disable the right device Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle --- arch/mips/rb532/devices.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/rb532') diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index 31619c601b1..2f22d714d5b 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c @@ -280,7 +280,7 @@ static int __init plat_setup_devices(void) { /* Look for the CF card reader */ if (!readl(IDT434_REG_BASE + DEV1MASK)) - rb532_devs[1] = NULL; + rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */ else { cf_slot0_res[0].start = readl(IDT434_REG_BASE + DEV1BASE); -- cgit v1.2.3 From 1b432840d0a4740020e29ae7a00717ef8f44954b Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 31 Oct 2008 14:24:29 +0100 Subject: MIPS: RB532: GPIO register offsets are relative to GPIOBASE This patch fixes the wrong use of GPIO register offsets in devices.c. To avoid further problems, use gpio_get_value to return the NAND status instead of our own expanded code. Also define the zero offset of the alternate function register to allow consistent access. Signed-off-by: Florian Fainelli Signed-off-by: Phil Sutter Signed-off-by: Ralf Baechle --- arch/mips/rb532/devices.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/rb532') diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index 2f22d714d5b..c1c29181bd4 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c @@ -118,7 +118,7 @@ static struct platform_device cf_slot0 = { /* Resources and device for NAND */ static int rb532_dev_ready(struct mtd_info *mtd) { - return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY; + return gpio_get_value(GPIO_RDY); } static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -- cgit v1.2.3 From 2e373952cc893207a8b47a5e68c2f5155f912449 Mon Sep 17 00:00:00 2001 From: Phil Sutter Date: Sat, 1 Nov 2008 15:13:21 +0100 Subject: MIPS: RB532: Provide functions for gpio configuration As gpiolib doesn't support pin multiplexing, it provides no way to access the GPIOFUNC register. Also there is no support for setting interrupt status and level. These functions provide access to them and are needed by the CompactFlash driver. Signed-off-by: Phil Sutter Signed-off-by: Ralf Baechle --- arch/mips/rb532/gpio.c | 193 +++++++++++++++++++------------------------------ 1 file changed, 73 insertions(+), 120 deletions(-) (limited to 'arch/mips/rb532') diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c index 70c4a672637..0e84c8ab6a3 100644 --- a/arch/mips/rb532/gpio.c +++ b/arch/mips/rb532/gpio.c @@ -39,10 +39,6 @@ struct rb532_gpio_chip { struct gpio_chip chip; void __iomem *regbase; - void (*set_int_level)(struct gpio_chip *chip, unsigned offset, int value); - int (*get_int_level)(struct gpio_chip *chip, unsigned offset); - void (*set_int_status)(struct gpio_chip *chip, unsigned offset, int value); - int (*get_int_status)(struct gpio_chip *chip, unsigned offset); }; struct mpmc_device dev3; @@ -111,15 +107,47 @@ unsigned char get_latch_u5(void) } EXPORT_SYMBOL(get_latch_u5); +/* rb532_set_bit - sanely set a bit + * + * bitval: new value for the bit + * offset: bit index in the 4 byte address range + * ioaddr: 4 byte aligned address being altered + */ +static inline void rb532_set_bit(unsigned bitval, + unsigned offset, void __iomem *ioaddr) +{ + unsigned long flags; + u32 val; + + bitval = !!bitval; /* map parameter to {0,1} */ + + local_irq_save(flags); + + val = readl(ioaddr); + val &= ~( ~bitval << offset ); /* unset bit if bitval == 0 */ + val |= ( bitval << offset ); /* set bit if bitval == 1 */ + writel(val, ioaddr); + + local_irq_restore(flags); +} + +/* rb532_get_bit - read a bit + * + * returns the boolean state of the bit, which may be > 1 + */ +static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr) +{ + return (readl(ioaddr) & (1 << offset)); +} + /* * Return GPIO level */ static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) { - u32 mask = 1 << offset; struct rb532_gpio_chip *gpch; gpch = container_of(chip, struct rb532_gpio_chip, chip); - return readl(gpch->regbase + GPIOD) & mask; + return rb532_get_bit(offset, gpch->regbase + GPIOD); } /* @@ -128,23 +156,10 @@ static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) static void rb532_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; struct rb532_gpio_chip *gpch; - void __iomem *gpvr; gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpvr = gpch->regbase + GPIOD; - - local_irq_save(flags); - tmp = readl(gpvr); - if (value) - tmp |= mask; - else - tmp &= ~mask; - writel(tmp, gpvr); - local_irq_restore(flags); + rb532_set_bit(value, offset, gpch->regbase + GPIOD); } /* @@ -152,21 +167,14 @@ static void rb532_gpio_set(struct gpio_chip *chip, */ static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { - unsigned long flags; - u32 mask = 1 << offset; - u32 value; struct rb532_gpio_chip *gpch; - void __iomem *gpdr; gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpdr = gpch->regbase + GPIOCFG; - local_irq_save(flags); - value = readl(gpdr); - value &= ~mask; - writel(value, gpdr); - local_irq_restore(flags); + if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) + return 1; /* alternate function, GPIOCFG is ignored */ + rb532_set_bit(0, offset, gpch->regbase + GPIOCFG); return 0; } @@ -176,117 +184,60 @@ static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) static int rb532_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; struct rb532_gpio_chip *gpch; - void __iomem *gpdr; gpch = container_of(chip, struct rb532_gpio_chip, chip); - writel(mask, gpch->regbase + GPIOD); - gpdr = gpch->regbase + GPIOCFG; - local_irq_save(flags); - tmp = readl(gpdr); - tmp |= mask; - writel(tmp, gpdr); - local_irq_restore(flags); + if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) + return 1; /* alternate function, GPIOCFG is ignored */ + /* set the initial output value */ + rb532_set_bit(value, offset, gpch->regbase + GPIOD); + + rb532_set_bit(1, offset, gpch->regbase + GPIOCFG); return 0; } -/* - * Set the GPIO interrupt level - */ -static void rb532_gpio_set_int_level(struct gpio_chip *chip, - unsigned offset, int value) -{ - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; - struct rb532_gpio_chip *gpch; - void __iomem *gpil; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpil = gpch->regbase + GPIOILEVEL; - - local_irq_save(flags); - tmp = readl(gpil); - if (value) - tmp |= mask; - else - tmp &= ~mask; - writel(tmp, gpil); - local_irq_restore(flags); -} +static struct rb532_gpio_chip rb532_gpio_chip[] = { + [0] = { + .chip = { + .label = "gpio0", + .direction_input = rb532_gpio_direction_input, + .direction_output = rb532_gpio_direction_output, + .get = rb532_gpio_get, + .set = rb532_gpio_set, + .base = 0, + .ngpio = 32, + }, + }, +}; /* - * Get the GPIO interrupt level + * Set GPIO interrupt level */ -static int rb532_gpio_get_int_level(struct gpio_chip *chip, unsigned offset) +void rb532_gpio_set_ilevel(int bit, unsigned gpio) { - u32 mask = 1 << offset; - struct rb532_gpio_chip *gpch; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - return readl(gpch->regbase + GPIOILEVEL) & mask; + rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL); } +EXPORT_SYMBOL(rb532_gpio_set_ilevel); /* - * Set the GPIO interrupt status + * Set GPIO interrupt status */ -static void rb532_gpio_set_int_status(struct gpio_chip *chip, - unsigned offset, int value) +void rb532_gpio_set_istat(int bit, unsigned gpio) { - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; - struct rb532_gpio_chip *gpch; - void __iomem *gpis; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpis = gpch->regbase + GPIOISTAT; - - local_irq_save(flags); - tmp = readl(gpis); - if (value) - tmp |= mask; - else - tmp &= ~mask; - writel(tmp, gpis); - local_irq_restore(flags); + rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT); } +EXPORT_SYMBOL(rb532_gpio_set_istat); /* - * Get the GPIO interrupt status + * Configure GPIO alternate function */ -static int rb532_gpio_get_int_status(struct gpio_chip *chip, unsigned offset) +static void rb532_gpio_set_func(int bit, unsigned gpio) { - u32 mask = 1 << offset; - struct rb532_gpio_chip *gpch; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - return readl(gpch->regbase + GPIOISTAT) & mask; + rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC); } -static struct rb532_gpio_chip rb532_gpio_chip[] = { - [0] = { - .chip = { - .label = "gpio0", - .direction_input = rb532_gpio_direction_input, - .direction_output = rb532_gpio_direction_output, - .get = rb532_gpio_get, - .set = rb532_gpio_set, - .base = 0, - .ngpio = 32, - }, - .get_int_level = rb532_gpio_get_int_level, - .set_int_level = rb532_gpio_set_int_level, - .get_int_status = rb532_gpio_get_int_status, - .set_int_status = rb532_gpio_set_int_status, - }, -}; - int __init rb532_gpio_init(void) { struct resource *r; @@ -310,9 +261,11 @@ int __init rb532_gpio_init(void) return -ENXIO; } - /* Set the interrupt status and level for the CF pin */ - rb532_gpio_set_int_level(&rb532_gpio_chip->chip, CF_GPIO_NUM, 1); - rb532_gpio_set_int_status(&rb532_gpio_chip->chip, CF_GPIO_NUM, 0); + /* configure CF_GPIO_NUM as CFRDY IRQ source */ + rb532_gpio_set_func(0, CF_GPIO_NUM); + rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM); + rb532_gpio_set_ilevel(1, CF_GPIO_NUM); + rb532_gpio_set_istat(0, CF_GPIO_NUM); return 0; } -- cgit v1.2.3